NXP LPC4088FBD208 Lpc408x/407x user manual Datasheet

UM10562
LPC408x/407x User manual
Rev. 1 — 13 September 2012
User manual
Document information
Info
Content
Keywords
LPC4088FBD208, LPC4088FET208, LPC4088FET180,
LPC4088FBD144, LPC4078FBD208, LPC4078FET208,
LPC4078FBD144, LPC4078FBD80, LPC4076FET180, LPC4074FBD144,
LPC4074FBD80, ARM, ARM Cortex-M4, 32-bit, USB, Ethernet, LCD,
CAN, I2C, I2S, Flash, EEPROM, Microcontroller
Abstract
LPC408x/407x user manual
UM10562
NXP Semiconductors
LPC408x/407x User Manual
Revision history
Rev
Date
Description
1
20120913
Inital LPC408x/407x User manual version.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
2 of 942
UM10562
Chapter 1: Introductory information
Rev. 1 — 13 September 2012
User manual
1.1 Introduction
The LPC408x/407x is an ARM Cortex-M4 based microcontroller for embedded
applications requiring a high level of integration and low power dissipation.
The Cortex-M4 processor is a high-performance 32-bit processor with a 3-stage pipeline
Harvard architecture with separate local instruction and data buses, as well as a third bus
with slightly lower performance for peripherals. The Cortex-M4 uses the Thumb®
instruction set, providing high code density and reduced program memory requirements.
The Cortex-M4 CPU also includes an internal prefetch unit that supports speculative
branches. The LPC408x/407x adds a specialized flash memory accelerator to give
optimal performance when executing code from flash. The LPC408x/407x is targeted to
operate at up to a 120 MHz CPU frequency under worst case commercial conditions.
The peripheral complement of the LPC408x/407x includes up to 512 kB of Flash memory,
up to 96 kB of data memory, 4,032 bytes of EEPROM memory, an External Memory
Controller for SDRAM and static memory access, an LCD panel controller, an Ethernet
MAC, a high speed SPI flash memory interface (SPIFI), a General Purpose DMA
controller, a USB device/host/OTG interface, 5 UARTs, 3 SSP controllers, 3 I2C
interfaces, an I2S serial audio interface, a 2-channel CAN interface, an SD card interface,
an 8 channel 12-bit ADC, a 10-bit DAC, analog comparators, a Motor Control PWM, a
Quadrature Encoder Interface, 4 general purpose timers, a 6-output general purpose
PWM, an ultra-low power RTC with separate battery supply and event monitor/recorder, a
windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins,
and more.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
3 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
1.2 Features
Refer to Section 1.4 for details of features for specific part numbers.
• Functional replacement for LPC23xx and 24xx family devices.
• ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. The Cortex-M4
executes the Thumb®-2 instruction set for optimal performance and code size,
including hardware division, single cycle multiply, and bit-field manipulation. A
Memory Protection Unit (MPU) supporting eight regions is included.
• Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
• Cortex-M4 Floating Point Unit (FPU), supporting single-precision floating-point
computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The
FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also performs a variety of conversions between fixed-point,
floating-point, and integer data formats. The FPU is not available on LPC4074
devices.
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
• Up to 96 kB on-chip SRAM includes:
– Up to 64 kB of Main SRAM on the CPU code/data bus for high-performance CPU
access.
– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, LCD, and DMA memory, as
well as for general purpose instruction and data storage.
– Up to 4,032 bytes of on-chip EEPROM.
• External Memory Controller provides support for asynchronous static memory devices
such as RAM, ROM and Flash up to 64 MB, as well as dynamic memories such as
Single Data Rate SDRAM.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, SD/MMC, CRC engine,
Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals,
GPIO, and for memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, LCD
controller, and the USB interface. This interconnect provides communication with no
arbitration delays unless two masters attempt to access the same slave at the same
time.
• Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
• LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. The LCD controller is not available on LPC407x devices.
– Dedicated DMA controller.
– Selectable display resolution (up to 1024 × 768 pixels).
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
4 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
– Supports up to 24-bit true-color mode.
• Serial interfaces:
– Ethernet MAC with MII/RMII interface and dedicated DMA controller.
– USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller. USB Host and OTG are not available on LPC4074 devices.
– Five UARTs with fractional baud rate generation, internal FIFOs, IrDA, DMA
support, and RS-485/EIA-485 support on most LPC408x/407x devices. UART1
also has a full set of modem handshaking signals. UART4 includes a synchronous
mode and a Smart Card mode supporting ISO 7816-3. UART4 is not available on
LPC4074 devices.
– Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
– Three enhanced I2C-bus interfaces, one with an open-drain output supporting the
full I2C specification and Fast mode Plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
– Two-channel CAN controller.
– I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S interface can be used with the GPDMA. The I2S interface supports
3-wire data transmit and receive or 4-wire combined transmit and receive
connections, as well as master clock output.
– SPIFI (SPI Flash Interface). This interface uses an SPI bus superset with 4 data
lines to access off-chip Quad SPI Flash memory at a much higher rate than is
possible using standard SPI or SSP interfaces. The SPIFI function allows memory
mapping the contents of the off-chip SPI Flash memory such that it can be
executed as if it were on-chip code memory. Supports SPI memories with 1 or 4
data lines.
• Other peripherals:
– SD card interface that also supports MMC cards. The SD card interface is not
available on LPC4074 devices.
– General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open
drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast
access, and support Cortex-M4 bit-banding. GPIOs can be accessed by the
General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate
an interrupt. There are 165 GPIOs on 208-pin packages, 141 GPIOs on 180-pin
packages, and 109 GPIOs on 144-pin packages.
– 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
– 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
– Dual analog comparator with multiple selectable inputs, selectable internal
reference voltages, and versatile interrupt generation. The comparators are not
available on LPC4074 devices.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
5 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
– Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
– One motor control PWM with support for three-phase motor control.
– Quadrature encoder interface that can monitor one external quadrature encoder.
The QEI is not available on LPC4074 devices.
– Two standard PWM/timer blocks with external count input option.
– Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V Lithium button
cell. The RTC will continue working when the battery voltage drops to as low as
2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.
– Event Monitor/Recorder that can capture the RTC value when an event occurs on
any of 3 inputs. The event identification and the time it occurred are stored in
registers. The Event Monitor/Recorder is in the RTC power domain, and can
therefore operate as long as there is RTC power.
– Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal
oscillator, watchdog warning interrupt, and safety features.
– CRC Engine block can calculate a CRC on supplied data using 1 of 3 standard
polynomials. The CRC engine can be used in conjunction with the DMA controller
to generate a CRC without CPU involvement in the data transfer.
– Cortex-M4 system tick timer, including an external clock input option.
• Standard JTAG test/debug interface as well as Serial Wire Debug and Serial Wire
Trace Port options.
• Emulation trace module supports real-time trace.
• Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of -40 °C to 85 °C.
• Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
Power-down.
• Power savings for operation at or below 100 MHz by reducing on-chip regulator
output.
• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
• Non-maskable Interrupt (NMI) input.
• Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, USB clock, SPIFI clock, or the watchdog timer clock.
• The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep Power-down modes.
• Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI).
• Brownout detect with separate threshold for interrupt and forced reset.
• On-chip Power-On Reset (POR).
• On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
6 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
• 12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
• An on-chip PLL allows CPU operation up to the maximum CPU rate without the need
for a high-frequency crystal. May be run from the main oscillator or the internal RC
oscillator.
• A second, dedicated PLL may be used for the USB and/or SPIFI interfaces in order to
allow added flexibility for the Main PLL settings.
• Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
• Boundary scan for simplified board testing.
• Unique device serial number for identification purposes.
• Available as 208-pin LQFP, 208-pin TFBGA, 180-pin TFBGA, 144-pin LQFP, 80-pin
LQFP packages.
1.3 Applications
• Communications
– Point-of-sale terminals, Web servers, multi-protocol bridges
• Industrial/Medical
– Automation controllers, application control, robotic controls, HVAC, PLC, inverters,
circuit breakers, medical scanning, security monitoring, motor drive, video intercom
• Consumer/Appliance
– Audio, MP3 decoders, alarm systems, displays, printers, scanners, small
appliances, fitness equipment
• Automotive
– Aftermarket, car alarms, GPS/Fleet Monitor
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
7 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
1.4 Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm
SOT459-1
LPC4088
LPC4088FBD208 LQFP208
LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 × 15 × 0.7 mm SOT950-1
LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 × 12 × 0.8 mm
SOT570-2
LPC4088FBD144 LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
SOT486-1
plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm
SOT459-1
LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 × 12 × 0.8 mm
SOT570-2
LPC4078FBD144 LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
SOT486-1
LPC4078FBD80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
LPC4078
LPC4078FBD208 LQFP208
LQFP80
LPC4076
LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 × 12 × 0.8 mm
SOT570-2
LPC4074
LPC4074FBD144 LQFP144
plastic low profile quad flat package; 144 leads; body 20 × 20 × 1.4 mm
SOT486-1
LPC4074FBD80
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
SOT315-1
LQFP80
1.4.1 Part options summary
Table 2.
Ordering options for LPC408x/407x parts
Type
Flash SRAM EEPROM FPU Ethernumber [1]
kB
kB [2]
bytes
net [3]
USB
Ext. LCD UART QEI SD Comp- PackBus [4]
arators age(s)
LPC4088
512
96
4,032
Y
Y
H/O/D 32-bit/
16-bit/
8-bit
Y
5
Y
Y
Y
208,
180,
144
LPC4078
512
96
4,032
Y
Y
H/O/D 32-bit/
16-bit/
8-bit/
none
N
5
Y
Y
Y
208,
180,
144,
80
LPC4076
256
80
4,032
Y
Y
H/O/D 16-bit
N
5
Y
Y
Y
180
LPC4074
128
40
2,048
N
N
N
4
N
N
N
144,
80
D
none
[1]
All types include SPIFI, Event Recorder, 2 CAN channels, 3 SSP interfaces, 3 I2C interfaces, I2S, DAC, and an 8-channel 12-bit ADC.
[2]
96kB = 64kB Main + 32kB peripheral SRAM; 80kB = 64kB Main + 16kB peripheral SRAM; 40kB = 32kB Main + 8kB peripheral SRAM.
[3]
Devices that include Ethernet in packages with 180 pins and greater support both MII and RMII. Smaller packages support only RMII.
[4]
Maximum data bus width for each package, smaller widths may also be used. On 180-pin packages, the external bus is limited to 16
bits. On 144-pin packages, the external bus is limited to 8 bits. 80-pin devices do not support an external bus.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
8 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
TEST/DEBUG
INTERFACE
ARM Cortex-M4
with FPU
I-code
bus
General
Purpose
DMA
controller
Ethernet
10/100
MAC
USB bus or
tranceiver
USB
OTG/
Host/
Device
LCD
panel
interface
General Purpose
I/O ports
EEPROM
Up to 4 kB
SPI Flash
Interface
Flash
Accelerator
Ethernet
registers
LCD
registers
USB
registers
CRC
engine
Boot ROM
8 kB
Static / Dynamic
Memory Controller
APB slave group 0
UARTs 0 & 1
APB slave group 1
SSP1
SSP0 & 2
I2S
2
I C2
Capture/Match timer 0 & 1
Capture/Match timer 2 & 3
PWM0 & 1
SD card interface
12-bit ADC
DAC
Pin connect block
Motor control PWM
GPIO interrupt control
Quadrature Encoder i/f
Analog comparators
External interrupts
Event Inputs
System control
Windowed Watchdog
Note:
- Orange shaded peripheral blocks
support General Purpose DMA.
- Yellow shaded peripheral blocks
include a dedicated DMA controller.
Event Monitor/
Recorder
ALARM
32 kHz oscillator
ultra-low power
regulator
26-bit addr
32-bit data
UARTs 2, 3, & 4
I C0&1
Watchdog oscillator
Flash
Up to 512 kB
SRAM
Up to 96 kB
Multilayer AHB Matrix
2
Real Time Clock
Backup registers
(20 bytes)
RTC Power Domain
Fig 1.
clock generation,
power control,
and other
system functions
D-code System
bus
bus
CAN 1 & 2
Vbat
clocks
and
controls
RST
Ethernet PHY LCD
interface
panel
Xtalin
JTAG
interface
Xtalout
5. Simplified block diagram
120229
LPC408x/407x simplified block diagram
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
9 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
1.6 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to Tightly Coupled Memory
interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access
(D-code). The use of two core buses allows for simultaneous operations if concurrent
operations target different devices.
The LPC408x/407x uses a multi-layer AHB matrix to connect the Cortex-M4 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals on different slaves ports of the matrix to be accessed simultaneously
by different bus masters. Details of the multilayer matrix connections are shown in
Figure 2.
APB peripherals are connected to the CPU via two APB buses using separate slave ports
from the multilayer AHB matrix. This allows for better performance by reducing collisions
between the CPU and the DMA controller. The APB bus bridges are configured to buffer
writes so that the CPU or DMA controller can write to APB devices without always waiting
for APB write completion.
1.7 ARM Cortex-M4 processor
The ARM Cortex-M4 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M4 offers a Thumb-2
instruction set, low interrupt latency, interruptible/continuable multiple load and store
instructions, automatic state save and restore for interrupts, tightly integrated interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
Information about Cortex-M4 configuration options can be found in Section 40.1.
1.8 On-chip flash memory system
The LPC408x/407x contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for CPU accesses. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc.
1.9 On-chip Static RAM
The LPC408x/407x contains up to 96 kB of on-chip static RAM memory. Up to 64 kB of
SRAM, accessible by the CPU and the General Purpose DMA controller, is on a
higher-speed bus. Up to 32 kB SRAM is provided in up to two additional 16 kB SRAM
blocks for use primarily for peripheral data. When both SRAMs are present, they are
situated on separate slave ports on the AHB multilayer matrix.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
10 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters. It also allows separation of
data for different peripherals functions, in order to improve system performance. For
example, LCD DMA can be occurring in one SRAM while Ethernet DMA is occurring in
another, all while the CPU is using the Main SRAM for data and/or instruction access.
1.10 On-chip EEPROM
The LPC408x/407x contains up to 4,032 bytes of on-chip EEPROM memory. The
EEPROM is accessible only by the CPU.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
11 of 942
UM10562
NXP Semiconductors
Chapter 1: Introductory information
TEST/DEBUG
INTERFACE
ARM Cortex-M4
with FPU
I-code
bus
General
Purpose
DMA
controller
Ethernet
10/100
MAC
LCD
panel
interface
USB bus or
tranceiver
D-code System
bus
bus
clock generation, CLK
power control, OUT
and other
system functions
Vdd
voltage regulator
clocks
and
controls
internal
power
USB
OTG/
Host/Dev
EEPROM
Up to 4 kB
Flash
Accelerator
Flash
Up to 512 kB
Main SRAM
Up to 64 kB
Boot ROM
8 kB
Driver ROM
16 kB
Periph. SRAM Periph. SRAM
Up to 16 kB
Up to 16 kB
Mem Ctl
registers
Multilayer
AHB Matrix
GPDMA
registers
Ethernet
registers
AHB to
APB bridge
AHB to
APB bridge
USB
registers
CRC
engine
SSP1
SSP0 & 2
CAN 1 & 2
I2S
I2C 0 & 1
I2C 2
Capture/Match timer 0 & 1
Capture/Match timer 2 & 3
PWM0 & 1
SD card interface
12-bit ADC
DAC
Pin connect block
Motor control PWM
GPIO interrupt control
Quadrature Encoder i/f
UARTs 2, 3, & 4
External interrupts
Windowed Watchdog
System control
Note:
- Orange shaded peripheral blocks
support General Purpose DMA.
- Yellow shaded peripheral blocks
include a dedicated DMA controller.
Event Monitor/
Recorder
ALARM
32 kHz oscillator
ultra-low power
regulator
HS
GPIO
SPI Flash
Interface
APB slave group 1
Event Inputs
Real Time Clock
Backup registers
(20 bytes)
120621
RTC Power Domain
Fig 2.
D[31:0]
Static / Dynamic A[25:0]
Memory
control
Controller
APB slave group 0
UARTs 0 & 1
Watchdog oscillator
Vbat
LCD
registers
RST
Ethernet PHY LCD
interface
panel
Xtalin
JTAG
interface
Xtalout
1.11 Detailed block diagram
LPC408x/407x block diagram, CPU and buses
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
12 of 942
UM10562
Chapter 2: LPC408x/407x Memory map
Rev. 1 — 13 September 2012
User manual
2.1 Memory map and peripheral addressing
The ARM Cortex-M4 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC408x/407x.
Table 3.
Memory usage and details
Address range
General Use
Address range details and description
0x0000 0000 to
0x1FFF FFFF
On-chip non-volatile
memory
0x0000 0000 - 0x0007 FFFF
For devices with 512 kB of flash memory.
0x0000 0000 - 0x0003 FFFF
For devices with 256 kB of flash memory.
0x0000 0000 - 0x0001 FFFF
For devices with 128 kB of flash memory.
0x1000 0000 - 0x1000 FFFF
For devices with 64 kB of Main SRAM.
0x1000 0000 - 0x1000 7FFF
For devices with 32 kB of Main SRAM.
Boot ROM
0x1FFF 0000 - 0x1FFF 7FFF
8 kB Boot ROM with flash services.
Driver ROM
0x1FFF 8000 - 0x1FFF 1FFF
16 kB Driver ROM
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 - 0x2000 1FFF
Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 - 0x2000 3FFF
Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 - 0x2000 7FFF
Peripheral SRAM - bank 1 (16 kB)
AHB peripherals
0x2008 0000 - 0x200B FFFF
See Section 2.3.1 for details
SPIFI buffer space
0x2800 0000 - 0x28FF FFFF
SPIFI memory mapped access space
APB Peripherals
0x4000 0000 - 0x4007 FFFF
APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 - 0x400F FFFF
APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
On-chip SRAM
0x2000 0000 to
0x3FFF FFFF
0x4000 0000 to
0x7FFF FFFF
0x8000 0000 to
0xDFFF FFFF
Off-chip Memory via
the External Memory
Controller
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF
Static memory chip select 0 (up to 64 MB)[1]
0x9000 0000 - 0x93FF FFFF
Static memory chip select 1 (up to 64 MB)[2]
0x9800 0000 - 0x9BFF FFFF
Static memory chip select 2 (up to 64 MB)
0x9C00 0000 - 0x9FFF FFFF
Static memory chip select 3 (up to 64 MB)
Four dynamic memory chip selects:
0xA000 0000 - 0xAFFF FFFF
0xE000 0000 to
0xE00F FFFF
UM10562
User manual
Cortex-M4 Private
Peripheral Bus
Dynamic memory chip select 0 (up to 256MB)
0xB000 0000 - 0xBFFF FFFF
Dynamic memory chip select 1 (up to 256MB)
0xC000 0000 - 0xCFFF FFFF
Dynamic memory chip select 2 (up to 256MB)
0xD000 0000 - 0xDFFF FFFF
Dynamic memory chip select 3 (up to 256MB)
0xE000 0000 - 0xE00F FFFF
Cortex-M4 related functions, includes the NVIC
and System Tick Timer.
[1]
Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See SCS register
bit 0 (Section 3.3.7.1).
[2]
Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See SCS register
bit 0 (Section 3.3.7.1).
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
13 of 942
UM10562
NXP Semiconductors
Chapter 2: LPC408x/407x Memory map
2.2 Memory maps
The LPC408x/407x incorporates several distinct memory regions, shown in the following
figures. Figure 3 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping,
which is described later in this section.
Figure 3 and Table 5 show different views of the peripheral address space. The AHB
peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
14 of 942
UM10562
NXP Semiconductors
Chapter 2: LPC408x/407x Memory map
Memory space
4 GB
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
0xE004 0000
reserved
0xE000 0000
external memory
(4 dynamic chip selects)
0xA000 0000
external memory
(4 static chip selects)
2 GB
0x8000 0000
reserved
0x4400 0000
APB peripheral
bit-band addressing
0x4200 0000
reserved
0x4010 0000
APB peripheral group 1
0x4008 0000
APB peripheral group 0
1 GB
0x4000 0000
reserved
0x2900 0000
SPIFI memory
mapped space
0x2800 0000
reserved
reserved
0x2200 0000
0x200C 0000
AHB peripherals
0x2008 0000
peripheral SRAM 1
0x2000 4000
peripheral SRAM 0
Boot ROM and Driver ROM
reserved
I-Code and
D-Code
memory space
0x2000 0000
0x1FFF 0000
0x1001 0000
64 kB Main SRAM
0x1000 0000
reserved
0x0008 0000
512 kB flash memory
0x0000 0000
0x0400
0x0000
active interrupt
vectors
120420
Fig 3.
31
system control
30-17
reserved
16
15
SD card
QEI
14
motor ctl PWM
13-12
reserved
11
SSP2
10
I2S
9
UART4
8
7
6
5
4
I2C2
UART3
UART2
Timer3
Timer2
3
2
1-0
DAC
SSP0
reserved
AHB peripherals
0x200A 0000
7 EMC registers
0x2009 C000
6
GPIO
0x2009 8000
5 SPIFI registers
0x2009 4000
4 CRC engine
0x2009 0000
3
USB
0x2008 C000
2 LCD controller
0x2008 8000
1
Ethernet
0x2008 4000
0 GP DMA ctlr
0x2008 0000
0x400B C000
0x400B 8000
0x400B 0000
0x400A C000
0x400A 8000
0x400A 4000
0x400A 0000
0x4008 8000
0x4008 0000
APB0 peripherals
31-24
23
reserved
I2C1
22-19
18
reserved
CAN 2
17
16
CAN 1
CAN common
15 CAN AF registers
14
CAN AF RAM
13
ADC
12
SSP1
11
pin connect
10
9
8
7
6
GPIO interrupts
RTC
Comparators
I2C0
PWM1
5
4
3
2
PWM0
UART1
UART0
Timer1
1
0
0x4010 0000
0x400F C000
0x400C 4000
0x400C 0000
0x4009 C000
0x4009 8000
0x4009 4000
0x4009 0000
0x4008 C000
0x2400 0000
peripheral SRAM bit-band
addressing
0.5 GB
APB1 peripherals
0x4008 0000
0x4006 0000
0x4005 C000
0x4004 C000
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x4003 4000
0x4003 0000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
Timer0
0x4000 4000
Watchdog timer
0x4000 0000
System memory map
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
15 of 942
UM10562
NXP Semiconductors
Chapter 2: LPC408x/407x Memory map
2.3 On-chip peripherals
All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required
to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
2.3.1 AHB peripherals
The following table shows the addresses of peripheral functions that reside directly on the
AHB bus matrix. Complete register descriptions may be found in the relevant chapters.
Table 4.
AHB peripherals and base addresses
AHB peripheral
Address range
Peripheral name
0
0x2008 0000 to 0x2008 3FFF
General Purpose DMA controller
1
0x2008 4000 to 0x2008 7FFF
Ethernet MAC
2
0x2008 8000 to 0x2008 BFFF
LCD controller
3
0x2008 C000 to 0x2008 FFFF
USB interface
4
0x2009 0000 to 0x2009 3FFF
CRC engine
5
0x2009 4000 to 0x2009 7FFF
SPIFI
6
0x2009 8000 to 0x2009 BFFF
GPIO
7
0x2009 C000 to 0x2009 FFFF
External Memory Controller
8 to 15
0x200A 0000 to 0x200B FFFF
reserved
2.3.2 APB peripheral addresses
The following table shows the address maps of the 2 APB buses. APB peripherals do not
use all of the 16 kB space allocated to them. Typically each device’s registers are
"aliased" or repeated at multiple locations within each 16 kB range.
Table 5.
UM10562
User manual
APB0 peripherals and base addresses
APB0 peripheral
Base address
Peripheral name
0
0x4000 0000
Watchdog Timer
1
0x4000 4000
Timer 0
2
0x4000 8000
Timer 1
3
0x4000 C000
UART0
4
0x4001 0000
UART1
5
0x4001 4000
PWM0
6
0x4001 8000
PWM1
7
0x4001 C000
I2C0
8
0x4002 0000
Comparators
9
0x4002 4000
RTC and Event Monitor/Recorder
10
0x4002 8000
GPIO interrupts
11
0x4002 C000
Pin Connect Block
12
0x4003 0000
SSP1
13
0x4003 4000
ADC
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
16 of 942
UM10562
NXP Semiconductors
Chapter 2: LPC408x/407x Memory map
Table 5.
APB0 peripherals and base addresses
APB0 peripheral
Base address
Peripheral name
14
0x4003 8000
CAN Acceptance Filter RAM
15
0x4003 C000
CAN Acceptance Filter Registers
16
0x4004 0000
CAN Common Registers
17
0x4004 4000
CAN Controller 1
18
0x4004 8000
CAN Controller 2
19 to 22
0x4004 C000 to 0x4005 8000
reserved
23
0x4005 C000
I2C1
24 to 31
0x4006 0000 to 0x4007 C000
reserved
Table 6.
APB1 peripherals and base addresses
APB1 peripheral
Base address
Peripheral name
0 to 1
0x4008 0000 to 0x4008 4000
reserved
2
0x4008 8000
SSP0
3
0x4008 C000
DAC
4
0x4009 0000
Timer 2
5
0x4009 4000
Timer 3
6
0x4009 8000
UART2
7
0x4009 C000
UART3
8
0x400A 0000
I2C2
9
0x400A 4000
UART4
10
0x400A 8000
I2S
11
0x400A C000
SSP2
12 to 13
0x400B 0000 to 0x400B 4000
reserved
14
0x400B 8000
Motor control PWM
15
0x400B C000
Quadrature Encoder Interface
16
0x400C 0000
SD card interface
17 to 30
0x400D 0000 to 0x400F 8000
reserved
31
0x400F C000
System control
2.4 Memory re-mapping
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the Cortex-M4. Refer to the NVIC description in Section 5.4 and to
the ARM Cortex-M4 User Guide referred to in Section 40.1.
Boot ROM re-mapping
Following a hardware reset, the Boot ROM is temporarily mapped to address 0. This is
normally transparent to the user. However, if execution is halted immediately after reset by
a debugger, it should correct the mapping for the user. See Section 39.8.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
17 of 942
UM10562
NXP Semiconductors
Chapter 2: LPC408x/407x Memory map
2.5 AHB arbitration
The Multilayer AHB Matrix arbitrates between several masters, only if they attempt to
access the same matrix slave port at the same time. By default, the Cortex-M4 D-code
bus has the highest priority, followed by the I-Code bus. All other masters share a lower
priority.
The default priority can be altered by the user if care is taken. This may be particularly
useful if the LCD interface is used and it has difficulty getting sufficient data.
2.5.1 Matrix Arbitration register
The Matrix Arbitration register provides the ability to change the default AHB Matrix
arbitration priorities.
Table 7.
Matrix Arbitration register (Matrix_Arb - 0x400F C188) bit description
Bit
Symbol
Description
1:0
PRI_ICODE
I-Code bus priority. Should be lower than PRI_DCODE for proper operation.
Reset value
0x1
3:2
PRI_DCODE
D-Code bus priority.
0x3
5:4
PRI_SYS
System bus priority.
0
7:6
PRI_GPDMA
General Purpose DMA controller priority.
0
9:8
PRI_ETH
Ethernet DMA priority.
0
11:10
PRI_LCD
LCD DMA priority.
0
13:12
PRI_USB
USB DMA priority.
0
15:14
-
Reserved. Read value is undefined, only zero should be written.
16
ROM_LAT
ROM latency select. Should always be 0.
31:17
-
Reserved. Read value is undefined, only zero should be written.
NA
0
NA
The values used for the various priorities are 3 = highest, 0 = lowest.
An example of a way to give priority to the LCD DMA is to use the value 0x0000 0C09.
The gives the LCD highest priority, D-code second priority, I-Code third priority, and all
others lowest priority.
Where in the memory space code and various types of data are located can be managed
to help minimize the need for arbitration and possible starvation of any of the bus masters,
as well as a need for changing the default priorities. For instance, LCD refresh from
off-chip memory connected to the EMC, while also executing off-chip code via the EMC
can cause a great deal of arbitration.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
18 of 942
UM10562
Chapter 3: LPC408x/407x System and clock control
Rev. 1 — 13 September 2012
User manual
3.1 Introduction
The system control block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
•
•
•
•
Chip Reset (see Section 3.4)
Peripheral Reset control (see Section 3.5)
Brown-Out Detection (see Section 3.6)
External Interrupt Inputs (see Section 3.7)
Each type of function has its own registers if any are required and unneeded bits are
defined as reserved in order to allow future expansion.
3.1.1 Summary of clocking and power control functions
This section describes the generation of the various clocks needed for device operation,
and options of clock source selection, as well as power control and wake-up from reduced
power modes. Functions described in the following subsections include:
•
•
•
•
•
•
UM10562
User manual
Oscillators (see Section 3.8)
PLLs (see Section 3.10)
Clock selection and dividers (see Section 3.11)
Power control (see Section 3.12)
Wake-up timer (see Section 3.13)
External clock output (see Section 3.14)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
19 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
system clock select
CLKSRCSEL[0]
irc_clk
osc_clk
120601
PLL0 settings
PLL0CON, PLL0CFG
0
PLL0 (Main PLL)
1
pll_clk
sysclk
alt_pll_clk
PLL1 (Alt PLL)
PLL1 settings
PLL1CON, PLL1CFG
sysclk
0
pll_clk
1
CPU clock select
CCLKSEL[8]
CPU Clock
Divider
cclk
CPU divide select
CCLKSEL[4:0]
EMC Clock
Divider
emc_clk
EMC divide select
EMCCLKSEL[0]
Peripheral
Clock Divider
pclk
PCLK divide select
PCLKSEL[4:0]
sysclk
pll_clk
alt_pll_clk
00
01
10
USB clock select
USBCLKSEL[9:8]
sysclk
pll_clk
alt_pll_clk
Fig 4.
USB Clock
Divider
usb_clk
USB divide select
USBCLKSEL[4:0]
00
01
10
SPIFI Clock
Divider
SPIFI clock select
SPIFICLKSEL[9:8)
SPIFI divide select
SPIFICLKSEL[4:0]
spifi_clk
Clock generation
3.2 Pin description
Table 8 shows pins that are associated with System Control block functions.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
20 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 8.
Pin summary
Pin name
Pin direction
Pin description
EINT0
Input
External Interrupt Input 0 - An active low/high level or falling/rising edge general purpose
interrupt input. This pin may be used to wake up the processor from Sleep, Deep-sleep, or
Power-down modes.
EINT1
Input
External Interrupt Input 1 - See the EINT0 description above.
EINT2
Input
External Interrupt Input 2 - See the EINT0 description above.
EINT3
Input
External Interrupt Input 3 - See the EINT0 description above.
RESET
Input
External Reset input - A LOW on this pin resets the chip, causing I/O ports and peripherals to
take on their default states, and the processor to begin execution at address 0x0000 0000.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
21 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 9.
Register overview: System control (base address 0x400F C000)
Name
Access
Address
offset
Description
Reset value Reference
3.3.1
PLL registers
PLLCON0:1
R/W
0x080; 0xA0 PLL0 and PLL1 Control registers
0
3.3.1.1
PLLCFG0:1
R/W
0x084; 0xA4 PLL0 and PLL1 Configuration registers
0
3.3.1.2
PLLSTAT0:1
RO
0x088; 0xA8 PLL0 and PLL1 Status registers
0
3.3.1.3
PLLFEED0:1
WO
0x08C; 0xAC PLL0 and PLL1 Feed registers
NA
3.3.1.5
3.3.2
Power control
PCON
R/W
0x0C0
Power Control register
0
PCONP
R/W
0x0C4
Power Control for Peripherals
PCONP1
R/W
0x0C8
Power Control for Peripherals 1
0x8
3.3.2.2
PBOOST
R/W
0x1B0
Power boost register
0x3
3.3.2.3
0x0408 829E 3.3.2.2
3.3.3
Clock selection and divider registers
EMCCLKSEL
R/W
3.3.2.1
0x100
External Memory Controller Clock Selection register
0
3.3.3.1
CCLKSEL
R/W
0x104
CPU Clock Selection register
1
3.3.3.2
USBCLKSEL
R/W
0x108
USB Clock Selection register
0
3.3.3.3
CLKSRCSEL
R/W
0x10C
Clock Source Select Register
0
3.3.3.4
PCLKSEL
R/W
0x1A8
Peripheral Clock Selection register
0x10
3.3.3.5
SPIFICLKSEL
R/W
0x1B4
SPIFI Clock Selection register
0
3.3.3.6
3.3.4
External interrupts
EXTINT
R/W
0x140
External Interrupt Flag Register
0
3.3.4.1
EXTMODE
R/W
0x148
External Interrupt Mode register
0
3.3.4.2
EXTPOLAR
R/W
0x14C
External Interrupt Polarity Register
0
3.3.4.3
3.3.5
Device and peripheral reset
RSID
R/W
0x180
Reset Source Identification Register
see Table 28 3.3.5.1
RSTCON0
R/W
0x1CC
Individual peripheral reset control bits
0
3.3.5.2
RSTCON1
R/W
0x1D0
Individual peripheral reset control bits
0
3.3.5.3
3.3.6
EMC delay control and calibration
EMCDLYCTL
R/W
0x1DC
Values for the 4 programmable delays associated
with SDRAM operation.
0x210
3.3.6.1
EMCCAL
R/W
0x1E0
Controls the calibration counter for programmable
delays and returns the result value.
0x1F00
3.3.6.2
3.3.7
Miscellaneous system control registers
SCS
R/W
0x1A0
LCD_CFG
R/W
CANSLEEPCLR
R/W
CANWAKEFLAGS
R/W
UM10562
User manual
System Control and Status
0
3.3.7.1
0x1B8
LCD Clock configuration register
0
3.3.7.2
0x110
Allows clearing the current CAN channel sleep state
as well as reading back that state.
0
3.3.7.3
0x114
Indicates the wake-up state of the CAN channels.
0
3.3.7.4
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
22 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 9.
Register overview: System control (base address 0x400F C000)
Name
Access
Address
offset
USBINTST
R/W
DMACREQSEL
CLKOUTCFG
UM10562
User manual
Description
Reset value Reference
0x1C0
USB Interrupt Status
0x8000 0000 3.3.7.5
R/W
0x1C4
Selects between alternative requests on DMA
channels 0 through 7 and 10 through 15.
0
3.3.7.6
R/W
0x1C8
Clock Output Configuration register
0
3.3.7.7
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
23 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.1 PLL registers
3.3.1.1 PLL Control registers
The PLLCON registers contains the bits that enable and connect each PLL. Enabling a
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Changes to a PLLCON register do not take effect until a correct PLL feed sequence has
been given for that PLL (see Section 3.3.1.5 and Section 3.3.1.2).
Table 10.
PLL Control registers (PLLCON[0:1] - addresses 0x400F C080 (PLLCON0) and 0x400F C0A0 (PLLCON1))
bit description
Bit
Symbol
Description
0
PLLE
PLL Enable. When one, and after a valid PLL feed, this bit will activate the related PLL
and allow it to lock to the requested frequency. See PLLSTAT register, Table 12.
Reset value
31:1
-
Reserved. Read value is undefined, only zero should be written.
0
NA
Each PLL must be set up, enabled, and lock established before it may be used as a clock
source. The hardware does not insure that the PLL is locked before it is selected nor does
it automatically disconnect the PLL if lock is lost during operation.
3.3.1.2 PLL Configuration registers
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 3.3.1.5). Calculations for the PLL frequency, and multiplier and divider values are
found in Section 3.10.5.
Table 11.
PLL Configuration registers (PLLCFG[0:1] - addresses 0x400F C084 (PLLCFG0) and 0x400F C0A4
(PLLCFG1)) bit description
Bit
Symbol
Description
Reset value
4:0
MSEL
PLL Multiplier value. Supplies the value "M" in the PLL frequency calculations. The value
stored here is the M value minus 1.
0
Note: For details on selecting the right value for MSEL see Section 3.10.4.
6:5
PSEL
PLL Divider value. Supplies the value "P" in the PLL frequency calculations. This value is
encoded as follows:
0
00 (0x0) = divide by 1
01 (0x1) = divide by 2
10 (0x2) = divide by 4
11 (0x3) = divide by 8
Note: For details on selecting the right value for PSEL see Section 3.10.4.
31:7
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
24 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.1.3 PLL Status registers
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see Section 3.3.1.5 “PLL Feed registers”).
Table 12.
PLL Status registers (PLLSTAT[0:1] - addresses 0x400F C088 (PLLSTAT0) and 0x400F C0A8 (PLLSTAT1))
bit description
Bit
Symbol
Description
Reset value
4:0
MSEL
Read-back for the PLL Multiplier value. This is the value currently used by the related
PLL.
0
6:5
PSEL
Read-back for the PLL Divider value. This is the value currently used by the related
PLL.
0
7
-
Reserved. The value read from a reserved bit is not defined.
8
PLLE_STAT
Read-back for the PLL Enable bit. When one, the related PLL is currently activated.
When zero, the related PLL is turned off. This bit is automatically cleared when
Power-down mode is activated.
9
-
Reserved. The value read from a reserved bit is not defined.
10
PLOCK
Reflects the PLL Lock status. When zero, the related PLL is not locked. When one, the
related PLL is locked onto the requested frequency.
31:11
-
Reserved. The value read from a reserved bit is not defined.
NA
0
NA
0
NA
3.3.1.4 PLL Interrupts: PLOCK0 and PLOCK1
The PLOCK bit in the PLLSTAT register reflects the lock status of the related PLL1. When
the PLL is first enabled, or when its parameters are changed, the PLL requires some time
to establish lock under the new conditions. The related PLOCK bit can be monitored to
determine when the PLL may be connected for use.
Each PLOCK bit is connected to the interrupt controller. This allows for software to turn on
the PLL and continue with other functions without having to wait for the PLL to achieve
lock. When the interrupt occurs, the PLL may be selected as a clock source, and the
interrupt disabled. PLOCK0 and PLOCK1 appear as exception numbers 32 and 48
respectively in Table 50. Note that each PLOCK bit remains asserted whenever the
related PLL is locked, so if the interrupt is used, the interrupt service routine must disable
the interrupt prior to exiting.
3.3.1.5 PLL Feed registers
A correct feed sequence must be written to the related PLLFEED register in order for
changes to the related PLLCON and PLLCFG registers to take effect. The feed sequence
is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and there must be no other register
access in the same address space (0x400F C000 to 0x400F FFFF) between them.
Because of this, it may be necessary to disable interrupts for the duration of the PLL feed
operation, if there is a possibility that an interrupt service routine could write to another
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
25 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
register in that space. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 13.
PLL Feed registers (PLLFEED[0:1] - addresses 0x400F C08C (PLLFEED0) and 0x400F C0AC (PLLFEED1))
bit description
Bit
Symbol
Description
7:0
PLLFEED
The PLL feed sequence must be written to this register in order for the related PLL’s
configuration and control register changes to take effect.
31:8
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0x00
NA
© NXP B.V. 2012. All rights reserved.
26 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.2 Power control
3.3.2.1 Power Mode Control register
Controls for some reduced power modes and other power related controls are contained
in the PCON register, as described in Table 14.
Table 14.
Power Mode Control register (PCON - address 0x400F C0C0) bit description
Bit
Symbol
Description
Reset
value
0
PM0
Power mode control bit 0. This bit controls entry to the Power-down mode. See
Section 3.3.2.1.1 below for details.
0
1
PM1
Power mode control bit 1. This bit controls entry to the Deep Power-down mode. See
Section 3.3.2.1.1 below for details.
0
2
BODRPM
Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be
turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further
reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up
source from the reduced power mode will be lost.
0
When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep
modes.
See the System Control Block chapter for details of Brown-Out detection.
3
BOGD
Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at
all times, and does not consume power.
0
When 0, the Brown-Out Detect circuitry is enabled.
See the System Control Block chapter for details of Brown-Out detection.
Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (see
Section 5.1) must be disabled when software changes the value of this bit.
4
BORD
Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the
VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not
affected.
0
When BORD is 0, the BOD reset is enabled.
See the Section 3.6 for details of Brown-Out detection.
7:3
-
Reserved. Read value is undefined, only zero should be written.
8
SMFLAG
Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software
writing a one to this bit.
0 [1][2]
9
DSFLAG
Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by
software writing a one to this bit.
0 [1][2]
10
PDFLAG
Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by
software writing a one to this bit.
0 [1][2]
11
DPDFLAG Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered.
Cleared by software writing a one to this bit.
0 [1][3]
31:12
-
UM10562
User manual
NA
Reserved. Read value is undefined, only zero should be written.
NA
[1]
Only one of these flags will be valid at a specific time.
[2]
Hardware reset value only for a power-up of core power or by a brownout detect event.
[3]
Hardware reset value only for a power-up event on Vbat.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
27 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.2.1.1
Encoding of Reduced Power Modes
The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The
encoding of these bits allows backward compatibility with devices that previously only
supported Sleep and Power-down modes. Table 15 below shows the encoding for the
three reduced power modes.
Table 15.
PM1, PM0
Encoding of reduced power modes
Description
00
Execution of WFI or WFE enters either Sleep or Deep Sleep mode as defined by the
SLEEPDEEP bit in the Cortex-M4 System Control Register.
01
Execution of WFI or WFE enters Power-down mode if the SLEEPDEEP bit in the
Cortex-M4 System Control Register is 1.
10
Reserved, this setting should not be used.
11
Execution of WFI or WFE enters Deep Power-down mode if the SLEEPDEEP bit in
the Cortex-M4 System Control Register is 1.
3.3.2.2 Power Control for Peripherals registers
The PCONP registers allow turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer
and the System Control block).
Some peripherals, particularly those that include analog functions, may consume power
that is not clock dependent. These peripherals may contain a separate disable control that
turns off additional circuitry to reduce power. When this is the case, the peripheral should
be disabled internally first, then turned off using PCONP, in order to get the greatest power
savings. Information on peripheral specific power saving features may be found in the
chapter describing that peripheral.
Each bit in PCONP controls one peripheral as shown in Table 16.
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral control bit is 0, that
peripheral’s clock is disabled (gated off) to conserve power. For example if bit 19 is 1, the
I2C1 interface is enabled. If bit 19 is 0, the I2C1 interface is disabled.
Important: valid data reads from a peripheral register and valid data writes to a
peripheral register are possible only if that peripheral is enabled in the PCONP
register!
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
28 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 16.
Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit description
Bit
Symbol
Description
Reset
value
0
PCLCD
LCD controller power/clock control bit.
0
1
PCTIM0
Timer/Counter 0 power/clock control bit.
1
2
PCTIM1
Timer/Counter 1 power/clock control bit.
1
3
PCUART0
UART0 power/clock control bit.
1
4
PCUART1
UART1 power/clock control bit.
1
5
PCPWM0
PWM0 power/clock control bit.
0
6
PCPWM1
PWM1 power/clock control bit.
0
1
7
PCI2C0
I2C0
8
PCUART4
UART4 power/clock control bit.
0
9
PCRTC
RTC and Event Monitor/Recorder power/clock control bit.
1
10
PCSSP1
SSP 1 interface power/clock control bit.
0
11
PCEMC
External Memory Controller power/clock control bit.
0
12
PCADC
A/D converter (ADC) power/clock control bit.
0
interface power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before
attempting to set PDN.
13
PCCAN1
CAN Controller 1 power/clock control bit.
0
14
PCCAN2
CAN Controller 2 power/clock control bit.
0
15
PCGPIO
Power/clock control bit for IOCON, GPIO, and GPIO interrupts.
1
16
PCSPIFI
SPI Flash Interface power/clock control bit.
0
17
PCMCPWM Motor Control PWM power/clock control bit.
0
18
PCQEI
Quadrature Encoder Interface power/clock control bit.
0
1
19
PCI2C1
I2C1
20
PCSSP2
SSP2 interface power/clock control bit.
0
21
PCSSP0
SSP0 interface power/clock control bit.
0
22
PCTIM2
Timer 2 power/clock control bit.
0
23
PCTIM3
Timer 3 power/clock control bit.
0
24
PCUART2
UART 2 power/clock control bit.
0
25
PCUART3
UART 3 power/clock control bit.
0
PCI2C2
I2C
interface 2 power/clock control bit.
1
27
PCI2S
I2S
interface power/clock control bit.
0
28
PCSDC
SD Card interface power/clock control bit.
0
29
PCGPDMA
GPDMA function power/clock control bit.
0
30
PCENET
Ethernet block power/clock control bit.
0
31
PCUSB
USB interface power/clock control bit.
0
26
UM10562
User manual
interface power/clock control bit.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
29 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 17.
Power Control for Peripherals register (PCONP1 - address 0x400F C0C8) bit description
Bit
Symbol
Description
Reset
value
2:0
-
Reserved. Read value is undefined, only zero should be written.
3
PCCMP
Comparator power/clock control bit.
31:4
-
Reserved. Read value is undefined, only zero should be written.
NA
1
NA
Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC,
its output must be selected to appear on the related pin, P0[26], by configuring the
relevant IOCON register. See Section 7.4.1.
3.3.2.3 Power Boost control register
The Power Boost control register allows choosing between high-speed operation above
100 MHz, or power savings when operation is at 100 MHz or lower, by controlling the
output of the main on-chip regulator. The boost feature is turned on when user code is first
executed following reset. It can then be turned off by user code if the CPU clock rate will
always be at or below 100 MHz, thus saving power that is only needed for operation
above 100 MHz. Details are show in Table 18.
Table 18.
Power Boost control register (PBOOST - address 0x400F C1B0) bit description
Bit
Symbol
Description
1:0
Boost
Boost control bits.
Reset
value
0x3
00 : Boost is off, operation must be below 100 MHz.
11 : Boost is on, operation up to 120 MHz is supported.
Other values are not allowed.
31:2
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
30 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.3 Clock selection and divider registers
3.3.3.1 EMC Clock Selection register
The EMCCLKSEL register controls division of the clock before it is used by the EMC. The
EMC uses the same base clock as the CPU and the APB peripherals. The EMC clock can
be the same as the CPU clock, or half that. This is intended to be used primarily when the
CPU is running faster than the external bus can support.
Table 19.
EMC Clock Selection register (EMCCLKSEL - address 0x400F C100) bit description
Bit
Symbol
0
EMCDIV
31:1
-
Value
Description
Reset value
Selects the EMC clock rate relative to the CPU clock.
0
The EMC uses the same clock as the CPU.
1
The EMC uses a clock at half the rate of the CPU.
Reserved. Read value is undefined, only zero should be written.
0
NA
3.3.3.2 CPU Clock Selection register
The CCLKSEL register controls selection of the clock used as the Main PLL input, and
also controls the division of the PLL0 output before it is used by the CPU. When PLL0 is
bypassed, the division may be by 1. When PLL0 is running, the output must be divided in
order to bring the CPU clock frequency (CCLK) within operating limits. A 5-bit divider
allows a range of options, including slowing CPU operation to a low rate for temporary
power savings without turning off PLL0. Note that the CPU clock rate should not be set
lower than the peripheral clock rate.
The two clock sources that may be chosen to drive PLL0 and ultimately the CPU and
on-chip peripheral devices are the main oscillator and the Internal RC oscillator.
The clock source selection for PLL0 can only be changed safely when PLL0 is not being
used. For a detailed description of how to change the clock source in a system using PLL0
see Section 3.10.7 “PLL configuration examples”.
Note the following restrictions regarding the choice of clock sources:
• The IRC oscillator should not be used (via PLL0) as the clock source for the USB
subsystem.
• The IRC oscillator should not be used (via PLL0) as the clock source for the CAN
controllers if the CAN baud rate is higher than 100 kbit/s.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
31 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 20.
CPU Clock Selection register (CCLKSEL - address 0x400F C104) bit description
Bit
Symbol
4:0
CCLKDIV
Value Description
Reset value
Selects the divide value for creating the CPU clock (CCLK) from the selected
clock source.
0x01
0 = The divider is turned off., no clock will be provided to the CPU. This setting
should typically not be used, the CPU will be halted and a reset will be required
to restore operation.
1 = The input clock is divided by 1 to produce the CPU clock.
2 = The input clock is divided by 2 to produce the CPU clock.
3 = The input clock is divided by 3 to produce the CPU clock.
...
31 = The input clock is divided by 31 to produce the CPU clock.
7:5
-
Reserved. Read value is undefined, only zero should be written.
8
CCLKSEL
Selects the input clock for the CPU clock divider.
31:9
0
Sysclk is used as the input to the CPU clock divider.
1
The output of the Main PLL is used as the input to the CPU clock divider.
-
NA
0
Reserved. Read value is undefined, only zero should be written.
NA
3.3.3.3 USB Clock Selection register
The USBCLKSEL register controls selection of the clock used for the USB subsystem,
and also controls the division of the that clock before it is used by the USB. The output of
the selected PLL must be divided in order to bring the USB clock frequency to 48 MHz
with a 50% duty cycle. A divider allows obtaining the correct USB clock from any even
multiple of 48 MHz (i.e. any multiple of 96 MHz) within the PLL operating range.
Remark: A clock derived from the Internal RC oscillator should not be used to clock the
USB subsystem.
Table 21.
USB Clock Selection register (USBCLKSEL - address 0x400F C108) bit description
Bit
Symbol
4:0
USBDIV
Value
Description
Reset value
Selects the divide value for creating the USB clock from the selected PLL
output. Only the values shown below can produce even number multiples of 48
MHz from the PLL.
0
Warning: Improper setting of this value will result in incorrect operation of the
USB interface. Only the main oscillator in conjunction with either PLL0 or PLL1
can provide a clock that meets USB accuracy and jitter specifications.
Other values cannot produce the 48 MHz clock required for USB operation.
7:5
-
UM10562
User manual
0x0
The divider is turned off, no clock will be provided to the USB subsystem.
0x1
The selected output is divided by 1. The PLL output must be 48 MHz.
0x2
The selected output is divided by 2. The PLL output must be 96 MHz.
0x3
The selected output is divided by 3. The PLL output must be 144 MHz.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
32 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 21.
USB Clock Selection register (USBCLKSEL - address 0x400F C108) bit description
Bit
Symbol
9:8
USBSEL
31:10
Value
Description
Reset value
Selects the input clock for the USB clock divider.
0x0
Sysclk is used as the input to the USB clock divider. When this clock is
selected, the USB can be accessed by software but cannot perform USB
functions.
0x1
The output of the Main PLL is used as the input to the USB clock divider.
0x2
The output of the Alt PLL is used as the input to the USB clock divider.
0x3
Reserved, this setting should not be used.
-
0
Reserved. Read value is undefined, only zero should be written.
NA
3.3.3.4 Clock Source Selection register
The CLKSRCSEL register controls selection of the clock used for sysclk and PLL0.
Table 22.
Clock Source Selection register (CLKSRCSEL - address 0x400F C10C) bit description
Bit
Symbol
0
CLKSRC
31:1
-
Value Description
Reset value
Selects the clock source for sysclk and PLL0 as follows:
0
0
Selects the Internal RC oscillator as the sysclk and PLL0 clock source (default).
1
Selects the main oscillator as the sysclk and PLL0 clock source.
Reserved. Read value is undefined, only zero should be written.
NA
3.3.3.5 Peripheral Clock Selection register
The PCLKSEL register controls the base clock used for all APB peripherals. A clock
divider allows a range of frequencies to be used. Note that the peripheral clock rate
should not be set higher than the CPU clock rate.
Table 23.
Peripheral Clock Selection register (PCLKSEL - address 0x400F C1A8) bit description
Bit
Symbol
Description
Reset value
4:0
PCLKDIV
Selects the divide value for the clock used for all APB peripherals.
0x04
0 = The divider is turned off., no clock will be provided to APB peripherals.
1 = The input clock is divided by 1 to produce the APB peripheral clock.
2 = The input clock is divided by 2 to produce the APB peripheral clock.
3 = The input clock is divided by 3 to produce the APB peripheral clock.
4 = The input clock is divided by 4 to produce the APB peripheral clock.
Other values = not supported.
31:5
-
Reserved. Read value is undefined, only zero should be written.
NA
3.3.3.6 SPIFI Clock Selection register
The SPIFICLKSEL register controls selection of the clock used for the SPIFI, and also
controls the division of that clock before it is used by the SPIFI. If a PLL is used as the
SPIFI clock source, its output must be divided in order to bring the frequency down to one
that will work with the SPIFI. A 5-bit divider allows a range of frequencies to be used.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
33 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 24.
SPIFI Clock Selection register (SPIFICLKSEL - address 0x400F C1B4) bit description
Bit
Symbol
4:0
SPIFIDIV
Value
Description
Reset value
Selects the divide value for creating the SPIFI clock from the selected clock
0
source.
0 = The divider is turned off., no clock will be provided to the SPIFI.
1 = The input clock is divided by 1 to produce the SPIFI clock.
2 = The input clock is divided by 2 to produce the SPIFI clock.
3 = The input clock is divided by 3 to produce the SPIFI clock.
...
31 = The input clock is divided by 31 to produce the SPIFI clock.
7:5
-
9:8
SPIFISEL
31:10
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
NA
Selects the input clock for the USB clock divider.
0
0x0
Sysclk is used as the input to the SPIFI clock divider.
0x1
The output of the Main PLL is used as the input to the SPIFI clock divider.
0x2
The output of the Alt PLL is used as the input to the SPIFI clock divider.
0x3
Reserved, this setting should not be used.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
34 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.4 External interrupts
3.3.4.1 External Interrupt flag register
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the NVIC, which will
cause an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see
Section 3.3.4.2 “External Interrupt Mode register” and Section 3.3.4.3 “External Interrupt
Polarity register”.
For example, if a system wakes up from Power-down using low level on external interrupt
0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the
Power-down mode. If EINT0 bit is left set to 1, any subsequent attempt to invoke
Power-down mode will fail. The same goes for external interrupt handling.
More details on Power-down mode will be discussed in the following chapters.
Table 25.
External Interrupt Flag register (EXTINT - address 0x400F C140) bit description
Bit
Symbol Description
0
EINT0
Reset
value
In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its
active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and
the selected edge occurs on the pin.
0
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state.[1]
1
EINT1
In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its
active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and
the selected edge occurs on the pin.
0
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state.[1]
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
35 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 25.
External Interrupt Flag register (EXTINT - address 0x400F C140) bit description
Bit
Symbol Description
2
EINT2
Reset
value
In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its
active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and
the selected edge occurs on the pin.
0
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state.[1]
3
EINT3
In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its
active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and
the selected edge occurs on the pin.
0
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state.[1]
31:4 -
Reserved. Read value is undefined, only zero should be written.
[1]
NA
Example: e.g. if the EINTx is selected to be low level sensitive and low level is present on
corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the
pin becomes high.
3.3.4.2 External Interrupt Mode register
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see Section 7.3) and enabled in the appropriate
NVIC register) can cause interrupts from the External Interrupt function (though of course
pins selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt could be set by changing the mode and not
having the EXTINT cleared.
Table 26.
External Interrupt Mode register (EXTMODE - address 0x400F C148) bit description
Bit
Symbol
0
EXTMODE0
1
2
3
Value Description
0
Level sensitive.
1
Edge sensitive.
EXTMODE1
Level or edge sensitivity select for EINT1.
0
Level sensitive.
1
Edge sensitive.
EXTMODE2
Level or edge sensitivity select for EINT2.
0
Level sensitive.
1
Edge sensitive.
EXTMODE3
Level or edge sensitivity select for EINT3.
0
1
31:4 -
UM10562
User manual
Reset value
Level or edge sensitivity select for EINT0.
0
0
0
0
Level sensitive.
Edge sensitive.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
36 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.4.3 External Interrupt Polarity register
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are
selected for the EINT function (see Section 7.3) and enabled in the appropriate NVIC
register) can cause interrupts from the External Interrupt function (though of course pins
selected for other functions may cause interrupts from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the NVIC (state readable in the ISERn/ICERn registers), and should write
the corresponding 1 to EXTINT before enabling (initializing) or re-enabling the
interrupt. An extraneous interrupt could be set by changing the polarity and not
having the EXTINT cleared.
Table 27.
External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description
Bit
Symbol
0
EXTPOLAR0
1
2
Value Description
External interrupt polarity for EINT0.
0
Low-active or falling-edge sensitive (depending on EXTMODE0).
1
High-active or rising-edge sensitive (depending on EXTMODE0).
EXTPOLAR1
External interrupt polarity for EINT1.
0
Low-active or falling-edge sensitive (depending on EXTMODE1).
1
High-active or rising-edge sensitive (depending on EXTMODE1).
EXTPOLAR2
External interrupt polarity for EINT2.
0
1
3
31:4
EXTPOLAR3
-
UM10562
User manual
Reset value
0
0
0
Low-active or falling-edge sensitive (depending on EXTMODE2).
High-active or rising-edge sensitive (depending on EXTMODE2).
External interrupt polarity for EINT3.
0
Low-active or falling-edge sensitive (depending on EXTMODE3).
1
High-active or rising-edge sensitive (depending on EXTMODE3).
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
37 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.5 Device and Peripheral Reset
3.3.5.1 Reset Source Identification Register
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
Table 28.
Reset Source Identification register (RSID - address 0x400F C180) bit description
Bit
Symbol
Description
Reset
value
0
POR
Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But
See
if another Reset signal (e.g., External Reset) remains asserted after the POR signal is
description
negated, then its bit is set. This bit is not affected by any of the other sources of Reset.
1
EXTR
Assertion of the external RESET signal sets this bit. This bit is cleared only by software or
POR.
See
description
2
WDTR
This bit is set when the Watchdog Timer times out and the WDTRESET bit in the
Watchdog Mode Register is 1. This bit is cleared only by software or POR.
See
description
3
BODR
This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level
See
(typically 1.85 V under nominal room temperature conditions).
description
If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset
trip level and recovers, the BODR bit will be set to 1.
If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset
trip level and continues to decline to the level at which POR is asserted (nominally 1 V),
the BODR bit is cleared.
If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD
reset trip level, the BODR will be set to 1.
This bit is cleared only by software or POR.
Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if
the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.
4
SYSRESET This bit is set if the processor has been reset due to a system reset request. Setting the
SYSRESETREQ bit in the Cortex-M4 AIRCR register causes a chip reset. This bit is
cleared only by software or POR.
5
LOCKUP
31:6 -
UM10562
User manual
See
description
This bit is set if the processor has been reset due to a lockup of the CPU (see Cortex-M4
See
documentation for details). The lockup state causes a chip reset. This bit is cleared only by description
software or POR.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
38 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.5.2 Reset control register 0
Many peripherals may be given a hardware reset using the RSTCON0 register. Some
additional peripherals may be reset using the RSTCON1 register following.
Table 29.
Reset control register 0 (RSTCON0 - address 0x400F C1CC) bit description
Bit
Symbol
Description
Reset value
0
RSTLCD
LCD controller reset control bit.
0
1
RSTTIM0
Timer/Counter 0 reset control bit.
0
2
RSTTIM1
Timer/Counter 1 reset control bit.
0
3
RSTUART0
UART0 reset control bit.
0
4
RSTUART1
UART1 reset control bit.
0
5
RSTPWM0
PWM0 reset control bit.
0
6
RSTPWM1
PWM1 reset control bit.
0
7
RSTI2C0
The I2C0 interface reset control bit.
0
8
RSTUART4
UART4 reset control bit.
0
9
RSTRTC
RTC and Event Monitor/Recorder reset control bit. RTC reset is limited, see
Table 626 “Register overview: Real-Time Clock (base address 0x4002 4000)” for
details.
0
10
RSTSSP1
The SSP 1 interface reset control bit.
0
11
RSTEMC
External Memory Controller reset control bit.
0
12
RSTADC
A/D converter (ADC) reset control bit.
0
13
RSTCAN1
CAN Controller 1 reset control bit. Note: The CAN acceptance filter may be reset by
a separate bit in the RSTCON1 register.
0
14
RSTCAN2
CAN Controller 2 reset control bit. Note: The CAN acceptance filter may be reset by
a separate bit in the RSTCON1 register.
0
15
RSTGPIO
Reset control bit for GPIO, and GPIO interrupts. Note: IOCON may be reset by a
separate bit in the RSTCON1 register.
0
16
RSTSPIFI
SPI Flash Interface reset control bit.
0
17
RSTMCPWM
Motor Control PWM reset control bit.
0
18
RSTQEI
Quadrature Encoder Interface reset control bit.
0
19
RSTI2C1
The I2C1 interface reset control bit.
0
20
RSTSSP2
The SSP2 interface reset control bit.
0
21
RSTSSP0
The SSP0 interface reset control bit.
0
22
RSTTIM2
Timer 2 reset control bit.
0
23
RSTTIM3
Timer 3 reset control bit.
0
24
RSTUART2
UART 2 reset control bit.
0
25
RSTUART3
UART 3 reset control bit.
0
26
RSTI2C2
I2C interface 2 reset control bit.
0
27
RSTI2S
I2S interface reset control bit.
0
28
RSTSDC
SD Card interface reset control bit.
0
29
RSTGPDMA
GPDMA function reset control bit.
0
30
RSTENET
Ethernet block reset control bit.
0
31
RSTUSB
USB interface reset control bit.
0
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
39 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.5.3 Reset control register 1
Some additional peripherals may be given a hardware reset using the RSTCON1 register,
as shown in Table 30 below.
Table 30.
Reset control register 1 (RSTCON1 - address 0x400F C1D0) bit description
Bit
Symbol
Description
0
RSTIOCON
Reset control bit for the IOCON registers.
0
1
RSTDAC
D/A converter (DAC) reset control bit.
0
2
RSTCANACC
CAN acceptance filter reset control bit.
31:3
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
40 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.6 EMC delay control and calibration
3.3.6.1 EMC Delay Control register
The EMCDLYCTL register controls on-chip programmable delays that can b used to fine
tune timing to external SDRAM memories. Delays can be configured in increments of
approximately 250 picoseconds up to a maximum of roughly 7.75 ns. See Section 9.5.6
for an overview of the programmable delays. Figure 5 shows the detailed connections of
the programmable delays. Table 31 shows the bit assignments in EMCDLYCTL.
100811
programmable delay block
4 ns
2 ns
1 ns
0.5 ns
0.25 ns
1
1
1
1
1
0
0
0
0
0
emc_clk
EMCCLKDELAY
EMCDELAYCTL[4:0]
CLKOUT[0] or CLKOUT[1]
programmable delay block
FBCLKIN
programmable delay block
EMC_CLKOUT[0]
programmable delay block
EMC_CLKOUT[1]
EMCDELAYCTL[12:8]
CLKOUT[0]
EMCDELAYCTL[20:16]
CLKOUT[1]
EMCDELAYCTL[28:24]
Fig 5.
EMC programmable delays
Table 31.
Delay Control register (EMCDLYCTL - 0x400F C1DC) bit description
Bit
Symbol
Description
Reset Value
4:0
CMDDLY
Programmable delay value for EMC outputs in command delayed mode. See
Section 9.13.6. The delay amount is roughly (CMDDLY+1) * 250 picoseconds.
0x10
This field applies only when the command delayed read strategy is selected in the
EMCDynamicReadConfig register. In this mode, all control outputs from the EMC are
delayed, but the output clock is not. Delaying the control outputs changes dynamic
characteristics defined in the device data sheet.
7:5
-
Reserved. Read value is undefined, only zero should be written.
12:8
FBCLKDLY
Programmable delay value for the feedback clock that controls input data sampling.
See Section 9.5.3. The delay amount is roughly (FBCLKDLY+1) * 250 picoseconds.
15:13 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
0x02
NA
© NXP B.V. 2012. All rights reserved.
41 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 31.
Bit
Delay Control register (EMCDLYCTL - 0x400F C1DC) bit description
Symbol
Description
Reset Value
20:16 CLKOUT0DLY Programmable delay value for the CLKOUT0 output. This would typically be used in
clock delayed mode. See Section 9.13.6 The delay amount is roughly
(CLKOUT0DLY+1) * 250 picoseconds. Delaying the clock output changes dynamic
characteristics defined in the device data sheet.
23:21 -
Reserved. Read value is undefined, only zero should be written.
NA
28:24 CLKOUT1DLY Programmable delay value for the CLKOUT1 output. This would typically be used in
clock delayed mode. See Section 9.13.6 The delay amount is roughly
(CLKOUT1DLY+1) * 250 picoseconds.
31:29 -
0
Reserved. Read value is undefined, only zero should be written.
0
NA
3.3.6.2 EMC Calibration register
The EMCCAL register allows calibration of the EMC programmable delays by providing a
real-time representation of the value of those delays. Delay settings that are in use in the
application can be calibrated to compensate for intrinsic differences between devices, and
for changes in ambient conditions. Figure 6 below shows the delay calibration circuit.
Table 32 shows the bit assignments in EMCCAL.
EMCCAL register
31
16
(reserved)
15
14
Done Start
13
8 7
(reserved)
0
CALVALUE
clear
enable
control
8-bit counter
overflow
clear
enable
5-bit counter
~50 MHz
(varies with process,
voltage, and temperature)
ring
oscillator
IRC reference clock
(factory calibrated to 12 MHz)
100813
Fig 6.
EMC delay calibration
Table 32.
EMC Calibration register (EMCCAL - 0x400F C1E0) bit description
Bit
Symbol
7:0
CALVALUE Returns the count of the approximately 50 MHz ring oscillator that occur during 32 clocks
of the IRC oscillator. This represents the composite effect of processing variation,
internal regulator supply voltage, and ambient temperature.
13:8
-
Reserved. Read value is undefined, only zero should be written.
14
START
Start control bit for the EMC calibration counter. Writing a 1 to this bit begins the
measurement process. This bit is cleared automatically when the measurement is
complete.
0
15
DONE
Measurement completion flag. this bit is set when a calibration measurement is
completed. This bit is cleared automatically when the START bit is set.
0
31:16 -
UM10562
User manual
Description
Reset Value
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
NA
© NXP B.V. 2012. All rights reserved.
42 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Procedure for calibrating programmable delays
1. Write 1 to the START bit of the EMCCAL register.
2. Wait until the DONE bit of the same register becomes 1. Other operations can be
done during this time, the calibration requires 32 clocks of the 12 MHz IRC clock, or
about 2.7 microseconds.
3. Read the calibration value from the bottom 8 bits of the EMCCAL register. A typical
value at room temperature is 0x86.
4. Adjust one or more programmable delays if needed based on the calibration result.
The calibration procedure should typically be repeated periodically, depending on how
rapidly ambient conditions may change in the application environment.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
43 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.7 Miscellaneous system control registers
3.3.7.1 System Controls and Status register
The SCS register contains special control and status bits related to various aspects of chip
operation. These functions are described in Table 33.
Several of these bits apply to the main oscillator. Since chip operation always begins
using the Internal RC Oscillator, and the main oscillator may not be used at all in some
applications, it will only be started by software request. This is accomplished by setting the
OSCEN bit in the SCS register, as described in Table 3-13. The main oscillator provides a
status flag (the OSCSTAT bit in the SCS register) so that software can determine when
the oscillator is running and stable. At that point, software can control switching to the
main oscillator as a clock source. Prior to starting the main oscillator, a frequency range
must be selected by configuring the OSCRANGE bit in the SCS register.
Table 33.
System Controls and Status register (SCS - address 0x400F C1A0) bit description
Bit
Function
0
EMCSC
1
2
Value Description
EMC Shift Control. Controls how addresses are output on the EMC address
pins for static memories. Also see Section 9.9 in the EMC chapter.
0
Static memory addresses are shifted to match the data bus width. For
example, when accessing a 32-bit wide data bus, the address is shifted right
2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this
device is connected to address bit 0 of the memory device, thus simplifying
memory connections. This also makes a larger memory address range
possible, because additional upper address bits can appear on the higher
address pins due to the shift.
1
Static memory addresses are always output as byte addresses regardless
of the data bus width. For example, when word data is accessed on a 32-bit
bus, address bits 1 and 0 will always be 0. In this mode, one or both lower
address bits may not be connected to memories that are part of a bus that is
wider than 8 bits. This mode matches the operation of LPC23xx and
LPC24xx devices.
EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see
Section 9.8 in the EMC chapter.
EMCRD
0
Both EMC resets are asserted when any type of chip reset event occurs. In
this mode, all registers and functions of the EMC are initialized upon any
reset condition.
1
Many portions of the EMC are only reset by a power-on or brown-out event,
in order to allow the EMC to retain its state through a warm reset (external
reset or watchdog reset). If the EMC is configured correctly, auto-refresh
can be maintained through a warm reset.
EMCBC
UM10562
User manual
Access Reset
value
External Memory Controller burst control. Also see Section 9.10 in the EMC
chapter.
0
Burst enabled.
1
Burst disabled. This mode can be used to prevent multiple sequential
accesses to memory mapped I/O devices connected to EMC static memory
chip selects. These unrequested accesses can cause issues with some I/O
devices.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
R/W
1
R/W
0
R/W
0
© NXP B.V. 2012. All rights reserved.
44 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 33.
System Controls and Status register (SCS - address 0x400F C1A0) bit description
Bit
Function
3
MCIPWRAL
4
0
SD_PWR is active low (inverted output of the SD Card interface block).
1
SD_PWR is active high (follows the output of the SD Card interface block).
Main oscillator range select.
0
The frequency range of the main oscillator is 1 MHz to 20 MHz.
1
The frequency range of the main oscillator is 15 MHz to 25 MHz.
OSCEN
6
Main oscillator enable.
0
The main oscillator is disabled.
1
The main oscillator is enabled, and will start up if the correct external
circuitry is connected to the XTAL1 and XTAL2 pins.
OSCSTAT
31:7
-
Access Reset
value
MCIPWR Active Level[1]. Selects the active level of the SD card interface
signal SD_PWR.
OSCRS
5
[1]
Value Description
Main oscillator status.
0
The main oscillator is not ready to be used as a clock source.
1
The main oscillator is ready to be used as a clock source. The main
oscillator must be enabled via the OSCEN bit.
Reserved. Read value is undefined, only zero should be written.
R/W
1
R/W
0
R/W
0
RO
0
-
NA
The state of this bit is preserved through a software reset, and only a POR or a BOD event will reset it to its default value.
3.3.7.2 LCD Configuration register
The LCD_CFG register controls the prescaling of the clock used for LCD data generation.
The contents of the LCD_CFG register are described in Table 34.
Table 34.
LCD Configuration register (LCD_CFG, address - 0x400F C1B8) bit description
Bits
Symbol
Description
4:0
CLKDIV
LCD panel clock prescaler selection. The value in the this register plus 1 is used to divide the
selected input clock (see the CLKSEL bit in the LCD_POL register), to produce the panel clock.
0
31:5
-
Reserved. Read value is undefined, only zero should be written.
-
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
45 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.7.3 CAN Sleep Clear register
This register provides the current sleep state of the two CAN channels and provides a
means to restore the clocks to that channel following wake-up. Refer to Section 20.8.2
“Sleep mode” for more information on the CAN sleep feature.
Table 35.
CAN Sleep Clear register (CANSLEEPCLR - address 0x400F C110) bit description
Bit
Symbol
Function
0
-
Reserved. Read value is undefined, only zero should be written.
Reset Value
1
CAN1SLEEP
Sleep status and control for CAN channel 1.
NA
0
Read: when 1, indicates that CAN channel 1 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 1.
2
CAN2SLEEP
Sleep status and control for CAN channel 2.
0
Read: when 1, indicates that CAN channel 2 is in the sleep mode.
Write: writing a 1 causes clocks to be restored to CAN channel 2.
31:3
-
Reserved. Read value is undefined, only zero should be written.
NA
3.3.7.4 CAN Wake-up Flags register
This register provides the wake-up status for the two CAN channels and allows clearing
wake-up events. Refer to Section 20.8.2 “Sleep mode” for more information on the CAN
sleep feature.
Table 36.
CAN Wake-up Flags register (CANWAKEFLAGS - address 0x400F C114) bit description
Bit
Symbol
Function
0
-
Reserved. Read value is undefined, only zero should be written.
CAN1WAKE
Wake-up status for CAN channel 1.
1
Reset Value
NA
0
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 1.
Write: writing a 1 clears this bit.
2
CAN2WAKE
Wake-up status for CAN channel 2.
0
Read: when 1, indicates that a falling edge has occurred on the receive data line of
CAN channel 2.
Write: writing a 1 clears this bit.
31:3
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
46 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.7.5 USB Interrupt Status Register
The USB OTG controller has seven interrupt lines. Only the first three interrupts
(USB_INT_REQ_LP, USB_INT_REQ_HP, and USB_INT_REQ_HP) and the
USB_NEED_CLK signal are used for the device controller. The interrupt lines are ORed
together to a single channel of the vectored interrupt controller. This register allows
software to determine their status with a single read operation.
Table 37.
USB Interrupt Status register - (USBINTST - address 0x400F C1C0) bit description
Bit
Symbol
Description
0
USB_INT_REQ_LP
Low priority interrupt line status. This bit is read-only.
0
1
USB_INT_REQ_HP
High priority interrupt line status. This bit is read-only.
0
2
USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only.
0
3
USB_HOST_INT
USB host interrupt line status. This bit is read-only.
0
4
USB_ATX_INT
External ATX interrupt line status. This bit is read-only.
0
5
USB_OTG_INT
OTG interrupt line status. This bit is read-only.
0
6
USB_I2C_INT
I2C
7
-
Reserved. Read value is undefined, only zero should be written.
8
USB_NEED_CLK
USB need clock indicator. This bit is read-only.
This bit is set to 1 when USB activity or a change of state on the USB data pins is
detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once
USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been
received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred.
A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB
bus is selected to wake up the part from the Power-down mode (see Section 3.12.8
“Wake-up from Reduced Power Modes” for details). Also see Section 3.10.3 “PLLs
and Power-down mode” and Section 3.3.2.2 “Power Control for Peripherals
registers” for considerations about the PLL and invoking the Power-down mode. This
bit is read-only.
30:9
-
Reserved. Read value is undefined, only zero should be written.
31
EN_USB_INTS
Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed
output of the USB interrupt lines.
UM10562
User manual
Reset
Value
module interrupt line status. This bit is read-only.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
1
NA
1
© NXP B.V. 2012. All rights reserved.
47 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.3.7.6 DMA Request Select register
DMACReqSel is a read/write register that allows selecting between potential DMA
requests for DMA inputs 0 through 7 and 10 through 15. Table 38 shows the bit
assignments of the DMACReqSel Register.
Table 38.
DMA Request Select register bit description
Bit
Name
Description
0
DMASEL00
Selects the DMA request for GPDMA input 0:
0 - (unused)
Reset
value
0
1 - Timer 0 match 0 is selected.
1
DMASEL01
Selects the DMA request for GPDMA input 1:
0 - SD card interface is selected.
0
1 - Timer 0 match 1 is selected.
2
DMASEL02
Selects the DMA request for GPDMA input 2:
0 - SSP0 transmit is selected.
0
1 - Timer 1 match 0 is selected.
3
DMASEL03
Selects the DMA request for GPDMA input 3:
0 - SSP0 receive is selected.
0
1 - Timer 1 match 1 is selected.
4
DMASEL04
Selects the DMA request for GPDMA input 4:
0 - SSP1 transmit is selected.
0
1 - Timer 2 match 0 is selected.
5
DMASEL05
Selects the DMA request for GPDMA input 5:
0 - SSP1 receive is selected.
0
1 - Timer 2 match 1 is selected.
6
DMASEL06
0
Selects the DMA request for GPDMA input 6:
0 - SSP2 transmit is selected.
1 - I2S channel 0 is selected.
7
DMASEL07
0
Selects the DMA request for GPDMA input 7:
0 - SSP2 receive is selected.
1 - I2S channel 1 is selected.
9:8
-
Reserved. Read value is undefined, only zero should be written.
-
10
DMASEL10
Selects the DMA request for GPDMA input 10:
0 - UART0 transmit is selected.
0
1 - UART3 transmit is selected.
11
DMASEL11
Selects the DMA request for GPDMA input 11:
0 - UART0 receive is selected.
0
1 - UART3 receive is selected.
12
DMASEL12
Selects the DMA request for GPDMA input 12:
0 - UART1 transmit is selected.
0
1 - UART4 transmit is selected.
13
DMASEL13
Selects the DMA request for GPDMA input 13:
0 - UART1 receive is selected.
0
1 - UART4 receive is selected.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
48 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 38.
DMA Request Select register bit description …continued
Bit
Name
Description
14
DMASEL14
Selects the DMA request for GPDMA input 14:
0 - UART2 transmit is selected.
Reset
value
0
1 - Timer 3 match 0 is selected.
15
DMASEL15
Selects the DMA request for GPDMA input 15:
0 - UART2 receive is selected.
0
1 - Timer 3 match 1 is selected.
31:16 -
3.3.7.6.1
Reserved. Read value is undefined, only zero should be written.
-
Timer DMA requests
Timer DMA requests are generated by the timer when the timer value matches the related
Match register (see Section 24.6.12). If the DMA controller is configured so that a timer
DMA request is selected as an input to a DMA channel, and the DMA channel is enabled,
the DMA controller will act on that request.
3.3.7.7 Clock Output Configuration register
The CLKOUTCFG register controls the selection of the internal clock that appears on the
CLKOUT pin and allows dividing the clock by an integer value up to 16. The divider can be
used to produce a system clock that is related to one of the on-chip clocks. For most clock
sources, the division may be by 1. When the CPU clock is selected and is higher than
approximately 50 MHz, the output must be divided in order to bring the frequency within
the ability of the pin to switch with reasonable logic levels. If a clock is selected that is not
running, there will be no signal on CLKOUT.
Note: The CLKOUT multiplexer is designed to switch cleanly, without glitches, between
the possible clock sources. The divider is also designed to allow changing the divide value
without glitches.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
49 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 39.
Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description
Bit
Symbol
Description
Reset value
3:0
CLKOUTSEL
Selects the clock source for the CLKOUT function.
0
0x0 = Selects the CPU clock as the CLKOUT source.
0x1 = Selects the main oscillator as the CLKOUT source.
0x2 = Selects the Internal RC oscillator as the CLKOUT source.
0x3 = Selects the USB clock as the CLKOUT source.
0x4 = Selects the RTC oscillator as the CLKOUT source.
0x5 = Selects the SPIFI clock as the CLKOUT source.
0x6 = Selects the Watchdog oscillator as the CLKOUT source.
Other settings are reserved. Do not use.
7:4
CLKOUTDIV
Integer value to divide the output clock by, minus one.
0
0x0 = Clock is divided by 1.
0x1 = Clock is divided by 2.
0x2 = Clock is divided by 3.
...
0xF = Clock is divided by 16.
8
CLKOUT_EN
9
CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when
CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed
being stopped.
31:10
-
UM10562
User manual
CLKOUT enable control, allows switching the CLKOUT source without glitches.
Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
NA
© NXP B.V. 2012. All rights reserved.
50 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.4 Chip reset
Reset has 6 sources: the RESET pin, Watchdog Reset, Power On Reset (POR), Brown
Out Detect (BOD), system reset, and lockup.
The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once
the operating voltage attains a usable level, starts the wake-up timer (see description in
Section 3.13 “Wake-up timer” in this chapter), causing reset to remain asserted until the
external Reset is de-asserted, the oscillator is running, a fixed number of clocks have
passed, and the flash controller has completed its initialization. The reset logic is shown in
the following block diagram (see Figure 7).
lockup
external
reset
POR
system
reset
wake-up
complete
reset to on-chip
circuitry
clr
Q
set
to wake-up
logic
BOD
watchdog
reset
Fig 7.
120601
Reset block diagram
On the assertion of a reset source external to the CPU (POR, BOD reset, External reset,
and Watchdog reset), the IRC starts up. After the IRC-start-up time (maximum of 60 s on
power-up) and after the IRC provides a stable clock output, the reset signal is latched and
synchronized on the IRC clock. Then the following two sequences start simultaneously:
1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is
de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times
out. The boot code performs the boot tasks and may jump to the flash. If the flash is
not ready to access, the Flash Accelerator will insert wait cycles until the flash is
ready.
2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is
de-asserted. The flash wakeup-timer generates the 100 s flash start-up time. Once it
times out, the flash initialization sequence is started, which takes about 250 cycles.
When it’s done, the Flash Accelerator will be granted access to the flash.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Figure 8 shows an example of the relationship between the RESET, the IRC, and the
processor status when the device starts up after reset. See Section 3.8.2 “Main oscillator”
for start-up of the main oscillator if selected by the user code.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
51 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
IRC
starts
IRC
stable
IRC status
RESET
VDD(REG)(3V3)
valid threshold
GND
60 μs
1 μs; IRC stability count
boot time
supply ramp-up
time
boot code executing
user code
processor status
boot code
execution
finishes;
user code starts
Fig 8.
Example of start-up after reset
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
52 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.5 Peripheral reset control
Most peripheral functions can have a hardware reset initiated by software by setting
appropriate bits in the RSTCON0 and RSTCON1 registers. Software must clear the
RSTCON register after this in order to allow the peripheral to function. A peripheral
remains in a hardware reset state as long as the corresponding bit in RSTCON = 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
53 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.6 Brown-out detection
A Brown-Out Detector (BOD) is included that provides 2-stage monitoring of the voltage
on the VDD(REG)(3V3) pins. If this voltage falls below the BOD interrupt trip level (typically
2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
the Raw Interrupt Status Register.
The second stage of low-voltage detection asserts Reset to inactivate the device when the
voltage on the VDD(REG)(3V3) pins falls below the BOD reset trip level (typically 1.85 V
under nominal room temperature conditions). This Reset prevents alteration of the flash
as operation of the various elements of the chip would otherwise become unreliable due
to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the
Power-On Reset circuitry maintains the overall Reset.
Both the BOD reset interrupt level and the BOD reset trip level thresholds include some
hysteresis. In normal operation, this hysteresis allows the BOD reset interrupt level
detection to reliably interrupt, or a regularly-executed event loop to sense the condition.
But when Brown-Out Detection is enabled to bring the device out of Power-down mode
(which is itself not a guaranteed operation -- see Section 3.3.2.1 “Power Mode Control
register”), the supply voltage may recover from a transient before the wake-up timer has
completed its delay. In this case, the net result of the transient BOD is that the part wakes
up and continues operation after the instructions that set Power-down mode, without any
interrupt occurring and with the BOD bit in the RSID being 0. Since all other wake-up
conditions have latching flags (see Section 3.3.4.1 “External Interrupt flag register” and
Section 29.6.2), a wake-up of this type, without any apparent cause, can be assumed to
be a Brown-Out that was too short to be fully captured.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
54 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.7 External interrupt inputs
Four External Interrupt Inputs are included as selectable pin functions. The logic of an
individual external interrupt is represented in Figure 9. In addition, external interrupts have
the ability to wake up the CPU from Power-down mode. Refer to Section 3.12.8 “Wake-up
from Reduced Power Modes” for details.
EINTi interrupt enable
EINTi pin
EINTi to wake-up logic
GLITCH
FILTER
Interrupt flag
(one bit of EXTINT)
EXTPOLARi
S
1
EXTMODEi
D
S
Q
S
Q
R
R
PCLK
PCLK
internal reset
write to EXTINTi
Fig 9.
Q
to interrupt
controller
APB read
of EXTINTi
120601
External interrupt logic
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
55 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.7.1 Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level
and edge sensitivity parameters.
Table 40.
External Interrupt registers
Name
Description
Access
Reset
value[1]
Address
EXTINT
The External Interrupt Flag Register contains interrupt flags for EINT0,
EINT1, EINT2 and EINT3. See Table 25.
R/W
0x00
0x400F C140
EXTMODE
The External Interrupt Mode Register controls whether each pin is edgeor level-sensitive. See Table 26.
R/W
0x00
0x400F C148
EXTPOLAR
The External Interrupt Polarity Register controls which level or edge on
each pin will cause an interrupt. See Table 27.
R/W
0x00
0x400F C14C
[1]
UM10562
User manual
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
56 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.8 Oscillators
Three independent oscillators are included. These are the Main Oscillator, the Internal RC
Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose
as required in a particular application. This can be seen in Figure 4.
Following Reset, the device will operate from the Internal RC Oscillator until switched by
software. This allows systems to operate without any external crystal, and allows the boot
loader code to operate at a known frequency.
3.8.1 Internal RC oscillator
The Internal RC Oscillator (IRC) may be used as the clock that drives PLL0 and
subsequently the CPU. The precision of the IRC does not allow for use of the USB
interface, which requires a much more precise time base in order to comply with the USB
specification (only the main oscillator can meet that specification). Also, the IRC should
not be used with the CAN1/2 block if the CAN baud rate is higher than 100 kbit/s.The IRC
frequency is 12 MHz, factory trimmed to within ±1% accuracy.
Upon power-up or any chip reset, the IRC is used as the clock source. Software may later
switch to one of the other available clock sources.
3.8.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using
PLL0. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency
can be boosted to a higher frequency, up to the maximum CPU operating frequency, by
the Main PLL (PLL0). The oscillator output is called OSC_CLK. The clock selected as the
PLL0 input is PLLCLKIN and the ARM processor clock frequency is referred to as CCLK
for purposes of rate equations, etc. elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL0 is active and connected. Refer
to Section 3.10 for details.
The on-board oscillator can operate in one of two modes: slave mode and oscillation
mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(CC in Figure 10, drawing a), with an amplitude between 200 mVrms and 1000 mVrms.
This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4
V. The XTAL2 pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 10,
drawings b and c, and in Table 41 and Table 42. Since the feedback resistance is
integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected
externally in case of fundamental mode oscillation (the fundamental frequency is
represented by L, CL and RS). Capacitance CP in Figure 10, drawing c, represents the
parallel package capacitance and should not be larger than 7 pF. Parameters FC, CL, RS
and CP are supplied by the crystal manufacturer.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
57 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Microcontroller
XTAL1
Microcontroller
XTAL2
XTAL1
XTAL2
L
<=>
CC
CL
CP
Xtal
Clock
CX1
CX2
a)
RS
b)
c)
Fig 10. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
crystal model used for CX1/X2 evaluation
Table 41.
Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode (OSCRANGE = 0, see Table 33)
Fundamental oscillation
frequency FOSC
1 MHz - 5 MHz
5 MHz - 10 MHz
10 MHz - 15 MHz
15 MHz - 20 MHz
Table 42.
15 MHz - 20 MHz
20 MHz - 25 MHz
User manual
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
10 pF
< 300 
18 pF, 18 pF
20 pF
< 300 
39 pF, 39 pF
30 pF
< 300 
57 pF, 57 pF
10 pF
< 300 
18 pF, 18 pF
20 pF
< 200 
39 pF, 39 pF
30 pF
< 100 
57 pF, 57 pF
10 pF
< 160 
18 pF, 18 pF
20 pF
< 60 
39 pF, 39 pF
10 pF
< 80 
18 pF, 18 pF
Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode (OSCRANGE = 1, see Table 33)
Fundamental oscillation
frequency FOSC
UM10562
Crystal load
capacitance CL
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
10 pF
< 180 
18 pF, 18 pF
20 pF
< 100 
39 pF, 39 pF
10 pF
< 160 
18 pF, 18 pF
20 pF
< 80 
39 pF, 39 pF
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
58 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.8.2.1 Main oscillator startup
Since chip operation always begins using the Internal RC Oscillator, and the main
oscillator may not be used at all in some applications, it will only be started by software
request. This is accomplished by setting the OSCEN bit in the SCS register, as described
in Table 33. The main oscillator provides a status flag (the OSCSTAT bit in the SCS
register) so that software can determine when the oscillator is running and stable. At that
point, software can control switching to the main oscillator as a clock source. Prior to
starting the main oscillator, a frequency range must be selected by configuring the
OSCRANGE bit in the SCS register.
3.8.3 RTC oscillator
The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can
be output on the CLKOUT pin in order to allow trimming the RTC oscillator without
interference from a probe.
3.8.4 Watchdog oscillator
The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the
Watchdog Timer that is always running if the Watchdog Timer is enabled. The Watchdog
oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency.
In order to allow Watchdog Timer operation with minimum power consumption, which can
be important in reduced power modes, the Watchdog oscillator frequency is not tightly
controlled. The Watchdog oscillator frequency will vary over temperature and power
supply within a particular part, and may vary by processing across different parts. This
variation should be taken into account when determining Watchdog reload values.
Within a particular part, temperature and power supply variations can produce up to a
±17% frequency variation. Frequency variation between devices under the same
operating conditions can be up to ±30%.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
59 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.9 Clock source selection multiplexer
Two clock sources may be chosen to drive the system clock (sysclk) and PLL0. These are
the Internal RC oscillator and the main oscillator.
The clock source selection should only be changed safely when PLL0 is not connected.
For a detailed description of how to change the clock source in a system using PLL0 see
Section 3.10.6 “PLL configuration sequence”.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
60 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.10 PLL0 and PLL1 (Phase Locked Loops)
PLL0 (also called the Main PLL) and PLL1 (also called the Alt PLL) are functionally
identical, but have somewhat different input possibilities and output connections. These
possibilities are shown in Figure 4. The Main PLL can receive its input from either the IRC
or the Main Oscillator, and can potentially be used to provide the clocks to nearly
everything on the device. The Alt PLL receives its input only from the main oscillator and
is intended to be used as an alternate source of clocking to the USB and the SPIFI. This
peripheral has timing needs that may not always be filled by the Main PLL.
Both PLLs are disabled and powered off on reset. If the Alt PLL is left disabled, the USB
and SPIFI clocks can be supplied by PLL0 if everything is set up to provide 48 MHz to the
USB clock and the desired SPIFI clock through that route. The source for each clock must
be selected via the CLKSEL registers (see Section 3.11), and can be further reduced by
clock dividers as needed.
PLL activation is controlled via the PLLCON registers. PLL multiplier and divider values
are controlled by the PLLCFG registers. The PLLCFG registers are protected in order to
prevent accidental deactivation of PLLs or accidental alteration PLL operating
parameters. The protection is accomplished by a feed sequence similar to that of the
Watchdog Timer. Details are provided in the descriptions of the PLLFEED registers.
PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only
the Main PLL is used, then its output frequency must be an integer multiple of all other
clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring
an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled
Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional
dividers to bring the output down to the desired frequencies. The minimum output divider
value is 2, insuring that the output of the PLLs have a 50% duty cycle. Figure 11 shows a
block diagram of PLL internal connections.
If the USB is used, the possibilities for the CPU clock and other clocks will be limited by
the requirements that the frequency be precise and very low jitter, and that the PLL0
output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the
operating range of the PLL FCCO are 192 and 288 MHz. Also, only the main oscillator in
conjunction with the PLL can meet the precision and jitter specifications for USB. It is due
to these limitations that the Alt PLL is provided.
The Alt PLL accepts an input clock frequency from the main oscillator in the range of
10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up
to a multiple of 48 MHz (192 or 288 MHz as described above). The Alt PLL can also
provide the clock to the SPIFI through a separate divider, if needed.
3.10.1 PLL and startup/boot code interaction
When there is no valid user code (determined by the checksum word) in the user flash or
the ISP enable pin (P2[10]) is pulled low on startup, the ISP mode will be entered and the
boot code will setup the Main PLL with the IRC. Therefore it can not be assumed that the
Main PLL is disabled when the user opens a debug session to debug the application
code. The user startup code must follow the steps described in this chapter to disconnect
the Main PLL.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
61 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.10.2 PLL register description
The PLLs are controlled by the registers shown in Table 43. More detailed descriptions
follow.
Warning: Improper setting of PLL values may result in incorrect operation of the
USB subsystem!
Table 43.
PLL1 registers
Generic
Name
Description
PLLCON
PLL Control Register. Holding register for updating PLL
control bits. Values written to this register do not take
effect until a valid PLL feed sequence has taken place.
R/W
0
PLL0CON - 0x400F C080
PLL1CON - 0x400F C0A0
10
PLLCFG
PLL Configuration Register. Holding register for
updating PLL configuration values. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place.
R/W
0
PLL0CFG - 0x400F C084
PLL1CFG - 0x400F C0A4
11
PLLSTAT PLL Status Register. Read-back register for PLL control
and configuration information. If PLLCON or PLLCFG
have been written to, but a PLL feed sequence has not
yet occurred, they will not reflect the current PLL state.
Reading this register provides the actual values
controlling PLL, as well as PLL status.
RO
0
PLL0STAT - 0x400F C088
PLL1STAT - 0x400F C0A8
12
PLLFEED PLL Feed Register. This register enables loading of PLL
control and configuration information from the PLLCON
and PLLCFG registers into the shadow registers that
actually affect PLL operation.
WO
NA
PLL0FEED - 0x400F C08C
PLL1FEED - 0x400F C0AC
13
Access
[1]
Reset PLLn Register Name and
value[1] Address
Table
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
PLOCK
PLLSTAT[10]
PLL input
clock
Phase
Detector
CurrentControlled
Oscillator
Fcco
Divide by 2P
PLL output
clock
PSEL
PLLSTAT[6:5]
Divide by M
MSEL
PLLSTAT[4:0]
120601
Fig 11. PLL0 and PLL1 block diagram
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
62 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.10.3 PLLs and Power-down mode
Power-down mode automatically turns off and disconnects activated PLLs, while
subsequent wake-up from Power-down mode does not automatically restore PLL settings.
This must be done in software. Typically, a routine to activate a PLL, wait for lock, and
then select the PLL can be called at the beginning of any interrupt service routine that
might be called due to the wake-up.
If activity on the USB data lines is not selected to wake the microcontroller from
Power-down mode (see Section 3.12.8 for details of wake up from reduced modes), both
the Main PLL (PLL0) and the Alt PLL (PLL1) will be automatically be turned off and
disconnected when Power-down mode is invoked, as described above. However, if the
USB activity interrupt is enabled and USB_NEED_CLK = 1 (see Table 253 for a
description of USB_NEED_CLK), it is not possible to go into Power-down mode and any
attempt to set the PD bit will fail, leaving the PLLs in the current state.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
63 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.10.4 PLL frequency calculation
Equations for both the Main and Alt PLLs use the following parameters:
Table 44.
Elements determining PLL frequency
Element
Description
pll_in_clk
the frequency of the input to the PLL
FCCO
the frequency of the PLL current controlled oscillator
pll_out_clk
the PLL output frequency
M
PLL Multiplier value from the MSEL bits in the PLLCFG register
P
PLL Divider value from the PSEL bits in the PLLCFG register
The PLL output frequency (when the PLL is active and locked) is given by:
pll_out_clk = M  pll_in_clk
- or -
pll_out_clk = FCCO / (2  P)
The CCO frequency can be computed as:
FCCO = pll_out_clk  2  P
- or -
FCCO = pll_in_clk  M  2  P
The PLL inputs and settings must meet the following criteria:
• M is in the range of 1 to 32.
• P is one of 1, 2, 4, 8.
• pll_in_clk is in the range of 10 MHz to 25 MHz.
• FCCO is in the range of 156 MHz to 320 MHz.
• pll_out_clk is in the range of 9.75 MHz to 160 MHz.
3.10.5 Procedure for determining PLL settings
In general, PLL configuration values may be found as follows:
1. Based on the desired PLL output frequency, choose an oscillator frequency (FOSC). If
the USB interface is to be used, an external crystal of either 12 MHz, 16 MHz, or 24
MHz must be provided. 12 MHz is recommended for this purpose in order to save
power and have more flexibility with PLL settings.
2. If the USB interface is used in the system, and if a PLL output of 96 MHz or 144 MHz
can provide the desired CPU clock frequency, it is probably possible to use only PLL0.
3. Calculate the value of M to configure the MSEL1 bits to obtain the desired PLL output
frequency. M = pll_out_clk / pll_in_clk. The value written to the MSEL bits in the
PLLCFG register is M  1 (or see Table 45). This is done for both PLLs if they are both
used.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
64 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
4. Find a value for P to configure the PSEL bits, such that FCCO is within its defined
operating frequency limits of 156 MHz to 320 MHz. FCCO is calculated using FCCO =
pll_out_clk  2  P. The value written to the PSEL bits in PLLCFG can be found in
Table 46.
Table 45.
PLL Multiplier values
Value of M
UM10562
User manual
MSEL Bits
MSEL hex
(PLLCFG bits [4:0])
1
00000
0
2
00001
0x01
3
00010
0x02
4
00011
0x03
5
00100
0x04
6
00101
0x05
7
00110
0x06
8
00111
0x07
9
01000
0x08
10
01001
0x09
11
01010
0x0A
12
01011
0x0B
13
01100
0x0C
14
01101
0x0D
15
01110
0x0E
16
01111
0x0F
17
10000
0x10
18
10001
0x11
19
10010
0x12
20
10011
0x13
21
10100
0x14
22
10101
0x15
23
10110
0x16
24
10111
0x17
25
11000
0x18
26
11001
0x19
27
11010
0x1A
28
11011
0x1B
29
11100
0x1C
30
11101
0x1D
31
11110
0x1E
32
11111
0x1F
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
65 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Table 46.
PLL Divider values
Value of P
PSEL Bits
(PLLCFG bits [6:5])
PSEL hex
1
00
0
2
01
0x1
4
10
0x2
8
11
0x3
3.10.6 PLL configuration sequence
The following discussions refer to PLLs and PLL related registers generically (e.g.
PLLCFG rather than PLL0CFG or PLL1CFG). The instructions have to be adapted to the
specific case being addressed in the application.
To set up a PLL and switch clocks to its output:
1. Make sure that the PLL output is not already being used. The CCLKSEL,
USBCLKSEL, and SPIFICLKSEL registers must not select the PLL being set up (see
“To switch clocks away from a PLL output:” below). Clock dividers included in these
registers may also be set up at this time if writing to any of the noted registers.
2. If the main PLL is being set up, and the main clock source is being changed (IRC
versus main oscillator), change this first by writing the correct value to the
CLKSRCSEL register.
3. Write PLL new setup values to the PLLCFG register. Write a 1 to the PLLE bit in the
PLLCON register. Perform a PLL feed sequence by writing first the value 0xAA, then
the value 0x55 to the PLLFEED register.
4. Set up the necessary clock dividers. These may include the CCLKSEL, PCLKSEL,
EMCCLKSEL, USBCLKSEL, and the SPIFICLKSEL registers.
5. Wait for the PLL to lock. This may be accomplished by polling the PLLSTAT register
and testing for PLOCK = 1, or by using the PLL lock interrupt.
6. Connect the PLL by selecting it output in the appropriate places. This may include the
CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers.
To switch clocks away from a PLL output:
1. To switch back to the mode of not using a PLL, write values to any or all of the
CCLKSEL, USBCLKSEL, and SPIFICLKSEL registers in order to select a different
clock source.
2. The related PLL may now be turned off by writing to the PLLCON register and
performing a PLL feed sequence, reconfigured by writing to the PLLCFG register, etc.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
66 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.10.7 PLL configuration examples
The following examples illustrate selecting PLL values based on different system
requirements.
Example 1).
Assumptions:
• The system design is planned to use the IRC to generate the CPU clock.
• A frequency as close to 80 MHz as possible is desired for the CPU clock.
Of the two PLLs, only PLL0 can supply the CPU clock, so this example is for PLL0. The
nearest multiple of the 12 MHz IRC frequency to 80 MHz is 84 MHz. Since pll_out_clk = M
 pll_in_clk, M = pll_out_clk / pll_in_clk = 84 / 12 = 7.
Now a value for P must be found that puts FCCO within the PLL operating range of 156
MHz to 320 MHz. FCCO = pll_out_clk  2  P. Start by finding the value of FCCO with P = 1,
which is 84 MHz  2 = 168 MHz. Since that is within the PLL operating range, no further
work is needed.
Set up the PLL for M = 7and P = 1. This requires putting the value 6 (M - 1, or see
Table 45 “PLL Multiplier values”) in the MSEL field of the PLL0CFG register. A value of 0
(see Table 46 “PLL Divider values”) is needed in the PSEL field of PLL0CFG. A single
write of both values would be PLL0CFG = 0x06. See Section 3.10.6 for a description of
the PLL setup sequence.
Example 2).
Assumptions:
• The system design is planned to use a 12 MHz crystal generate both the CPU clock
and the USB clock.
• A frequency close to 100 MHz is desired for the CPU clock.
Of the two PLLs, only PLL0 can supply both the CPU clock and the USB clock, so this
example is for PLL0. The PLL output must be an even integer multiple of 48 MHz for the
USB to operate correctly (i.e. a multiple of 96 MHz). Two multiples of 96 MHz fit within the
PLL operating range: 192 MHz (2  96 MHz), and 288 MHz (3  96 MHz). Of these, only
192 MHz can produce a CPU clock near 100 MHz (96 MHz). So, a 96 MHz PLL output
can be used to obtain the 2 needed frequencies. Since pll_out_clk = M  pll_in_clk, M =
pll_out_clk / pll_in_clk = 96 / 12 = 8.
Now a value for P must be found that puts FCCO within the PLL operating range of 156
MHz to 320 MHz. FCCO = pll_out_clk  2  P. Start by finding the value of FCCO with P = 1,
which is 96 MHz  2 = 192 MHz. Since that is within the PLL operating range, no further
work is needed.
Set up the PLL for M = 8 and P = 1. This requires putting the value 7 (M - 1, or see
Table 45) in the MSEL field of the PLL0CFG register. A value of 0 (see Table 46) is
needed in the PSEL field of PLL0CFG. A single write of both values would be PLL0CFG =
0x07. See Section 3.10.6 for a description of the PLL setup sequence.
Example 3)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
67 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Assumptions:
• The system design will use the USB interface.
• It is desired that the CPU clock remain flexible and able to operate at frequencies
unrelated to the USB clock.
In order to keep the CPU clock separate form the USB clock, the CPU will use PLL0. For
USB, PLL1 may be configured with the same values used in the last example. PLL0 can
be operated from either the IRC or the main oscillator to obtain whatever frequency is
needed, and the PLL0 setup can be changed without compromising USB operation.
3.11 Clock selection and division
The output of each PLL that is used must be divided down to whatever frequency is
needed by each subsystem. There are separate clocks for the CPU, External Memory
Controller, USB interface, SPIFI, and peripherals on the APB buses. Separate clock
selection multiplexers and clock dividers provide flexibility in the generation of these
clocks.
3.12 Power control
A variety of power control features are supported: Sleep mode, Deep Sleep mode,
Power-down mode, and Deep Power-down mode. The CPU clock rate may also be
controlled as needed by changing clock sources, re-configuring PLL values, and/or
altering the CPU clock divider value. This allows a trade-off of power versus processing
speed based on application requirements. In addition, Peripheral Power Control allows
shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required
for the application. A power boost feature allows operation up to 120 MHz, or power
savings when operation is at or below 100 MHz.
Entry to any reduced power mode begins with the execution of either a WFI (Wait For
Interrupt) or WFE (Wait For Exception) instruction by the CPU. The CPU internally
supports two reduced power modes: Sleep and Deep Sleep. These are selected by the
SLEEPDEEP bit in the Cortex-M4 System Control Register. Power-down and Deep
Power-down modes are selected by bits in the PCON register. See Table 14. The same
register contains flags that indicate whether entry into each reduced power mode actually
occurred.
A separate power domain is implemented in order to allow turning off power to the bulk of
the device while maintaining operation of the Real Time Clock.
Reduced power modes have some limitation during debug, see Section 39.7 for more
information.
3.12.1 Sleep mode
Note: Sleep mode on these devices corresponds to the Idle mode on older LPC2xxx
series devices. The name is changed because ARM has incorporated portions of reduced
power mode control into the Cortex-M4.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
68 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
When Sleep mode is entered, the clock to the core is stopped, and the SMFLAG bit in
PCON is set, see Table 14.Resumption from the Sleep mode does not need any special
sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or an interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
The DMA controller can continue to work in Sleep mode, and has access to the peripheral
SRAMs and all peripheral registers. The flash memory and the Main SRAM are not
available in Sleep mode, they are disabled in order to save power.
Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.
3.12.2 Deep Sleep mode
Note: Deep Sleep mode on these devices corresponds to the Sleep mode on older
LPC23xx and LPC24xx series devices. The name is changed because ARM has
incorporated portions of reduced power mode control into the Cortex-M4.
When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly
all clocks are stopped, and the DSFLAG bit in PCON is set, see Table 14. The IRC
remains running for fast startup. The 32 kHz RTC oscillator is not stopped and RTC
interrupts may be used as a wake-up source. The flash is left in the standby mode
allowing a quick wake-up. The PLLs are automatically turned off and the clock selection
multiplexers are set to use sysclk (the reset state). The clock divider control registers are
automatically reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep Sleep mode and the logic levels of chip pins remain static.
The Deep Sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep Sleep mode reduces chip power
consumption to a very low value.
On the wake-up of Deep Sleep mode, if the IRC was used before entering Deep Sleep
mode, a 2-bit IRC timer starts counting and the code execution and peripherals activities
will resume after the timer expires (4 cycles). If the main oscillator is used, the 12-bit main
oscillator timer starts counting and the code execution will resume when the timer expires
(4096 cycles). The user must remember to re-configure any required PLLs and clock
dividers after the wake-up.
Wake-up from Deep Sleep mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input
pin transition, or a Watchdog Timer timeout, when the related interrupt is enabled.
Wake-up will occur whenever any enabled interrupt occurs.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
69 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.12.3 Power-down mode
Power-down mode does everything that Deep Sleep mode does, but also turns off the
flash memory. Entry to Power-down mode causes the PDFLAG bit in PCON to be set, see
Table 14. This saves more power, but requires waiting for resumption of flash operation
before execution of code or data access in the flash memory can be accomplished.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The RTC remains running if it has been enabled and RTC interrupts may be
used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are
automatically turned off and the clock selection multiplexers are set to use sysclk (the
reset state). The clock divider control registers are automatically reset to zero. If the
Watchdog timer is running, it will continue running in Power-down mode.
Upon wake-up from Power-down mode, if the IRC was used before entering Power-down
mode, after IRC-start-up time (about 60 s), the 2-bit IRC timer starts counting and
expiring in 4 cycles. Code execution can then be resumed immediately following the
expiration of the IRC timer if the code was running from SRAM. In the meantime, the flash
wake-up timer measures flash start-up time of about 100 s. When it times out, access to
the flash is enabled. The user must remember to re-configure any required PLLs and
clock dividers after the wake-up.
Wake-up from Power-down mode can be brought about by NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), or a CAN input
pin transition, when the related interrupt is enabled.
3.12.4 Deep Power-down mode
In Deep Power-down mode, power is shut off to the entire chip with the exception of the
Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep
Power-down mode causes the DPDFLAG bit in PCON to be set, see Table 14.
To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the
VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before
device operation can be restarted.
Wake-up from Deep Power-down mode will occur when an external reset signal is
applied, or the RTC interrupt is enabled and an RTC interrupt is generated.
3.12.5 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. This is
detailed in the description of the PCONP register.
3.12.6 Power boost
A Power boost feature allows operation above 100 MHz, to the upper limit for this device
of 120 MHz. This boost is on by default when user code begins after a chip reset. Power
can be saved by turning of this mode when operation will be at 100 MHz or lower. See
Section 3.3.2.3.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
70 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.12.7 Register description
The Power Control function uses registers shown in Table 47. More detailed descriptions
follow.
Table 47.
Power Control registers
Name
Description
PCON
PCONP
Access
Reset
value[1]
Address
Table
Power Control Register. This register contains control bits that
enable some reduced power operating modes. See Table 14.
R/W
0
0x400F C0C0
14
Power Control for Peripherals Register. This register contains
control bits that enable and disable individual peripheral
functions, allowing elimination of power consumption by
peripherals that are not needed. See Table 16.
R/W
0x0408 829E 0x400F C0C4
16
PBOOST Power Boost control register. This register controls the output of
the main on-chip regulator, allowing a choice between
high-speed operation above 100 MHz, or power savings when
operation is at 100 MHz or lower.
[1]
R/W
0x3
0x400F C1B0
18
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
3.12.8 Wake-up from Reduced Power Modes
Any enabled interrupt can wake up the CPU from Sleep mode. Certain interrupts can
wake up the processor if it is in either Deep Sleep mode or Power-down mode.
Interrupts that can occur during Deep Sleep or Power-down mode will wake up the CPU if
the interrupt is enabled. After wake-up, execution will continue to the appropriate interrupt
service routine. These interrupts are NMI, External Interrupts EINT0 through EINT3, GPIO
interrupts, Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN Activity
Interrupt, USB Activity Interrupt, and Watchdog timer timeout. For the wake-up process to
take place, the corresponding interrupt must be enabled in the NVIC. For pin-related
peripheral functions, the related functions must also be mapped to pins.
The CAN Activity Interrupt is generated by activity on the CAN bus pins, and the USB
Activity Interrupt is generated by activity on the USB bus pins. These interrupts are only
useful to wake up the CPU when it is on Deep Sleep or Power-down mode, when the
peripheral functions are powered up, but not active. Typically, if these interrupts are used,
their flags should be polled just before enabling the interrupt and entering the desired
reduced power mode. This can save time and power by avoiding an immediate wake-up.
Upon wake-up, the interrupt service can turn off the related activity interrupt, do any
application specific setup, and exit to await a normal peripheral interrupt.
In Deep Power-down mode, internal power to most of the device is removed, which limits
the possibilities for waking up from this mode. External reset can wake-up the device.
Also, of the RTC is running and has been set up to cause an interrupt, that event can
wake-up the device.
3.12.9 Power control usage notes
After every reset, the PCONP register contains the value that enables selected interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to access
the PCONP in order to start using some of the on-board peripherals.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
71 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals that are actually used in the application. All other bits, declared to
be "Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
3.12.10 Power domains
Two independent power domains are provided that allow the bulk of the device to have
power removed while maintaining operation of the Real Time Clock.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. Whenever the device core
power is greater than VBAT, that power is used to operate the RTC.
3.13 Wake-up timer
At power-up and when awakened from Power-down mode, operation begins by using the
12 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If
the main oscillator or one or both PLLs are needed by the application, software will need
to enable these features and wait for them to stabilize before they are used as a clock
source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power-on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the Wake-up Timer.
The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD(REG)(3V3) ramp (in the case of power on), the type
of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other
external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the
existing ambient conditions.
Once a clock is detected, the Wake-up Timer counts a fixed number of clocks (4,096),
then sets the flag (OSCSTAT bit in the SCS register) that indicates that the main oscillator
is ready for use. Software can then switch to the main oscillator and start any required
PLLs. Refer to the Main Oscillator description in this chapter for details.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
72 of 942
UM10562
NXP Semiconductors
Chapter 3: LPC408x/407x System and clock control
3.14 External clock output pin
For system test and development purposes, any one of several internal clocks may be
brought out on the CLKOUT function available on the P1[25] or P1[27] pins, as shown in
Figure 12.
Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator
(osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), the RTC clock
(rtc_clk), the SPIFI clock (spifi_clk), and the Watchdog oscillator (wdt_clk).
120601
CLKOUTCFG[3:0]
cclk
osc_clk
irc_osc
usb_clk
rtc_clk
spifi_clk
wdt_clk
000
001
CLKOUTCFG[7:4]
CLKOUTCFG[8]
010
011
CLKOUT
Divider
Clock Enable CLKOUT
Syncronizer
100
101
CLKOUTCFG[9]
110
Fig 12. CLKOUT selection
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
73 of 942
UM10562
Chapter 4: LPC408x/407x Flash accelerator
Rev. 1 — 13 September 2012
User manual
4.1 Introduction
The flash accelerator block allows maximization of the performance of the CPU when it is
running code from flash memory, while also saving power. The flash accelerator also
provides speed and power improvements for data accesses to the flash memory.
4.2 Flash accelerator blocks
The flash accelerator is divided into several functional blocks:
• AHB-Lite bus interface, accessible by the I-code and D-code buses of the CPU, as
well as by the General Purpose DMA Controller
• An array of eight 128-bit buffers
• Flash accelerator control logic, including address compare and flash control
• A flash memory interface
Figure 13 shows a simplified diagram of the flash accelerator blocks and data paths.
DCode
bus
CPU
ICode
bus
Bus
Matrix
Flash Accelerator
Combined
AHB
AHB-Lite
bus interface
Instruction/
data buffers
Flash
Interface
Flash
Memory
Flash
Accelerator
Control
DMA
General
Purpose Master Port
DMA
Controller
120601
Fig 13. Simplified block diagram of the flash accelerator showing potential bus connections
In the following descriptions, the term “fetch” applies to an explicit flash read request from
the CPU. “Prefetch” is used to denote a flash read of instructions beyond the current
processor fetch address.
4.2.1 Flash memory bank
Flash programming operations are not controlled by the flash accelerator, but are handled
as a separate function. A Boot ROM contains flash programming algorithms that may be
called as part of the application program, and a loader that may be run to allow
programming of the flash memory.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
74 of 942
UM10562
NXP Semiconductors
Chapter 4: LPC408x/407x Flash accelerator
4.2.2 Flash programming Issues
Since the flash memory does not allow accesses during programming and erase
operations, it is necessary for the flash accelerator to force the CPU to wait if a memory
access to a flash address is requested while the flash memory is busy with a
programming operation. Under some conditions, this delay could result in a Watchdog
time-out. The user will need to be aware of this possibility and take steps to insure that an
unwanted Watchdog reset does not cause a system failure while programming or erasing
the flash memory.
In order to preclude the possibility of stale data being read from the flash memory, the
flash accelerator buffers are automatically invalidated at the beginning of any flash
programming or erase operation. Any subsequent read from a flash address will cause a
new fetch to be initiated after the flash operation has completed.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
75 of 942
UM10562
NXP Semiconductors
Chapter 4: LPC408x/407x Flash accelerator
4.3 Register description
The flash accelerator is controlled by the register shown in Table 48. More detailed
descriptions follow.
Table 48.
Summary of flash accelerator registers
Name
Description
FLASHCFG
Flash Accelerator Configuration Register.
Controls flash access timing. See Table 49.
[1]
Access
Reset
value[1]
Address
R/W
0x303A
0x400F C000
Reset Value reflects the data stored in defined bits only. It does not include reserved bits content.
4.4 Flash Accelerator Configuration register
Configuration bits select the flash access time, as shown in Table 49. The lower bits of
FLASHCFG control internal flash accelerator functions and should not be altered.
Following reset, flash accelerator functions are enabled and flash access timing is set to a
default value of 4 clocks.
Changing the FLASHCFG register value causes the flash accelerator to invalidate all of
the holding latches, resulting in new reads of flash information as required. This
guarantees synchronization of the flash accelerator to CPU operation.
Table 49.
Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) bit description
Bit
Symbol
11:0
-
Value Description
-
15:12 FLASHTIM
Reset
value
Reserved, user software should not change these bits from the reset value.
Flash access time. The value of this field plus 1 gives the number of CPU clocks used
for a flash access.
0x03A
0x3
Warning: improper setting of this value may result in incorrect operation of the device.
0000
Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock with power boost off
(see Section 3.12.6).
0001
Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock with power boost
off (see Section 3.12.6).
0010
Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock with power boost
off (see Section 3.12.6).
0011
Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock with power boost
off (see Section 3.12.6). Use this setting for operation from 100 to 120 MHz operation
with power boost on.
0100
Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock with power boost
off (see Section 3.12.6).
0101
Flash accesses use 6 CPU clocks. “Safe” setting for any allowed conditions.
Other Intended for potential future higher speed devices.
31:16 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
76 of 942
UM10562
NXP Semiconductors
Chapter 4: LPC408x/407x Flash accelerator
4.5 Operation
Simply put, the flash accelerator attempts to have the next instruction that will be needed
in its latches in time to prevent CPU fetch stalls. The flash accelerator includes an array of
eight 128-bit buffers to store both instructions and data in a configurable manner. Each
128-bit buffer in the array can include four 32-bit instructions, eight 16-bit instructions or
some combination of the two. During sequential code execution, a buffer typically contains
the current instruction and the entire flash line that contains that instruction, or one flash
line of data containing a previously requested address. Buffers are marked according to
how they are used (as instruction or data buffers), and when they have been accessed.
This information is used to carry out the buffer replacement strategy.
The CPU provides a separate bus for instruction access (I-code) and data access
(D-code) in the code memory space. These buses, plus the General Purpose DMA
Controllers’s master port, are arbitrated by the AHB multilayer matrix. Any access to the
flash memory’s address space is presented to the flash accelerator.
If a flash instruction fetch and a flash data access from the CPU occur at the same time,
the multilayer matrix gives precedence to the data access. This is because a stalled data
access always slows down execution, while a stalled instruction fetch often does not.
When the flash data access is concluded, any flash fetch or prefetch that had been in
progress is re-initiated.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. Buffer replacement strategy in the flash accelerator
attempts to maximize the chances that potentially reusable information is retained until it
is needed again.
If an attempt is made to write directly to the flash memory without using the normal flash
programming interface (via Boot ROM function calls), the flash accelerator generates an
error condition. The CPU treats this error as a data abort. The GPDMA handles error
conditions as described in Section 35.4.1.6.3.
When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has
a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated
for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the
CPU is stalled for a shorter time since the required flash access is already in progress.
Typically, a flash prefetch is begun whenever an access is made to a just prefetched
address, or to a buffer whose immediate successor is not already in another buffer. A
prefetch in progress may be aborted by a data access, in order to minimize CPU stalls.
A prefetched flash line is latched within the flash memory, but the flash accelerator does
not capture the line in a buffer until the CPU presents an address that is contained within
the prefetched flash line. If the core presents an instruction address that is not already
buffered and is not contained in the prefetched flash line, the prefetched line will be
discarded.
Some special cases include the possibility that the CPU will request a data access to an
address already contained in an instruction buffer. In this case, the data will be read from
the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction
address that can be satisfied from an existing data buffer, causes the instruction to be
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
77 of 942
UM10562
NXP Semiconductors
Chapter 4: LPC408x/407x Flash accelerator
supplied from the data buffer, and the buffer to be changed into an instruction buffer. This
causes the buffer to be handled differently when the flash accelerator is determining which
buffer is to be overwritten next.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
78 of 942
UM10562
Chapter 5: LPC408x/407x Nested Vectored Interrupt
Controller (NVIC)
Rev. 1 — 13 September 2012
User manual
5.1 Features
•
•
•
•
•
•
•
•
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M4
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
The NVIC supports 40 vectored interrupts in these devices
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt
Software interrupt generation
5.2 Description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M4. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts. The NVIC handles interrupts in addition to system exceptions.
Exceptions include Reset, NMI, Hard Fault, MemManage Fault, Bus Fault, Usage Fault,
SVCall, Debug Monitor, PendSV, and Systick.
See the ARM Cortex-M4 User Guide referred to in Section 40.1 for details of NVIC
operation.
5.3 Interrupt sources
Table 50 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source, as noted.
Exception numbers relate to where entries are stored in the exception vector table.
Interrupt numbers are used in some other contexts, such as software interrupts.
Note that system exceptions are hard-wired into the Cortex-M4 and are not shown in the
table. Some other information about the Systick interrupt can be found in the System Tick
Timer chapter, Section 25.1
In addition, the NVIC handles the Non-Maskable Interrupt (NMI). In order for NMI to
operate from an external signal, the NMI function must be connected to the related device
pin (P2[10] / EINT0n / NMI). When connected, a logic 1 on the pin will cause the NMI to be
processed. For details, refer to the Cortex-M4 User Guide that is an appendix to this User
Manual.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
79 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
Table 50.
Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt Exception Vector Function
ID
Number
Offset
Flag(s)
0
16
0x40
WDT
Watchdog Interrupt (WDINT)
1
17
0x44
Timer 0
Match 0 - 1 (MR0, MR1)
2
18
0x48
Timer 1
Match 0 - 2 (MR0, MR1, MR2)
Capture 0 - 1 (CR0, CR1)
Capture 0 - 1 (CR0, CR1)
3
19
0x4C
Timer 2
Match 0-3
Capture 0-1
4
20
0x50
Timer 3
Match 0-3
Capture 0-1
5
21
0x54
UART0
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
6
22
0x58
UART1
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Control Change
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
7
23
0x5C
UART 2
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
8
24
0x60
UART 3
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
9
25
0x64
PWM1
Match 0 - 6 of PWM1
Capture 0-1 of PWM1
10
26
0x68
I2C0
SI (state change)
0x6C
I2C1
SI (state change)
SI (state change)
-
11
27
12
28
0x70
I2C2
13
29
0x74
(unused)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
80 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
Table 50.
Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt Exception Vector Function
ID
Number
Offset
14
30
0x78
Flag(s)
SSP0
Tx FIFO half empty of SSP0
Rx FIFO half full of SSP0
Rx Timeout of SSP0
Rx Overrun of SSP0
15
31
0x7C
SSP 1
Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
16
32
0x80
PLL0 (Main PLL)
PLL0 Lock (PLOCK0)
17
33
0x84
RTC and Event
Monitor/Recorder
Counter Increment (RTCCIF), Alarm (RTCALF)
18
34
0x88
External Interrupt
External Interrupt 0 (EINT0)
19
35
0x8C
External Interrupt
External Interrupt 1 (EINT1)
20
36
0x90
External Interrupt
External Interrupt 2 (EINT2)
21
37
0x94
External Interrupt
External Interrupt 3 (EINT3)
22
38
0x98
ADC
A/D Converter end of conversion
23
39
0x9C
BOD
Brown Out detect
24
40
0xA0
USB
USB_INT_REQ_LP, USB_INT_REQ_HP, USB_INT_REQ_DMA,
USB_HOST_INT, USB_ATX_INT, USB_OTG_INT, USB_I2C_INT
25
41
0xA4
CAN
CAN Common, CAN 0 Tx, CAN 0 Rx, CAN 1 Tx, CAN 1 Rx
26
42
0xA8
DMA Controller
Interrupt status of all DMA channels
irq, dmareq1, dmareq2
EV0, EV1, EV2
27
43
0xAC
I2S
28
44
0xB0
Ethernet
WakeupInt, SoftInt, TxDoneInt, TxFinishedInt, TxErrorInt,
TxUnderrunInt, RxDoneInt, RxFinishedInt, RxErrorInt,
RxOverrunInt.
29
45
0xB4
SD Card Interface
RxDataAvlbl, TxDataAvlbl, RxFifoEmpty, TxFifoEmpty, RxFifoFull,
TxFifoFull, RxFifoHalfFull, TxFifoHalfEmpty, RxActive, TxActive,
CmdActive, DataBlockEnd, StartBitErr, DataEnd, CmdSent,
CmdRespEnd, RxOverrun, TxUnderrun, DataTimeOut,
CmdTimeOut, DataCrcFail, CmdCrcFail
30
46
0xB8
Motor Control PWM
IPER[2:0], IPW[2:0], ICAP[2:0], FES
31
47
0xBC
Quadrature Encoder
INX_Int, TIM_Int, VELC_Int, DIR_Int, ERR_Int, ENCLK_Int,
POS0_Int, POS1_Int, POS2_Int, REV_Int, POS0REV_Int,
POS1REV_Int, POS2REV_Int
32
48
0xC0
PLL1 (Alt PLL)
PLL1 Lock (PLOCK1)
33
49
0xC4
USB Activity Interrupt USB_NEED_CLK
34
50
0xC8
CAN Activity Interrupt CAN1WAKE, CAN2WAKE
35
51
0xCC
UART4
Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
End of Auto-Baud (ABEO)
Auto-Baud Time-Out (ABTO)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
81 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
Table 50.
Connection of interrupt sources to the Vectored Interrupt Controller
Interrupt Exception Vector Function
ID
Number
Offset
36
52
0xD0
Flag(s)
SSP2
Tx FIFO half empty of SSP2
Rx FIFO half full of SSP2
Rx Timeout of SSP2
Rx Overrun of SSP2
37
53
0xD4
LCD controller
BER, VCompI, LNBUI, FUFI, CrsrI
38
54
0xD8
GPIO interrupts
P0xREI, P2xREI, P0xFEI, P2xFEI
39
55
0xDC
PWM0
Match 0 - 6 of PWM0
Capture 0-1 of PWM0
40
56
0xE0
EEPROM
EE_PROG_DONE, EE_RW_DONE
5.4 Vector table remapping
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register (VTOR) contained in the Cortex-M4.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address
space. The vector table should be located on a 256 word (1024 byte) boundary to insure
alignment. See the ARM Cortex-M4 User Guide referred to in Section 40.1 for details of
the Vector Table Offset feature.
ARM describes bit 29 of the VTOR (TBLOFF) as selecting a memory region, either code
or SRAM. For simplicity, this bit can be thought as simply part of the address offset since
the split between the “code” space and the “SRAM” space occurs at the location
corresponding to bit 29 in a memory address.
Examples:
To place the vector table at the beginning of the Main SRAM, starting at address
0x1000 0000, place the value 0x1000 0000 in the VTOR register. This indicates address
0x1000 0000 in the code space, since bit 29 of the VTOR equals 0.
To place the vector table at the beginning of the peripheral SRAM, starting at address
0x2000 0000, place the value 0x2000 0000 in the VTOR register. This indicates address
0x2000 0000 in the SRAM space, since bit 29 of the VTOR equals 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
82 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5 Register description
The following table summarizes the registers in the NVIC as implemented in
LPC408x/407x devices. See the ARM Cortex-M4 User Guide referred to in Section 40.1
for functional details of the NVIC.
Table 51.
Name
NVIC register map
Description
Access Reset
value
ISER0 to Interrupt Set-Enable Registers. These registers allow enabling
ISER1
interrupts and reading back the interrupt enables for specific
peripheral functions.
RW
ICER0 to Interrupt Clear-Enable Registers. These registers allow
ICER1
disabling interrupts and reading back the interrupt enables for
specific peripheral functions.
RW
ISPR0 to Interrupt Set-Pending Registers. These registers allow
ISPR1
changing the interrupt state to pending and reading back the
interrupt pending state for specific peripheral functions.
RW
ICPR0 to Interrupt Clear-Pending Registers. These registers allow
ICPR1
changing the interrupt state to not pending and reading back
the interrupt pending state for specific peripheral functions.
RW
IABR0 to Interrupt Active Bit Registers. These registers allow reading the
IABR1
current interrupt active state for specific peripheral functions.
RO
IPR0 to
IPR10
RW
STIR
Interrupt Priority Registers. These registers allow assigning a
priority to each interrupt. Each register contains the 5-bit priority
fields for 4 interrupts.
Software Trigger Interrupt Register. This register allows
software to generate an interrupt.
UM10562
User manual
WO
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
0
0
0
0
-
Address
Table
ISER0 - 0xE000 E100
52
ISER1 - 0xE000 E104
53
ICER0 - 0xE000 E180
54
ICER1 - 0xE000 E184
55
ISPR0 - 0xE000 E200
56
ISPR1 - 0xE000 E204
57
ICPR0 - 0xE000 E280
58
ICPR1 - 0xE000 E284
59
IABR0 - 0xE000 E300
60
IABR1 - 0xE000 E304
61
IPR0 - 0xE000 E400
62
IPR1 - 0xE000 E404
63
IPR2 - 0xE000 E408
64
IPR3 - 0xE000 E40C
65
IPR4 - 0xE000 E410
66
IPR5 - 0xE000 E414
67
IPR6 - 0xE000 E418
68
IPR7 - 0xE000 E41C
69
IPR8 - 0xE000 E420
70
IPR9 - 0xE000 E424
71
IPR10 - 0xE000 E428
72
STIR - 0xE000 EF00
73
© NXP B.V. 2012. All rights reserved.
83 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.1 Interrupt Set-Enable Register 0 register
The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are enabled via the ISER1
register (Section 5.5.2). Disabling interrupts is done through the ICER0 and ICER1
registers (Section 5.5.3 and Section 5.4).
Table 52.
Interrupt Set-Enable Register 0 register
Bit
Name
Function
0
ISE_WDT
Watchdog Timer interrupt enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1
ISE_TIMER0
Timer 0 interrupt enable. See functional description for bit 0.
2
ISE_TIMER1
Timer 1 interrupt enable. See functional description for bit 0.
3
ISE_TIMER2
Timer 2 interrupt enable. See functional description for bit 0.
4
ISE_TIMER3
Timer 3 interrupt enable. See functional description for bit 0.
5
ISE_UART0
UART0 interrupt enable. See functional description for bit 0.
6
ISE_UART1
UART1 interrupt enable. See functional description for bit 0.
7
ISE_UART2
UART2 interrupt enable. See functional description for bit 0.
8
ISE_UART3
UART3 interrupt enable. See functional description for bit 0.
9
ISE_PWM1
PWM1 interrupt enable. See functional description for bit 0.
10
ISE_I2C0
I2C0 interrupt enable. See functional description for bit 0.
11
ISE_I2C1
I2C1 interrupt enable. See functional description for bit 0.
12
ISE_I2C2
I2C2 interrupt enable. See functional description for bit 0.
13
-
Reserved. Read value is undefined, only zero should be written.
14
ISE_SSP0
SSP0 interrupt enable. See functional description for bit 0.
15
ISE_SSP1
SSP1 interrupt enable. See functional description for bit 0.
16
ISE_PLL0
PLL0 (Main PLL) interrupt enable. See functional description for bit 0.
17
ISE_RTC
Real Time Clock (RTC) and Event Monitor/Recorder interrupt enable. See description of bit 0.
18
ISE_EINT0
External Interrupt 0 interrupt enable. See functional description for bit 0.
19
ISE_EINT1
External Interrupt 1 interrupt enable. See functional description for bit 0.
20
ISE_EINT2
External Interrupt 2 interrupt enable. See functional description for bit 0.
21
ISE_EINT3
External Interrupt 3 interrupt enable. See functional description for bit 0.
22
ISE_ADC
ADC interrupt enable. See functional description for bit 0.
23
ISE_BOD
BOD interrupt enable. See functional description for bit 0.
24
ISE_USB
USB interrupt enable. See functional description for bit 0.
25
ISE_CAN
CAN interrupt enable. See functional description for bit 0.
26
ISE_DMA
GPDMA interrupt enable. See functional description for bit 0.
27
ISE_I2S
I2S interrupt enable. See functional description for bit 0.
28
ISE_ENET
Ethernet interrupt enable. See functional description for bit 0.
29
ISE_SD
SD card interface interrupt enable. See functional description for bit 0.
30
ISE_MCPWM
Motor Control PWM interrupt enable. See functional description for bit 0.
31
ISE_QEI
Quadrature Encoder Interface interrupt enable. See functional description for bit 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
84 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.2 Interrupt Set-Enable Register 1 register
The ISER1 register allows enabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Disabling interrupts is done through the
ICER0 and ICER1 registers (Section 5.5.3 and Section 5.4).
Table 53.
Interrupt Set-Enable Register 1 register
Bit
Name
Function
0
ISE_PLL1
PLL1 (Alt PLL) interrupt enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1
ISE_USBACT
USB Activity interrupt enable. See functional description for bit 0.
2
ISE_CANACT
CAN Activity interrupt enable. See functional description for bit 0.
3
ISE_UART4
UART4 interrupt enable. See functional description for bit 0.
4
ISE_SSP2
SSP2 interrupt enable. See functional description for bit 0.
5
ISE_LCD
LCD interrupt enable. See functional description for bit 0.
6
ISE_GPIO
GPIO interrupt enable. See functional description for bit 0.
7
ISE_PWM0
PWM0 interrupt enable. See functional description for bit 0.
8
ISE_FLASH
Flash and EEPROM interrupt enable. See functional description for bit 0.
31:9 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
85 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.3 Interrupt Clear-Enable Register 0
The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the
enabled state of those interrupts. The remaining interrupts are disabled via the ICER1
register (Section 5.4). Enabling interrupts is done through the ISER0 and ISER1 registers
(Section 5.5.1 and Section 5.5.2).
Table 54.
Interrupt Clear-Enable Register 0
Bit
Name
Function
0
ICE_WDT
Watchdog Timer interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1
ICE_TIMER0
Timer 0 interrupt disable. See functional description for bit 0.
2
ICE_TIMER1
Timer 1 interrupt disable. See functional description for bit 0.
3
ICE_TIMER2
Timer 2 interrupt disable. See functional description for bit 0.
4
ICE_TIMER3
Timer 3 interrupt disable. See functional description for bit 0.
5
ICE_UART0
UART0 interrupt disable. See functional description for bit 0.
6
ICE_UART1
UART1 interrupt disable. See functional description for bit 0.
7
ICE_UART2
UART2 interrupt disable. See functional description for bit 0.
8
ICE_UART3
UART3 interrupt disable. See functional description for bit 0.
9
ICE_PWM1
PWM1 interrupt disable. See functional description for bit 0.
10
ICE_I2C0
I2C0 interrupt disable. See functional description for bit 0.
11
ICE_I2C1
I2C1 interrupt disable. See functional description for bit 0.
12
ICE_I2C2
I2C2 interrupt disable. See functional description for bit 0.
13
-
Reserved. Read value is undefined, only zero should be written.
14
ICE_SSP0
SSP0 interrupt disable. See functional description for bit 0.
15
ICE_SSP1
SSP1 interrupt disable. See functional description for bit 0.
16
ICE_PLL0
PLL0 (Main PLL) interrupt disable. See functional description for bit 0.
17
ICE_RTC
Real Time Clock (RTC) and Event Monitor/Recorder interrupt disable. See description of bit 0.
18
ICE_EINT0
External Interrupt 0 interrupt disable. See functional description for bit 0.
19
ICE_EINT1
External Interrupt 1 interrupt disable. See functional description for bit 0.
20
ICE_EINT2
External Interrupt 2 interrupt disable. See functional description for bit 0.
21
ICE_EINT3
External Interrupt 3 interrupt disable. See functional description for bit 0.
22
ICE_ADC
ADC interrupt disable. See functional description for bit 0.
23
ICE_BOD
BOD interrupt disable. See functional description for bit 0.
24
ICE_USB
USB interrupt disable. See functional description for bit 0.
25
ICE_CAN
CAN interrupt disable. See functional description for bit 0.
26
ICE_DMA
GPDMA interrupt disable. See functional description for bit 0.
27
ICE_I2S
I2S interrupt disable. See functional description for bit 0.
28
ICE_ENET
Ethernet interrupt disable. See functional description for bit 0.
29
ICE_SD
SD card interface interrupt disable. See functional description for bit 0.
30
ICE_MCPWM
Motor Control PWM interrupt disable. See functional description for bit 0.
31
ICE_QEI
Quadrature Encoder Interface interrupt disable. See functional description for bit 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
86 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.4 Interrupt Clear-Enable Register 1 register
The ICER1 register allows disabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Enabling interrupts is done through the
ISER0 and ISER1 registers (Section 5.5.1 and Section 5.5.2).
Table 55.
Interrupt Clear-Enable Register 1 register
Bit
Name
Function
0
ICE_PLL1
PLL1 (Alt PLL) interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1
ICE_USBACT
USB Activity interrupt disable. See functional description for bit 0.
2
ICE_CANACT
CAN Activity interrupt disable. See functional description for bit 0.
3
ICE_UART4
UART4 interrupt disable. See functional description for bit 0.
4
ICE_SSP2
SSP2 interrupt disable. See functional description for bit 0.
5
ICE_LCD
LCD interrupt disable. See functional description for bit 0.
6
ICE_GPIO
GPIO interrupt disable. See functional description for bit 0.
7
ICE_PWM0
PWM0 interrupt disable. See functional description for bit 0.
8
ICE_EEPROM
EEPROM interrupt disable. See functional description for bit 0.
31:9 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
87 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.5 Interrupt Set-Pending Register 0 register
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or
for reading the pending state of those interrupts. The remaining interrupts can have their
pending state set via the ISPR1 register (Section 5.5.6). Clearing the pending state of
interrupts is done through the ICPR0 and ICPR1 registers (Section 5.5.7 and
Section 5.5.8).
Table 56.
Interrupt Set-Pending Register 0 register
Bit
Name
Function
0
ISP_WDT
Watchdog Timer interrupt pending set.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1
ISP_TIMER0
Timer 0 interrupt pending set. See functional description for bit 0.
2
ISP_TIMER1
Timer 1 interrupt pending set. See functional description for bit 0.
3
ISP_TIMER2
Timer 2 interrupt pending set. See functional description for bit 0.
4
ISP_TIMER3
Timer 3 interrupt pending set. See functional description for bit 0.
5
ISP_UART0
UART0 interrupt pending set. See functional description for bit 0.
6
ISP_UART1
UART1 interrupt pending set. See functional description for bit 0.
7
ISP_UART2
UART2 interrupt pending set. See functional description for bit 0.
8
ISP_UART3
UART3 interrupt pending set. See functional description for bit 0.
9
ISP_PWM1
PWM1 interrupt pending set. See functional description for bit 0.
10
ISP_I2C0
I2C0 interrupt pending set. See functional description for bit 0.
11
ISP_I2C1
I2C1 interrupt pending set. See functional description for bit 0.
12
ISP_I2C2
I2C2 interrupt pending set. See functional description for bit 0.
13
-
Reserved. Read value is undefined, only zero should be written.
14
ISP_SSP0
SSP0 interrupt pending set. See functional description for bit 0.
15
ISP_SSP1
SSP1 interrupt pending set. See functional description for bit 0.
16
ISP_PLL0
PLL0 (Main PLL) interrupt pending set. See functional description for bit 0.
17
ISP_RTC
Real Time Clock (RTC) and Event Monitor/Recorder interrupt pending set. See description of bit 0.
18
ISP_EINT0
External Interrupt 0 interrupt pending set. See functional description for bit 0.
19
ISP_EINT1
External Interrupt 1 interrupt pending set. See functional description for bit 0.
20
ISP_EINT2
External Interrupt 2 interrupt pending set. See functional description for bit 0.
21
ISP_EINT3
External Interrupt 3 interrupt pending set. See functional description for bit 0.
22
ISP_ADC
ADC interrupt pending set. See functional description for bit 0.
23
ISP_BOD
BOD interrupt pending set. See functional description for bit 0.
24
ISP_USB
USB interrupt pending set. See functional description for bit 0.
25
ISP_CAN
CAN interrupt pending set. See functional description for bit 0.
26
ISP_DMA
GPDMA interrupt pending set. See functional description for bit 0.
27
ISP_I2S
I2S interrupt pending set. See functional description for bit 0.
28
ISP_ENET
Ethernet interrupt pending set. See functional description for bit 0.
29
ISP_SD
SD card interface interrupt pending set. See functional description for bit 0.
30
ISP_MCPWM
Motor Control PWM interrupt pending set. See functional description for bit 0.
31
ISP_QEI
Quadrature Encoder Interface interrupt pending set. See functional description for bit 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
88 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.6 Interrupt Set-Pending Register 1 register
The ISPR1 register allows setting the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Clearing the pending state
of interrupts is done through the ICPR0 and ICPR1 registers (Section 5.5.7 and
Section 5.5.8).
Table 57.
Interrupt Set-Pending Register 1 register
Bit
Name
Function
0
ISP_PLL1
PLL1 (Alt PLL) interrupt pending set.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1
ISP_USBACT
USB Activity interrupt pending set. See functional description for bit 0.
2
ISP_CANACT
CAN Activity interrupt pending set. See functional description for bit 0.
3
ISP_UART4
UART4 interrupt pending set. See functional description for bit 0.
4
ISP_SSP2
SSP2 interrupt pending set. See functional description for bit 0.
5
ISP_LCD
LCD interrupt pending set. See functional description for bit 0.
6
ISP_GPIO
GPIO interrupt pending set. See functional description for bit 0.
7
ISP_PWM0
PWM0 interrupt pending set. See functional description for bit 0.
8
ISP_EEPROM
31:9 -
UM10562
User manual
EEPROM interrupt pending set. See functional description for bit 0.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
89 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.7 Interrupt Clear-Pending Register 0 register
The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts,
or for reading the pending state of those interrupts. The remaining interrupts can have
their pending state cleared via the ICPR1 register (Section 5.5.8). Setting the pending
state of interrupts is done through the ISPR0 and ISPR1 registers (Section 5.5.5 and
Section 5.5.6).
Table 58.
Interrupt Clear-Pending Register 0 register
Bit
Name
Function
0
ICP_WDT
Watchdog Timer interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1
ICP_TIMER0
Timer 0 interrupt pending clear. See functional description for bit 0.
2
ICP_TIMER1
Timer 1 interrupt pending clear. See functional description for bit 0.
3
ICP_TIMER2
Timer 2 interrupt pending clear. See functional description for bit 0.
4
ICP_TIMER3
Timer 3 interrupt pending clear. See functional description for bit 0.
5
ICP_UART0
UART0 interrupt pending clear. See functional description for bit 0.
6
ICP_UART1
UART1 interrupt pending clear. See functional description for bit 0.
7
ICP_UART2
UART2 interrupt pending clear. See functional description for bit 0.
8
ICP_UART3
UART3 interrupt pending clear. See functional description for bit 0.
9
ICP_PWM1
PWM1 interrupt pending clear. See functional description for bit 0.
10
ICP_I2C0
I2C0 interrupt pending clear. See functional description for bit 0.
11
ICP_I2C1
I2C1 interrupt pending clear. See functional description for bit 0.
12
ICP_I2C2
I2C2 interrupt pending clear. See functional description for bit 0.
13
-
Reserved. Read value is undefined, only zero should be written.
14
ICP_SSP0
SSP0 interrupt pending clear. See functional description for bit 0.
15
ICP_SSP1
SSP1 interrupt pending clear. See functional description for bit 0.
16
ICP_PLL0
PLL0 (Main PLL) interrupt pending clear. See functional description for bit 0.
17
ICP_RTC
Real Time Clock (RTC) and Event Monitor/Recorder interrupt pending clear. See description of bit 0.
18
ICP_EINT0
External Interrupt 0 interrupt pending clear. See functional description for bit 0.
19
ICP_EINT1
External Interrupt 1 interrupt pending clear. See functional description for bit 0.
20
ICP_EINT2
External Interrupt 2 interrupt pending clear. See functional description for bit 0.
21
ICP_EINT3
External Interrupt 3 interrupt pending clear. See functional description for bit 0.
22
ICP_ADC
ADC interrupt pending clear. See functional description for bit 0.
23
ICP_BOD
BOD interrupt pending clear. See functional description for bit 0.
24
ICP_USB
USB interrupt pending clear. See functional description for bit 0.
25
ICP_CAN
CAN interrupt pending clear. See functional description for bit 0.
26
ICP_DMA
GPDMA interrupt pending clear. See functional description for bit 0.
27
ICP_I2S
I2S interrupt pending clear. See functional description for bit 0.
28
ICP_ENET
Ethernet interrupt pending clear. See functional description for bit 0.
29
ICP_SD
SD Card interface interrupt pending clear. See functional description for bit 0.
30
ICP_MCPWM
Motor Control PWM interrupt pending clear. See functional description for bit 0.
31
ICP_QEI
Quadrature Encoder Interface interrupt pending clear. See functional description for bit 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
90 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.8 Interrupt Clear-Pending Register 1 register
The ICPR1 register allows clearing the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Setting the pending state of
interrupts is done through the ISPR0 and ISPR1 registers (Section 5.5.5 and
Section 5.5.6).
Table 59.
Interrupt Clear-Pending Register 1 register
Bit
Name
Function
0
ICP_PLL1
PLL1 (Alt PLL) interrupt pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1
ICP_USBACT
USB Activity interrupt pending clear. See functional description for bit 0.
2
ICP_CANACT
CAN Activity interrupt pending clear. See functional description for bit 0.
3
ICP_UART4
UART4 interrupt pending clear. See functional description for bit 0.
4
ICP_SSP2
SSP2 interrupt pending clear. See functional description for bit 0.
5
ICP_LCD
LCD interrupt pending clear. See functional description for bit 0.
6
ICP_GPIO
GPIO interrupt pending clear. See functional description for bit 0.
7
ICP_PWM0
PWM0 interrupt pending clear. See functional description for bit 0.
8
ICP_EEPROM
EEPROM interrupt pending clear. See functional description for bit 0.
31:9 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
91 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.9 Interrupt Active Bit Register 0
The IABR0 register is a read-only register that allows reading the active state of the first
32 peripheral interrupts. Bits in IABR are set while the corresponding interrupt service
routines are in progress. Additional interrupts can have their active state read via the
IABR1 register (Section 5.5.10).
Table 60.
Interrupt Active Bit Register 0
Bit
Name
0
IAB_WDT
Function
Watchdog Timer interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
1
IAB_TIMER0
Timer 0 interrupt active. See functional description for bit 0.
2
IAB_TIMER1
Timer 1 interrupt active. See functional description for bit 0.
3
IAB_TIMER2
Timer 2 interrupt active. See functional description for bit 0.
4
IAB_TIMER3
Timer 3 interrupt active. See functional description for bit 0.
5
IAB_UART0
UART0 interrupt active. See functional description for bit 0.
6
IAB_UART1
UART1 interrupt active. See functional description for bit 0.
7
IAB_UART2
UART2 interrupt active. See functional description for bit 0.
8
IAB_UART3
UART3 interrupt active. See functional description for bit 0.
9
IAB_PWM1
PWM1 interrupt active. See functional description for bit 0.
10
IAB_I2C0
I2C0 interrupt active. See functional description for bit 0.
11
IAB_I2C1
I2C1 interrupt active. See functional description for bit 0.
12
IAB_I2C2
I2C2 interrupt active. See functional description for bit 0.
13
-
Reserved. Read value is undefined, only zero should be written.
14
IAB_SSP0
SSP0 interrupt active. See functional description for bit 0.
15
IAB_SSP1
SSP1 interrupt active. See functional description for bit 0.
16
IAB_PLL0
PLL0 (Main PLL) interrupt active. See functional description for bit 0.
17
IAB_RTC
Real Time Clock (RTC) and Event Monitor/Recorder interrupt active. See description of bit 0.
18
IAB_EINT0
External Interrupt 0 interrupt active. See functional description for bit 0.
19
IAB_EINT1
External Interrupt 1 interrupt active. See functional description for bit 0.
20
IAB_EINT2
External Interrupt 2 interrupt active. See functional description for bit 0.
21
IAB_EINT3
External Interrupt 3 interrupt active. See functional description for bit 0.
22
IAB_ADC
ADC interrupt active. See functional description for bit 0.
23
IAB_BOD
BOD interrupt active. See functional description for bit 0.
24
IAB_USB
USB interrupt active. See functional description for bit 0.
25
IAB_CAN
CAN interrupt active. See functional description for bit 0.
26
IAB_DMA
GPDMA interrupt active. See functional description for bit 0.
27
IAB_I2S
I2S interrupt active. See functional description for bit 0.
28
IAB_ENET
Ethernet interrupt active. See functional description for bit 0.
29
IAB_SD
Repetitive Interrupt Timer interrupt active. See functional description for bit 0.
30
IAB_MCPWM
Motor Control PWM interrupt active. See functional description for bit 0.
31
IAB_QEI
Quadrature Encoder Interface interrupt active. See functional description for bit 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
92 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.10 Interrupt Active Bit Register 1
The IABR1 register is a read-only register that allows reading the active state of the
second group of peripheral interrupts. Bits in IABR are set while the corresponding
interrupt service routines are in progress.
Table 61.
Interrupt Active Bit Register 1
Bit
Name
0
IAB_PLL1
Function
PLL1 (Alt PLL) interrupt active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
1
IAB_USBACT
USB Activity interrupt active. See functional description for bit 0.
2
IAB_CANACT
CAN Activity interrupt active. See functional description for bit 0.
3
IAB_UART4
UART4 interrupt active. See functional description for bit 0.
4
IAB_SSP2
SSP2 interrupt active. See functional description for bit 0.
5
IAB_LCD
LCD interrupt active. See functional description for bit 0.
6
IAB_GPIO
GPIO interrupt active. See functional description for bit 0.
7
IAB_PWM0
PWM0 interrupt active. See functional description for bit 0.
8
IAB_EEPROM
EEPROM interrupt active. See functional description for bit 0.
31:9 -
UM10562
User manual
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
93 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.11 Interrupt Priority Register 0
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
Table 62.
Interrupt Priority Register 0
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_WDT
Watchdog Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_TIMER0
Timer 0 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_TIMER1
Timer 1 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_TIMER2
Timer 2 interrupt priority. See functional description for bits 7-3.
5.5.12 Interrupt Priority Register 1
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 63.
Interrupt Priority Register 1
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_TIMER3
Timer 3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_UART0
UART0 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_UART1
UART1 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_UART2
UART2 interrupt priority. See functional description for bits 7-3.
5.5.13 Interrupt Priority Register 2
The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 64.
Interrupt Priority Register 2
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_UART3
UART3 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_PWM1
PWM1 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_I2C0
I2C0 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_I2C1
I2C1 interrupt priority. See functional description for bits 7-3.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
94 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.14 Interrupt Priority Register 3
The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 65.
Interrupt Priority Register 3
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_I2C2
I2C2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 -
Reserved. Read value is undefined, only zero should be written.
18:8
These bits ignore writes, and read as 0.
Unimplemented
23:19 IP_SSP0
SSP0 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_SSP1
SSP1 interrupt priority. See functional description for bits 7-3.
5.5.15 Interrupt Priority Register 4
The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 66.
Interrupt Priority Register 4
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_PLL0
PLL0 (Main PLL) interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_RTC
Real Time Clock (RTC) interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_EINT0
External Interrupt 0 interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_EINT1
External Interrupt 1 interrupt priority. See functional description for bits 7-3.
5.5.16 Interrupt Priority Register 5
The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 67.
Interrupt Priority Register 5
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_EINT2
External Interrupt 2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_EINT3
External Interrupt 3 interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_ADC
ADC interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_BOD
BOD interrupt priority. See functional description for bits 7-3.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
95 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.17 Interrupt Priority Register 6
The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 68.
Interrupt Priority Register 6
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_USB
USB interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_CAN
CAN interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_DMA
GPDMA interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_I2S
I2S interrupt priority. See functional description for bits 7-3.
5.5.18 Interrupt Priority Register 7
The IPR7 register controls the priority of the eighth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 69.
Interrupt Priority Register 7
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_ENET
Ethernet interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_SD
SD Card interface interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_MCPWM
Motor Control PWM interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_QEI
Quadrature Encoder Interface interrupt priority. See functional description for bits 7-3.
5.5.19 Interrupt Priority Register 8
The IPR8 register controls the priority of the ninth and last group of 4 peripheral interrupts.
Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 70.
Interrupt Priority Register 8
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_PLL1
PLL1 (Alt PLL) interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_USBACT
USB Activity interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_CANACT
CAN Activity interrupt priority. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_UART4
UART4 interrupt priority. See functional description for bits 7-3.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
96 of 942
UM10562
NXP Semiconductors
Chapter 5: LPC408x/407x Nested Vectored Interrupt Controller (NVIC)
5.5.20 Interrupt Priority Register 9
The IPR9 register controls the priority of the tenth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 71.
Interrupt Priority Register 9
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_SSP2
SSP2 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
10:8
Unimplemented
These bits ignore writes, and read as 0.
15:11 IP_LCD
LCD controller interrupt priority. See functional description for bits 7-3.
18:16 Unimplemented
These bits ignore writes, and read as 0.
23:19 IP_GPIO
Priority of GPIO interrupts. See functional description for bits 7-3.
26:24 Unimplemented
These bits ignore writes, and read as 0.
31:27 IP_PWM0
PWM0 interrupt priority. See functional description for bits 7-3.
5.5.21 Interrupt Priority Register 10
The IPR10 register controls the priority of the eleventh group of 4 peripheral interrupts.
Each interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 72.
Interrupt Priority Register 10
Bit
Name
Function
2:0
Unimplemented
These bits ignore writes, and read as 0.
7:3
IP_EEPROM
EEPROM programming interrupt. 0 = highest priority. 31 (0x1F) = lowest priority.
31:8
Unimplemented
These bits ignore writes, and read as 0.
5.5.22 Software Trigger Interrupt Register
The STIR register provides an alternate way for software to generate an interrupt, in
addition to using the ISPR registers. This mechanism can only be used to generate
peripheral interrupts, not system exceptions.
By default, only privileged software can write to the STIR register. Unprivileged software
can be given this ability if privileged software sets the USERSETMPEND bit in the CCR
register (see the ARM Cortex-M4 User Guide referred to in Section 40.1 for details).
Table 73.
Software Trigger Interrupt Register
Bit
Name
Function
8:0
INTID
Writing a value to this field generates an interrupt for the specified Interrupt ID (see Table 50).
31:9
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
97 of 942
UM10562
Chapter 6: LPC408x/407x Pin configuration
Rev. 1 — 13 September 2012
User manual
6.1 Pin configuration
For information about the individual LPC408x/407x devices, refer to specific data sheets.
Table 74 lists pins in order by pin name, and includes description of each potential pin
function.
See the IOCON registers (Section 7.4.1) to configure pins for the desired function.
I/O pins are 5V tolerant and have input hysteresis unless otherwise indicated in the table
below. Crystal pins, power pins, and reference voltage pins are not 5V tolerant. In
addition, when pins are selected to be A to D converter inputs, they are no longer 5V
tolerant and must be limited to the voltage at the ADC positive reference pin (VREFP).
Table 74.
Pin description
Symbol
Type
IOCON Description
select[1]
P0[0] to P0[31]
I/O
P0[0]/ CAN_RD1/
U3_TXD/ I2C1_SDA/
U0_TXD
I/O
0
P0[0] — General purpose digital input/output pin.
P0[1]/ CAN1_TD/
U3_RXD/ I2C1_SCL/
U0_RXD
P0[2]/ U0_TXD/
U3_TXD
P0[3]/ U0_RXD/
U3_RXD
UM10562
User manual
Port 0: Port 0 provides up to 32 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
I
1
CAN_RD1 — CAN1 receiver input.
O
2
U3_TXD — Transmitter output for UART 3.
I/O
3
I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I/O
4
U0_TXD — Transmitter output for UART 0.
I/O
0
P0[1] — General purpose digital input/output pin.
O
1
CAN1_TD — CAN1 transmitter output.
I
2
U3_RXD — Receiver input for UART 3.
I/O
3
I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I
4
U0_RXD — Receiver input for UART 0.
I/O
0
P0[2] — General purpose digital input/output pin.
O
1
U0_TXD — Transmitter output for UART 0. Used for ISP communication, see
Section 38.1.
O
2
U3_TXD — Transmitter output for UART 3.
I/O
0
P0[3] — General purpose digital input/output pin.
I
1
U0_RXD — Receiver input for UART 0. Used for ISP communication, see
Section 38.1.
I
2
U3_RXD — Receiver input for UART 3.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
98 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P0[4]/ I2S_RX_SCK/
CAN_RD2/
T2_CAP0/
CMP_ROSC/
LCD_VD[0]
P0[5]/ I2S_RX_WS/
CAN_TD2/
T2_CAP1/
CMP_RESET/
LCD_VD[1]
P0[6]/ I2S_RX_SDA/
SSP1_SSEL/
T2_MAT0/ U1_RTS/
CMP_ROSC/
LCD_VD[8]
P0[7]/ I2S_TX_SCK/
SSP1_SCK/
T2_MAT1/
RTC_EV0/
CMP_VREF/
LCD_VD[9]
P0[8]/ I2S_TX_WS/
SSP1_MISO/
T2_MAT2/
RTC_EV1/
CMP1_IN[4]/
LCD_VD[16]
UM10562
User manual
IOCON Description
select[1]
I/O
0
P0[4] — General purpose digital input/output pin.
I/O
1
I2S_RX_SCK — I2S Receive clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I
2
CAN_RD2 — CAN2 receiver input.
I
3
T2_CAP0 — Capture input for Timer 2, channel 0.
O
5
CMP_ROSC — Comparator relaxation oscillator output.
O
7
LCD_VD[0] — LCD data.
I/O
0
P0[5] — General purpose digital input/output pin.
I/O
1
I2S_RX_WS — I2S Receive word select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
O
2
CAN_TD2 — CAN2 transmitter output.
I
3
T2_CAP1 — Capture input for Timer 2, channel 1.
O
5
CMP_RESET — Comparator reset input.
O
7
LCD_VD[1] — LCD data.
I/O
0
P0[6] — General purpose digital input/output pin.
I/O
1
I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
2
SSP1_SSEL1 — Slave Select for SSP1.
O
3
T2_MAT0 — Match output for Timer 2, channel 0.
O
4
U1_RTS — Request to Send output for UART 1. Can also be configured to be an
RS-485/EIA-485 output enable signal for UART 1.
O
5
CMP_ROSC — Comparator relaxation oscillator output.
O
7
LCD_VD[8] — LCD data.
I/O
0
P0[7] — General purpose digital input/output pin.
I/O
1
I2S_TX_SCK — I2S transmit clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I/O
2
SSP1_SCK — Serial Clock for SSP1.
O
3
T2_MAT1 — Match output for Timer 2, channel 1.
I
4
RTC_EV0 — Event input 0 to Event Monitor/Recorder.
O
5
CMP_VREF — Comparator voltage reference input.
O
7
LCD_VD[9] — LCD data.
I/O
0
P0[8] — General purpose digital input/output pin.
I/O
1
I2S_TX_WS — I2S Transmit word select. It is driven by the master and received by
the slave. Corresponds to the signal WS in the I2S-bus specification.
I/O
2
SSP1_MISO — Master In Slave Out for SSP1.
O
3
T2_MAT2 — Match output for Timer 2, channel 2.
I
4
RTC_EV1 — Event input 1 to Event Monitor/Recorder.
O
5
CMP1_IN[4] — Comparator input.
O
7
LCD_VD[16] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
99 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P0[9]/ I2S_TX_SDA/
SSP1_MOSI/
T2_MAT3/
RTC_EV2/
CMP1_IN[3]/
LCD_VD[17]
P0[10]/ U2_TXD/
I2C2_SDA/
T3_MAT0/
LCD_VD[5]
P0[11]/ U2_RXD/
I2C2_SCL/
T3_MAT1/
LCD_VD[10]
P0[12]/
USB_PPWR2/
SSP1_MISO/ AD0[6]
P0[13]/
USB_UP_LED2/
SSP1_MOSI/ AD0[7]
P0[14]/
USB_HSTEN2/
SSP1_SSEL/
USB_CONNECT2
UM10562
User manual
IOCON Description
select[1]
I/O
0
P0[9] — General purpose digital input/output pin.
I/O
1
I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
I/O
2
SSP1_MOSI — Master Out Slave In for SSP1.
O
3
T2_MAT3 — Match output for Timer 2, channel 3.
I
4
RTC_EV2 — Event input 2 to Event Monitor/Recorder.
O
5
CMP1_IN[3] — Comparator input.
O
7
LCD_VD[17] — LCD data.
I/O
0
P0[10] — General purpose digital input/output pin.
O
1
U2_TXD — Transmitter output for UART 2.
I/O
2
I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
3
T3_MAT0 — Match output for Timer 3, channel 0.
O
7
LCD_VD[5] — LCD data.
I/O
0
P0[11] — General purpose digital input/output pin.
I
1
U2_RXD — Receiver input for UART 2.
I/O
2
I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
3
T3_MAT1 — Match output for Timer 3, channel 1.
O
7
LCD_VD[10] — LCD data.
I/O
0
P0[12] — General purpose digital input/output pin.
O
1
USB_PPWR2 — Port Power enable signal for USB port 2.
I/O
2
SSP1_MISO — Master In Slave Out for SSP1.
I
3
AD0[6] — A/D converter 0, input 6. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
0
P0[13] — General purpose digital input/output pin.
O
1
USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is
configured (non-control endpoints enabled) or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, when
host is enabled and has not detected a device on the bus, or during global suspend.
It toggles between low and high when host is enabled and detects activity on the
bus.
I/O
2
SSP1_MOSI — Master Out Slave In for SSP1.
I
3
AD0[7] — A/D converter 0, input 7. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
0
P0[14] — General purpose digital input/output pin.
O
1
USB_HSTEN2 — Host Enabled status for USB port 2.
I/O
2
SSP1_SSEL — Slave Select for SSP1.
O
3
USB_CONNECT2 — SoftConnect control for USB port 2. The USB_CONNECT pin
indicates when the pull-up resistor must be enabled when running in USB device
mode. If it is used in USB device mode, this function can be implemented by using
another GPIO pin. If the chip is only used in USB host mode, there is no need to use
this pin.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
100 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P0[15]/ U1_TXD/
SSP0_SCK/
SPIFI_IO[2]
P0[16]/ U1_RXD/
SSP0_ SSEL/
SPIFI_IO[3]
P0[17]/ U1_CTS/
SSP0_MISO/
SPIFI_IO[1]
P0[18]/ U1_DCD/
SSP0_MOSI/
SPIFI_IO[0]
P0[19]/ U1_DSR/
SD_CLK/
I2C1_SDA/
LCD_VD[13]
P0[20]/ U1_DTR/
SD_CMD/
I2C1_SCL/
LCD_VD[14]
P0[21]/ U1_RI/
SD_PWR/ U4_OE/
CAN_RD1
UM10562
User manual
IOCON Description
select[1]
I/O
0
P0[15] — General purpose digital input/output pin.
O
1
U1_TXD — Transmitter output for UART 1.
I/O
2
SSP0_SCK — Serial clock for SSP0.
I/O
5
SPIFI_IO[2] — Data bit 2 for SPIFI.
I/O
0
P0 [16] — General purpose digital input/output pin.
I
1
U1_RXD — Receiver input for UART 1.
I/O
2
SSP0_SSEL — Slave Select for SSP0.
I/O
5
SPIFI_IO[3] — Data bit 3 for SPIFI.
I/O
0
P0[17] — General purpose digital input/output pin.
I
1
U1_CTS — Clear to Send input for UART 1.
I/O
2
SSP0_MISO — Master In Slave Out for SSP0.
I/O
5
SPIFI_IO[1] — Data bit 1 for SPIFI.
I/O
0
P0[18] — General purpose digital input/output pin.
I
1
U1_DCD — Data Carrier Detect input for UART 1.
I/O
2
SSP0_MOSI — Master Out Slave In for SSP0.
I/O
5
SPIFI_IO[0] — Data bit 0 for SPIFI.
I/O
0
P0[19] — General purpose digital input/output pin.
I
1
U1_DSR — Data Set Ready input for UART 1.
O
2
SD_CLK — Clock output line for SD card interface.
I/O
3
I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
7
LCD_VD[13] — LCD data.
I/O
0
P0[20] — General purpose digital input/output pin.
O
1
U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be
an RS-485/EIA-485 output enable signal for UART 1.
I/O
2
SD_CMD — Command line for SD card interface.
I/O
3
I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
7
LCD_VD[14] — LCD data.
I/O
0
P0[21] — General purpose digital input/output pin.
I
1
U1_RI — Ring Indicator input for UART 1.
O
2
SD_PWR — Power Supply Enable for external SD card power supply.
O
3
U4_OE — RS-485/EIA-485 output enable signal for UART 4.
I
4
CAN_RD1 — CAN1 receiver input.
I/O
5
U4_SCLK — UART 4 clock input or output in synchronous mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
101 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P0[22]/ U1_RTS/
SD_DAT[0]/
U4_TXD/ CAN_TD1/
SPIFI_CLK
P0[23]/ AD0[0]/
I2S_RX_SCK/
T3_CAP0
P0[24]/ AD0[1]/
I2S_RX_WS/
T3_CAP1
P0[25]/ AD0[2]/
I2S_RX_SDA/
U3_TXD
P0[26]/ AD0[3]/
DAC_OUT/ U3_RXD
P0[27]/ I2C0_SDA/
USB_SDA
P0[28]/ I2C0_SCL/
USB_SCL
P0[29]/ USB_D+1/
EINT0
UM10562
User manual
IOCON Description
select[1]
I/O
0
P0[22] — General purpose digital input/output pin.
O
1
U1_RTS — Request to Send output for UART 1. Can also be configured to be an
RS-485/EIA-485 output enable signal for UART 1.
I/O
2
SD_DAT[0] — Data line 0 for SD card interface.
O
3
U4_TXD — Transmitter output for UART 4 (input/output in smart card mode).
O
4
CAN_TD1 — CAN1 transmitter output.
O
5
SPIFI_CLK — Clock output for SPIFI.
I/O
0
P0[23] — General purpose digital input/output pin.
I
1
AD0[0] — A/D converter 0, input 0. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
2
I2S_RX_SCK — Receive Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
I
3
T3_CAP0 — Capture input for Timer 3, channel 0.
I/O
0
P0[24] — General purpose digital input/output pin.
I
1
AD0[1] — A/D converter 0, input 1. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
2
I2S_RX_WS — Receive Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I2S-bus specification.
I
3
T3_CAP1 — Capture input for Timer 3, channel 1.
I/O
0
P0[25] — General purpose digital input/output pin.
I
1
AD0[2] — A/D converter 0, input 2. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
2
I2S_RX_SDA — Receive data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
O
3
U3_TXD — Transmitter output for UART 3.
I/O
0
P0[26] — General purpose digital input/output pin.
I
1
AD0[3] — A/D converter 0, input 3. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
O
2
DAC_OUT — D/A converter output. When configured as the DAC output, the digital
function of the pin must be disabled (see Section 7.4.1).
I
3
U3_RXD — Receiver input for UART 3.
I/O
0
P0[27] — General purpose digital input/output pin.
I/O
1
I2C0_SDA — I2C0 data input/output. (this pin uses a specialized I2C pad, see
Section 22.1 for details).
I/O
2
USB_SDA — I2C serial data for communication with an external USB transceiver.
I/O
0
P0[28] — General purpose digital input/output pin.
I/O
1
I2C0_SCL0 — I2C0 clock input/output (this pin uses a specialized I2C pad, see
Section 22.1 for details).
I/O
2
USB_SCL — I2C serial clock for communication with an external USB transceiver.
I/O
0
P0[29] — General purpose digital input/output pin. When used as GPIO, P0[29]
shares a direction control with P0[30].
I/O
1
USB_D+1 — USB port 1 bidirectional D+ line.
I
2
EINT0 — External interrupt 0 input.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
102 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P0[30]/ USB_D1/
EINT1
IOCON Description
select[1]
I/O
0
P0[30] — General purpose digital input/output pin. When used as GPIO, P0[30]
shares a direction control with P0[29].
I/O
1
USB_D1 — USB port 1 bidirectional D line.
I
2
EINT1 — External interrupt 1 input.
P0[31]/ USB_D+2
I/O
0
P0[31] — General purpose digital input/output pin.
I/O
1
USB_D+2 — USB port 2 bidirectional D+ line.
P1[0] to P1[31]
I/O
P1[0]/ ENET_TXD0/
T3_CAP1/
SSP2_SCK
I/O
0
P1[0] — General purpose digital input/output pin.
O
1
ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
I
3
T3_CAP1 — Capture input for Timer 3, channel 1.
I/O
4
SSP2_SCK — Serial clock for SSP2.
I/O
0
P1[1] — General purpose digital input/output pin.
P1[1]/ ENET_TXD1/
T3_MAT3/
SSP2_MOSI
P1[2]/ ENET_TXD2/
SD_CLK/ PWM0[1]
P1[3]/ ENET_TXD3/
SD_CMD/ PWM0[2]
P1[4]/
ENET_TX_EN/
T3_MAT2/
SSP2_MISO
P1[5]/
ENET_TX_ER/
SD_PWR/ PWM0[3]/
CMP1_IN[2]
P1[6]/
ENET_TX_CLK/
SD_DAT[0]/
PWM0[4]/
CMP0_IN[4]
UM10562
User manual
Port 1: Port 1 provides up to 32 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
O
1
ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
O
3
T3_MAT3 — Match output for Timer 3, channel 3.
I/O
4
SSP2_MOSI — Master Out Slave In for SSP2.
I/O
0
P1[2] — General purpose digital input/output pin.
O
1
ENET_TXD2 — Ethernet transmit data 2 (MII interface).
O
2
SD_CLK — Clock output line for SD card interface.
O
3
PWM0[1] — Pulse Width Modulator 0, output 1.
I/O
0
P1[3] — General purpose digital input/output pin.
O
1
ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O
2
SD_CMD — Command line for SD card interface.
O
3
PWM0[2] — Pulse Width Modulator 0, output 2.
I/O
0
P1[4] — General purpose digital input/output pin.
O
1
ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).
O
3
T3_MAT2 — Match output for Timer 3, channel 2.
I/O
4
SSP2_MISO — Master In Slave Out for SSP2.
I/O
0
P1[5] — General purpose digital input/output pin.
O
1
ENET_TX_ER — Ethernet Transmit Error (MII interface).
O
2
SD_PWR — Power Supply Enable for external SD card power supply.
O
3
PWM0[3] — Pulse Width Modulator 0, output 3.
O
5
CMP1_IN[2] — Comparator input.
I/O
0
P1[6] — General purpose digital input/output pin.
I
1
ENET_TX_CLK — Ethernet Transmit Clock (MII interface).
I/O
2
SD_DAT[0] — Data line 0 for SD card interface.
O
3
PWM0[4] — Pulse Width Modulator 0, output 4.
O
5
CMP0_IN[4] — Comparator input.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
103 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P1[7]/ ENET_COL/
SD_DAT[1]/
PWM0[5] /
CMP1_IN[1]
IOCON Description
select[1]
I/O
0
P1[7] — General purpose digital input/output pin.
I
1
ENET_COL — Ethernet Collision detect (MII interface).
I/O
2
SD_DAT[1] — Data line 1 for SD card interface.
O
3
PWM0[5] — Pulse Width Modulator 0, output 5.
O
5
CMP1_IN[1] — Comparator input.
I/O
0
P1[8] — General purpose digital input/output pin.
I
1
ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or Ethernet
Carrier Sense/Data Valid (RMII interface).
O
3
T3_MAT1 — Match output for Timer 3, channel 1.
I/O
4
SSP2_SSEL — Slave Select for SSP2.
I/O
0
P1[9] — General purpose digital input/output pin.
I
1
ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
O
3
T3_MAT0 — Match output for Timer 3, channel 0.
P1[10]/
ENET_RXD1/
T3_CAP0
I/O
0
P1[10] — General purpose digital input/output pin.
I
1
ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
I
3
T3_CAP0 — Capture input for Timer 3, channel 0.
P1[11]/
ENET_RXD2/
SD_DAT[2]/
PWM0[6]
I/O
0
P1[11] — General purpose digital input/output pin.
P1[8]/ ENET_CRS
(ENET_CRS_DV)/
T3_MAT1/
SSP2_SSEL
P1[9]/ ENET_RXD0/
T3_MAT0
P1[12]/
ENET_RXD3/
SD_DAT[3]/
PWM0_CAP0/
CMP1_OUT
I
1
ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
I/O
2
SD_DAT[2] — Data line 2 for SD card interface.
O
3
PWM0[6] — Pulse Width Modulator 0, output 6.
I/O
0
P1[12] — General purpose digital input/output pin.
I
1
ENET_RXD3 — Ethernet Receive Data (MII interface).
I/O
2
SD_DAT[3] — Data line 3 for SD card interface.
I
3
PWM0_CAP0 — Capture input for PWM0, channel 0.
O
5
CMP1_OUT — Comparator 1 output.
P1[13]/
ENET_RX_DV
I/O
0
P1[13] — General purpose digital input/output pin.
I
1
ENET_RX_DV — Ethernet Receive Data Valid (MII interface).
P1[14]/
ENET_RX_ER/
T2_CAP0/
CMP0_IN[1]
I/O
0
P1[14] — General purpose digital input/output pin.
I
1
ENET_RX_ER — Ethernet receive error (RMII/MII interface).
P1[15]/
ENET_RX_CLK
(ENET_REF_CLK)/
I2C2_SDA
P1[16]/ ENET_MDC/
I2S_TX_MCLK/
CMP0_IN[2]
UM10562
User manual
I
3
T2_CAP0 — Capture input for Timer 2, channel 0.
O
5
CMP0_IN[1] — Comparator input.
I/O
0
P1[15] — General purpose digital input/output pin.
I
1
ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII interface) or
Ethernet Reference Clock (RMII interface).
I/O
3
I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I/O
0
P1[16] — General purpose digital input/output pin.
O
1
ENET_MDC — Ethernet MIIM clock.
O
2
I2S_TX_MCLK — I2S transmitter master clock output.
O
5
CMP0_IN[2] — Comparator input.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
104 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P1[17]/
ENET_MDIO/
I2S_RX_MCLK/
CMP0_IN[3]
P1[18]/
USB_UP_LED1/
PWM1[1]/ T1_CAP0/
SSP1_MISO
P1[19]/ USB_TX_E1/
USB_PPWR1/
T1_CAP1/ MC_0A/
SSP1_SCK/ U2_OE
P1[20]/
USB_TX_DP1/
PWM1[2]/ QEI_PHA/
MC_FB0/
SSP0_SCK/
LCD_VD[6]/
LCD_VD[10]
P1[21]/
USB_TX_DM1/
PWM1[3]/
SSP0_SSEL/
MC_ABORT/
LCD_VD[7]/
LCD_VD[11]
UM10562
User manual
I/O
IOCON Description
select[1]
0
P1[17] — General purpose digital input/output pin.
I/O
1
ENET_MDIO — Ethernet MIIM data input and output.
O
2
I2S_RX_MCLK — I2S receiver master clock output.
O
5
CMP0_IN[3] — Comparator input.
I/O
0
P1[18] — General purpose digital input/output pin.
O
1
USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is
configured (non-control endpoints enabled) or when host is enabled and has
detected a device on the bus. It is HIGH when the device is not configured, when
host is enabled and has not detected a device on the bus, or during global suspend.
It toggles between low and high when host is enabled and detects activity on the
bus.
O
2
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
I
3
T1_CAP0 — Capture input for Timer 1, channel 0.
I/O
5
SSP1_MISO — Master In Slave Out for SSP1.
I/O
0
P1[19] — General purpose digital input/output pin.
O
1
USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver).
O
2
USB_PPWR1 — Port Power enable signal for USB port 1.
I
3
T1_CAP1 — Capture input for Timer 1, channel 1.
O
4
MC_0A — Motor control PWM channel 0, output A.
I/O
5
SSP1_SCK — Serial clock for SSP1.
O
6
U2_OE — RS-485/EIA-485 output enable signal for UART 2.
I/O
0
P1[20] — General purpose digital input/output pin.
O
1
USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).
O
2
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I
3
QEI_PHA — Quadrature Encoder Interface PHA input.
I
4
MC_FB0 — Motor control PWM channel 0 feedback input.
I/O
5
SSP0_SCK0 — Serial clock for SSP0.
O
6
LCD_VD[6] — LCD data.
O
7
LCD_VD[10] — LCD data.
I/O
0
P1[21] — General purpose digital input/output pin.
O
1
USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).
O
2
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I/O
3
SSP0_SSEL — Slave Select for SSP0.
I
4
MC_ABORT — Motor control PWM, active low fast abort.
O
6
LCD_VD[7] — LCD data.
O
7
LCD_VD[11] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
105 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P1[22]/ USB_RCV1/
USB_PWRD1/
T1_MAT0/ MC_0B/
SSP1_MOSI/
LCD_VD[8]/
LCD_VD[12]
P1[23]/
USB_RX_DP1/
PWM1[4]/ QEI_PHB/
MC_FB1/
SSP0_MISO/
LCD_VD[9]/
LCD_VD[13]
P1[24]/
USB_RX_DM1/
PWM1[5]/ QEI_IDX/
MC_FB2/
SSP0_MOSI/
LCD_VD[10]/
LCD_VD[14]
P1[25]/ USB_LS1/
USB_HSTEN1/
T1_MAT1/ MC_1A/
CLKOUT/
LCD_VD[11]/
LCD_VD[15]
UM10562
User manual
IOCON Description
select[1]
I/O
0
P1[22] — General purpose digital input/output pin.
I
1
USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).
I
2
USB_PWRD1 — Power Status for USB port 1 (host power switch). When using the
chip in USB host mode, the USB_PWRD input must be enabled. The USB host
controller will only detect a device connect event when the port power bit is set in
the OHCI and the USB_PWRD bit is asserted for the corresponding port.
O
3
T1_MAT0 — Match output for Timer 1, channel 0.
O
4
MC_0B — Motor control PWM channel 0, output B.
I/O
5
SSP1_MOSI — Master Out Slave In for SSP1.
O
6
LCD_VD[8] — LCD data.
O
7
LCD_VD[12] — LCD data.
I/O
0
P1[23] — General purpose digital input/output pin.
I
1
USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).
O
2
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I
3
QEI_PHB — Quadrature Encoder Interface PHB input.
I
4
MC_FB1 — Motor control PWM channel 1 feedback input.
I/O
5
SSP0_MISO — Master In Slave Out for SSP0.
O
6
LCD_VD[9] — LCD data.
O
7
LCD_VD[13] — LCD data.
I/O
0
P1[24] — General purpose digital input/output pin.
I
1
USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).
O
2
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I
3
QEI_IDX — Quadrature Encoder Interface INDEX input.
I
4
MC_FB2 — Motor control PWM channel 2 feedback input.
I/O
5
SSP0_MOSI — Master Out Slave in for SSP0.
O
6
LCD_VD[10]/LCD_VD[14] — LCD data.
O
7
LCD_VD[10]/LCD_VD[14] — LCD data.
I/O
0
P1[25] — General purpose digital input/output pin.
O
1
USB_LS1 — Low Speed status for USB port 1 (OTG transceiver).
O
2
USB_HSTEN1 — Host Enabled status for USB port 1.
O
3
T1_MAT1 — Match output for Timer 1, channel 1.
O
4
MC_1A — Motor control PWM channel 1, output A.
O
5
CLKOUT — Selectable clock output.
O
6
LCD_VD[11] — LCD data.
O
7
LCD_VD[15] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
106 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P1[26]/
USB_SSPND1/
PWM1[6]/ T0_CAP0/
MC_1B/
SSP1_SSEL/
LCD_VD[12]/
LCD_VD[20]
P1[27]/ USB_INT1/
USB_OVRCR1/
T0_CAP1/ CLKOUT/
LCD_VD[13]/
LCD_VD[21]
P1[28]/ USB_SCL1/
PWM1_CAP0/
T0_MAT0/ MC_2A/
SSP0_SSEL/
LCD_VD[14]/
LCD_VD[22]
P1[29]/ USB_SDA1/
PWM1_CAP1/
T0_MAT1/ MC_2B/
U4_TXD/
LCD_VD[15]/
LCD_VD[23]
UM10562
User manual
IOCON Description
select[1]
I/O
0
P1[26] — General purpose digital input/output pin.
O
1
USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).
O
2
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
I
3
T0_CAP0 — Capture input for Timer 0, channel 0.
O
4
MC_1B — Motor control PWM channel 1, output B.
I/O
5
SSP1_SSEL — Slave Select for SSP1.
O
6
LCD_VD[12] — LCD data.
O
7
LCD_VD[20] — LCD data.
I/O
0
P1[27] — General purpose digital input/output pin.
I
1
USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).
I
2
USB_OVRCR1 — USB port 1 Over-Current status. The USB_OVRCR pin is used
to set status in the OHCI controller to inform the host firmware that there is an
overcurrent condition. It is possible to use instead a GPIO pin and observe that pin
for overcurrent situations.
I
3
T0_CAP1 — Capture input for Timer 0, channel 1.
O
4
CLKOUT — Selectable clock output.
O
6
LCD_VD[13] — LCD data.
O
7
LCD_VD[21] — LCD data.
I/O
0
P1[28] — General purpose digital input/output pin.
I/O
1
USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver).
I
2
PWM1_CAP0 — Capture input for PWM1, channel 0.
O
3
T0_MAT0 — Match output for Timer 0, channel 0.
O
4
MC_2A — Motor control PWM channel 2, output A.
I/O
5
SSP0_SSEL — Slave Select for SSP0.
O
6
LCD_VD[14] — LCD data.
O
7
LCD_VD[22] — LCD data.
I/O
0
P1[29] — General purpose digital input/output pin.
I/O
1
USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).
I
2
PWM1_CAP1 — Capture input for PWM1, channel 1.
O
3
T0_MAT1 — Match output for Timer 0, channel 1.
O
4
MC_2B — Motor control PWM channel 2, output B.
O
5
U4_TXD — Transmitter output for UART 4 (input/output in smart card mode).
O
6
LCD_VD[15] — LCD data.
O
7
LCD_VD[23] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
107 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P1[30]/
USB_PWRD2/
USB_VBUS/ AD0[4]/
I2C0_SDA/ U3_OE
IOCON Description
select[1]
I/O
0
P1[30] — General purpose digital input/output pin.
I
1
USB_PWRD2 — Power Status for USB port 2. When using the chip in USB host
mode, the USB_PWRD input must be enabled. The USB host controller will only
detect a device connect event when the port power bit is set in the OHCI and the
USB_PWRD bit is asserted for the corresponding port.
I
2
USB_VBUS — Monitors the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
P1[31]/
USB_OVRCR2/
SSP1_SCK/ AD0[5]/
I2C0_SCL
I
3
AD0[4] — A/D converter 0, input 4. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
4
I2C0_SDA — I2C0 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
5
U3_OE — RS-485/EIA-485 output enable signal for UART 3.
I/O
0
P1[31] — General purpose digital input/output pin.
I
1
USB_OVRCR2 — Over-Current status for USB port 2. The USB_OVRCR pin is
used to set status in the OHCI controller to inform the host firmware that there is an
overcurrent condition. It is possible to use instead a GPIO pin and observe that pin
for overcurrent situations.
I/O
2
SSP1_SCK — Serial Clock for SSP1.
I
3
AD0[5] — A/D converter 0, input 5. When configured as an ADC input, the digital
function of the pin must be disabled (see Section 7.4.1).
I/O
4
I2C0_SCL — I2C0 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
P2[0] to P2[31]
I/O
P2[0]/ PWM1[1]/
U1_TXD/ LCD_PWR
I/O
0
P2[0] — General purpose digital input/output pin.
O
1
PWM1[1] — Pulse Width Modulator 1, channel 1 output.
O
2
U1_TXD — Transmitter output for UART 1.
O
7
LCD_PWR — LCD panel power enable.
I/O
0
P2[1] — General purpose digital input/output pin.
O
1
PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I
2
U1_RXD — Receiver input for UART 1.
O
7
LCD_LE — Line end signal.
I/O
0
P2[2] — General purpose digital input/output pin.
O
1
PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I
2
U1_CTS — Clear to Send input for UART 1.
O
3
T2_MAT3 — Match output for Timer 2, channel 3.
O
5
TRACEDATA[3] — Trace data, bit 3.
O
7
LCD_DCLK — LCD panel clock.
P2[1]/ PWM1[2]/
U1_RXD/ LCD_LE
P2[2]/ PWM1[3]/
U1_CTS/ T2_MAT3/
TRACEDATA[3]/
LCD_DCLK
UM10562
User manual
Port 2: Port 2 provides up to 32 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
108 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P2[3]/ PWM1[4]/
U1_DCD/ T2_MAT2/
TRACEDATA[2]/
LCD_FP
P2[4]/ PWM1[5]/
U1_DSR/ T2_MAT1/
TRACEDATA[1]/
LCD_ENAB_M
P2[5]/ PWM1[6]/
U1_DTR/ T2_MAT0/
TRACEDATA[0]/
LCD_LP
P2[6]/ PWM1_CAP0/
U1_RI/ T2_CAP0/
U2_OE/
TRACECLK/
LCD_VD[0]/
LCD_VD[4]
P2[7]/ CAN_RD2/
U1_RTS/ SPIFI_CS/
LCD_VD[1]/
LCD_VD[5]
UM10562
User manual
I/O
IOCON Description
select[1]
0
P2[3] — General purpose digital input/output pin.
O
1
PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I
2
U1_DCD — Data Carrier Detect input for UART 1.
O
3
T2_MAT2 — Match output for Timer 2, channel 2.
O
5
TRACEDATA[2] — Trace data, bit 2.
O
7
LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT).
I/O
0
P2[4] — General purpose digital input/output pin.
O
1
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I
2
U1_DSR — Data Set Ready input for UART 1.
O
3
T2_MAT1 — Match output for Timer 2, channel 1.
O
5
TRACEDATA[1] — Trace data, bit 1.
O
7
LCD_ENAB_M — STN AC bias drive or TFT data enable output.
I/O
0
P2[5] — General purpose digital input/output pin.
O
1
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
O
2
U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be
an RS-485/EIA-485 output enable signal for UART 1.
O
3
T2_MAT0 — Match output for Timer 2, channel 0.
O
5
TRACEDATA[0] — Trace data, bit 0.
O
7
LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse
(TFT).
I/O
0
P2[6] — General purpose digital input/output pin.
I
1
PWM1_CAP0 — Capture input for PWM1, channel 0.
I
2
U1_RI — Ring Indicator input for UART 1.
I
3
T2_CAP0 — Capture input for Timer 2, channel 0.
O
4
U2_OE — RS-485/EIA-485 output enable signal for UART 2.
O
5
TRACECLK — Trace clock.
O
6
LCD_VD[0] — LCD data.
O
7
LCD_VD[4] — LCD data.
I/O
0
P2[7] — General purpose digital input/output pin.
I
1
CAN_RD2 — CAN2 receiver input.
O
2
U1_RTS — Request to Send output for UART 1. Can also be configured to be an
RS-485/EIA-485 output enable signal for UART 1.
O
5
SPIFI_CS — Chip select output for SPIFI.
O
6
LCD_VD[1] — LCD data.
O
7
LCD_VD[5] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
109 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P2[8]/ CAN_TD2/
U2_TXD/ U1_CTS/
ENET_MDC/
LCD_VD[2]/
LCD_VD[6]
P2[9]/
USB_CONNECT1/
U2_RXD/ U4_RXD/
ENET_MDIO/
LCD_VD[3]/
LCD_VD[7]
P2[10]/ EINT0/ NMI
I/O
IOCON Description
select[1]
0
P2[8] — General purpose digital input/output pin.
O
1
CAN_TD2 — CAN2 transmitter output.
O
2
U2_TXD — Transmitter output for UART 2.
I
3
U1_CTS — Clear to Send input for UART 1.
O
4
ENET_MDC — Ethernet MIIM clock.
O
6
LCD_VD[2] — LCD data.
O
7
LCD_VD[6] — LCD data.
I/O
0
P2[9] — General purpose digital input/output pin.
O
1
USB_CONNECT1 — USB1 SoftConnect control. The USB_CONNECT pin
indicates when the pull-up resistor must be enabled when running in USB device
mode. If it is used in USB device mode, this function can be implemented by using
another GPIO pin. If the chip is only used in USB host mode, there is no need to use
this pin.
I
2
U2_RXD — Receiver input for UART 2.
I
3
U4_RXD — Receiver input for UART 4.
I/O
4
ENET_MDIO — Ethernet MIIM data input and output.
I
6
LCD_VD[3] — LCD data.
I
7
LCD_VD[7] — LCD data.
I/O
0
P2[10] — General purpose digital input/output pin. This pin includes a 5 ns input
glitch filter.
Note: A LOW on this pin while RESET is LOW forces the on-chip boot loader to
take over control of the part after a reset and go into ISP mode. See Section 38.3.
P2[11]/ EINT1/
SD_DAT[1]/
I2S_TX_SCK/
LCD_CLKIN
P2[12]/ EINT2/
SD_DAT[2]/
I2S_TX_WS/
LCD_VD[4]/
LCD_VD[3]/
LCD_VD[8]/
LCD_VD[18]
UM10562
User manual
I
1
EINT0 — External interrupt 0 input.
I
2
NMI — Non-maskable interrupt input.
I/O
0
P2[11] — General purpose digital input/output pin. This pin includes a 5 ns input
glitch filter.
I
1
EINT1 — External interrupt 1 input.
I/O
2
SD_DAT[1] — Data line 1 for SD card interface.
I/O
3
I2S_TX_SCK — Transmit Clock. It is driven by the master and received by the
slave. Corresponds to the signal SCK in the I2S-bus specification.
O
7
LCD_CLKIN — LCD clock.
I/O
0
P2[12] — General purpose digital input/output pin. This pin includes a 5 ns input
glitch filter.
I
1
EINT2 — External interrupt 2 input.
I/O
2
SD_DAT[2] — Data line 2 for SD card interface.
I/O
3
I2S_TX_WS — Transmit Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I2S-bus specification.
O
4
LCD_VD[4] — LCD data.
O
5
LCD_VD[3] — LCD data.
O
6
LCD_VD[8] — LCD data.
O
7
LCD_VD[18] — LCD data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
110 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P2[13]/ EINT3/
SD_DAT[3]/
I2S_TX_SDA/
LCD_VD[5]/
LCD_VD[9]/
LCD_VD[19]
P2[14]/ EMC_CS2/
I2C1_SDA/
T2_CAP0
IOCON Description
select[1]
I/O
0
P2[13] — General purpose digital input/output pin. This pin includes a 5 ns input
glitch filter.
I
1
EINT3 — External interrupt 3 input.
I/O
2
SD_DAT[3] — Data line 3 for SD card interface.
I/O
3
I2S_TX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
O
5
LCD_VD[5] — LCD data.
O
6
LCD_VD[9] — LCD data.
O
7
LCD_VD[19] — LCD data.
I/O
0
P2[14] — General purpose digital input/output pin.
O
1
EMC_CS2 — LOW active Chip Select 2 signal.
I/O
2
I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I
3
T2_CAP0 — Capture input for Timer 2, channel 0.
I/O
0
P2[15] — General purpose digital input/output pin.
O
1
EMC_CS3 — LOW active Chip Select 3 signal.
I/O
2
I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I
3
T2_CAP1 — Capture input for Timer 2, channel 1.
I/O
0
P2[16] — General purpose digital input/output pin.
O
1
EMC_CAS — LOW active SDRAM Column Address Strobe.
I/O
0
P2[17] — General purpose digital input/output pin.
O
1
EMC_RAS — LOW active SDRAM Row Address Strobe.
I/O
0
P2[18] — General purpose digital input/output pin.
O
1
EMC_CLK0 — SDRAM clock 0.
I/O
0
P2[19] — General purpose digital input/output pin.
O
1
EMC_CLK1 — SDRAM clock 1.
P2[20]/
EMC_DYCS0
I/O
0
P2[20] — General purpose digital input/output pin.
O
1
EMC_DYCS0 — SDRAM chip select 0.
P2[21]/
EMC_DYCS1
I/O
0
P2[21] — General purpose digital input/output pin.
O
1
EMC_DYCS1 — SDRAM chip select 1.
P2[22]/
EMC_DYCS2/
SSP0_SCK/
T3_CAP0
I/O
0
P2[22] — General purpose digital input/output pin.
O
1
EMC_DYCS2 — SDRAM chip select 2.
I/O
2
SSP0_SCK — Serial clock for SSP0.
I
3
T3_CAP0 — Capture input for Timer 3, channel 0.
I/O
0
P2[23] — General purpose digital input/output pin.
O
1
EMC_DYCS3 — SDRAM chip select 3.
I/O
2
SSP0_SSEL — Slave Select for SSP0.
I
3
T3_CAP1 — Capture input for Timer 3, channel 1.
I/O
0
P2[24] — General purpose digital input/output pin.
O
1
EMC_CKE0 — SDRAM clock enable 0.
P2[15]/ EMC_CS3/
I2C1_SCL/
T2_CAP1
P2[16]/ EMC_CAS
P2[17]/ EMC_RAS
P2[18]/ EMC_CLK0
P2[19]/ EMC_CLK1
P2[23]/
EMC_DYCS3/
SSP0_SSEL/
T3_CAP1
P2[24]/ EMC_CKE0
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
111 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
IOCON Description
select[1]
P2[25]/ EMC_CKE1
I/O
0
P2[25] — General purpose digital input/output pin.
O
1
EMC_CKE1 — SDRAM clock enable 1.
P2[26]/ EMC_CKE2/
SSP0_MISO/
T3_MAT0
I/O
0
P2[26] — General purpose digital input/output pin.
O
1
EMC_CKE2 — SDRAM clock enable 2.
I/O
2
SSP0_MISO — Master In Slave Out for SSP0.
O
3
T3_MAT0 — Match output for Timer 3, channel 0.
P2[27]/ EMC_CKE3/
SSP0_MOSI/
T3_MAT1
I/O
0
P2[27] — General purpose digital input/output pin.
O
1
EMC_CKE3 — SDRAM clock enable 3.
I/O
2
SSP0_MOSI — Master Out Slave In for SSP0.
O
3
T3_MAT1 — Match output for Timer 3, channel 1.
P2[28]/ EMC_DQM0
I/O
0
P2[28] — General purpose digital input/output pin.
O
1
EMC_DQM0 — Data mask 0 used with SDRAM and static devices.
P2[29]/ EMC_DQM1
I/O
0
P2[29] — General purpose digital input/output pin.
O
1
EMC_DQM1 — Data mask 1 used with SDRAM and static devices.
P2[30]/ EMC_DQM2/
I2C2_SDA/
T3_MAT2
I/O
0
P2[30] — General purpose digital input/output pin.
O
1
EMC_DQM2 — Data mask 2 used with SDRAM and static devices.
I/O
2
I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
3
T3_MAT2 — Match output for Timer 3, channel 2.
I/O
0
P2[31] — General purpose digital input/output pin.
O
1
EMC_DQM3 — Data mask 3 used with SDRAM and static devices.
I/O
2
I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
3
T3_MAT3 — Match output for Timer 3, channel 3.
P2[31]/ EMC_DQM3/
I2C2_SCL/
T3_MAT3
P3[0] to P3[31]
I/O
P3[0]/ EMC_D[0]
I/O
0
P3[0] — General purpose digital input/output pin.
I/O
1
EMC_D[0] — External memory data line 0.
I/O
0
P3[1] — General purpose digital input/output pin.
I/O
1
EMC_D[1] — External memory data line 1.
I/O
0
P3[2] — General purpose digital input/output pin.
I/O
1
EMC_D[2] — External memory data line 2.
I/O
0
P3[3] — General purpose digital input/output pin.
I/O
1
EMC_D[3] — External memory data line 3.
I/O
0
P3[4] — General purpose digital input/output pin.
I/O
1
EMC_D[4] — External memory data line 4.
I/O
0
P3[5] — General purpose digital input/output pin.
I/O
1
EMC_D[5] — External memory data line 5.
I/O
0
P3[6] — General purpose digital input/output pin.
I/O
1
EMC_D[6] — External memory data line 6.
P3[1]/ EMC_D[1]
P3[2]/ EMC_D[2]
P3[3]/ EMC_D[3]
P3[4]/ EMC_D[4]
P3[5]/ EMC_D[5]
P3[6]/ EMC_D[6]
UM10562
User manual
Port 3: Port 3 provides up to 32 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
112 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P3[7]/ EMC_D[7]
IOCON Description
select[1]
I/O
0
P3[7] — General purpose digital input/output pin.
I/O
1
EMC_D[7] — External memory data line 7.
I/O
0
P3[8] — General purpose digital input/output pin.
I/O
1
EMC_D[8] — External memory data line 8.
I/O
0
P3[9] — General purpose digital input/output pin.
I/O
1
EMC_D[9] — External memory data line 9.
I/O
0
P3[10] — General purpose digital input/output pin.
I/O
1
EMC_D[10] — External memory data line 10.
P3[11]/ EMC_D[11]
I/O
0
P3[11] — General purpose digital input/output pin.
I/O
1
EMC_D[11] — External memory data line 11.
P3[12]/ EMC_D[12]
I/O
0
P3[12] — General purpose digital input/output pin.
I/O
1
EMC_D[12] — External memory data line 12.
P3[13]/ EMC_D[13]
I/O
0
P3[13] — General purpose digital input/output pin.
I/O
1
EMC_D[13] — External memory data line 13.
P3[14]/ EMC_D[14]
I/O
0
P3[14] — General purpose digital input/output pin.
I/O
1
EMC_D[14] — External memory data line 14. On POR, this pin serves as the
BOOT0 pin (see P3[15] description below.
I/O
0
P3[15] — General purpose digital input/output pin.
I/O
1
EMC_D[15] — External memory data line 15.
P3[8]/ EMC_D[8]
P3[9]/ EMC_D[9]
P3[10]/ EMC_D[10]
P3[15]/ EMC_D[15]
BOOT[1:0] = 00 selects 8-bit external memory on EMC_CS1.
BOOT[1:0] = 01 is reserved. Do not use.
BOOT[1:0] = 10 selects 32-bit external memory on EMC_CS1.
BOOT[1:0] = 11 selects 16-bit external memory on EMC_CS1.
P3[16]/ EMC_D[16]/
PWM0[1]/ U1_TXD
P3[17]/ EMC_D[17]/
PWM0[2]/ U1_RXD
P3[18]/ EMC_D[18]/
PWM0[3]/ U1_CTS
P3[19]/ EMC_D[19]/
PWM0[4]/ U1_DCD
UM10562
User manual
I/O
0
P3[16] — General purpose digital input/output pin.
I/O
1
EMC_D[16] — External memory data line 16.
O
2
PWM0[1] — Pulse Width Modulator 0, output 1.
O
3
U1_TXD — Transmitter output for UART 1.
I/O
0
P3[17] — General purpose digital input/output pin.
I/O
1
EMC_D[17] — External memory data line 17.
O
2
PWM0[2] — Pulse Width Modulator 0, output 2.
I
3
U1_RXD — Receiver input for UART 1.
I/O
0
P3[18] — General purpose digital input/output pin.
I/O
1
EMC_D[18] — External memory data line 18.
O
2
PWM0[3] — Pulse Width Modulator 0, output 3.
I
3
U1_CTS — Clear to Send input for UART 1.
I/O
0
P3[19] — General purpose digital input/output pin.
I/O
1
EMC_D[19] — External memory data line 19.
O
2
PWM0[4] — Pulse Width Modulator 0, output 4.
I
3
U1_DCD — Data Carrier Detect input for UART 1.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
113 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P3[20]/ EMC_D[20]/
PWM0[5]/ U1_DSR
P3[21]/ EMC_D[21]/
PWM0[6]/ U1_DTR
P3[22]/ EMC_D[22]/
PWM0_CAP0/
U1_RI
P3[23]/ EMC_D[23]/
PWM1_CAP0/
T0_CAP0
P3[24]/ EMC_D[24]/
PWM1[1]/ T0_CAP1
P3[25]/ EMC_D[25]/
PWM1[2]/ T0_MAT0
P3[26]/ EMC_D[26]/
PWM1[3]/ T0_MAT1/
STCLK
P3[27]/ EMC_D[27]/
PWM1[4]/ T1_CAP0
P3[28]/ EMC_D[28]/
PWM1[5]/ T1_CAP1
UM10562
User manual
I/O
IOCON Description
select[1]
0
P3[20] — General purpose digital input/output pin.
I/O
1
EMC_D[20] — External memory data line 20.
O
2
PWM0[5] — Pulse Width Modulator 0, output 5.
I
3
U1_DSR — Data Set Ready input for UART 1.
I/O
0
P3[21] — General purpose digital input/output pin.
I/O
1
EMC_D[21] — External memory data line 21.
O
2
PWM0[6] — Pulse Width Modulator 0, output 6.
O
3
U1_DTR — Data Terminal Ready output for UART 1. Can also be configured to be
an RS-485/EIA-485 output enable signal for UART 1.
I/O
0
P3[22] — General purpose digital input/output pin.
I/O
1
EMC_D[22] — External memory data line 22.
I
2
PWM0_CAP0 — Capture input for PWM0, channel 0.
I
3
U1_RI — Ring Indicator input for UART 1.
I/O
0
P3[23] — General purpose digital input/output pin.
I/O
1
EMC_D[23] — External memory data line 23.
I
2
PWM1_CAP0 — Capture input for PWM1, channel 0.
I
3
T0_CAP0 — Capture input for Timer 0, channel 0.
I/O
0
P3[24] — General purpose digital input/output pin.
I/O
1
EMC_D[24] — External memory data line 24.
O
2
PWM1[1] — Pulse Width Modulator 1, output 1.
I
3
T0_CAP1 — Capture input for Timer 0, channel 1.
I/O
0
P3[25] — General purpose digital input/output pin.
I/O
1
EMC_D[25] — External memory data line 25.
O
2
PWM1[2] — Pulse Width Modulator 1, output 2.
O
3
T0_MAT0 — Match output for Timer 0, channel 0.
I/O
0
P3[26] — General purpose digital input/output pin.
I/O
1
EMC_D[26] — External memory data line 26.
O
2
PWM1[3] — Pulse Width Modulator 1, output 3.
O
3
T0_MAT1 — Match output for Timer 0, channel 1.
I
4
STCLK — System tick timer clock input.
I/O
0
P3[27] — General purpose digital input/output pin.
I/O
1
EMC_D[27] — External memory data line 27.
O
2
PWM1[4] — Pulse Width Modulator 1, output 4.
I
3
T1_CAP0 — Capture input for Timer 1, channel 0.
I/O
0
P3[28] — General purpose digital input/output pin.
I/O
1
EMC_D[28] — External memory data line 28.
O
2
PWM1[5] — Pulse Width Modulator 1, output 5.
I
3
T1_CAP1 — Capture input for Timer 1, channel 1.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
114 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P3[29]/ EMC_D[29]/
PWM1[6]/ T1_MAT0
P3[30]/ EMC_D[30]/
U1_RTS/ T1_MAT1
P3[31]/ EMC_D[31]/
T1_MAT2
I/O
IOCON Description
select[1]
0
P3[29] — General purpose digital input/output pin.
I/O
1
EMC_D[29] — External memory data line 29.
O
2
PWM1[6] — Pulse Width Modulator 1, output 6.
O
3
T1_MAT0 — Match output for Timer 1, channel 0.
I/O
0
P3[30] — General purpose digital input/output pin.
I/O
1
EMC_D[30] — External memory data line 30.
O
2
U1_RTS — Request to Send output for UART 1. Can also be configured to be an
RS-485/EIA-485 output enable signal for UART 1.
O
3
T1_MAT1 — Match output for Timer 1, channel 1.
I/O
0
P3[31] — General purpose digital input/output pin.
I/O
1
EMC_D[31] — External memory data line 31.
O
3
T1_MAT2 — Match output for Timer 1, channel 2.
P4[0] to P4[31]
I/O
P4[0]/ EMC_A[0]
I/O
0
P4[0] — ]General purpose digital input/output pin.
I/O
1
EMC_A[0] — External memory address line 0.
I/O
0
P4[1] — General purpose digital input/output pin.
I/O
1
EMC_A[1] — External memory address line 1.
I/O
0
P4[2] — General purpose digital input/output pin.
I/O
1
EMC_A[2] — External memory address line 2.
I/O
0
P4[3] — General purpose digital input/output pin.
I/O
1
EMC_A[3] — External memory address line 3.
I/O
0
P4[4] — General purpose digital input/output pin.
I/O
1
EMC_A[4] — External memory address line 4.
I/O
0
P4[5] — General purpose digital input/output pin.
I/O
1
EMC_A[5] — External memory address line 5.
I/O
0
P4[6] — General purpose digital input/output pin.
I/O
1
EMC_A[6] — External memory address line 6.
I/O
0
P4[7] — General purpose digital input/output pin.
I/O
1
EMC_A[7] — External memory address line 7.
I/O
0
P4[8] — General purpose digital input/output pin.
I/O
1
EMC_A[8] — External memory address line 8.
I/O
0
P4[9] — General purpose digital input/output pin.
I/O
1
EMC_A[9] — External memory address line 9.
I/O
0
P4[10] — General purpose digital input/output pin.
I/O
1
EMC_A[10] — External memory address line 10.
I/O
0
P4[11] — General purpose digital input/output pin.
I/O
1
EMC_A[11] — External memory address line 11.
I/O
0
P4[12] — General purpose digital input/output pin.
I/O
1
EMC_A[12] — External memory address line 12.
P4[1]/ EMC_A[1]
P4[2]/ EMC_A[2]
P4[3]/ EMC_A[3]
P4[4]/ EMC_A[4]
P4[5]/ EMC_A[5]
P4[6]/ EMC_A[6]
P4[7]/ EMC_A[7]
P4[8]/ EMC_A[8]
P4[9]/ EMC_A[9]
P4[10]/ EMC_A[10]
P4[11]/ EMC_A[11]
P4[12]/ EMC_A[12]
UM10562
User manual
Port 4: Port 4 provides up to 32 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
115 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P4[13]/ EMC_A[13]
0
P4[13] — General purpose digital input/output pin.
I/O
1
EMC_A[13] — External memory address line 13.
I/O
0
P4[14] — General purpose digital input/output pin.
I/O
1
EMC_A[14] — External memory address line 14.
I/O
0
P4[15] — General purpose digital input/output pin.
I/O
1
EMC_A[15] — External memory address line 15.
I/O
0
P4[16] — General purpose digital input/output pin.
I/O
1
EMC_A[16] — External memory address line 16.
I/O
0
P4[17] — General purpose digital input/output pin.
I/O
1
EMC_A[17] — External memory address line 17.
I/O
0
P4[18] — General purpose digital input/output pin.
I/O
1
EMC_A[18] — External memory address line 18.
P4[19]/ EMC_A[19]
I/O
0
P4[19] — General purpose digital input/output pin.
I/O
1
EMC_A[19] — External memory address line 19.
P4[20]/ EMC_A[20]/
I2C2_SDA/
SSP1_SCK
I/O
0
P4[20] — General purpose digital input/output pin.
I/O
1
EMC_A[20] — External memory address line 20.
I/O
2
I2C2_SDA — I2C2 data input/output ((this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I/O
3
SSP1_SCK — Serial Clock for SSP1.
I/O
0
P4[21] — General purpose digital input/output pin.
I/O
1
EMC_A[21] — External memory address line 21.
I/O
2
I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
I/O
3
SSP1_SSEL — Slave Select for SSP1.
I/O
0
P4[22] — General purpose digital input/output pin.
I/O
1
EMC_A[22] — External memory address line 22.
O
2
U2_TXD — Transmitter output for UART 2.
I/O
3
SSP1_MISO — Master In Slave Out for SSP1.
I/O
0
P4[23] — General purpose digital input/output pin.
I/O
1
EMC_A[23] — External memory address line 23.
I
2
U2_RXD — Receiver input for UART 2.
I/O
3
SSP1_MOSI — Master Out Slave In for SSP1.
P4[24]/ EMC_OE
I/O
0
P4[24] — General purpose digital input/output pin.
O
1
EMC_OE — LOW active Output Enable signal.
P4[25]/ EMC_WE
I/O
0
P4[25] — General purpose digital input/output pin.
O
1
EMC_WE — LOW active Write Enable signal.
P4[26]/ EMC_BLS0
I/O
0
P4[26] — General purpose digital input/output pin.
O
1
EMC_BLS0 — LOW active Byte Lane select signal 0.
P4[27]/ EMC_BLS1
I/O
0
P4[27] — General purpose digital input/output pin.
O
1
EMC_BLS1 — LOW active Byte Lane select signal 1.
P4[14]/ EMC_A[14]
P4[15]/ EMC_A[15]
P4[16]/ EMC_A[16]
P4[17]/ EMC_A[17]
P4[18]/ EMC_A[18]
P4[21]/ EMC_A[21]/
I2C2_SCL/
SSP1_SSEL
P4[22]/ EMC_A[22]/
U2_TXD/
SSP1_MISO
P4[23]/ EMC_A[23]/
U2_RXD/
SSP1_MOSI
UM10562
User manual
I/O
IOCON Description
select[1]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
116 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
P4[28]/ EMC_BLS2/
U3_TXD/ T2_MAT0/
LCD_VD[6]/
LCD_VD[10]/
LCD_VD[2]
P4[29]/ EMC_BLS3/
U3_RXD/ T2_MAT1/
I2C2_SCL/
LCD_VD[7]/
LCD_VD[11]/
LCD_VD[3]
P4[30]/ EMC_CS0/
CMP0_OUT
P4[31]/ EMC_CS1
IOCON Description
select[1]
I/O
0
P4 [28] — General purpose digital input/output pin.
O
1
EMC_BLS2 — LOW active Byte Lane select signal 2.
O
2
TXD3 — Transmitter output for UART 3.
O
3
T2_MAT0 — Match output for Timer 2, channel 0.
O
5
LCD_VD[6] — LCD data.
O
6
LCD_VD[10] — LCD data.
O
7
LCD_VD[2] — LCD data.
I/O
0
P4[29] — General purpose digital input/output pin.
O
1
EMC_BLS3 — LOW active Byte Lane select signal 3.
I
2
U3_RXD — Receiver input for UART 3.
O
3
T2_MAT1 — Match output for Timer 2, channel 1.
I/O
4
I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad,
see Section 22.1 for details).
O
5
LCD_VD[7] — LCD data.
O
6
LCD_VD[11] — LCD data.
O
7
LCD_VD[3] — LCD data.
I/O
0
P4[30] — General purpose digital input/output pin.
O
1
EMC_CS0 — LOW active Chip Select 0 signal.
O
5
CMP0_OUT — Comparator 0 output.
I/O
0
P4[31] — General purpose digital input/output pin.
O
1
EMC_CS1 — LOW active Chip Select 1 signal.
P5[0] to P5[4]
I/O
P5[0]/ EMC_A[24]/
T2_MAT2
I/O
0
P5[0] — General purpose digital input/output pin.
I/O
1
EMC_A[24] — External memory address line 24.
O
3
T2_MAT2 — Match output for Timer 2, channel 2.
P5[1]/ EMC_A[25]/
T2_MAT3
I/O
0
P5[1] — General purpose digital input/output pin.
I/O
1
EMC_A[25] — External memory address line 25.
O
3
T2_MAT3 — Match output for Timer 2, channel 3.
I/O
0
P5[2] — General purpose digital input/output pin.
O
3
T3_MAT2 — Match output for Timer 3, channel 2.
I/O
5
I2C0_SDA — I2C0 data input/output (this pin uses a specialized I2C pad that
supports I2C Fast Mode Plus).
I/O
0
P5[3] — General purpose digital input/output pin.
I
4
U4_RXD — Receiver input for UART 4.
I/O
5
I2C0_SCL0 — I2C0 clock input/output (this pin uses a specialized I2C pad that
supports I2C Fast Mode Plus.
I/O
0
P5[4] — General purpose digital input/output pin.
O
1
U0_OE — RS-485/EIA-485 output enable signal for UART 0.
O
3
T3_MAT3 — Match output for Timer 3, channel 3.
O
4
U4_TXD — Transmitter output for UART 4 (input/output in smart card mode).
P5[2]/ T3_MAT2/
I2C0_SDA
P5[3]/ U4_RXD/
I2C0_SCL
P5[4]/ U0_OE/
T3_MAT3/ U4_TXD
UM10562
User manual
Port 5: Port 5 provides up to 5 I/O pins, depending on the package. Each pin has
individual direction control, pin mode configuration, and function selection.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
117 of 942
UM10562
NXP Semiconductors
Chapter 6: LPC408x/407x Pin configuration
Table 74.
Pin description …continued
Symbol
Type
IOCON Description
select[1]
RTC_ALARM
O
RTC_ALARM — RTC controlled output. This pin has a low drive strength and is
powered by VBAT (see data sheet for details). It is driven high when an RTC alarm is
generated.
USB_D2
I/O
USB_D2 — USB port 2 bidirectional D line.
JTAG_TDO (SWO)
O
JTAG_TDO — Test Data Out for JTAG interface.
SWO — Serial wire trace output.
JTAG_TDI
I
TDI — Test Data In for JTAG interface. This pin includes an internal pull-up, see
Section 39.1.
JTAG_TMS
(SWDIO)
I
TMS — Test Mode Select for JTAG interface. This pin includes an internal pull-up,
see Section 39.1.
SWDIO — Serial wire debug data input/output.
JTAG_TRST
I
TRST — Test Reset for JTAG interface. This pin includes an internal pull-up, see
Section 39.1.
JTAG_TCK
(SWDCLK)
I
TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the
CPU clock (CCLK) for the JTAG interface to operate.
SWDCLK — Serial wire clock.
RSTOUT
O
Reset status output. A LOW output on this pin indicates that the device is in the
reset state, for any reason. This reflects the RESET input pin and all internal reset
sources.
RESET
I
External reset input. A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. This pin includes a 20 ns input glitch filter.
XTAL1[2]
I
Input to the oscillator circuit and internal clock generator circuits.
XTAL2[2]
O
Output from the oscillator amplifier.
RTCX1[2]
I
Input to the RTC 32 kHz ultra-low power oscillator circuit.
RTCX2[2]
O
Output from the RTC 32 kHz ultra-low power oscillator circuit.
[2]
I
ground: 0 V reference for digital IO pins.
VSSREG[2]
I
ground: 0 V reference for internal logic.
I
analog ground: 0 V power supply and reference for the ADC and DAC. This should
be the same voltage as VSS, but should be isolated to minimize noise and error.
VDD(3V3)[2]
I
3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the
Vbat domain.
VDD(REG)(3V3)[2]
I
3.3 V regulator supply voltage: This is the power supply for the on-chip voltage
regulator that supplies internal logic.
VDDA[2]
I
analog 3.3 V pad supply voltage: This can be connected to the same supply as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC. Note: this pin should be tied to 3.3V if the ADC and
DAC are not used.
VREFP[2]
I
ADC positive reference voltage: This should be the same voltage as VDDA, but
should be isolated to minimize noise and error. The voltage level on this pin is used
as a reference for ADC and DAC. Note: this pin should be tied to 3.3V if the ADC
and DAC are not used.
VBAT[2]
I
RTC power supply: 3.3 V on this pin supplies power to the RTC.
VSS
VSSA
[2]
[1]
These values are used in the FUNC field of the IOCON registers, described in Section 7.4.1.
[2]
These pins provide special analog functionality.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
118 of 942
UM10562
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
User manual
7.1 Introduction
A separate register is provided to configure each GPIO pin. This configuration includes
which internal function is connected to the pin, the output mode (plain, pull-up, pull-down,
or repeater), open drain mode control, hysteresis enable, slew rate control, and buffer
setup for analog functions. Some pins include additional special controls, such as for I2C
buffer modes. These registers are summarized in Table 75.
Table 75.
Port
Summary of I/O pin configuration registers
Registers
Detail Table
IOCON_P0_nn, where nn is the port pin number, from 0 to 31
[1]
Table 76
Port 1 pins
IOCON_P1_nn, where nn is the port pin number, from 0 to 31
[1]
Table 77
Port 2 pins
IOCON_P2_nn, where nn is the port pin number, from 0 to 31 [1]
Table 78
Port 3 pins
IOCON_P3_nn, where nn is the port pin number, from 0 to 31
[1]
Table 79
IOCON_P4_nn, where nn is the port pin number, from 0 to 31
[1]
Table 80
Port 0 pins
Port 4 pins
Port 5 pins
[1]
IOCON_P5_nn, where nn is the port pin number, from 0 to 4
[1]
Table 81
Which pins are available depends on the part number and package combination.
7.2 Description
The pin connect block allows most pins of the microcontroller to have more than one
potential function. Configuration registers control the multiplexers to allow connection
between the pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin excludes other peripheral functions available
on the same pin. However, the GPIO input stays connected and may be read by software
or used to contribute to the GPIO interrupt feature.
7.3 IOCON registers
The IOCON registers control the functions of device pins. Each GPIO pin has a dedicated
control register to select its function and characteristics. Each pin has a unique set of
functional capabilities. Not all pin characteristics are selectable on all pins. For instance,
pins that have an I2C function can be configured for different I2C-bus modes, while pins
that have an analog alternate function have an analog mode can be selected.Details of
the IOCON registers are in Section 7.4.1. The following sections describe specific
characteristics of pins.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
119 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Multiple connections
Since a particular peripheral function may be allowed on more than one pin, it is possible
to configure more than one pin to perform the same function. If a peripheral output
function is configured to appear on more than one pin, it will in fact be routed to those
pins. If a peripheral input function is defined as coming from more than one source, the
values will be logically combined, possibly resulting in incorrect peripheral operation.
Therefore care should be taken to avoid this situation.
VDD
open-drain enable
strong
pull-up
output enable
pin configured
as digital output
VDD
ESD
data output
Px[y]
strong
pull-down
ESD
VDD
weak
pull-up
pull-up enable
repeater
mode enable
weak
pull-down
pull-down enable
pin configured
as digital input
digital
input
10 ns
glitch filter
enable
input invert
enable
glitch filter
pin configured
as analog input
enable
analog input
analog
input
100818
Fig 14. I/O configurations
7.3.1 Pin function
The FUNC bits in the IOCON registers can be set to GPIO (typically value 000) or to a
special function. For pins set to GPIO, the FIOnDIR registers determine whether the pin is
configured as an input or output (see Section 8.5.1.1). For any special function, the pin
direction is controlled automatically depending on the function. The FIOnDIR registers
have no effect for special functions.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
120 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.3.2 Pin mode
The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down
resistors for each pin or select the repeater mode.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is high and enables the
pull-down resistor if the pin is low. This causes the pin to retain its last known state if it is
configured as an input and is not driven externally. Such state retention is not applicable to
the Deep Power-down mode. Repeater mode may typically be used to prevent a pin from
floating (and potentially using significant power if it floats to an indeterminate state) if it is
temporarily not driven.
7.3.3 Hysteresis
The input buffer for digital functions can be configured with or without hysteresis. See the
appropriate specific device data sheet for quantitative details.
7.3.4 Input Inversion
This option is included to save users from having to include an external inverter on an
input that is only available in the opposite polarity from an external source. Do not set this
option on a GPIO output. Doing so can result in inadvertent toggling of an output with
input inversion selected, as a result of operations on other pins in the same port. For
example, if software reads a GPIO Port register, modifies other bits/outputs in the value,
and writes the result back to the Port register, any output in the port that has input
inversion selected will change state.
7.3.5 Analog/digital mode
In Analog mode, the analog input connection is enabled. In digital mode, the analog input
connection is disabled. This protects the analog input from voltages outside the range of
the analog power supply and reference that may sometimes be present on digital pins,
since they are typically 5V tolerant.
If Analog mode is selected, the MODE field should be “Inactive” (00); the HYS, INV,
FILTR, SLEW, and OD settings have no effect. For an unconnected pin that has an analog
function, keep the ADMODE bit set to 1 (digital mode), and pull-up or pull-down mode
selected in the MODE field.
7.3.6 Input filter
Type A and W pins include a filter that can be selectively enabled. The filter suppresses
input pulses smaller than about 10 ns.
7.3.7 Output slew rate
The SLEW bits of digital outputs that do not need to switch state very quickly should be
set to “standard”. This setting allows multiple outputs to switch simultaneously without
noticeably degrading the power/ground distribution of the device, and has only a small
effect on signal transition time. This is particularly important if analog accuracy is
significant to the application. See the relevant specific device data sheet for more details.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
121 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.3.8 I2C modes
Pins that support I2C with specialized pad electronics (P0[27], P0[28], P5[2], and P5[3])
have additional configuration bits. These are not hardwired so that the pins can be more
easily used for non-I2C functions.
The HS bit applies to standard, Fast-mode, and Fast-mode Plus I2C, and is available for
all the pins noted above.
The HIDRIVE bit applies only to pins P5[2] and P5[3], and is used to select between
Standard mode and Fast-mode I2C or Fast-mode Plus I2C.
• For any I2C mode, clear the HS bit so that the input glitch filter is enabled. Clear the
HIDRIVE bit if it exists for that pin to select the correct drive strength for Standard
mode or Fast-mode I2C
• For Fast-mode Plus I2C operation, set the HIDRIVE bit to select the correct drive
strength for Fast-mode Plus I2C.
• For non-I2C operation, these pins remain open-drain and can only drive low,
regardless of how HS and HIDRIVE are set. They would typically be used with an
external pull-up resistor if they are used as outputs unless they are used only to sink
current. Leave HS = 1 and HIDRIVE = 0 (if applicable) to maximize compatibility with
other GPIO pins.
7.3.9 Open-Drain Mode
When output is selected, either by selecting a special function in the FUNC field, or by
selecting the GPIO function for a pin having a 1 in its FIOnDIR register, a 1 in the OD bit
selects open-drain operation, that is, a 1 disables the high-drive transistor. This option has
no effect on the primary I2C pins. Note that the properties of a pin in this simulated
open-drain mode are somewhat different than those of a true open drain output.
7.3.10 DAC enable
The pin that includes the DAC output as a potential function includes an enable for the
function that must be set if the DAC output is used.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
122 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4 Register description
The pin connect block contains an I/O Control register (IOCON) for each pin that has
programmable attributes, and selects peripheral functions associated with that pin. These
registers are shown by GPIO port number in Tables 7–76 through 7–81.
Table 76.
I/O Control registers for port 0
Access
Reset
Value[1]
Address
IOCON type[2]
IOCON_P0_00
R/W
0x030
0x4002 C000
D (tables 82, 83)
x
x
x
x
P0[1]
IOCON_P0_01
R/W
0x030
0x4002 C004
D (tables 82, 83)
x
x
x
x
P0[2]
IOCON_P0_02
R/W
0x030
0x4002 C008
D (tables 82, 83)
x
x
x
x
P0[3]
IOCON_P0_03
R/W
0x030
0x4002 C00C
D (tables 82, 83)
x
x
x
x
P0[4]
IOCON_P0_04
R/W
0x030
0x4002 C010
D (tables 82, 83)
x
x
x
-
P0[5]
IOCON_P0_05
R/W
0x030
0x4002 C014
D (tables 82, 83)
x
x
x
-
P0[6]
IOCON_P0_06
R/W
0x030
0x4002 C018
D (tables 82, 83)
x
x
x
x
P0[7]
IOCON_P0_07
R/W
0x0A0
0x4002 C01C
W (tables 90, 91)
x
x
x
x
P0[8]
IOCON_P0_08
R/W
0x0A0
0x4002 C020
W (tables 90, 91)
x
x
x
x
P0[9]
IOCON_P0_09
R/W
0x0A0
0x4002 C024
W (tables 90, 91)
x
x
x
x
P0[10]
IOCON_P0_10
R/W
0x030
0x4002 C028
D (tables 82, 83)
x
x
x
x
P0[11]
IOCON_P0_11
R/W
0x030
0x4002 C02C
D (tables 82, 83)
x
x
x
x
P0[12]
IOCON_P0_12
R/W
0x1B0
0x4002 C030
A (tables 84, 85)
x
x
x
-
Port
pin
Register
P0[0]
208-pin 180-pin 144-pin
80-pin
P0[13]
IOCON_P0_13
R/W
0x1B0
0x4002 C034
A (tables 84, 85)
x
x
x
-
P0[14]
IOCON_P0_14
R/W
0x030
0x4002 C038
D (tables 82, 83)
x
x
x
-
P0[15]
IOCON_P0_15
R/W
0x030
0x4002 C03C
D (tables 82, 83)
x
x
x
x
P0[16]
IOCON_P0_16
R/W
0x030
0x4002 C040
D (tables 82, 83)
x
x
x
x
P0[17]
IOCON_P0_17
R/W
0x030
0x4002 C044
D (tables 82, 83)
x
x
x
x
P0[18]
IOCON_P0_18
R/W
0x030
0x4002 C048
D (tables 82, 83)
x
x
x
x
P0[19]
IOCON_P0_19
R/W
0x030
0x4002 C04C
D (tables 82, 83)
x
x
x
-
P0[20]
IOCON_P0_20
R/W
0x030
0x4002 C050
D (tables 82, 83)
x
x
x
-
P0[21]
IOCON_P0_21
R/W
0x030
0x4002 C054
D (tables 82, 83)
x
x
x
-
P0[22]
IOCON_P0_22
R/W
0x030
0x4002 C058
D (tables 82, 83)
x
x
x
x
P0[23]
IOCON_P0_23
R/W
0x1B0
0x4002 C05C
A (tables 84, 85)
x
x
x
-
P0[24]
IOCON_P0_24
R/W
0x1B0
0x4002 C060
A (tables 84, 85)
x
x
x
-
P0[25]
IOCON_P0_25
R/W
0x1B0
0x4002 C064
A (tables 84, 85)
x
x
x
x
P0[26]
IOCON_P0_26
R/W
0x1B0
0x4002 C068
A (tables 84, 85)
x
x
x
x
P0[27]
IOCON_P0_27
R/W
0
0x4002 C06C
I (tables 88, 89)
x
x
x
-
P0[28]
IOCON_P0_28
R/W
0
0x4002 C070
I (tables 88, 89)
x
x
x
-
P0[29]
IOCON_P0_29
R/W
0
0x4002 C074
U (tables 86, 87)
x
x
x
x
P0[30]
IOCON_P0_30
R/W
0
0x4002 C078
U (tables 86, 87)
x
x
x
x
P0[31]
IOCON_P0_31
R/W
0
0x4002 C07C
U (tables 86, 87)
x
x
x
-
UM10562
User manual
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
[2]
IOCON types are D (standard digital pin), and other pins with a specialized function: A (analog), U (USB), I
(I2C), and W.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
123 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 77.
I/O Control registers for port 1
Port
pin
Register
Access
Reset
Value[1]
Address
IOCON type
P1[0]
208-pin 180-pin 144-pin
80-pin
IOCON_P1_00
R/W
0x030
0x4002 C080
D (tables 82, 83)
x
x
x
x
P1[1]
IOCON_P1_01
R/W
0x030
0x4002 C084
D (tables 82, 83)
x
x
x
x
P1[2]
IOCON_P1_02
R/W
0x030
0x4002 C088
D (tables 82, 83)
x
x
-
-
P1[3]
IOCON_P1_03
R/W
0x030
0x4002 C08C
D (tables 82, 83)
x
x
-
-
P1[4]
IOCON_P1_04
R/W
0x030
0x4002 C090
D (tables 82, 83)
x
x
x
x
P1[5]
IOCON_P1_05
R/W
0x030
0x4002 C094
W (tables 90, 91)
x
x
-
-
P1[6]
IOCON_P1_06
R/W
0x030
0x4002 C098
W (tables 90, 91)
x
x
-
-
P1[7]
IOCON_P1_07
R/W
0x030
0x4002 C09C
W (tables 90, 91)
x
x
-
-
P1[8]
IOCON_P1_08
R/W
0x030
0x4002 C0A0
D (tables 82, 83)
x
x
x
x
P1[9]
IOCON_P1_09
R/W
0x030
0x4002 C0A4
D (tables 82, 83)
x
x
x
x
P1[10]
IOCON_P1_10
R/W
0x030
0x4002 C0A8
D (tables 82, 83)
x
x
x
x
P1[11]
IOCON_P1_11
R/W
0x030
0x4002 C0AC
D (tables 82, 83)
x
x
-
-
P1[12]
IOCON_P1_12
R/W
0x030
0x4002 C0B0
D (tables 82, 83)
x
x
-
-
P1[13]
IOCON_P1_13
R/W
0x030
0x4002 C0B4
D (tables 82, 83)
x
x
-
-
P1[14]
IOCON_P1_14
R/W
0x030
0x4002 C0B8
W (tables 90, 91)
x
x
x
x
P1[15]
IOCON_P1_15
R/W
0x030
0x4002 C0BC
D (tables 82, 83)
x
x
x
x
P1[16]
IOCON_P1_16
R/W
0x030
0x4002 C0C0
W (tables 90, 91)
x
x
x
-
P1[17]
IOCON_P1_17
R/W
0x030
0x4002 C0C4
W (tables 90, 91)
x
x
x
-
P1[18]
IOCON_P1_18
R/W
0x030
0x4002 C0C8
D (tables 82, 83)
x
x
x
x
P1[19]
IOCON_P1_19
R/W
0x030
0x4002 C0CC
D (tables 82, 83)
x
x
x
x
P1[20]
IOCON_P1_20
R/W
0x030
0x4002 C0D0
D (tables 82, 83)
x
x
x
x
P1[21]
IOCON_P1_21
R/W
0x030
0x4002 C0D4
D (tables 82, 83)
x
x
x
-
P1[22]
IOCON_P1_22
R/W
0x030
0x4002 C0D8
D (tables 82, 83)
x
x
x
x
P1[23]
IOCON_P1_23
R/W
0x030
0x4002 C0DC
D (tables 82, 83)
x
x
x
x
P1[24]
IOCON_P1_24
R/W
0x030
0x4002 C0E0
D (tables 82, 83)
x
x
x
x
P1[25]
IOCON_P1_25
R/W
0x030
0x4002 C0E4
D (tables 82, 83)
x
x
x
x
P1[26]
IOCON_P1_26
R/W
0x030
0x4002 C0E8
D (tables 82, 83)
x
x
x
x
P1[27]
IOCON_P1_27
R/W
0x030
0x4002 C0EC
D (tables 82, 83)
x
x
x
-
P1[28]
IOCON_P1_28
R/W
0x030
0x4002 C0F0
D (tables 82, 83)
x
x
x
x
P1[29]
IOCON_P1_29
R/W
0x030
0x4002 C0F4
D (tables 82, 83)
x
x
x
x
P1[30]
IOCON_P1_30
R/W
0x1B0
0x4002 C0F8
A (tables 84, 85)
x
x
x
x
P1[31]
IOCON_P1_31
R/W
0x1B0
0x4002 C0FC
A (tables 84, 85)
x
x
x
x
[1]
UM10562
User manual
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
124 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 78.
I/O Control registers for port 2
Port
pin
Register
Access
Reset
Value[1]
Address
IOCON type
P2[0]
IOCON_P2_00
R/W
0x030
0x4002 C100
D (tables 82, 83)
x
x
x
x
P2[1]
IOCON_P2_01
R/W
0x030
0x4002 C104
D (tables 82, 83)
x
x
x
x
P2[2]
IOCON_P2_02
R/W
0x030
0x4002 C108
D (tables 82, 83)
x
x
x
x
P2[3]
IOCON_P2_03
R/W
0x030
0x4002 C10C
D (tables 82, 83)
x
x
x
x
P2[4]
IOCON_P2_04
R/W
0x030
0x4002 C110
D (tables 82, 83)
x
x
x
x
P2[5]
IOCON_P2_05
R/W
0x030
0x4002 C114
D (tables 82, 83)
x
x
x
x
P2[6]
IOCON_P2_06
R/W
0x030
0x4002 C118
D (tables 82, 83)
x
x
x
x
P2[7]
IOCON_P2_07
R/W
0x030
0x4002 C11C
D (tables 82, 83)
x
x
x
x
P2[8]
IOCON_P2_08
R/W
0x030
0x4002 C120
D (tables 82, 83)
x
x
x
x
P2[9]
IOCON_P2_09
R/W
0x030
0x4002 C124
D (tables 82, 83)
x
x
x
x
P2[10]
IOCON_P2_10
R/W
0x030
0x4002 C128
D (tables 82, 83)
x
x
x
x
P2[11]
IOCON_P2_11
R/W
0x030
0x4002 C12C
D (tables 82, 83)
x
x
x
-
P2[12]
IOCON_P2_12
R/W
0x030
0x4002 C130
D (tables 82, 83)
x
x
x
-
P2[13]
IOCON_P2_13
R/W
0x030
0x4002 C134
D (tables 82, 83)
x
x
x
-
P2[14]
IOCON_P2_14
R/W
0x030
0x4002 C138
D (tables 82, 83)
x
-
-
-
P2[15]
IOCON_P2_15
R/W
0x030
0x4002 C13C
D (tables 82, 83)
x
-
-
-
P2[16]
IOCON_P2_16
R/W
0x030
0x4002 C140
D (tables 82, 83)
x
x
-
-
P2[17]
IOCON_P2_17
R/W
0x030
0x4002 C144
D (tables 82, 83)
x
x
-
-
P2[18]
IOCON_P2_18
R/W
0x030
0x4002 C148
D (tables 82, 83)
x
x
-
-
P2[19]
IOCON_P2_19
R/W
0x030
0x4002 C14C
D (tables 82, 83)
x
x
-
-
P2[20]
IOCON_P2_20
R/W
0x030
0x4002 C150
D (tables 82, 83)
x
x
-
-
P2[21]
IOCON_P2_21
R/W
0x030
0x4002 C154
D (tables 82, 83)
x
x
-
-
P2[22]
IOCON_P2_22
R/W
0x030
0x4002 C158
D (tables 82, 83)
x
-
-
-
P2[23]
IOCON_P2_23
R/W
0x030
0x4002 C15C
D (tables 82, 83)
x
-
-
-
P2[24]
IOCON_P2_24
R/W
0x030
0x4002 C160
D (tables 82, 83)
x
x
-
-
P2[25]
IOCON_P2_25
R/W
0x030
0x4002 C164
D (tables 82, 83)
x
x
-
-
P2[26]
IOCON_P2_26
R/W
0x030
0x4002 C168
D (tables 82, 83)
x
-
-
-
P2[27]
IOCON_P2_27
R/W
0x030
0x4002 C16C
D (tables 82, 83)
x
-
-
-
P2[28]
IOCON_P2_28
R/W
0x030
0x4002 C170
D (tables 82, 83)
x
x
-
-
P2[29]
IOCON_P2_29
R/W
0x030
0x4002 C174
D (tables 82, 83)
x
x
-
-
P2[30]
IOCON_P2_30
R/W
0x030
0x4002 C178
D (tables 82, 83)
x
-
-
-
P2[31]
IOCON_P2_31
R/W
0x030
0x4002 C17C
D (tables 82, 83)
x
-
-
-
[1]
UM10562
User manual
208-pin 180-pin 144-pin
80-pin
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
125 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 79.
I/O Control registers for port 3
Port
pin
Register
Access
Reset
Value[1]
Address
IOCON type
P3[0]
IOCON_P3_00
R/W
0x030
0x4002 C180
D (tables 82, 83)
x
x
x
-
P3[1]
IOCON_P3_01
R/W
0x030
0x4002 C184
D (tables 82, 83)
x
x
x
-
P3[2]
IOCON_P3_02
R/W
0x030
0x4002 C188
D (tables 82, 83)
x
x
x
-
P3[3]
IOCON_P3_03
R/W
0x030
0x4002 C18C
D (tables 82, 83)
x
x
x
-
P3[4]
IOCON_P3_04
R/W
0x030
0x4002 C190
D (tables 82, 83)
x
x
x
-
P3[5]
IOCON_P3_05
R/W
0x030
0x4002 C194
D (tables 82, 83)
x
x
x
-
P3[6]
IOCON_P3_06
R/W
0x030
0x4002 C198
D (tables 82, 83)
x
x
x
-
P3[7]
IOCON_P3_07
R/W
0x030
0x4002 C19C
D (tables 82, 83)
x
x
x
-
P3[8]
IOCON_P3_08
R/W
0x030
0x4002 C1A0
D (tables 82, 83)
x
x
-
-
P3[9]
IOCON_P3_09
R/W
0x030
0x4002 C1A4
D (tables 82, 83)
x
x
-
-
P3[10]
IOCON_P3_10
R/W
0x030
0x4002 C1A8
D (tables 82, 83)
x
x
-
-
P3[11]
IOCON_P3_11
R/W
0x030
0x4002 C1AC
D (tables 82, 83)
x
x
-
-
P3[12]
IOCON_P3_12
R/W
0x030
0x4002 C1B0
D (tables 82, 83)
x
x
-
-
P3[13]
IOCON_P3_13
R/W
0x030
0x4002 C1B4
D (tables 82, 83)
x
x
-
-
P3[14]
IOCON_P3_14
R/W
0x030
0x4002 C1B8
D (tables 82, 83)
x
x
-
-
P3[15]
IOCON_P3_15
R/W
0x030
0x4002 C1BC
D (tables 82, 83)
x
x
-
-
P3[16]
IOCON_P3_16
R/W
0x030
0x4002 C1C0
D (tables 82, 83)
x
-
-
-
P3[17]
IOCON_P3_17
R/W
0x030
0x4002 C1C4
D (tables 82, 83)
x
-
-
-
P3[18]
IOCON_P3_18
R/W
0x030
0x4002 C1C8
D (tables 82, 83)
x
-
-
-
P3[19]
IOCON_P3_19
R/W
0x030
0x4002 C1CC
D (tables 82, 83)
x
-
-
-
P3[20]
IOCON_P3_20
R/W
0x030
0x4002 C1D0
D (tables 82, 83)
x
-
-
-
P3[21]
IOCON_P3_21
R/W
0x030
0x4002 C1D4
D (tables 82, 83)
x
-
-
-
P3[22]
IOCON_P3_22
R/W
0x030
0x4002 C1D8
D (tables 82, 83)
x
-
-
-
P3[23]
IOCON_P3_23
R/W
0x030
0x4002 C1DC
D (tables 82, 83)
x
x
x
-
P3[24]
IOCON_P3_24
R/W
0x030
0x4002 C1E0
D (tables 82, 83)
x
x
x
-
P3[25]
IOCON_P3_25
R/W
0x030
0x4002 C1E4
D (tables 82, 83)
x
x
x
-
P3[26]
IOCON_P3_26
R/W
0x030
0x4002 C1E8
D (tables 82, 83)
x
x
x
-
P3[27]
IOCON_P3_27
R/W
0x030
0x4002 C1EC
D (tables 82, 83)
x
-
-
-
P3[28]
IOCON_P3_28
R/W
0x030
0x4002 C1F0
D (tables 82, 83)
x
-
-
-
P3[29]
IOCON_P3_29
R/W
0x030
0x4002 C1F4
D (tables 82, 83)
x
-
-
-
P3[30]
IOCON_P3_30
R/W
0x030
0x4002 C1F8
D (tables 82, 83)
x
-
-
-
P3[31]
IOCON_P3_31
R/W
0x030
0x4002 C1FC
D (tables 82, 83)
x
-
-
-
[1]
UM10562
User manual
208-pin 180-pin 144-pin
80-pin
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
126 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 80.
I/O Control registers for port 4
Port
pin
Register
Access
Reset
Value[1]
Address
IOCON type
P4[0]
IOCON_P4_00
R/W
0x030
0x4002 C200
D (tables 82, 83)
x
x
x
-
P4[1]
IOCON_P4_01
R/W
0x030
0x4002 C204
D (tables 82, 83)
x
x
x
-
P4[2]
IOCON_P4_02
R/W
0x030
0x4002 C208
D (tables 82, 83)
x
x
x
-
P4[3]
IOCON_P4_03
R/W
0x030
0x4002 C20C
D (tables 82, 83)
x
x
x
-
P4[4]
IOCON_P4_04
R/W
0x030
0x4002 C210
D (tables 82, 83)
x
x
x
-
P4[5]
IOCON_P4_05
R/W
0x030
0x4002 C214
D (tables 82, 83)
x
x
x
-
P4[6]
IOCON_P4_06
R/W
0x030
0x4002 C218
D (tables 82, 83)
x
x
x
-
P4[7]
IOCON_P4_07
R/W
0x030
0x4002 C21C
D (tables 82, 83)
x
x
x
-
P4[8]
IOCON_P4_08
R/W
0x030
0x4002 C220
D (tables 82, 83)
x
x
x
-
P4[9]
IOCON_P4_09
R/W
0x030
0x4002 C224
D (tables 82, 83)
x
x
x
-
P4[10]
IOCON_P4_10
R/W
0x030
0x4002 C228
D (tables 82, 83)
x
x
x
-
P4[11]
IOCON_P4_11
R/W
0x030
0x4002 C22C
D (tables 82, 83)
x
x
x
-
P4[12]
IOCON_P4_12
R/W
0x030
0x4002 C230
D (tables 82, 83)
x
x
x
-
P4[13]
IOCON_P4_13
R/W
0x030
0x4002 C234
D (tables 82, 83)
x
x
x
-
P4[14]
IOCON_P4_14
R/W
0x030
0x4002 C238
D (tables 82, 83)
x
x
x
-
P4[15]
IOCON_P4_15
R/W
0x030
0x4002 C23C
D (tables 82, 83)
x
x
x
-
P4[16]
IOCON_P4_16
R/W
0x030
0x4002 C240
D (tables 82, 83)
x
x
-
-
P4[17]
IOCON_P4_17
R/W
0x030
0x4002 C244
D (tables 82, 83)
x
x
-
-
P4[18]
IOCON_P4_18
R/W
0x030
0x4002 C248
D (tables 82, 83)
x
x
-
-
P4[19]
IOCON_P4_19
R/W
0x030
0x4002 C24C
D (tables 82, 83)
x
x
-
-
P4[20]
IOCON_P4_20
R/W
0x030
0x4002 C250
D (tables 82, 83)
x
-
-
-
P4[21]
IOCON_P4_21
R/W
0x030
0x4002 C254
D (tables 82, 83)
x
-
-
-
P4[22]
IOCON_P4_22
R/W
0x030
0x4002 C258
D (tables 82, 83)
x
-
-
-
P4[23]
IOCON_P4_23
R/W
0x030
0x4002 C25C
D (tables 82, 83)
x
-
-
-
P4[24]
IOCON_P4_24
R/W
0x030
0x4002 C260
D (tables 82, 83)
x
x
x
-
P4[25]
IOCON_P4_25
R/W
0x030
0x4002 C264
D (tables 82, 83)
x
x
x
-
P4[26]
IOCON_P4_26
R/W
0x030
0x4002 C268
D (tables 82, 83)
x
x
-
-
P4[27]
IOCON_P4_27
R/W
0x030
0x4002 C26C
D (tables 82, 83)
x
x
-
-
P4[28]
IOCON_P4_28
R/W
0x030
0x4002 C270
D (tables 82, 83)
x
x
x
x
P4[29]
IOCON_P4_29
R/W
0x030
0x4002 C274
D (tables 82, 83)
x
x
x
x
P4[30]
IOCON_P4_30
R/W
0x030
0x4002 C278
D (tables 82, 83)
x
x
x
-
P4[31]
IOCON_P4_31
R/W
0x030
0x4002 C27C
D (tables 82, 83)
x
x
x
-
[1]
UM10562
User manual
208-pin 180-pin 144-pin
80-pin
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
127 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 81.
I/O Control registers for port 5
Port
pin
Register
Access
Reset
Value[1]
Address
IOCON type
P5[0]
IOCON_P5_00
R/W
0x030
0x4002 C280
D (tables 82, 83)
x
x
x
-
P5[1]
IOCON_P5_01
R/W
0x030
0x4002 C284
D (tables 82, 83)
x
x
x
-
P5[2]
IOCON_P5_02
R/W
0
0x4002 C288
I (tables 88, 89)
x
x
x
-
P5[3]
IOCON_P5_03
R/W
0
0x4002 C28C
I (tables 88, 89)
x
x
x
-
P5[4]
IOCON_P5_04
R/W
0x030
0x4002 C290
D (tables 82, 83)
x
x
x
-
[1]
UM10562
User manual
208-pin 180-pin 144-pin
80-pin
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
128 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1 I/O configuration register contents (IOCON)
The functions of bits in the IOCON register for each GPIO port pin is described in the
following sections. There are some differences in IOCON for special port pins compared
to most other port pins. These include pins that support analog functions (such as ADC
inputs and the DAC output), the USB D+/D- pins, and specialized I2C pins:
•
•
•
•
•
UM10562
User manual
”Type D IOCON registers (applies to most GPIO port pins)”
”Type A IOCON registers (applies to pins that include an analog function)”
”Type U IOCON registers (applies to pins that include a USB D+ or D- function)”
”Type I IOCON registers (applies to pins that include a specialized I2C function)”
”Type W IOCON registers (these pins are otherwise the same as Type D, but include
a selectable input glitch filter, and default to pull-down/pull-up disabled).”
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
129 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1.1 Type D IOCON registers (applies to most GPIO port pins)
This IOCON table applies to all port pins except P0[7 to 9], P0[12 to 13], P0[23 to 31],
P1[30 to 31], and P5[2 to 3]. Those pins include DAC, ADC, USB, I2C, or input glitch filter
functions that alter the contents of the related IOCON registers.
Table 82.
Type D IOCON registers bit description
Bit
Symbol Value Description
2:0
FUNC
Selects pin function. See Table 83 for specific values.
000
4:3
MODE
Selects function mode (on-chip pull-up/pull-down resistor control). See Section 7.3.2 “Pin
mode”.
10
5
6
Inactive (no pull-down/pull-up resistor enabled).
01
Pull-down resistor enabled.
10
Pull-up resistor enabled.
11
Repeater mode.
Hysteresis. See Section 7.3.3 “Hysteresis”.
0
Disable.
1
Enable.
INV
-
9
SLEW
10
00
HYS
8:7
Input is not inverted (a HIGH on the pin reads as 1)
1
Input is inverted (a HIGH on the pin reads as 0)
NA
Driver slew rate. See Section 7.3.7 “Output slew rate”.
0
0
Standard mode, output slew rate control is enabled. More outputs can be switched
simultaneously.
1
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data
sheet for details.
Controls open-drain mode. See Section 7.3.9 “Open-Drain Mode”.
1
User manual
0
Reserved. Read value is undefined, only zero should be written.
0
UM10562
1
Input polarity. See Section 7.3.4 “Input Inversion”.
0
OD
31:11 -
Reset
value
0
Normal push-pull output
Simulated open-drain output (high drive disabled)
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
130 of 942
NXP Semiconductors
UM10562
User manual
Table 83.
Type D I/O Control registers: FUNC values and pin functions
Value of FUNC field in IOCON register
Register
000
001
010
011
100
IOCON_P0_0
P0[0]
CAN_RD1
U3_TXD
I2C1_SDA
U0_TXD
IOCON_P0_1
P0[1]
CAN_TD1
U3_RXD
I2C1_SCL
U0_RXD
IOCON_P0_2
P0[2]
U0_TXD
U3_TXD
IOCON_P0_3
P0[3]
U0_RXD
U3_RXD
101
110
111
P0[4]
I2S_RX_SCK
CAN_RD2
T2_CAP0
CMP_ROSC
LCD_VD[0]
P0[5]
I2S_RX_WS
CAN_TD2
T2_CAP1
CMP_RESET
LCD_VD[1]
IOCON_P0_6
P0[6]
I2S_RX_SDA
SSP1_SSEL
T2_MAT0
CMP_ROSC
LCD_VD[8]
IOCON_P0_10
P0[10]
U2_TXD
I2C2_SDA
T3_MAT0
LCD_VD[5]
LCD_VD[10]
U1_RTS
P0[11]
U2_RXD
I2C2_SCL
T3_MAT1
IOCON_P0_14
P0[14]
USB_HSTEN2
SSP1_SSEL
USB_CONNECT2
IOCON_P0_15
P0[15]
U1_TXD
SSP0_SCK
SPIFI_IO[2]
IOCON_P0_16
P0[16]
U1_RXD
SSP0_SSEL
SPIFI_IO[3]
IOCON_P0_17
P0[17]
U1_CTS
SSP0_MISO
SPIFI_IO[1]
IOCON_P0_18
P0[18]
U1_DCD
SSP0_MOSI
SPIFI_IO[0]
IOCON_P0_19
P0[19]
U1_DSR
SD_CLK
I2C1_SDA
LCD_VD[13]
IOCON_P0_20
P0[20]
U1_DTR
SD_CMD
I2C1_SCL
LCD_VD[14]
IOCON_P0_21
P0[21]
U1_RI
SD_PWR
U4_OE
CAN_RD1
U4_CLK
IOCON_P0_22
P0[22]
U1_RTS
SD_DAT[0]
U4_TXD
CAN_TD1
SPIFI_CLK
IOCON_P1_0
P1[0]
ENET_TXD0
T3_CAP1
SSP2_SCK
IOCON_P1_1
P1[1]
ENET_TXD1
T3_MAT3
SSP2_MOSI
IOCON_P1_2
P1[2]
ENET_TXD2
SD_CLK
PWM0[1]
IOCON_P1_3
P1[3]
ENET_TXD3
SD_CMD
PWM0[2]
IOCON_P1_4
P1[4]
ENET_TX_EN
T3_MAT2
SSP2_MISO
IOCON_P1_8
P1[8]
ENET_CRS
T3_MAT1
SSP2_SSEL
IOCON_P1_9
P1[9]
ENET_RXD0
T3_MAT0
IOCON_P1_10
P1[10]
ENET_RXD1
T3_CAP0
IOCON_P1_11
P1[11]
ENET_RXD2
SD_DAT[2]
PWM0[6]
IOCON_P1_12
P1[12]
ENET_RXD3
SD_DAT[3]
PWM0_CAP0
IOCON_P1_13
P1[13]
ENET_RX_DV
CMP1_OUT
UM10562
131 of 942
© NXP B.V. 2012. All rights reserved.
IOCON_P0_11
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
All information provided in this document is subject to legal disclaimers.
IOCON_P0_4
IOCON_P0_5
Type D I/O Control registers: FUNC values and pin functions
NXP Semiconductors
UM10562
User manual
Table 83.
Value of FUNC field in IOCON register
Register
000
001
010
011
100
101
110
111
IOCON_P1_15
P1[15]
ENET_RX_CLK
IOCON_P1_18
P1[18]
USB_UP_LED1
PWM1[1]
T1_CAP0
IOCON_P1_19
P1[19]
USB_TX_E1
USB_PPWR1
T1_CAP1
MC_0A
SSP1_SCK
U2_OE
IOCON_P1_20
P1[20]
USB_TX_DP1
PWM1[2]
QEI_PHA
MC_FB0
SSP0_SCK
LCD_VD[6]
LCD_VD[10]
IOCON_P1_21
P1[21]
USB_TX_DM1
PWM1[3]
SSP0_SSEL
MC_ABORT
LCD_VD[7]
LCD_VD[11]
I2C2_SDA
SSP1_MISO
P1[22]
USB_RCV1
USB_PWRD1
T1_MAT0
MC_0B
SSP1_MOSI
LCD_VD[8]
LCD_VD[12]
IOCON_P1_23
P1[23]
USB_RX_DP1
PWM1[4]
QEI_PHB
MC_FB1
SSP0_MISO
LCD_VD[9]
LCD_VD[13]
IOCON_P1_24
P1[24]
USB_RX_DM1
PWM1[5]
QEI_IDX
MC_FB2
SSP0_MOSI
LCD_VD[10] LCD_VD[14]
IOCON_P1_25
P1[25]
USB_LS1
USB_HSTEN1 T1_MAT1
MC_1A
CLKOUT
LCD_VD[11] LCD_VD[15]
MC_1B
SSP1_SSEL
LCD_VD[12] LCD_VD[20]
IOCON_P1_26
P1[26]
USB_SSPND1
PWM1[6]
IOCON_P1_27
P1[27]
USB_INT1
USB_OVRCR1 T0_CAP1
CLKOUT
IOCON_P1_28
P1[28]
USB_SCL1
PWM1_CAP0
T0_MAT0
MC_2A
SSP0_SSEL
LCD_VD[14] LCD_VD[22]
IOCON_P1_29
P1[29]
USB_SDA1
PWM1_CAP1
T0_MAT1
MC_2B
U4_TXD
LCD_VD[15] LCD_VD[23]
IOCON_P2_0
P2[0]
PWM1[1]
U1_TXD
LCD_PWR
IOCON_P2_1
P2[1]
PWM1[2]
U1_RXD
LCD_LE
IOCON_P2_2
P2[2]
PWM1[3]
U1_CTS
T2_MAT3
TRACEDATA[3]
LCD_DCLK
IOCON_P2_3
P2[3]
PWM1[4]
U1_DCD
T2_MAT2
TRACEDATA[2]
LCD_FP
T0_CAP0
LCD_VD[13] LCD_VD[21]
P2[4]
PWM1[5]
U1_DSR
T2_MAT1
TRACEDATA[1]
LCD_ENAB_M
IOCON_P2_5
P2[5]
PWM1[6]
U1_DTR
T2_MAT0
TRACEDATA[0]
LCD_LP
IOCON_P2_6
P2[6]
PWM1_CAP0
U1_RI
T2_CAP0
IOCON_P2_7
P2[7]
CAN_RD2
U1_RTS
IOCON_P2_8
P2[8]
CAN_TD2
U2_TXD
U1_CTS
IOCON_P2_9
P2[9]
USB_CONNECT1 U2_RXD
U4_RXD
IOCON_P2_10
P2[10]
EINT0
NMI
IOCON_P2_11
P2[11]
EINT1
SD_DAT[1]
I2S_TX_SCK
IOCON_P2_12
P2[12]
EINT2
SD_DAT[2]
I2S_TX_WS
IOCON_P2_13
P2[13]
EINT3
SD_DAT[3]
I2S_TX_SDA
IOCON_P2_14
P2[14]
EMC_CS2
I2C1_SDA
T2_CAP0
IOCON_P2_15
P2[15]
EMC_CS3
I2C1_SCL
T2_CAP1
IOCON_P2_16
P2[16]
EMC_CAS
U2_OE
TRACECLK
LCD_VD[0]
LCD_VD[4]
SPIFI_CS
LCD_VD[1]
LCD_VD[5]
ENET_MDC
LCD_VD[2]
LCD_VD[6]
ENET_MDIO
LCD_VD[3]
LCD_VD[7]
LCD_CLKIN
LCD_VD[4]
LCD_VD[3]
LCD_VD[8]
LCD_VD[18]
LCD_VD[5]
LCD_VD[9]
LCD_VD[19]
UM10562
132 of 942
© NXP B.V. 2012. All rights reserved.
IOCON_P2_4
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
All information provided in this document is subject to legal disclaimers.
IOCON_P1_22
Type D I/O Control registers: FUNC values and pin functions
NXP Semiconductors
UM10562
User manual
Table 83.
Value of FUNC field in IOCON register
001
010
011
IOCON_P2_17
P2[17]
EMC_RAS
IOCON_P2_18
P2[18]
EMC_CLK0
IOCON_P2_19
P2[19]
EMC_CLK1
IOCON_P2_20
P2[20]
EMC_DYCS0
IOCON_P2_21
P2[21]
EMC_DYCS1
IOCON_P2_22
P2[22]
IOCON_P2_23
P2[23]
EMC_DYCS2
SSP0_SCK
T3_CAP0
EMC_DYCS3
SSP0_SSEL
T3_CAP1
IOCON_P2_24
P2[24]
EMC_CKE0
IOCON_P2_25
P2[25]
EMC_CKE1
IOCON_P2_26
P2[26]
IOCON_P2_27
P2[27]
EMC_CKE2
SSP0_MISO
T3_MAT0
EMC_CKE3
SSP0_MOSI
T3_MAT1
IOCON_P2_28
P2[28]
EMC_DQM0
IOCON_P2_29
P2[29]
EMC_DQM1
IOCON_P2_30
P2[30]
IOCON_P2_31
P2[31]
EMC_DQM2
I2C2_SDA
T3_MAT2
EMC_DQM3
I2C2_SCL
T3_MAT3
IOCON_P3_0
P3[0]
EMC_D[0]
IOCON_P3_1
P3[1]
EMC_D[1]
IOCON_P3_2
P3[2]
EMC_D[2]
IOCON_P3_3
P3[3]
EMC_D[3]
IOCON_P3_4
P3[4]
EMC_D[4]
IOCON_P3_5
P3[5]
EMC_D[5]
IOCON_P3_6
P3[6]
EMC_D[6]
IOCON_P3_7
P3[7]
EMC_D[7]
IOCON_P3_8
P3[8]
EMC_D[8]
IOCON_P3_9
P3[9]
EMC_D[9]
IOCON_P3_10
P3[10]
EMC_D[10]
IOCON_P3_11
P3[11]
EMC_D[11]
IOCON_P3_12
P3[12]
EMC_D[12]
IOCON_P3_13
P3[13]
EMC_D[13]
IOCON_P3_14
P3[14]
EMC_D[14]
100
101
110
111
UM10562
133 of 942
© NXP B.V. 2012. All rights reserved.
000
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
All information provided in this document is subject to legal disclaimers.
Register
Type D I/O Control registers: FUNC values and pin functions
NXP Semiconductors
UM10562
User manual
Table 83.
Value of FUNC field in IOCON register
Register
000
001
010
011
IOCON_P3_15
P3[15]
EMC_D[15]
IOCON_P3_16
P3[16]
IOCON_P3_17
P3[17]
EMC_D[16]
PWM0[1]
U1_TXD
EMC_D[17]
PWM0[2]
U1_RXD
IOCON_P3_18
P3[18]
EMC_D[18]
PWM0[3]
U1_CTS
IOCON_P3_19
P3[19]
EMC_D[19]
PWM0[4]
U1_DCD
EMC_D[20]
PWM0[5]
U1_DSR
P3[21]
EMC_D[21]
PWM0[6]
U1_DTR
IOCON_P3_22
P3[22]
EMC_D[22]
PWM0_CAP0
U1_RI
IOCON_P3_23
P3[23]
EMC_D[23]
PWM1_CAP0
T0_CAP0
IOCON_P3_24
P3[24]
EMC_D[24]
PWM1[1]
T0_CAP1
IOCON_P3_25
P3[25]
EMC_D[25]
PWM1[2]
T0_MAT0
IOCON_P3_26
P3[26]
EMC_D[26]
PWM1[3]
T0_MAT1
IOCON_P3_27
P3[27]
EMC_D[27]
PWM1[4]
T1_CAP0
IOCON_P3_28
P3[28]
EMC_D[28]
PWM1[5]
T1_CAP1
IOCON_P3_29
P3[29]
EMC_D[29]
PWM1[6]
T1_MAT0
IOCON_P3_30
P3[30]
EMC_D[30]
U1_RTS
T1_MAT1
IOCON_P3_31
P3[31]
EMC_D[31]
IOCON_P4_0
P4[0]
EMC_A[0]
IOCON_P4_1
P4[1]
EMC_A[1]
IOCON_P4_2
P4[2]
EMC_A[2]
IOCON_P4_3
P4[3]
EMC_A[3]
IOCON_P4_4
P4[4]
EMC_A[4]
IOCON_P4_5
P4[5]
EMC_A[5]
IOCON_P4_6
P4[6]
EMC_A[6]
IOCON_P4_7
P4[7]
EMC_A[7]
IOCON_P4_8
P4[8]
EMC_A[8]
IOCON_P4_9
P4[9]
EMC_A[9]
IOCON_P4_10
P4[10]
EMC_A[10]
IOCON_P4_11
P4[11]
EMC_A[11]
IOCON_P4_12
P4[12]
EMC_A[12]
T1_MAT2
110
111
STCLK
UM10562
134 of 942
© NXP B.V. 2012. All rights reserved.
P3[20]
IOCON_P3_21
101
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
All information provided in this document is subject to legal disclaimers.
IOCON_P3_20
100
Type D I/O Control registers: FUNC values and pin functions
NXP Semiconductors
UM10562
User manual
Table 83.
Value of FUNC field in IOCON register
000
001
010
011
IOCON_P4_13
P4[13]
EMC_A[13]
IOCON_P4_14
P4[14]
EMC_A[14]
IOCON_P4_15
P4[15]
EMC_A[15]
IOCON_P4_16
P4[16]
EMC_A[16]
IOCON_P4_17
P4[17]
EMC_A[17]
IOCON_P4_18
P4[18]
EMC_A[18]
IOCON_P4_19
P4[19]
EMC_A[19]
IOCON_P4_20
P4[20]
EMC_A[20]
I2C2_SDA
SSP1_SCK
IOCON_P4_21
P4[21]
EMC_A[21]
I2C2_SCL
SSP1_SSEL
IOCON_P4_22
P4[22]
EMC_A[22]
U2_TXD
SSP1_MISO
IOCON_P4_23
P4[23]
EMC_A[23]
U2_RXD
SSP1_MOSI
IOCON_P4_24
P4[24]
EMC_OE
IOCON_P4_25
P4[25]
EMC_WE
IOCON_P4_26
P4[26]
EMC_BLS0
IOCON_P4_27
P4[27]
EMC_BLS1
IOCON_P4_28
P4[28]
EMC_BLS2
U3_TXD
T2_MAT0
IOCON_P4_29
P4[29]
EMC_BLS3
U3_RXD
T2_MAT1
IOCON_P4_30
P4[30]
EMC_CS0
IOCON_P4_31
P4[31]
EMC_CS1
IOCON_P5_0
P5[0]
EMC_A[24]
T2_MAT2
IOCON_P5_1
P5[1]
EMC_A[25]
T2_MAT3
IOCON_P5_4
P5[4]
U0_OE
T3_MAT3
100
I2C2_SCL
101
110
LCD_VD[6]
LCD_VD[10] LCD_VD[2]
LCD_VD[7]
LCD_VD[11] LCD_VD[3]
CMP0_OUT
U4_TXD
111
UM10562
135 of 942
© NXP B.V. 2012. All rights reserved.
Chapter 7: LPC408x/407x I/O configuration
Rev. 1 — 13 September 2012
All information provided in this document is subject to legal disclaimers.
Register
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1.2 Type A IOCON registers (applies to pins that include an analog function)
This IOCON table applies to pins P0[12 to 13], P0[23 to 26], and P1[30 to 31]. The
presence of the DAC output on P0[26] makes that pin slightly different, see the description
of bit 16 below.
Table 84.
Bit
Type A IOCON registers bit description
Symbol
Value Description
Reset
value
2:0
FUNC
Selects pin function. See Table 85 for specific values.
0
4:3
MODE
Selects function mode (on-chip pull-up/pull-down resistor control). See Section 7.3.2 “Pin
mode”.
10
00
Inactive (no pull-down/pull-up resistor enabled).
01
Pull-down resistor enabled.
10
Pull-up resistor enabled.
11
Repeater mode.
5
-
Reserved. Read value is undefined, only zero should be written.
6
INVERT
Input polarity. See Section 7.3.4 “Input Inversion”.
7
8
0
Input is not inverted (a HIGH on the pin reads as 1)
1
Input is inverted (a HIGH on the pin reads as 0)
ADMODE
NA
0
Select Analog/Digital mode. See Section 7.3.5 “Analog/digital mode”.
0
Analog mode.
1
Digital mode.
FILTER
1
Controls glitch filter. See Section 7.3.6 “Input filter”.
0
Noise pulses below approximately 10 ns are filtered out
1
No input filtering is done
9
-
Reserved. Read value is undefined, only zero should be written.
10
OD
Controls open-drain mode. See Section 7.3.9 “Open-Drain Mode”.
0
Normal push-pull output
1
Simulated open-drain output (high drive disabled)
1
NA
0
14:11 -
Reserved. Read value is undefined, only zero should be written.
16
DAC enable control. This bit applies only to P0[26], which includes the DAC output
function DAC_OUT. See Section 7.3.10 “DAC enable”.
DACEN
31:17 -
UM10562
User manual
0
DAC is disabled
1
DAC is enabled
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
0
NA
© NXP B.V. 2012. All rights reserved.
136 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 85.
Type A I/O Control registers: FUNC values and pin functions
Value of FUNC field in IOCON register
Register
000
001
010
011
IOCON_P0_12
P0[12]
USB_PPWR2
SSP1_MISO
ADC0[6]
ADC0[7]
100
101
IOCON_P0_13
P0[13]
USB_UP_LED2 SSP1_MOSI
IOCON_P0_23
P0[23]
ADC0[0]
I2S_RX_SCK T3_CAP0
IOCON_P0_24
P0[24]
ADC0[1]
I2S_RX_WS
IOCON_P0_25
P0[25]
ADC0[2]
I2S_RX_SDA U3_TXD
IOCON_P0_26
P0[26]
ADC0[3]
DAC_OUT
U3_RXD
IOCON_P1_30
P1[30]
USB_PWRD2
USB_VBUS
ADC[4]
I2C0_SDA U3_OE
IOCON_P1_31
P1[31]
USB_OVRCR2
SSP1_SCK
ADC[5]
I2C0_SCL
UM10562
User manual
110
111
T3_CAP1
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
137 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1.3 Type U IOCON registers (applies to pins that include a USB D+ or Dfunction)
This IOCON table applies to pins P0[29], P0[30], and P0[31]. These special function pins
do not include the selectable modes and options of other pins.
Table 86.
Type U IOCON registers bit description
Bit
Symbol
Description
2:0
FUNC
Selects pin function. See Table 87 for specific values.
000
31:3
-
Reserved. Read value is undefined, only zero should be written.
NA
Table 87.
Reset value
Type U I/O Control registers: FUNC values and pin functions
Value of FUNC field in IOCON register
Register
000
001
010
IOCON_P0_29
P0[29]
USB_D+1
EINT0
IOCON_P0_30
P0[30]
USB_D-1
EINT1
IOCON_P0_31
P0[31]
USB_D+2
UM10562
User manual
011
100
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
101
110
111
© NXP B.V. 2012. All rights reserved.
138 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1.4 Type I IOCON registers (applies to pins that include a specialized I2C
function)
This IOCON table applies to pins P0[27 to 28] and P5[2 to 3].
Table 88.
Type I IOCON registers bit description
Bit
Symbol
Value Description
Reset
value
2:0
FUNC
5:3
-
Reserved. Read value is undefined, only zero should be written.
6
INVERT
Input polarity. See Section 7.3.4 “Input Inversion”.
Selects pin function. See Table 89 for specific values.
0
Input is not inverted (a HIGH on the pin reads as 1)
1
Input is inverted (a HIGH on the pin reads as 0)
0
NA
0
7
-
Reserved. Read value is undefined, only zero should be written.
8
HS
Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.
See Section 7.3.8 “I2C modes”.
9
0
I2C 50ns glitch filter and slew rate control enabled.
1
I2C 50ns glitch filter and slew rate control disabled.
0
Controls sink current capability of the pin, only for P5[2] and P5[3]. See Section 7.3.8 “I2C
modes”.
HIDRIVE
0
Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C.
1
Output drive sink is 20 mA. This is needed for Fast Mode Plus I2C. Refer to the
appropriate specific device data sheet for details.
31:10 -
Table 89.
NA
Reserved. Read value is undefined, only zero should be written.
0
NA
Type I I/O Control registers: FUNC values and pin functions
Value of FUNC field in IOCON register
Register
000
001
010
IOCON_P0_27
P0[27]
I2C0_SDA
USB_SDA1
IOCON_P0_28
P0[28]
I2C0_SCL
USB_SCL1
IOCON_P5_2
P5[2]
IOCON_P5_3
P5[3]
UM10562
User manual
011
100
T3_MAT2
101
110
111
I2C0_SDA
U4_RXD
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
I2C0_SCL
© NXP B.V. 2012. All rights reserved.
139 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
7.4.1.5 Type W IOCON registers (these pins are otherwise the same as Type D, but
include a selectable input glitch filter, and default to pull-down/pull-up
disabled).
This IOCON table applies to pins P0[7], P0[8], and P0[9].
Table 90.
Type W IOCON registers bit description
Bit
Symbol
Value Description
2:0
FUNC
Selects pin function. See Table 91 for specific values.
000
4:3
MODE
Selects the output functional mode for the pin (on-chip pull-up/pull-down resistor control).
See Section 7.3.2 “Pin mode”.
00
00
Inactive (no pull-down/pull-up resistor enabled).
01
Pull-down resistor enabled.
10
Pull-up resistor enabled.
11
5
6
7
8
HYS
0
Disable.
1
Enable.
0
Input is not inverted (a HIGH on the pin reads as 1)
1
Input is inverted (a HIGH on the pin reads as 0)
INV
ADMODE
0
Analog mode.
1
Digital mode.
0
Noise pulses below approximately 10 ns are filtered out
No input filtering is done
Driver slew rate. See Section 7.3.7 “Output slew rate”.
0
0
Standard mode, output slew rate control is enabled. More outputs can be switched
simultaneously.
1
Fast mode, slew rate control is disabled. Refer to the appropriate specific device data
sheet for details.
OD
Controls open-drain mode. See Section 7.3.9 “Open-Drain Mode”.
0
1
User manual
1
Controls glitch filter. See Section 7.3.6 “Input filter”.
SLEW
UM10562
0
Select Analog/Digital mode. See Section 7.3.5 “Analog/digital mode”.
FILTER
31:11 -
1
Input polarity. See Section 7.3.4 “Input Inversion”.
1
10
Repeater mode.
Hysteresis. See Section 7.3.3 “Hysteresis”.
0
9
Reset
value
0
Normal push-pull output
Simulated open-drain output (high drive disabled)
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
140 of 942
UM10562
NXP Semiconductors
Chapter 7: LPC408x/407x I/O configuration
Table 91.
Type W I/O Control registers: FUNC values and pin functions
Value of FUNC field in IOCON register
Register
000
001
010
011
100
IOCON_P0_7
P0[7]
I2S_TX_SCK
SSP1_SCK
T2_MAT1
RTC_EV0 CMP_VREF
101
LCD_VD[9]
IOCON_P0_8
P0[8]
I2S_TX_WS
SSP1_MISO
T2_MAT2
RTC_EV1 CMP1_IN[4]
LCD_VD[16]
IOCON_P0_9
P0[9]
I2S_TX_SDA
SSP1_MOSI
T2_MAT3
RTC_EV2 CMP1_IN[3]
LCD_VD[17]
SD_PWR
IOCON_P1_5
P1[5]
ENET_TX_ER
PWM0[3]
CMP1_IN[2]
IOCON_P1_6
P1[6]
ENET_TX_CLK SD_DAT[0]
PWM0[4]
CMP0_IN[4]
IOCON_P1_7
P1[7]
ENET_COL
PWM0[5]
CMP1_IN[1]
T2_CAP0
CMP0_IN[1]
SD_DAT[1]
IOCON_P1_14 P1[14]
ENET_RX_ER
IOCON_P1_16 P1[16]
ENET_MDC
I2S_TX_MCLK
CMP0_IN[2]
IOCON_P1_17 P1[17]
ENET_MDIO
I2S_RX_MCLK
CMP0_IN[3]
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
110
111
© NXP B.V. 2012. All rights reserved.
141 of 942
UM10562
Chapter 8: LPC408x/407x GPIO
Rev. 1 — 13 September 2012
User manual
8.1 Basic configuration
GPIOs are configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCGPIO. This enables the
GPIOs themselves, GPIO interrupts, and the IOCON block.
2. Pins: See Section 7.4.1 for GPIO pins and their modes.
3. Wake-up: GPIO ports 0 and 2 can be used for wake-up if needed, see
(Section 3.12.8).
4. Interrupts: Enable GPIO interrupts in EnR (Table 104 or Table 109) and EnF
(Table 105 or Table 110). Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register.
8.2 Features
8.2.1 Digital I/O ports
• Accelerated GPIO functions:
– GPIO registers are located on a peripheral AHB bus for fast I/O timing.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte, half-word, and word addressable.
– Entire port value can be written in one instruction.
– GPIO registers are accessible by the GPDMA.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• All GPIO registers support bit-banding operations by the CPU.
• GPIO registers are accessible by the GPDMA controller to allow DMA of data to or
from GPIOs, synchronized to any DMA request.
• Direction control of individual port bits.
• All I/Os default to input with pull-up after reset.
8.2.2 Interrupt generating digital ports
• Port 0 and Port 2 can provide a single interrupt for any combination of port pins.
• Each port pin can be programmed to generate an interrupt on a rising edge, a falling
edge, or both.
• Edge detection is asynchronous, so it may operate when clocks are not present, such
as during Power-down mode. With this feature, level triggered interrupts are not
needed.
• Each enabled interrupt contributes to a wake-up signal that can be used to bring the
part out of Power-down mode.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
142 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
• Registers provide a software view of pending rising edge interrupts, pending falling
edge interrupts, and overall pending GPIO interrupts.
• The GPIO interrupt function does not require that the pin be configured for GPIO. This
allows interrupting on a change to a pin that is part of an operating peripheral
interface.
8.3 Applications
•
•
•
•
•
General purpose I/O
Driving LEDs or other indicators
Controlling off-chip devices
Sensing digital inputs, detecting edges
Bringing the part out of Power-down mode
8.4 Pin description
Table 92.
GPIO pin description
Pin Name
Type
Description
P0[31:0];
P1[31:0];
P2[31:0];
P3[31:0];
P4[31:0];
P5[4:0]
Input/
Output
General purpose input/output. These are typically shared with other peripherals functions and will
therefore not all be available in an application. Packaging options may affect the number of GPIOs
available in a particular device.
UM10562
User manual
Some pins may be limited by requirements of the alternate functions of the pin. For example, some
pins that can be used for I2C are special pins, and some of that behavior is inherited by any other
function selected on that pin. Details may be found in Section 6.1.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
143 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5 Register description
The registers represent the enhanced GPIO features available on all of the GPIO ports.
These registers are located on an AHB bus for fast read and write timing. They can all be
accessed in byte, half-word, and word sizes. A mask register allows access to a group of
bits in a single GPIO port independently from other bits in the same port.
Table 93.
Register overview: GPIO (base address 0x2009 8000)
Name
Access
Address offset Description
Reset value
Table
DIR0
R/W
0x000
GPIO Port0 Direction control register.
0
95
MASK0
R/W
0x010
Mask register for Port0.
0
96
PIN0
R/W
0x014
Port0 Pin value register using FIOMASK.
0
97
SET0
R/W
0x018
Port0 Output Set register using FIOMASK.
0
98
CLR0
WO
0x01C
Port0 Output Clear register using FIOMASK.
-
99
DIR1
R/W
0x020
GPIO Port1 Direction control register.
0
95
MASK1
R/W
0x030
Mask register for Port1.
0
96
PIN1
R/W
0x034
Port1 Pin value register using FIOMASK.
0
97
SET1
R/W
0x038
Port1 Output Set register using FIOMASK.
0
98
CLR1
WO
0x03C
Port1 Output Clear register using FIOMASK.
-
99
DIR2
R/W
0x040
GPIO Port2 Direction control register.
0
95
MASK2
R/W
0x050
Mask register for Port2.
0
96
PIN2
R/W
0x054
Port2 Pin value register using FIOMASK.
0
97
SET2
R/W
0x058
Port2 Output Set register using FIOMASK.
0
98
CLR2
WO
0x05C
Port2 Output Clear register using FIOMASK.
-
99
DIR3
R/W
0x060
GPIO Port3 Direction control register.
0
95
MASK3
R/W
0x070
Mask register for Port3.
0
96
PIN3
R/W
0x074
Port3 Pin value register using FIOMASK.
0
97
SET3
R/W
0x078
Port3 Output Set register using FIOMASK.
0
98
CLR3
WO
0x07C
Port3 Output Clear register using FIOMASK.
-
99
DIR4
R/W
0x080
GPIO Port4 Direction control register.
0
95
MASK4
R/W
0x090
Mask register for Port4.
0
96
PIN4
R/W
0x094
Port4 Pin value register using FIOMASK.
0
97
SET4
R/W
0x098
Port4 Output Set register using FIOMASK.
0
98
CLR4
WO
0x09C
Port4 Output Clear register using FIOMASK.
-
99
DIR5
R/W
0x0A0
GPIO Port5 Direction control register.
0
95
MASK5
R/W
0x0B0
Mask register for Port5.
0
96
PIN5
R/W
0x0B4
Port5 Pin value register using FIOMASK.
0
97
SET5
R/W
0x0B8
Port5 Output Set register using FIOMASK.
0
98
CLR5
WO
0x0BC
Port5 Output Clear register using FIOMASK.
-
99
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
144 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
Table 94.
Name
User manual
Access Address Description
offset
Reset Table
value[1]
STATUS
RO
0x080
GPIO overall Interrupt Status.
0
100
STATR0
RO
0x084
GPIO Interrupt Status for Rising edge for Port 0.
0
101
STATF0
RO
0x088
GPIO Interrupt Status for Falling edge for Port 0.
0
102
CLR0
WO
0x08C
GPIO Interrupt Clear.
-
103
ENR0
R/W
0x090
GPIO Interrupt Enable for Rising edge for Port 0.
0
104
ENF0
R/W
0x094
GPIO Interrupt Enable for Falling edge for Port 0.
0
105
STATR2
RO
0x0A4
GPIO Interrupt Status for Rising edge for Port 0.
0
106
STATF2
RO
0x0A8
GPIO Interrupt Status for Falling edge for Port 0.
0
107
CLR2
WO
0x0AC
GPIO Interrupt Clear.
-
108
ENR2
R/W
0x0B0
GPIO Interrupt Enable for Rising edge for Port 0.
0
109
ENF2
R/W
0x0B4
GPIO Interrupt Enable for Falling edge for Port 0.
0
110
[1]
UM10562
Register overview: GPIO interrupt (base address 0x4002 8000)
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
145 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.1 GPIO port registers
8.5.1.1 GPIO port Direction register
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Note that GPIO pins P0[29] and P0[30] are shared with the USB_D+ and USB_D- pins
and must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero,
both P0[29] and P0[30] will be inputs. If both FIO0DIR bits 29 and 30 are ones, both
P0[29] and P0[30] will be outputs.
Aside from the 32-bit long and word only accessible DIRx register, every fast GPIO port
can also be controlled via byte and half-word access.
Table 95.
GPIO port Direction register (DIR[0:5] - addresses 0x2009 8000 (DIR0) to
0x200980A0 (DIR5)) bit description
Bit
Symbol
Description
Reset value
31:0
PINDIR
Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls
pin Px[0], bit 31 in DIRx controls pin Px[31].
0x0
0 = Controlled pin is input.
1 = Controlled pin is output.
8.5.1.2 Fast GPIO port Mask register
This register is used to select port pins that will and will not be affected by write accesses
to the PINx, SETx or CLRx register. Mask register also filters out port’s content when the
PINx register is read.
A zero in this register’s bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated PINx register. For software
examples, see Section 8.6.
Table 96.
Bit
Fast GPIO port Mask register (MASK[0:5] - addresses 0x2009 8010 (MASK0) to 0x2009 80B0 (MASK5)) bit
description
Symbol
31:0 PINMASK
Description
Reset
value
Fast GPIO physical pin access control.
0x0
0 = Controlled pin is affected by writes to the port’s SETx, CLRx, and PINx registers. Current
state of the pin can be read from the PINx register.
1 = Controlled pin is not affected by writes into the port’s SETx, CLRx and PINx registers.
When the PINx register is read, this bit will not be updated with the state of the physical pin.
Aside from the 32-bit long and word only accessible MASKx register, every fast GPIO port
can also be controlled via byte and half-word access.
8.5.1.3 GPIO port Pin value register
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
146 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding PINx register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the PINx register is not valid.
Writing to the PINx register stores the value in the port output register, bypassing the need
to use both the SETx and CLRx registers to obtain the entire written value. This feature
should be used carefully in an application since it affects the entire port.
Access to a port pin via the PINx register is conditioned by the corresponding bit of the
MASKx register (see Section 8.5.1.2).
Only pins masked with zeros in the Mask register (see Section 8.5.1.2) will be correlated
to the current content of the Fast GPIO port pin value register.
Table 97.
Fast GPIO port Pin value register (PIN[0:5] - addresses 0x2009 8014 (PIN0) to
0x2009 80B4 (PIN5)) bit description
Bit
Symbol
Description
Reset value
31:0
PINVAL
Fast GPIO output value Set bits. Bit 0 in CLRx corresponds to pin
Px[0], bit 31 in CLRx corresponds to pin Px[31].
0x0
0 = Controlled pin output is set to LOW.
1 = Controlled pin output is set to HIGH.
Aside from the 32-bit long and word only accessible PINx register, every fast GPIO port
can also be controlled via byte and half-word access.
8.5.1.4 GPIO port output Set register
This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing
1 to the corresponding bit in the SETx has no effect.
Reading the SETx register returns the value of this register, as determined by previous
writes to SETx and CLRx (or PINx as noted above). This value does not reflect the effect
of any outside world influence on the I/O pins.
Access to a port pin via the SETx register is conditioned by the corresponding bit of the
MASKx register (see Section 8.5.1.2).
Table 98.
Fast GPIO port output Set register (SET[0:5] - addresses 0x2009 8018 (SET0) to
0x2009 80B8 (SET5)) bit description
Bit
Symbol
Description
Reset value
31:0
PINSET
Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0],
bit 31 in SETx controls pin Px[31].
0x0
0 = Controlled pin output is unchanged.
1 = Controlled pin output is set to HIGH.
Aside from the 32-bit long and word only accessible SETx register, every fast GPIO port
can also be controlled via byte and half-word access.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
147 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.1.5 GPIO port output Clear register
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the SETx register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to CLRx has no effect.
Access to a port pin via the CLRx register is conditioned by the corresponding bit of the
MASKx register (see Section 8.5.1.2).
Table 99.
Fast GPIO port output Clear register (CLR[0:5] - addresses 0x2009 801C (CLR0) to
0x2009 80BC (CLR5)) bit description
Bit
Symbol
Description
31:0
PINCLR
Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31
controls pin Px[31].
0 = Controlled pin output is unchanged.
1 = Controlled pin output is set to LOW.
Aside from the 32-bit long and word only accessible CLRx register, every fast GPIO port
can also be controlled via byte and half-word access.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
148 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2 GPIO interrupt registers
The following registers configure the pins of Port 0 and Port 2 to generate interrupts.
APB
Bus
Rising Edge
Enable Register
(GPIOIntEnR)
1
GPIOIntStatR
Register
(Read Only)
GPIOIntStatus
Register
D Q
Pin
Pin
Int
R
Write 1 to
GPIOIntCl
Port
Wakeup
R
1
APB
Bus
Port Int
To
NVIC
Other Port Ints
plus one existing
interrupt
To
Wakeup
D Q
Falling Edge
Enable Register
(GPIOIntEnF)
GPIOIntStatF
Register
(Read Only)
for each supported
GPIO pin
Other
Pinj Ints
GPIOWake
(from IntWake
Register)
for each supported
GPIO port
Other Port
Wakeups
One per device
120608
Fig 15. GPIO interrupt block diagram
8.5.2.1 GPIO overall Interrupt Status register
This read-only register indicates the presence of interrupt pending on all of the GPIO ports
that support GPIO interrupts. Only status one bit per port is required.
Table 100. GPIO overall Interrupt Status register (STATUS - address 0x4002 8080) bit
description
Bit
Symbol
0
P0INT
1
-
2
P2INT
31:2
UM10562
User manual
-
Value
Description
Reset value
Port 0 GPIO interrupt pending.
0
No pending interrupts on Port 0.
1
At least one pending interrupt on Port 0.
0
Reserved. The value read from a reserved bit is not
defined.
Port 2 GPIO interrupt pending.
0
No pending interrupts on Port 2.
1
At least one pending interrupt on Port 2.
0
Reserved. The value read from a reserved bit is not
defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
NA
© NXP B.V. 2012. All rights reserved.
149 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.2 GPIO Interrupt Status for port 0 Rising Edge Interrupt
Each bit in these read-only registers indicates the rising edge interrupt status for port 0.
Table 101. GPIO Interrupt Status for port 0 Rising Edge Interrupt (STATR0 - 0x4002 8084) bit
description
Bit
Symbol
Description
0
P0_0REI
Rising Edge Interrupt status for P0[0].
Reset
value
0
0 = No rising edge detected.
1 = Rising edge interrupt generated.
UM10562
User manual
1
P0_1REI
Rising Edge Interrupt status for P0[1]. See bit 0 description.
0
2
P0_2REI
Rising Edge Interrupt status for P0[2]. See bit 0 description.
0
3
P0_3REI
Rising Edge Interrupt status for P0[3]. See bit 0 description.
0
4
P0_4REI
Rising Edge Interrupt status for P0[4]. See bit 0 description.
0
5
P0_5REI
Rising Edge Interrupt status for P0[5]. See bit 0 description.
0
6
P0_6REI
Rising Edge Interrupt status for P0[6]. See bit 0 description.
0
7
P0_7REI
Rising Edge Interrupt status for P0[7]. See bit 0 description.
0
8
P0_8REI
Rising Edge Interrupt status for P0[8]. See bit 0 description.
0
9
P0_9REI
Rising Edge Interrupt status for P0[9]. See bit 0 description.
0
10
P0_10REI
Rising Edge Interrupt status for P0[10]. See bit 0 description.
0
11
P0_11REI
Rising Edge Interrupt status for P0[11]. See bit 0 description.
0
12
P0_12REI
Rising Edge Interrupt status for P0[12]. See bit 0 description.
0
13
P0_13REI
Rising Edge Interrupt status for P0[13]. See bit 0 description.
0
14
P0_14REI
Rising Edge Interrupt status for P0[14]. See bit 0 description.
0
15
P0_15REI
Rising Edge Interrupt status for P0[15]. See bit 0 description.
0
16
P0_16REI
Rising Edge Interrupt status for P0[16]. See bit 0 description.
0
17
P0_17REI
Rising Edge Interrupt status for P0[17]. See bit 0 description.
0
18
P0_18REI
Rising Edge Interrupt status for P0[18]. See bit 0 description.
0
19
P0_19REI
Rising Edge Interrupt status for P0[19]. See bit 0 description.
0
20
P0_20REI
Rising Edge Interrupt status for P0[20]. See bit 0 description.
0
21
P0_21REI
Rising Edge Interrupt status for P0[21]. See bit 0 description.
0
22
P0_22REI
Rising Edge Interrupt status for P0[22]. See bit 0 description.
0
23
P0_23REI
Rising Edge Interrupt status for P0[23]. See bit 0 description.
0
24
P0_24REI
Rising Edge Interrupt status for P0[24]. See bit 0 description.
0
25
P0_25REI
Rising Edge Interrupt status for P0[25]. See bit 0 description.
0
26
P0_26REI
Rising Edge Interrupt status for P0[26]. See bit 0 description.
0
27
P0_27REI
Rising Edge Interrupt status for P0[27]. See bit 0 description.
0
28
P0_28REI
Rising Edge Interrupt status for P0[28]. See bit 0 description.
0
29
P0_29REI
Rising Edge Interrupt status for P0[29]. See bit 0 description.
0
30
P0_30REI
Rising Edge Interrupt status for P0[30]. See bit 0 description.
0
31
P0_31REI
Rising Edge Interrupt status for P0[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
150 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.3 GPIO Interrupt Status for port 0 Falling Edge Interrupt
Each bit in these read-only registers indicates the falling edge interrupt status for port 0.
Table 102. GPIO Interrupt Status for port 0 Falling Edge Interrupt (STATF0 - 0x4002 8088) bit
description
Bit
Symbol
0
P0_0FEI
Description
Reset
value
Falling Edge Interrupt status for P0[0].
0
0 = No falling edge detected.
1 = Falling edge interrupt generated.
UM10562
User manual
1
P0_1FEI
Falling Edge Interrupt status for P0[1]. See bit 0 description.
0
2
P0_2FEI
Falling Edge Interrupt status for P0[2]. See bit 0 description.
0
3
P0_3FEI
Falling Edge Interrupt status for P0[3]. See bit 0 description.
0
4
P0_4FEI
Falling Edge Interrupt status for P0[4]. See bit 0 description.
0
5
P0_5FEI
Falling Edge Interrupt status for P0[5]. See bit 0 description.
0
6
P0_6FEI
Falling Edge Interrupt status for P0[6]. See bit 0 description.
0
7
P0_7FEI
Falling Edge Interrupt status for P0[7]. See bit 0 description.
0
8
P0_8FEI
Falling Edge Interrupt status for P0[8]. See bit 0 description.
0
9
P0_9FEI
Falling Edge Interrupt status for P0[9]. See bit 0 description.
0
10
P0_10FEI
Falling Edge Interrupt status for P0[10]. See bit 0 description.
0
11
P0_11FEI
Falling Edge Interrupt status for P0[11]. See bit 0 description.
0
12
P0_12FEI
Falling Edge Interrupt status for P0[12]. See bit 0description.
0
13
P0_13FEI
Falling Edge Interrupt status for P0[13]. See bit 0 description.
0
14
P0_14FEI
Falling Edge Interrupt status for P0[14]. See bit 0 description.
0
15
P0_15FEI
Falling Edge Interrupt status for P0[15]. See bit 0 description.
0
16
P0_16FEI
Falling Edge Interrupt status for P0[16]. See bit 0 description.
0
17
P0_17FEI
Falling Edge Interrupt status for P0[17]. See bit 0 description.
0
18
P0_18FEI
Falling Edge Interrupt status for P0[18]. See bit 0 description.
0
19
P0_19FEI
Falling Edge Interrupt status for P0[19]. See bit 0 description.
0
20
P0_20FEI
Falling Edge Interrupt status for P0[20]. See bit 0 description.
0
21
P0_21FEI
Falling Edge Interrupt status for P0[21]. See bit 0 description.
0
22
P0_22FEI
Falling Edge Interrupt status for P0[22]. See bit 0 description.
0
23
P0_23FEI
Falling Edge Interrupt status for P0[23]. See bit 0 description.
0
24
P0_24FEI
Falling Edge Interrupt status for P0[24]. See bit 0 description.
0
25
P0_25FEI
Falling Edge Interrupt status for P0[25]. See bit 0 description.
0
26
P0_26FEI
Falling Edge Interrupt status for P0[26]. See bit 0 description.
0
27
P0_27FEI
Falling Edge Interrupt status for P0[27]. See bit 0 description.
0
28
P0_28FEI
Falling Edge Interrupt status for P0[28]. See bit 0 description.
0
29
P0_29FEI
Falling Edge Interrupt status for P0[29]. See bit 0 description.
0
30
P0_30FEI
Falling Edge Interrupt status for P0[30]. See bit 0 description.
0
31
P0_31FEI
Falling Edge Interrupt status for P0[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
151 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.4 GPIO Interrupt Clear register for port 0
Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding
port 0 pin.
Table 103. GPIO Interrupt Clear register for port 0 (CLR0 - 0x4002 808C) bit description
Bit
Symbol
Description
0
P0_0CI
Clear GPIO port Interrupts for P0[0].
0 = No effect.
1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
UM10562
User manual
1
P0_1CI
Clear GPIO port Interrupts for P0[1]. See bit 0 description.
2
P0_2CI
Clear GPIO port Interrupts for P0[2]. See bit 0 description.
3
P0_3CI
Clear GPIO port Interrupts for P0[3]. See bit 0 description.
4
P0_4CI
Clear GPIO port Interrupts for P0[4]. See bit 0 description.
5
P0_5CI
Clear GPIO port Interrupts for P0[5]. See bit 0 description.
6
P0_6CI
Clear GPIO port Interrupts for P0[6]. See bit 0 description.
7
P0_7CI
Clear GPIO port Interrupts for P0[7]. See bit 0 description.
8
P0_8CI
Clear GPIO port Interrupts for P0[8]. See bit 0 description.
9
P0_9CI
Clear GPIO port Interrupts for P0[9]. See bit 0 description.
10
P0_10CI Clear GPIO port Interrupts for P0[10]. See bit 0 description.
11
P0_11CI
12
P0_12CI Clear GPIO port Interrupts for P0[12]. See bit 0 description.
13
P0_13CI Clear GPIO port Interrupts for P0[13]. See bit 0 description.
14
P0_14CI Clear GPIO port Interrupts for P0[14]. See bit 0 description.
15
P0_15CI Clear GPIO port Interrupts for P0[15]. See bit 0 description.
16
P0_16CI Clear GPIO port Interrupts for P0[16]. See bit 0 description.
17
P0_17CI Clear GPIO port Interrupts for P0[17]. See bit 0 description.
18
P0_18CI Clear GPIO port Interrupts for P0[18]. See bit 0 description.
19
P0_19CI Clear GPIO port Interrupts for P0[19]. See bit 0 description.
20
P0_20CI Clear GPIO port Interrupts for P0[20]. See bit 0 description.
21
P0_21CI Clear GPIO port Interrupts for P0[21]. See bit 0 description.
22
P0_22CI Clear GPIO port Interrupts for P0[22]. See bit 0 description.
23
P0_23CI Clear GPIO port Interrupts for P0[23]. See bit 0 description.
24
P0_24CI Clear GPIO port Interrupts for P0[24]. See bit 0 description.
25
P0_25CI Clear GPIO port Interrupts for P0[25]. See bit 0 description.
26
P0_26CI Clear GPIO port Interrupts for P0[26]. See bit 0 description.
27
P0_27CI Clear GPIO port Interrupts for P0[27]. See bit 0 description.
28
P0_28CI Clear GPIO port Interrupts for P0[28]. See bit 0 description.
29
P0_29CI Clear GPIO port Interrupts for P0[29]. See bit 0 description.
30
P0_30CI Clear GPIO port Interrupts for P0[30]. See bit 0 description.
31
P0_31CI Clear GPIO port Interrupts for P0[31]. See bit 0 description.
Clear GPIO port Interrupts for P0[11]. See bit 0 description.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
152 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.5 GPIO Interrupt Enable for port 0 Rising Edge
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 0 pin.
Which pins are available depends on the part number and package combination. See the
specific device data sheet for details.
Table 104. GPIO Interrupt Enable for port 0 Rising Edge (ENR0 - 0x4002 8090) bit
description
Bit
Symbol
Description
0
P0_0ER
Enable rising edge interrupt for P0[0].
Reset value
0
0 = Disable rising edge interrupt.
1 = Enable rising edge interrupt.
UM10562
User manual
1
P0_1ER
Enable rising edge interrupt for P0[1]. See bit 0 description.
0
2
P0_2ER
Enable rising edge interrupt for P0[2]. See bit 0 description.
0
3
P0_3ER
Enable rising edge interrupt for P0[3]. See bit 0 description.
0
4
P0_4ER
Enable rising edge interrupt for P0[4]. See bit 0 description.
0
5
P0_5ER
Enable rising edge interrupt for P0[5]. See bit 0 description.
0
6
P0_6ER
Enable rising edge interrupt for P0[6]. See bit 0 description.
0
7
P0_7ER
Enable rising edge interrupt for P0[7]. See bit 0 description.
0
8
P0_8ER
Enable rising edge interrupt for P0[8]. See bit 0 description.
0
9
P0_9ER
Enable rising edge interrupt for P0[9]. See bit 0 description.
0
10
P0_10ER
Enable rising edge interrupt for P0[10]. See bit 0 description.
0
11
P0_11ER
Enable rising edge interrupt for P0[11]. See bit 0 description.
0
12
P0_12ER
Enable rising edge interrupt for P0[12]. See bit 0 description.
0
13
P0_13ER
Enable rising edge interrupt for P0[13]. See bit 0 description.
0
14
P0_14ER
Enable rising edge interrupt for P0[14]. See bit 0 description.
0
15
P0_15ER
Enable rising edge interrupt for P0[15]. See bit 0 description.
0
16
P0_16ER
Enable rising edge interrupt for P0[16]. See bit 0 description.
0
17
P0_17ER
Enable rising edge interrupt for P0[17]. See bit 0 description.
0
18
P0_18ER
Enable rising edge interrupt for P0[18]. See bit 0 description.
0
19
P0_19ER
Enable rising edge interrupt for P0[19]. See bit 0 description.
0
20
P0_20ER
Enable rising edge interrupt for P0[20]. See bit 0 description.
0
21
P0_21ER
Enable rising edge interrupt for P0[21]. See bit 0 description.
0
22
P0_22ER
Enable rising edge interrupt for P0[22]. See bit 0 description.
0
23
P0_23ER
Enable rising edge interrupt for P0[23]. See bit 0 description.
0
24
P0_24ER
Enable rising edge interrupt for P0[24]. See bit 0 description.
0
25
P0_25ER
Enable rising edge interrupt for P0[25]. See bit 0 description.
0
26
P0_26ER
Enable rising edge interrupt for P0[26]. See bit 0 description.
0
27
P0_27ER
Enable rising edge interrupt for P0[27]. See bit 0 description.
0
28
P0_28ER
Enable rising edge interrupt for P0[28]. See bit 0 description.
0
29
P0_29ER
Enable rising edge interrupt for P0[29]. See bit 0 description.
0
30
P0_30ER
Enable rising edge interrupt for P0[30]. See bit 0 description.
0
31
P0_31ER
Enable rising edge interrupt for P0[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
153 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.6 GPIO Interrupt Enable for port 0 Falling Edge
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 0 pin.
Table 105. GPIO Interrupt Enable for port 0 Falling Edge (ENF0 - address 0x4002 8094) bit
description
Bit
Symbol
Description
0
P0_0EF
Enable falling edge interrupt for P0[0].
Reset
value
0
0 = Disable falling edge interrupt.
1 = Enable falling edge interrupt.
UM10562
User manual
1
P0_1EF
Enable falling edge interrupt for P0[1]. See bit 0 description.
0
2
P0_2EF
Enable falling edge interrupt for P0[2]. See bit 0 description.
0
3
P0_3EF
Enable falling edge interrupt for P0[3]. See bit 0 description.
0
4
P0_4EF
Enable falling edge interrupt for P0[4]. See bit 0 description.
0
5
P0_5EF
Enable falling edge interrupt for P0[5]. See bit 0 description.
0
6
P0_6EF
Enable falling edge interrupt for P0[6]. See bit 0 description.
0
7
P0_7EF
Enable falling edge interrupt for P0[7]. See bit 0 description.
0
8
P0_8EF
Enable falling edge interrupt for P0[8]. See bit 0 description.
0
9
P0_9EF
Enable falling edge interrupt for P0[9]. See bit 0 description.
0
10
P0_10EF
Enable falling edge interrupt for P0[10]. See bit 0 description.
0
11
P0_11EF
Enable falling edge interrupt for P0[11]. See bit 0 description.
0
12
P0_12EF
Enable falling edge interrupt for P0[12]. See bit 0 description.
0
13
P0_13EF
Enable falling edge interrupt for P0[13]. See bit 0 description.
0
14
P0_14EF
Enable falling edge interrupt for P0[14]. See bit 0 description.
0
15
P0_15EF
Enable falling edge interrupt for P0[15]. See bit 0 description.
0
16
P0_16EF
Enable falling edge interrupt for P0[16]. See bit 0 description.
0
17
P0_17EF
Enable falling edge interrupt for P0[17]. See bit 0 description.
0
18
P0_18EF
Enable falling edge interrupt for P0[18]. See bit 0 description.
0
19
P0_19EF
Enable falling edge interrupt for P0[19]. See bit 0 description.
0
20
P0_20EF
Enable falling edge interrupt for P0[20]. See bit 0 description.
0
21
P0_21EF
Enable falling edge interrupt for P0[21]. See bit 0 description.
0
22
P0_22EF
Enable falling edge interrupt for P0[22]. See bit 0 description.
0
23
P0_23EF
Enable falling edge interrupt for P0[23]. See bit 0 description.
0
24
P0_24EF
Enable falling edge interrupt for P0[24]. See bit 0 description.
0
25
P0_25EF
Enable falling edge interrupt for P0[25]. See bit 0 description.
0
26
P0_26EF
Enable falling edge interrupt for P0[26]. See bit 0 description.
0
27
P0_27EF
Enable falling edge interrupt for P0[27]. See bit 0 description.
0
28
P0_28EF
Enable falling edge interrupt for P0[28]. See bit 0 description.
0
29
P0_29EF
Enable falling edge interrupt for P0[29]. See bit 0 description.
0
30
P0_30EF
Enable falling edge interrupt for P0[30]. See bit 0 description.
0
31
P0_31EF
Enable falling edge interrupt for P0[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
154 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt
Each bit in these read-only registers indicates the rising edge interrupt status for port 2.
Table 106. GPIO Interrupt Status for port 2 Rising Edge Interrupt (STATR2 - 0x4002 80A4) bit
description
Bit
Symbol
Description
0
P2_0REI
Reset
value
Status of Rising Edge Interrupt for P2[0].
0
0 = No rising edge detected.
1 = Rising edge interrupt generated.
UM10562
User manual
1
P2_1REI
Status of Rising Edge Interrupt for P2[1]. See bit 0 description.
0
2
P2_2REI
Status of Rising Edge Interrupt for P2[2]. See bit 0 description.
0
3
P2_3REI
Status of Rising Edge Interrupt for P2[3]. See bit 0 description.
0
4
P2_4REI
Status of Rising Edge Interrupt for P2[4]. See bit 0 description.
0
5
P2_5REI
Status of Rising Edge Interrupt for P2[5]. See bit 0 description.
0
6
P2_6REI
Status of Rising Edge Interrupt for P2[6]. See bit 0 description.
0
7
P2_7REI
Status of Rising Edge Interrupt for P2[7]. See bit 0 description.
0
8
P2_8REI
Status of Rising Edge Interrupt for P2[8]. See bit 0 description.
0
9
P2_9REI
Status of Rising Edge Interrupt for P2[9]. See bit 0 description.
0
10
P2_10REI
Status of Rising Edge Interrupt for P2[10]. See bit 0 description.
0
11
P2_11REI
Status of Rising Edge Interrupt for P2[11]. See bit 0 description.
0
12
P2_12REI
Status of Rising Edge Interrupt for P2[12]. See bit 0 description.
0
13
P2_13REI
Status of Rising Edge Interrupt for P2[13]. See bit 0 description.
0
14
P2_14REI
Status of Rising Edge Interrupt for P2[14]. See bit 0 description.
0
15
P2_15REI
Status of Rising Edge Interrupt for P2[15]. See bit 0 description.
0
16
P2_16REI
Status of Rising Edge Interrupt for P2[16]. See bit 0 description.
0
17
P2_17REI
Status of Rising Edge Interrupt for P2[17]. See bit 0 description.
0
18
P2_18REI
Status of Rising Edge Interrupt for P2[18]. See bit 0 description.
0
19
P2_19REI
Status of Rising Edge Interrupt for P2[19]. See bit 0 description.
0
20
P2_20REI
Status of Rising Edge Interrupt for P2[20]. See bit 0 description.
0
21
P2_21REI
Status of Rising Edge Interrupt for P2[21]. See bit 0 description.
0
22
P2_22REI
Status of Rising Edge Interrupt for P2[22]. See bit 0 description.
0
23
P2_23REI
Status of Rising Edge Interrupt for P2[23]. See bit 0 description.
0
24
P2_24REI
Status of Rising Edge Interrupt for P2[24]. See bit 0 description.
0
25
P2_25REI
Status of Rising Edge Interrupt for P2[25]. See bit 0 description.
0
26
P2_26REI
Status of Rising Edge Interrupt for P2[26]. See bit 0 description.
0
27
P2_27REI
Status of Rising Edge Interrupt for P2[27]. See bit 0 description.
0
28
P2_28REI
Status of Rising Edge Interrupt for P2[28]. See bit 0 description.
0
29
P2_29REI
Status of Rising Edge Interrupt for P2[29]. See bit 0 description.
0
30
P2_30REI
Status of Rising Edge Interrupt for P2[30]. See bit 0 description.
0
31
P2_31REI
Status of Rising Edge Interrupt for P2[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
155 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.8 GPIO Interrupt Status for port 2 Falling Edge Interrupt
Each bit in these read-only registers indicates the falling edge interrupt status for port 2.
Table 107. GPIO Interrupt Status for port 2 Falling Edge Interrupt (STATF2 - 0x4002 80A8) bit
description
Bit
Symbol
0
P2_0FEI
Description
Reset
value
Status of Falling Edge Interrupt for P2[0].
0
0 = No falling edge detected.
1 = Falling edge interrupt generated.
UM10562
User manual
1
P2_1FEI
Status of Falling Edge Interrupt for P2[1]. See bit 0 description.
0
2
P2_2FEI
Status of Falling Edge Interrupt for P2[2]. See bit 0 description.
0
3
P2_3FEI
Status of Falling Edge Interrupt for P2[3]. See bit 0 description.
0
4
P2_4FEI
Status of Falling Edge Interrupt for P2[4]. See bit 0 description.
0
5
P2_5FEI
Status of Falling Edge Interrupt for P2[5]. See bit 0 description.
0
6
P2_6FEI
Status of Falling Edge Interrupt for P2[6]. See bit 0 description.
0
7
P2_7FEI
Status of Falling Edge Interrupt for P2[7]. See bit 0 description.
0
8
P2_8FEI
Status of Falling Edge Interrupt for P2[8]. See bit 0 description.
0
9
P2_9FEI
Status of Falling Edge Interrupt for P2[9]. See bit 0 description.
0
10
P2_10FEI
Status of Falling Edge Interrupt for P2[10]. See bit 0 description.
0
11
P2_11FEI
Status of Falling Edge Interrupt for P2[11]. See bit 0 description.
0
12
P2_12FEI
Status of Falling Edge Interrupt for P2[12]. See bit 0 description.
0
13
P2_13FEI
Status of Falling Edge Interrupt for P2[13]. See bit 0 description.
0
14
P2_14FEI
Status of Falling Edge Interrupt for P2[14]. See bit 0 description.
0
15
P2_15FEI
Status of Falling Edge Interrupt for P2[15]. See bit 0 description.
0
16
P2_16FEI
Status of Falling Edge Interrupt for P2[16]. See bit 0 description.
0
17
P2_17FEI
Status of Falling Edge Interrupt for P2[17]. See bit 0 description.
0
18
P2_18FEI
Status of Falling Edge Interrupt for P2[18]. See bit 0 description.
0
19
P2_19FEI
Status of Falling Edge Interrupt for P2[19]. See bit 0 description.
0
20
P2_20FEI
Status of Falling Edge Interrupt for P2[20]. See bit 0 description.
0
21
P2_21FEI
Status of Falling Edge Interrupt for P2[21]. See bit 0 description.
0
22
P2_22FEI
Status of Falling Edge Interrupt for P2[22]. See bit 0 description.
0
23
P2_23FEI
Status of Falling Edge Interrupt for P2[23]. See bit 0 description.
0
24
P2_24FEI
Status of Falling Edge Interrupt for P2[24]. See bit 0 description.
0
25
P2_25FEI
Status of Falling Edge Interrupt for P2[25]. See bit 0 description.
0
26
P2_26FEI
Status of Falling Edge Interrupt for P2[26]. See bit 0 description.
0
27
P2_27FEI
Status of Falling Edge Interrupt for P2[27]. See bit 0 description.
0
28
P2_28FEI
Status of Falling Edge Interrupt for P2[28]. See bit 0 description.
0
29
P2_29FEI
Status of Falling Edge Interrupt for P2[29]. See bit 0 description.
0
30
P2_30FEI
Status of Falling Edge Interrupt for P2[30]. See bit 0 description.
0
31
P2_31FEI
Status of Falling Edge Interrupt for P2[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
156 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.9 GPIO Interrupt Clear register for port 2
Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding
port 2 pin.
Table 108. GPIO Interrupt Clear register for port 0 (CLR2 - 0x4002 80AC) bit description
Bit
Symbol
Description
0
P2_0CI
Clear GPIO port Interrupts for P2[0].
0 = No effect.
1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
UM10562
User manual
1
P2_1CI
Clear GPIO port Interrupts for P2[1]. See bit 0 description.
2
P2_2CI
Clear GPIO port Interrupts for P2[2]. See bit 0 description.
3
P2_3CI
Clear GPIO port Interrupts for P2[3]. See bit 0 description.
4
P2_4CI
Clear GPIO port Interrupts for P2[4]. See bit 0 description.
5
P2_5CI
Clear GPIO port Interrupts for P2[5]. See bit 0 description.
6
P2_6CI
Clear GPIO port Interrupts for P2[6]. See bit 0 description.
7
P2_7CI
Clear GPIO port Interrupts for P2[7]. See bit 0 description.
8
P2_8CI
Clear GPIO port Interrupts for P2[8]. See bit 0 description.
9
P2_9CI
Clear GPIO port Interrupts for P2[9]. See bit 0 description.
10
P2_10CI
Clear GPIO port Interrupts for P2[10]. See bit 0 description.
11
P2_11CI
Clear GPIO port Interrupts for P2[11]. See bit 0 description.
12
P2_12CI
Clear GPIO port Interrupts for P2[12]. See bit 0 description.
13
P2_13CI
Clear GPIO port Interrupts for P2[13]. See bit 0 description.
14
P2_14CI
Clear GPIO port Interrupts for P2[14]. See bit 0 description.
15
P2_15CI
Clear GPIO port Interrupts for P2[15]. See bit 0 description.
16
P2_16CI
Clear GPIO port Interrupts for P2[16]. See bit 0 description.
17
P2_17CI
Clear GPIO port Interrupts for P2[17]. See bit 0 description.
18
P2_18CI
Clear GPIO port Interrupts for P2[18]. See bit 0 description.
19
P2_19CI
Clear GPIO port Interrupts for P2[19]. See bit 0 description.
20
P2_20CI
Clear GPIO port Interrupts for P2[20]. See bit 0 description.
21
P2_21CI
Clear GPIO port Interrupts for P2[21]. See bit 0 description.
22
P2_22CI
Clear GPIO port Interrupts for P2[22]. See bit 0 description.
23
P2_23CI
Clear GPIO port Interrupts for P2[23]. See bit 0 description.
24
P2_24CI
Clear GPIO port Interrupts for P2[24]. See bit 0 description.
25
P2_25CI
Clear GPIO port Interrupts for P2[25]. See bit 0 description.
26
P2_26CI
Clear GPIO port Interrupts for P2[26]. See bit 0 description.
27
P2_27CI
Clear GPIO port Interrupts for P2[27]. See bit 0 description.
28
P2_28CI
Clear GPIO port Interrupts for P2[28]. See bit 0 description.
29
P2_29CI
Clear GPIO port Interrupts for P2[29]. See bit 0 description.
30
P2_30CI
Clear GPIO port Interrupts for P2[30]. See bit 0 description.
31
P2_31CI
Clear GPIO port Interrupts for P2[31]. See bit 0 description.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
157 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.10 GPIO Interrupt Enable for port 2 Rising Edge
Each bit in these read-write registers enables the rising edge interrupt for the
corresponding port 2 pin.
Which pins are available depends on the part number and package combination. See the
specific device data sheet for details.
Table 109. GPIO Interrupt Enable for port 2 Rising Edge (ENR2 - 0x4002 80B0) bit
description
Bit
Symbol
Description
0
P2_0ER
Enable rising edge interrupt for P2[0].
Reset value
0
0 = Disable rising edge interrupt.
1 = Enable rising edge interrupt.
UM10562
User manual
1
P2_1ER
Enable rising edge interrupt for P2[1]. See bit 0 description.
0
2
P2_2ER
Enable rising edge interrupt for P2[2]. See bit 0 description.
0
3
P2_3ER
Enable rising edge interrupt for P2[3]. See bit 0 description.
0
4
P2_4ER
Enable rising edge interrupt for P2[4]. See bit 0 description.
0
5
P2_5ER
Enable rising edge interrupt for P2[5]. See bit 0 description.
0
6
P2_6ER
Enable rising edge interrupt for P2[6]. See bit 0 description.
0
7
P2_7ER
Enable rising edge interrupt for P2[7]. See bit 0 description.
0
8
P2_8ER
Enable rising edge interrupt for P2[8]. See bit 0 description.
0
9
P2_9ER
Enable rising edge interrupt for P2[9]. See bit 0 description.
0
10
P2_10ER
Enable rising edge interrupt for P2[10]. See bit 0 description.
0
11
P2_11ER
Enable rising edge interrupt for P2[11]. See bit 0 description.
0
12
P2_12ER
Enable rising edge interrupt for P2[12]. See bit 0 description.
0
13
P2_13ER
Enable rising edge interrupt for P2[13]. See bit 0 description.
0
14
P2_14ER
Enable rising edge interrupt for P2[14]. See bit 0 description.
0
15
P2_15ER
Enable rising edge interrupt for P2[15]. See bit 0 description.
0
16
P2_16ER
Enable rising edge interrupt for P2[16]. See bit 0 description.
0
17
P2_17ER
Enable rising edge interrupt for P2[17]. See bit 0 description.
0
18
P2_18ER
Enable rising edge interrupt for P2[18]. See bit 0 description.
0
19
P2_19ER
Enable rising edge interrupt for P2[19]. See bit 0 description.
0
20
P2_20ER
Enable rising edge interrupt for P2[20]. See bit 0 description.
0
21
P2_21ER
Enable rising edge interrupt for P2[21]. See bit 0 description.
0
22
P2_22ER
Enable rising edge interrupt for P2[22]. See bit 0 description.
0
23
P2_23ER
Enable rising edge interrupt for P2[23]. See bit 0 description.
0
24
P2_24ER
Enable rising edge interrupt for P2[24]. See bit 0 description.
0
25
P2_25ER
Enable rising edge interrupt for P2[25]. See bit 0 description.
0
26
P2_26ER
Enable rising edge interrupt for P2[26]. See bit 0 description.
0
27
P2_27ER
Enable rising edge interrupt for P2[27]. See bit 0 description.
0
28
P2_28ER
Enable rising edge interrupt for P2[28]. See bit 0 description.
0
29
P2_29ER
Enable rising edge interrupt for P2[29]. See bit 0 description.
0
30
P2_30ER
Enable rising edge interrupt for P2[30]. See bit 0 description.
0
31
P2_31ER
Enable rising edge interrupt for P2[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
158 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.5.2.11 GPIO Interrupt Enable for port 2 Falling Edge
Each bit in these read-write registers enables the falling edge interrupt for the
corresponding GPIO port 2 pin.
Table 110. GPIO Interrupt Enable for port 2 Falling Edge (ENF2 - 0x4002 80B4) bit description
Bit
Symbol
Description
0
P2_0EF
Enable falling edge interrupt for P2[0].
Reset value
0
0 = Disable falling edge interrupt.
1 = Enable falling edge interrupt.
UM10562
User manual
1
P2_1EF
Enable falling edge interrupt for P2[1]. See bit 0 description.
0
2
P2_2EF
Enable falling edge interrupt for P2[2]. See bit 0 description.
0
3
P2_3EF
Enable falling edge interrupt for P2[3]. See bit 0 description.
0
4
P2_4EF
Enable falling edge interrupt for P2[4]. See bit 0 description.
0
5
P2_5EF
Enable falling edge interrupt for P2[5]. See bit 0 description.
0
6
P2_6EF
Enable falling edge interrupt for P2[6]. See bit 0 description.
0
7
P2_7EF
Enable falling edge interrupt for P2[7]. See bit 0 description.
0
8
P2_8EF
Enable falling edge interrupt for P2[8]. See bit 0 description.
0
9
P2_9EF
Enable falling edge interrupt for P2[9]. See bit 0 description.
0
10
P2_10EF
Enable falling edge interrupt for P2[10]. See bit 0 description.
0
11
P2_11EF
Enable falling edge interrupt for P2[11]. See bit 0 description.
0
12
P2_12EF
Enable falling edge interrupt for P2[12]. See bit 0 description.
0
13
P2_13EF
Enable falling edge interrupt for P2[13]. See bit 0 description.
0
14
P2_14EF
Enable falling edge interrupt for P2[14]. See bit 0 description.
0
15
P2_15EF
Enable falling edge interrupt for P2[15]. See bit 0 description.
0
16
P2_16EF
Enable falling edge interrupt for P2[16]. See bit 0 description.
0
17
P2_17EF
Enable falling edge interrupt for P2[17]. See bit 0 description.
0
18
P2_18EF
Enable falling edge interrupt for P2[18]. See bit 0 description.
0
19
P2_19EF
Enable falling edge interrupt for P2[19]. See bit 0 description.
0
20
P2_20EF
Enable falling edge interrupt for P2[20]. See bit 0 description.
0
21
P2_21EF
Enable falling edge interrupt for P2[21]. See bit 0 description.
0
22
P2_22EF
Enable falling edge interrupt for P2[22]. See bit 0 description.
0
23
P2_23EF
Enable falling edge interrupt for P2[23]. See bit 0 description.
0
24
P2_24EF
Enable falling edge interrupt for P2[24]. See bit 0 description.
0
25
P2_25EF
Enable falling edge interrupt for P2[25]. See bit 0 description.
0
26
P2_26EF
Enable falling edge interrupt for P2[26]. See bit 0 description.
0
27
P2_27EF
Enable falling edge interrupt for P2[27]. See bit 0 description.
0
28
P2_28EF
Enable falling edge interrupt for P2[28]. See bit 0 description.
0
29
P2_29EF
Enable falling edge interrupt for P2[29]. See bit 0 description.
0
30
P2_30EF
Enable falling edge interrupt for P2[30]. See bit 0 description.
0
31
P2_31EF
Enable falling edge interrupt for P2[31]. See bit 0 description.
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
159 of 942
UM10562
NXP Semiconductors
Chapter 8: LPC408x/407x GPIO
8.6 GPIO usage notes
8.6.1 Example: An instantaneous output of 0s and 1s on a GPIO port
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF ;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
FIO0PIN1 = 0xA5;
8.6.2 Writing to FIOSET/FIOCLR vs. FIOPIN
Writing to the FIOSET/FIOCLR registers allow a program to easily change a port’s output
pin(s) to both high and low levels at the same time. When FIOSET or FIOCLR are used,
only pin/bit(s) written with 1 will be changed, while those written as 0 will remain
unaffected.
Writing to the FIOPIN register enables instantaneous output of a desired value on the
parallel GPIO. Data written to the FIOPIN register will affect all pins configured as outputs
on that port: zeroes in the value will produce low level pin outputs and ones in the value
will produce high level pin outputs.
A subset of a port’s pins may be changed by using the FIOMASK register to define which
pins are affected. FIOMASK is set up to contain zeroes in bits corresponding to pins that
will be changed, and ones for all others. Solution 2 from Section 8.6.1 above illustrates
output of 0xA5 on PORT0 pins 15 to 8 while preserving all other PORT0 output pins as
they were before.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
160 of 942
UM10562
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Rev. 1 — 13 September 2012
User manual
9.1 How to read this chapter
This chapter describes the external memory controller for devices that support external
memory. EMC configurations vary with different packages for devices that support
external memory, see Table 111.
Table 111. EMC configuration
Device
package
Data bus Pins available
widths
supported
144-pin
8-bit
Dynamic memory
Static memory
configuration registers[1][2] configuration registers[1][3]
EMC_A[15:0]
EMCStaticConfig1/0
EMC_D[7:0]
EMCStaticWaitWen1/0
EMC_OE
EMCStaticWaitOen1/0
EMC_WE
EMCStaticWaitRd1/0
EMC_CS1:0
EMCStaticWaitPage1/0
External
memory
connections
Section 9.14.3
EMCStaticWaitWr1/0
EMCStaticWaitTurn1/0
180-pin
16-bit, 8-bit EMC_A[19:0]
EMC_D[15:0]
EMCDynamicConfig1/0
EMCStaticConfig1/0
EMCDynamicRasCas1/0
EMCStaticWaitWen1/0
EMC_OE
EMCStaticWaitOen1/0
EMC_WE
EMCStaticWaitRd1/0
EMC_BLS1:0
EMCStaticWaitPage1/0
EMC_CS1:0
EMCStaticWaitWr1/0
EMC_DYCS1:0
EMCStaticWaitTurn1/0
Section 9.14.2
Section 9.14.3
EMC_CAS
EMC_RAS
EMC_CLK1:0
EMC_CKE1:0
EMC_DQM1:0
208-pin
32-bit,
EMC_A[25:0]
16-bit, 8-bit EMC_D[31:0]
EMCDynamicConfig3/2/1/0
EMCStaticConfig3/2/1/0
Section 9.14.1
Section 9.14.2
Section 9.14.3
EMCDynamicRasCas3/2/1/0 EMCStaticWaitWen3/2/1/0
EMC_OE
EMCStaticWaitOen3/2/1/0
EMC_WE
EMCStaticWaitRd3/2/1/0
EMC_BLS3:0
EMCStaticWaitPage3/2/1/0
EMC_CS3:0
EMCStaticWaitWr3/2/1/0
EMC_DYCS3:0
EMCStaticWaitTurn3/2/1/0
EMC_CAS
EMC_RAS
EMC_CLK1:0
EMC_CKE3:0
EMC_DQM3:0
[1]
UM10562
User manual
In addition to the registers that are common to all EMC operations: EMCControl and EMCConfig.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
161 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
[2]
In addition to the registers that are common to all EMC dynamic chip selects: EMCDynamicControl,
EMCDynamicRefresh, EMCDynamicReadConfig, EMCDynamicRP, EMCDynamicRAS,
EMCDynamicSREX, EMCDynamicAPR, EMCDynamicDAL, EMCDynamicWR, EMCDynamicRC,
EMCDynamicRFC, EMCDynamicXSR, EMCDynamicRRD, and EMCDynamicMRD
[3]
In addition to the EMCStaticExtendedWait register which applies to all static chip selects.
9.2 Basic configuration
The EMC is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCEMC.
Remark: The EMC is enabled on reset (PCEMC = 1). On POR and warm reset, the
EMC is enabled as well, see Table 115 and Table 118.
2. Clock: The EMC clock can be the same as the CPU clock (the default), or half that.
The lower rate is intended to be used primarily when the CPU is running faster than
the external bus can support. Clock selection for the EMC is described in
Section 3.3.3.1.
3. Pins: Select EMC pins and pin modes through the relevant IOCON registers
(Section 7.4.1).
4. Configuration: See Table 115 to Table 118. Also see additional EMC configurations in
Section 3.3.7.1 “System Controls and Status register”. In particular make sure that the
address shift mode is configured correctly for the application hardware.
5. MPU: Default memory space permissions for the CPU do not allow program execution
from the address range that includes the dynamic memory chip selects. These
permissions can be changed by programming the MPU (see the ARM Cortex-M4
User Guide referred to in Section 40.1 for details of MPU operation.
6. To set the EMC delay clock see the EMC delay clock register in the system control
block (see Section 3.3.6.1).
7. To calibrate the EMC clock, see Section 3.3.6.2.
9.3 Introduction
The External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort Memory
Controller peripheral offering support for asynchronous static memory devices such as
RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
162 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.4 Features
• Static chip selects each support up to 64 MB of data. By enabling the address shift
mode, static chip select 0 can support up to 256 MB, and static chip select 1 can
support up to 128 MB (see SCS register bit 0 (Section 3.3.7.1)
• Dynamic chip selects each support up to 256 MB of data.
• Dynamic memory interface support including Single Data Rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and Flash, with or
without asynchronous page mode.
•
•
•
•
•
Low transaction latency.
Read and write buffers to reduce latency and to improve performance.
8-bit, 16-bit, and 32-bit wide static memory support.
16-bit and 32-bit wide chip select SDRAM memory support.
Static memory features include:
– Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts.
That is typical 512 Mbit, 256 Mbit, and 128 Mbit parts, with 4, 8, 16, or 32 data bits per
device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
• Programmable delay elements allow fine-tuning EMC timing.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
163 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.5 EMC functional description
Figure 16 shows a block diagram of the EMC.
Data buffers
(4 x 16 word)
EMC_D[31:0]
AHB slave
memory
interface
shared
signals
EMC_A[25:0]
EMC_WE
EMC_OE
static
memory
signals
AHB slave
register
interface
HCLK
Memory controller
state machine
EMCCLK
programmable
delay
EMCDLYCTL[4:0]
EMCCLKDELAY
EMC_CS3:0
Pad Interface
AHB bus
EMC_BLS3:0
EMC_DYCS3:0
EMC_CAS
EMC_RAS
EMC_CKE3:0
FBCLKIN
dynamic
memory
signals
EMC_DQM3:0
EMCDLYCTL[28:24]
programmable
delay
EMC_CLKOUT1
EMCDLYCTL[20:16]
programmable
delay
EMC_CLKOUT0
EMCDLYCTL[12:8]
programmable
delay
120524
Fig 16. EMC block diagram
The functions of the EMC blocks are described in the following sections:
•
•
•
•
•
AHB slave register interface.
AHB slave memory interfaces.
Data buffers.
Memory controller state machine.
Pad interface.
Note: For 32 bit wide chip selects data is transferred to and from dynamic memory in
SDRAM bursts of four. For 16 bit wide chip selects SDRAM bursts of eight are used.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
164 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.5.1 AHB slave register interface
The AHB slave register interface block enables the registers of the EMC to be
programmed. This module also contains most of the registers and performs the majority of
the register address decoding.
To eliminate the possibility of endianness problems, all data transfers to and from the
registers of the EMC must be 32 bits wide.
Note: If an access is attempted with a size other than a word (32 bits), it causes an
ERROR response to the AHB bus and the transfer is terminated.
9.5.2 AHB slave memory interface
The AHB slave memory interface allows access to external memories.
9.5.2.1 Memory transaction endianness
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the EMCConfig register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.
9.5.2.2 Memory transaction size
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.
9.5.2.3 Write protected memory areas
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.
9.5.3 Pad interface
The pad interface block provides the interface to the pads. The pad interface uses a
feedback clock, FBCLKIN, from the CLKOUT0 output of the EMC to resynchronize
SDRAM read data from the off-chip to on-chip domains.
9.5.4 Data buffers
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM initialization. The buffers must be enabled
during normal operation.
The buffers can be enabled or disabled for static memory using the EMCStaticConfig
Registers.
9.5.4.1 Write buffers
Write buffers are used to:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
165 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
• Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.
• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Write buffer operation:
• If the buffers are enabled, an AHB write operation writes into the Least Recently Used
(LRU) buffer, if empty.
If the LRU buffer is not empty, the contents of the buffer are flushed to memory to
make space for the AHB write data.
• If a buffer contains write data it is marked as dirty, and its contents are written to
memory before the buffer can be reallocated.
The write buffers are flushed whenever:
• The memory controller state machine is not busy performing accesses to external
memory.
The memory controller state machine is not busy performing accesses to external
memory, and an AHB interface is writing to a different buffer.
Note: For dynamic memory, the smallest buffer flush is a quadword of data. For static
memory, the smallest buffer flush is a byte of data.
9.5.4.2 Read buffers
Read buffers are used to:
• Buffer read requests from memory. Future read requests that hit the buffer read the
data from the buffer rather than memory, reducing transaction latency.
Convert all read transactions into quadword bursts on the external memory interface.
This enhances transfer efficiency for dynamic memory.
• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Read buffer operation:
• If the buffers are enabled and the read data is contained in one of the buffers, the read
data is provided directly from the buffer.
• If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is
dirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
166 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.5.5 Memory controller state machine
The memory controller state machine comprises a static memory controller and a dynamic
memory controller.
9.5.6 Timing control with programmable delay elements
Programmable delay elements are provided to allow fine-tuning the timing of various
aspects of EMC operation in connection with SDRAM memory.
• For the clock delayed operating mode, separate programmable delays are provided
for each potential clock output, CLKOUT0 and CLKOUT1.
• For the command delayed operating mode, a programmable delay is provided to
control delay of all command outputs.
• For both operating modes, a programmable delay is provided to control the time at
which input data from SDRAM memory is sampled.
The locations of the programmable delays are shown in the EMC overall block diagram
(Figure 16). See descriptions of the EMCDLYCTL and EMCCAL registers for more
information.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
167 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.6 Low-power operation
In many systems, the contents of the memory system have to be maintained during
low-power sleep modes. The EMC provides a mechanism to place the dynamic memories
into self-refresh mode.
Self-refresh mode can be entered by software by setting the SREFREQ bit in the
EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register.
Any transactions to memory that are generated while the memory controller is in
self-refresh mode are rejected and an error response is generated to the AHB bus.
Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to
normal operation. See the memory data sheet for refresh requirements.
Note: The static memory can be accessed as normal when the SDRAM memory is in
self-refresh mode.
9.6.1 Low-power SDRAM Deep-sleep Mode
The EMC supports JEDEC low-power SDRAM deep-sleep mode. Deep-sleep mode can
be entered by setting the deep-sleep mode (DP) bit, the dynamic memory clock enable bit
(CE), and the dynamic clock control bit (CS) in the EMCDynamicControl register. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
9.6.2 Low-power SDRAM partial array refresh
The EMC supports JEDEC low-power SDRAM partial array refresh. Partial array refresh
can be programmed by initializing the SDRAM memory device appropriately. When the
memory device is put into self-refresh mode only the memory banks specified are
refreshed. The memory banks that are not refreshed lose their data contents.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
168 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.7 Memory bank select
Eight independently-configurable memory chip selects are supported:
• Pins EMC_CS3 to EMC_CS0 are used to select static memory devices.
• Pins EMC_DYCS3 to EMC_DYCS0 are used to select dynamic memory devices.
Static memory chip select ranges are each 64 megabytes in size, while dynamic memory
chip selects cover a range of 256 megabytes each. Table 112 shows the address ranges
of the chip selects.
Table 112. Memory bank selection
Chip select pin
EMC_CS0
Address range
Memory type
Size of range
0x8000 0000 - 0x83FF FFFF
Static
64 MB
EMC_CS1
0x9000 0000 - 0x93FF FFFF
Static
64 MB
EMC_CS2
0x9800 0000 - 0x9BFF FFFF
Static
64 MB
EMC_CS3
0x9C00 0000 - 0x9FFF FFFF
Static
64 MB
EMC_DYCS0
0xA000 0000 - 0xAFFF FFFF
Dynamic
256 MB
EMC_DYCS1
0xB000 0000 - 0xBFFF FFFF
Dynamic
256 MB
EMC_DYCS2
0xC000 0000 - 0xCFFF FFFF
Dynamic
256 MB
EMC_DYCS3
0xD000 0000 - 0xDFFF FFFF
Dynamic
256 MB
9.8 EMC Reset
The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip
power is applied, and when a brown-out condition is detected (see the System Control
Block chapter for details of Brown-Out Detect). The other reset is from the external Reset
pin and the Watchdog Timer.
A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how
the EMC is reset (see Section 3.3.7.1 “System Controls and Status register”). The default
configuration (EMC_Reset_Disable = 0) is that both EMC resets are asserted when any
type of reset event occurs. In this mode, all registers and functions of the EMC are
initialized upon any reset condition.
If EMC_Reset_Disable is set to 1, many portions of the EMC are only reset by a power-on
or brown-out event, in order to allow the EMC to retain its state through a warm reset
(external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be
maintained through a warm reset.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
169 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.9 Address shift mode
The EMC supports an optional address shift mode for static memories that can simplify
board design and potentially increase external memory addressing range in some cases.
The latter cases are described in footnotes of Table 3 “Memory usage and details” in the
Memory Map chapter of this manual.
Address shift mode is controlled by a configuration bit in the SCS register, called EMC
Shift Control (see Section 3.3.7.1 “System Controls and Status register”).
When the address shift mode is not activated (the EMC Shift Control bit in the SCS
register = 1), static memory addresses are output as byte addresses. This means that for
memories wider than a byte, one or two address lines are not used, and that address
connections to memory devices must be shifted in the board design. For example, if a
32-bit wide memory system is connected, the lowest line address of the memory device(s)
would be connected to EMC address line 2, skipping bits 0 and 1.
When the address shift mode is activated (the EMC Shift Control bit in the SCS register =
0), static memory addresses are shifted to match the lowest address bit needed for bus
width. In this case, the lowest address line of the memory device(s) is always to EMC
address line 0.
9.10 Memory mapped I/O and burst disable
By default, the EMC uses buffering to obtain better external memory access performance.
However, in the case of memory mapped I/O devices, the read-ahead operations that
occur due to the buffering can cause issues with some such devices. This could be from a
change of status in one register caused by reading another register, or could simply cause
an unplanned read of a data FIFO when another register in the device is read intentionally.
To prevent this issue, the use of buffering to read ahead of actual CPU memory read
requests can be disabled. The configuration bit that controls this function is called EMC
Burst Control, and is found in the SCS register (see Section 3.3.7.1 “System Controls and
Status register”).
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
170 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.11 Using the EMC with SDRAM
9.11.1 Mode register setup
When using the EMC with SDRAM, the SDRAM devices must be configured appropriately
for the EMC. This includes setting up the SDRAMs for a 128-bit sequential burst. The
burst configuration is done through a mode register in the SDRAM memory. Figure 17
shows the layout for a JEDEC standard SDRAM mode register.
A11 A10 A9
A8
A7
Reserved WB OpMode
A6
A5
A4
CL
A3
BT
A2
A1
A0
BL
- Address bus
- Mode register
Burst Length
M2 M1 M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
M3 Type
0
Sequenctial
1
Interleaved
CAS Latency
M6 M5 M4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Operating Mode
M8 M7 M6-M0
0
0 Defined
-
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Mode
Standard operation
Others reserved
Write Burst Mode
M9 Mode
0
Programmed burst length
1
Single location access
120515
Fig 17. SDRAM mode register
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
171 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
The mode register is loaded by first sending the “Set Mode” Command to the SDRAM
using the DYNAMICCONTROL register’s SDRAM Initialization bits to send a MODE
command, and then reading the SDRAM at an address that is partially formed from the
new mode register value. The actual value loaded into the mode register is taken by the
SDRAM from the address lines of the EMC while they are sending the row address during
the read.
Example
To determine the address to read from to load the mode register, the portion of the EMC
address bits that map to the row address must be identified. In this example, we will use:
• a single 8M by 16-bit external SDRAM chip in Row, Bank, Column mode on CS0
• CAS latency of 2
Since the EMC uses bursts of 8 for a 16-bit external memory, we need to load the mode
register with a burst length of 8 (8 x 16 bits memory width = 128 bits). The mode register
configuration needed is 0x023. To load the mode register, we need to do a read from the
address constructed as follows:
Information needed:
• Base address for Dynamic Chip Select 0, found in Table 3. For this device, the
address is 0xA000 0000.
• Mode register value, based on information from both the SDRAM data sheet, as in
Figure 17, and the EMC. In this example, the value will be 0x23. This represents a
programmed burst length, CAS latency of 2, sequential burst type, and a burst length
of 8, as described in Section 9.5.
• Bank bits and column bits, look up in Table 134. In this example, it is 4 banks and 9
column bits.
• Bus width, defined in this example to be 16 bits.
The Mode register value calculation is:
Base address + (mode register value << (bank bits + column bits + bus width/16)
The shift operation aligns the mode register value with the row address bits.
In this example:
0xA000 0000 + (0x23 << (2 + 9 + 1)) = 0xA000 0000 + 0x23000 = 0xA002 3000
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
172 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.12 Pin description
Table 113 shows the interface and control signal pins for the EMC.
Table 113. Pad interface and control signal descriptions
Name
Type
Value on
POR reset
Value during
self-refresh
Description
EMC_A[23:0]
Output
0
Depends on static
memory accesses
External memory address output. Used for both static and
SDRAM devices. SDRAM memories use only bits [14:0].
EMC_D[31:0]
Input/
Output
Data
outputs = 0
Depends on static
memory accesses
External memory data lines. These are inputs when data is
read from external memory and outputs when data is
written to external memory.
EMC_OE
Output
1
Depends on static
memory accesses
Low active output enable for static memory devices.
EMC_BLS3:0
Output
0xF
Depends on static
memory accesses
Low active byte lane selects. Used for static memory
devices.
EMC_WE
Output
1
Depends on static
memory accesses
Low active write enable. Used for SDRAM and static
memories.
EMC_CS3:0
Output
0xF
Depends on static
memory accesses
Static memory chip selects. Default active LOW. Used for
static memory devices.
EMC_DYCS3:0
Output
0xF
0xF
EMC_CAS
Output
1
1
SDRAM chip selects. Used for SDRAM devices.
Column address strobe. Used for SDRAM devices.
EMC_RAS
Output
1
1
EMC_CLK1:0
Output
Follows
CCLK
Follows CCLK
EMC_CKE3:0
Output
0xF
0x0
SDRAM clock enables. Used for SDRAM devices. One is
allocated for each Chip Select.
EMC_DQM3:0
Output
0xF
0xF
Data mask output to SDRAMs. Used for SDRAM devices
and static memories.
UM10562
User manual
Row address strobe. Used for SDRAM devices.
SDRAM clocks. Used for SDRAM devices.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
173 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13 Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. .
The EMC clock configuration and clock calibration registers are located in the system
control block. See Section 3.3.6.1 and Section 3.3.6.2.
Table 114. Register overview: EMC (base address 0x2009 0000)
Register Name
CONTROL
Access
Address Description
offset
R/W
0x000
Controls operation of the memory controller.
STATUS
RO
0x004
Provides EMC status information.
CONFIG
R/W
0x008
Configures operation of the memory controller
DYNAMICCONTROL
R/W
0x020
Controls dynamic memory operation.
DYNAMICREFRESH
R/W
0x024
Configures dynamic memory refresh.
DYNAMICREADCONFIG
R/W
0x028
Configures dynamic memory read strategy.
DYNAMICRP
R/W
0x030
Precharge command period.
DYNAMICRAS
R/W
0x034
Active to precharge command period.
DYNAMICSREX
R/W
0x038
Self-refresh exit time.
DYNAMICAPR
R/W
0x03C
Last-data-out to active command time.
DYNAMICDAL
R/W
0x040
Data-in to active command time.
DYNAMICWR
R/W
0x044
Write recovery time.
DYNAMICRC
R/W
0x048
Selects the active to active command period.
DYNAMICRFC
R/W
0x04C
Selects the auto-refresh period.
DYNAMICXSR
R/W
0x050
Time for exit self-refresh to active command.
DYNAMICRRD
R/W
0x054
Latency for active bank A to active bank B.
DYNAMICMRD
R/W
0x058
STATICEXTENDEDWAIT
R/W
DYNAMICCONFIG0
Warm
POR Table
Reset
Reset
Value[1] Value[1]
0x1
0x3
115
-
0x5
116
-
0x0
117
-
0x006
118
-
0x0
119
-
0x0
120
-
0x0F
121
-
0xF
122
-
0xF
123
-
0xF
124
-
0xF
125
-
0xF
126
-
0x1F
127
-
0x1F
128
-
0x1F
129
-
0xF
130
Time for load mode register to active
command.
-
0xF
131
0x080
Time for long static memory read and write
transfers.
-
0x0
132
R/W
0x100
Configuration information for EMC_DYCS0.
-
0x0
133
DYNAMICRASCAS0
R/W
0x104
RAS and CAS latencies for EMC_DYCS0.
-
0x303
135
DYNAMICCONFIG1
R/W
0x120
Configuration information for EMC_DYCS1.
-
0x0
133
DYNAMICRASCAS1
R/W
0x124
RAS and CAS latencies for EMC_DYCS1.
-
0x303
135
DYNAMICCONFIG2
R/W
0x140
Configuration information for EMC_DYCS2.
-
0x0
133
DYNAMICRASCAS2
R/W
0x144
RAS and CAS latencies for EMC_DYCS2.
-
0x303
135
DYNAMICCONFIG3
R/W
0x160
Configuration information for EMC_DYCS3.
-
0x0
133
DYNAMICRASCAS3
R/W
0x164
RAS and CAS latencies for EMC_DYCS3.
-
0x303
135
STATICCONFIG0
R/W
0x200
Configuration for EMC_CS0.
-
0x0
136
STATICWAITWEN0
R/W
0x204
Delay from EMC_CS0 to write enable.
-
0x0
137
STATICWAITOEN0
R/W
0x208
Delay from EMC_CS0 or address change,
whichever is later, to output enable.
-
0x0
138
STATICWAITRD0
R/W
0x20C
Delay from EMC_CS0 to a read access.
-
0x1F
139
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
174 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Table 114. Register overview: EMC (base address 0x2009 0000) …continued
Register Name
Access
Address Description
offset
Warm
POR Table
Reset
Reset
Value[1] Value[1]
STATICWAITPAGE0
R/W
0x210
Delay for asynchronous page mode
sequential accesses for EMC_CS0.
-
0x1F
140
STATICWAITWR0
R/W
0x214
Delay from EMC_CS0 to a write access.
-
0x1F
141
STATICWAITTURN0
R/W
0x218
Number of bus turnaround cycles EMC_CS0.
-
0xF
142
STATICCONFIG1
R/W
0x220
Memory configuration for EMC_CS1.
-
0x0
136
STATICWAITWEN1
R/W
0x224
Delay from EMC_CS1 to write enable.
-
0x0
137
STATICWAITOEN1
R/W
0x228
Delay from EMC_CS1 or address change,
whichever is later, to output enable.
-
0x0
138
STATICWAITRD1
R/W
0x22C
Delay from EMC_CS1 to a read access.
-
0x1F
139
STATICWAITPAGE1
R/W
0x230
Delay for asynchronous page mode
sequential accesses for EMC_CS1.
-
0x1F
140
STATICWAITWR1
R/W
0x234
Delay from EMC_CS1 to a write access.
-
0x1F
141
STATICWAITTURN1
R/W
0x238
Bus turnaround cycles for EMC_CS1.
-
0xF
142
STATICCONFIG2
R/W
0x240
Memory configuration for EMC_CS2.
-
0x0
136
STATICWAITWEN2
R/W
0x244
Delay from EMC_CS2 to write enable.
-
0x0
137
STATICWAITOEN2
R/W
0x248
Delay from EMC_CS2 or address change,
whichever is later, to output enable.
-
0x0
138
STATICWAITRD2
R/W
0x24C
Delay from EMC_CS2 to a read access.
-
0x1F
139
STATICWAITPAGE2
R/W
0x250
Delay for asynchronous page mode
sequential accesses for EMC_CS2.
-
0x1F
140
STATICWAITWR2
R/W
0x254
Delay from EMC_CS2 to a write access.
-
0x1F
141
EMCStaticWaitTurn2
R/W
0x258
Bus turnaround cycles for EMC_CS2.
-
0xF
142
STATICCONFIG3
R/W
0x260
Memory configuration for EMC_CS3.
-
0x0
136
STATICWAITWEN3
R/W
0x264
Delay from EMC_CS3 to write enable.
-
0x0
137
STATICWAITOEN3
R/W
0x268
Delay from EMC_CS3 or address change,
whichever is later, to output enable.
-
0x0
138
STATICWAITRD3
R/W
0x26C
Delay from EMC_CS3 to a read access.
-
0x1F
139
STATICWAITPAGE3
R/W
0x270
Delay for asynchronous page mode
sequential accesses for EMC_CS3.
-
0x1F
140
STATICWAITWR3
R/W
0x274
Delay from EMC_CS3 to a write access.
-
0x1F
141
STATICWAITTURN3
R/W
0x278
Bus turnaround cycles for EMC_CS3.
-
0xF
142
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
175 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.1 EMC Control register
The EMCControl register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation. Table 115 shows the bit
assignments for the EMCControl register.
Table 115. EMC Control register (Control - address 0x2009 C000) bit description
Bit
Symbol Value Description
0
E
Reset
Value
EMC Enable. Indicates if the EMC is enabled or disabled:
0
Disabled
1
Enabled (POR and warm reset value).
1
Disabling the EMC reduces power consumption. When the memory controller is disabled
the memory is not refreshed. The memory controller is enabled by setting the enable bit, or
by reset. This bit must only be modified when the EMC is in idle state.[1]
1
M
Address mirror. Indicates normal or reset memory map:
0
Normal memory map.
1
Reset memory map. Static memory EMC_CS1 is mirrored onto EMC_CS0 and
EMC_DYCS0 (POR reset value).
1
On POR, EMC_CS1 is mirrored to both EMC_CS0 and EMC_DYCS0 memory areas.
Clearing the M bit enables EMC_CS0 and EMC_DYCS0 memory to be accessed.
2
31:3
L
-
Low-power mode. Indicates normal, or low-power mode:
0
Normal mode (warm reset value).
1
Low-power mode. Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The memory controller returns
to normal functional mode by clearing the low-power mode bit (L), or by POR. This bit must
only be modified when the EMC is in idle state.[1]
Reserved. Read value is undefined, only zero should be written.
[1]
UM10562
User manual
0
NA
The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
176 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.2 EMC Status register
The read-only EMCStatus register provides EMC status information.
Table 116. EMC Status register (STATUS - address 0x2009 C008) bit description
Bit
Symbol Value Description
0
B
1
2
Reset Value
Busy. This bit is used to ensure that the memory controller enters the low-power or
disabled mode cleanly by determining if the memory controller is busy or not.
0
EMC is idle (warm reset value).
1
EMC is busy performing memory transactions, commands, auto-refresh cycles, or is
in self-refresh mode (POR reset value).
S
Write buffer status.This bit enables the EMC to enter low-power mode or disabled
mode cleanly.
0
Write buffers empty (POR reset value)
1
Write buffers contain data.
SA
Self-refresh acknowledge. This bit indicates the operating mode of the EMC.
0
Normal mode
1
Self-refresh mode (POR reset value).
31:3 -
1
0
1
Reserved. The value read from a reserved bit is not defined.
NA
9.13.3 EMC Configuration register
The EMCConfig register configures the operation of the memory controller. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This register is accessed with one
wait state.
Table 117. EMC Configuration register (CONFIG - address 0x2009 C008) bit description
Bit
Symbol Value Description
0
EM
7:1
-
8
CLKR
31:9 -
UM10562
User manual
Reset Value
Endian mode. On power-on reset, the value of the endian bit is 0. All data must be
flushed in the EMC before switching between little-endian and big-endian modes.
0
Little-endian mode (POR reset value).
1
Big-endian mode.
Reserved. Read value is undefined, only zero should be written.
CCLK: CLKOUT ratio. This bit must contain 0 for proper operation of the EMC.
0
1:1 (POR reset value)
1
1:2 (this option is not available)
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
0
NA
© NXP B.V. 2012. All rights reserved.
177 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.4 Dynamic Memory Control register
The EMCDynamicControl register controls dynamic memory operation. The control bits
can be altered during normal operation.
Table 118. Dynamic Control register (DYNAMICCONTROL - address 0x2009 C020) bit description
Bit
Symbol
0
CE
1
2
Value Description
Reset
Value
Dynamic memory clock enable.
0
0
Clock enable of idle devices are deasserted to save power (POR reset value).
1
All clock enables are driven HIGH continuously.[1]
CS
Dynamic memory clock control. When clock control is LOW the output clock CLKOUT is
stopped when there are no SDRAM transactions. The clock is also stopped during
self-refresh mode.
0
CLKOUT stops when all SDRAMs are idle and during self-refresh mode.
1
CLKOUT runs continuously (POR reset value).
SR
Self-refresh request, EMCSREFREQ. By writing 1 to this bit self-refresh can be entered
under software control. Writing 0 to this bit returns the EMC to normal mode.
1
1
The self-refresh acknowledge bit in the Status register must be polled to discover the
current operating mode of the EMC.[2]
4:3
-
5
MMC
6
-
8:7
I
13:9
0
Normal mode.
1
Enter self-refresh mode (POR reset value).
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
-
Memory clock control.
0
0
CLKOUT enabled (POR reset value).
1
CLKOUT disabled.[3]
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
SDRAM initialization.
00
0x0
Issue SDRAM NORMAL operation command (POR reset value).
0x1
Issue SDRAM MODE command.
0x2
Issue SDRAM PALL (precharge all) command.
0x3
Issue SDRAM NOP (no operation) command)
-
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
-
31:14 -
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
-
[1]
Clock enable must be HIGH during SDRAM initialization.
[2]
The memory controller exits from power-on reset with the self-refresh bit HIGH. To enter normal functional
mode set this bit LOW.
[3]
Disabling CLKOUT can be performed if there are no SDRAM memory transactions. When enabled this bit
can be used in conjunction with the dynamic memory clock control (CS) field.
Remark: Deep-sleep mode can be entered by setting the deep-sleep mode (DP) bit, the
dynamic memory clock enable bit (CE), and the dynamic clock control bit (CS) to one. The
device is then put into a low-power mode where the device is powered down and no
longer refreshed. All data in the memory is lost.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
178 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.5 Dynamic Memory Refresh Timer register
The EMCDynamicRefresh register configures dynamic memory operation. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. However, these control bits can, if
necessary, be altered during normal operation. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed. .
Table 119. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address
0x2009 C024) bit description
Bit
Symbol
Description
Reset
value
10:0
REFRESH
Refresh timer.
Indicates the multiple of 16 CCLKs between SDRAM refresh cycles.
0x0 = Refresh disabled (POR reset value).
0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles.
For example:
0
0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles.
0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles
31:11 -
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
For example, for the refresh period of 16 µs, and a CCLK frequency of 50 MHz, the
following value must be programmed into this register:
(16 x 10-6 x 50 x 106) / 16 = 50 or 0x32
If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),
the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the
clock rate is reduced during the wake-up period of a reset cycle. During this period, the
EMC (and all other portions of the device that are being clocked) run from the IRC
oscillator at 12 MHz. So, 12 MHz must be considered the CCLK rate for refresh
calculations if auto-refresh through warm reset is requested.
Note: The refresh cycles are evenly distributed. However, there might be slight variations
when the auto-refresh command is issued depending on the status of the memory
controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
179 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.6 Dynamic Memory Read Configuration register
The EMCDynamicReadConfig register configures the dynamic memory read strategy.
This register must only be modified during system initialization. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects, so a single read
strategy must be used for all dynamic memories.
Table 120 shows the bit assignments for the EMCDynamicReadConfig register.
Table 120. Dynamic Memory Read Configuration register (DYNAMICREADCONFIG - address 0x2009 C028) bit
description
Bit
Symbol
1:0
RD
31:2
Value Description
Reset
Value
Read data strategy
0x0
0x0
Clock out delayed strategy, using CLKOUT (command not delayed, clock out
delayed). POR reset value.
0x1
Command delayed strategy, using EMCCLKDELAY (command delayed, clock out
not delayed).
0x2
Command delayed strategy plus one clock cycle, using EMCCLKDELAY
(command delayed, clock out not delayed).
0x3
Command delayed strategy plus two clock cycles, using EMCCLKDELAY
(command delayed, clock out not delayed).
-
Reserved. Read value is undefined, only zero should be written.
NA
When using command delayed strategy, programmable delays can be used to adjust the
timing of the control signals output by the EMC. See Section 9.5.6 and Section 3.3.6.1.
9.13.7 Dynamic Memory Precharge Command Period register
The EMCDynamicTRP register enables you to program the precharge command period,
tRP. This register must only be modified during system initialization. This value is normally
found in SDRAM data sheets as tRP. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 121. Dynamic Memory Precharge Command Period register (DYNAMICRP - address
0x2009 C030) bit description
UM10562
User manual
Bit
Symbol
Description
3:0
TRP
Precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset
value
0xF
-
© NXP B.V. 2012. All rights reserved.
180 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.8 Dynamic Memory Active to Precharge Command Period register
The EMCDynamicTRAS register enables you to program the active to precharge
command period, tRAS. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRAS. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 122. Dynamic Memory Active to Precharge Command Period register (DYNAMICRAS address 0x2009 C034) bit description
Bit
Symbol Description
Reset
value
3:0
TRAS
Active to precharge command period.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0xF
-
9.13.9 Dynamic Memory Self-refresh Exit Time register
The EMCDynamicTSREX register enables you to program the self-refresh exit time,
tSREX. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tSREX, for devices without this parameter you
use the same value as tXSR. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 123. Dynamic Memory Self Refresh Exit Time register (DYNAMICSREX - address
0x2009 C038) bit description
UM10562
User manual
Bit
Symbol
Description
3:0
TSREX
Self-refresh exit time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset
value
0xF
-
© NXP B.V. 2012. All rights reserved.
181 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.10 Dynamic Memory Last Data Out to Active Time register
The EMCDynamicTAPR register enables you to program the last-data-out to active
command time, tAPR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tAPR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 124. Dynamic Memory Last Data Out to Active Time register (DYNAMICAPR - address
0x2009 C03C) bit description
Bit
Symbol
Description
Reset
value
3:0
TAPR
Last-data-out to active command time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0xF
-
9.13.11 Dynamic Memory Data-in to Active Command Time register
The EMCDynamicTDAL register enables you to program the data-in to active command
time, tDAL. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tDAL, or tAPW. This register is accessed with
one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 125. Dynamic Memory Data In to Active Command Time register (DYNAMICDAL address 0x2009 C040) bit description
UM10562
User manual
Bit
Symbol Description
3:0
TDAL
Data-in to active command.
0x0 - 0xE = n clock cycles. The delay is in CCLK cycles.
0xF = 15 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset
value
0xF
-
© NXP B.V. 2012. All rights reserved.
182 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.12 Dynamic Memory Write Recovery Time register
The EMCDynamicTWR register enables you to program the write recovery time, tWR. It is
recommended that this register is modified during system initialization, or when there are
no current or outstanding transactions. This can be ensured by waiting until the EMC is
idle, and then entering low-power, or disabled mode. This value is normally found in
SDRAM data sheets as tWR, tDPL, tRWL, or tRDL. This register is accessed with one
wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 126. Dynamic Memory Write Recovery Time register (DYNAMICWR - address
0x2009 C044) bit description
Bit
Symbol Description
Reset
value
3:0
TWR
Write recovery time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0xF
-
9.13.13 Dynamic Memory Active to Active Command Period register
The EMCDynamicTRC register enables you to program the active to active command
period, tRC. It is recommended that this register is modified during system initialization, or
when there are no current or outstanding transactions. This can be ensured by waiting
until the EMC is idle, and then entering low-power, or disabled mode. This value is
normally found in SDRAM data sheets as tRC. This register is accessed with one wait
state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 127. Dynamic Memory Active to Active Command Period register (DYNAMICRC address 0x2009 C048) bit description
UM10562
User manual
Bit
Symbol
Description
Reset
value
4:0
TRC
Active to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
0x1F
31:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
183 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.14 Dynamic Memory Auto-refresh Period register
The EMCDynamicTRFC register enables you to program the auto-refresh period, and
auto-refresh to active command period, tRFC. It is recommended that this register is
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. This value is normally found in SDRAM data sheets as
tRFC, or sometimes as tRC. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 128. Dynamic Memory Auto Refresh Period register (DYNAMICRFC - address 0x2009
C04C) bit description
Bit
Symbol
Description
Reset
value
4:0
TRFC
Auto-refresh period and auto-refresh to active command period.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
0x1F
31:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
9.13.15 Dynamic Memory Exit Self-refresh register
The EMCDynamicTXSR register enables you to program the exit self-refresh to active
command time, tXSR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tXSR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 129. Dynamic Memory Exit Self Refresh register (DYNAMICXSR - address
0x2009 C050) bit description
UM10562
User manual
Bit
Symbol
Description
Reset
value
4:0
TXSR
Exit self-refresh to active command time.
0x0 - 0x1E = n + 1 clock cycles. The delay is in CCLK cycles.
0x1F = 32 clock cycles (POR reset value).
0x1F
31:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
184 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.16 Dynamic Memory Active Bank A to Active Bank B Time register
The EMCDynamicTRRD register enables you to program the active bank A to active bank
B latency, tRRD. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tRRD. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 130. Dynamic Memory Active Bank A to Active Bank B Time register (DYNAMICRRD address 0x2009 C054) bit description
Bit
Symbol
Description
Reset
value
3:0
TRRD
Active bank A to active bank B latency
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0xF
-
9.13.17 Dynamic Memory Load Mode register to Active Command Time
The EMCDynamicTMRD register enables you to program the load mode register to active
command time, tMRD. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tMRD, or tRSA. This register is
accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 131. Dynamic Memory Load Mode register to Active Command Time (DYNAMICMRD address 0x2009 C058) bit description
UM10562
User manual
Bit
Symbol
Description
3:0
TMRD
Load mode register to active command time.
0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.
0xF = 16 clock cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset
value
0xF
-
© NXP B.V. 2012. All rights reserved.
185 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.18 Static Memory Extended Wait register
ExtendedWait (EW) bit in the EMCStaticConfig register is set. It is recommended that this
register is modified during system initialization, or when there are no current or
outstanding transactions. However, if necessary, these control bits can be altered during
normal operation. This register is accessed with one wait state.
Table 132. Static Memory Extended Wait register (STATICEXTENDEDWAIT - address
0x2009 C080) bit description
Bit
Symbol
9:0
EXTENDEDWAIT Extended wait time out.
16 clock cycles (POR reset value). The delay is in CCLK
cycles.
0x0 = 16 clock cycles.
0x1 - 0x3FF = (n+1) x16 clock cycles.
31:10 -
Description
Reset
value
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
0x0
-
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register: (16 x 10-6 x 50 x
106) / 16 - 1 = 49
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
186 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.19 Dynamic Memory Configuration registers
The EMCDynamicConfig0-3 registers enable you to program the configuration information
for the relevant dynamic memory chip select. These registers are normally only modified
during system initialization. These registers are accessed with one wait state.
Table 133 shows the bit assignments for the EMCDynamicConfig0-3 registers.
Table 133. Dynamic Memory Configuration registers (DYNAMICCONFIG[0:3], address 0x2009 C100
(DYNAMICCONFIG0), 0x2009 C120 (DYNAMICCONFIG1), 0x2009 C140 (DYNAMICCONFIG2), 0x2009 C160
(DYNAMICCONFIG3)) bit description
Bit
Symbol
2:0
-
Value Description
Reserved. Read value is undefined, only zero should be written.
4:3
MD
Memory device.
0x0
6:5
Low-power SDRAM.
0x2
Reserved.
0x3
Reserved.
0
Reserved. Read value is undefined, only zero should be written.
value.[1]
12:7
AM0
See Table 134. 000000 = reset
13
-
Reserved. Read value is undefined, only zero should be written.
14
AM1
See Table 134. 0 = reset value.
18:15 19
20
Buffer enable.
1
Buffer enabled for accesses to this chip select.[2]
Write protect.
31:21 -
UM10562
User manual
Writes not protected (POR reset value).
1
Writes protected.
NA
0
Buffer disabled for accesses to this chip select (POR reset value).
0
NA
0
0
P
NA
0
Reserved. Read value is undefined, only zero should be written.
B
NA
SDRAM (POR reset value).
0x1
-
Reset Value
0
Reserved. Read value is undefined, only zero should be written.
NA
[1]
The SDRAM column and row width and number of banks are computed automatically from the address
mapping.
[2]
The buffers must be disabled during SDRAM initialization. The buffers must be enabled during normal
operation.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
187 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Address mappings that are not shown in Table 134 are reserved.
Table 134. Address mapping
14
12
11:9
8:7
Description
Banks
Row length
Column length
16 bit bus width (Row, Bank, Column)
0
0
000
00
16 Mbits (2M x 8)
2
11
9
0
0
000
01
16 Mbits (1M x 16)
2
11
8
0
0
001
00
64 Mbits (8M x 8)
4
12
9
0
0
001
01
64 Mbits (4M x 16)
4
12
8
0
0
010
00
128 Mbits (16M x 8)
4
12
10
0
0
010
01
128 Mbits (8M x 16)
4
12
9
0
0
011
00
256 Mbits (32M x 8)
4
13
10
0
0
011
01
256 Mbits (16M x 16)
4
13
9
0
0
100
00
512 Mbits (64M x 8)
4
13
11
0
0
100
01
512 Mbits (32M x 16)
4
13
10
16 bit bus width (Bank, Row, Column)
0
1
000
00
16 Mbits (2M x 8)
2
11
9
0
1
000
01
16 Mbits (1M x 16)
2
11
8
0
1
001
00
64 Mbits (8M x 8)
4
12
9
0
1
001
01
64 Mbits (4M x 16)
4
12
8
0
1
010
00
128 Mbits (16M x 8)
4
12
10
0
1
010
01
128 Mbits (8M x 16)
4
12
9
0
1
011
00
256 Mbits (32M x 8)
4
13
10
0
1
011
01
256 Mbits (16M x 16)
4
13
9
0
1
100
00
512 Mbits (64M x 8)
4
13
11
0
1
100
01
512 Mbits (32M x 16)
4
13
10
32 bit bus width (Row, Bank, Column)
1
0
000
00
16 Mbits (2M x 8)
2
11
9
1
0
000
01
16 Mbits (1M x 16)
2
11
8
1
0
001
00
64 Mbits (8M x 8)
4
12
9
1
0
001
01
64 Mbits (4M x 16)
4
12
8
1
0
001
10
64 Mbits (2M x 32)
4
11
8
1
0
010
00
128 Mbits (16M x 8)
4
12
10
1
0
010
01
128 Mbits (8M x 16)
4
12
9
1
0
010
10
128 Mbits (4M x 32)
4
12
8
1
0
011
00
256 Mbits (32M x 8)
4
13
10
1
0
011
01
256 Mbits (16M x 16)
4
13
9
1
0
011
10
256 Mbits (8M x 32)
4
13
8
1
0
100
00
512 Mbits (64M x 8)
4
13
11
1
0
100
01
512 Mbits (32M x 16)
4
13
10
32 bit bus width (Bank, Row, Column)
UM10562
User manual
1
1
000
00
16 Mbits (2M x 8)
2
11
9
1
1
000
01
16 Mbits (1M x 16)
2
11
8
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
188 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Table 134. Address mapping
14
12
11:9
8:7
Description
Banks
Row length
Column length
1
1
001
00
64 Mbits (8M x 8)
4
12
9
1
1
001
01
64 Mbits (4M x 16)
4
12
8
1
1
001
10
64 Mbits (2M x 32)
4
11
8
1
1
010
00
128 Mbits (16M x 8)
4
12
10
1
1
010
01
128 Mbits (8M x 16)
4
12
9
1
1
010
10
128 Mbits (4M x 32)
4
12
8
1
1
011
00
256 Mbits (32M x 8)
4
13
10
1
1
011
01
256 Mbits (16M x 16)
4
13
9
1
1
011
10
256 Mbits (8M x 32)
4
13
8
1
1
100
00
512 Mbits (64M x 8)
4
13
11
1
1
100
01
512 Mbits (32M x 16)
4
13
10
A chip select can be connected to a single memory device, in this case the chip select
data bus width is the same as the device width. Alternatively the chip select can be
connected to a number of external devices. In this case the chip select data bus width is
the sum of the memory device data bus widths.
For example, for a chip select connected to:
•
•
•
•
a 32 bit wide memory device, choose a 32 bit wide address mapping.
a 16 bit wide memory device, choose a 16 bit wide address mapping.
four x 8 bit wide memory devices, choose a 32 bit wide address mapping.
two x 8 bit wide memory devices, choose a 16 bit wide address mapping.
The SDRAM bank select pins BA1 and BA0 are connected to address lines A14 and A13,
respectively.
9.13.20 Dynamic Memory RAS & CAS Delay registers
The EMCDynamicRasCas0-3 registers enable you to program the RAS and CAS
latencies for the relevant dynamic memory. It is recommended that these registers are
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. These registers are accessed with one wait state.
Note: The values programmed into these registers must be consistent with the values
used to initialize the SDRAM memory device.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
189 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Table 135. Dynamic Memory RASCAS Delay registers (DYNAMICRASCAS[0:3], address 0x2009 C104
(DYNAMICRASCAS0), 0x2009 C124 (DYNAMICRASCAS1), 0x2009 C144 (DYNAMICRASCAS2),
0x2009 C164 (DYNAMICRASCAS3)) bit description
Bit
Symbol
1:0
RAS
7:2
-
9:8
CAS
31:10 -
UM10562
User manual
Value Description
Reset Value
RAS latency (active to read/write delay).
0x0
Reserved.
0x1
One CCLK cycle.
0x2
Two CCLK cycles.
0x3
Three CCLK cycles (POR reset value).
-
11
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
CAS latency.
0x0
Reserved.
0x1
One CCLK cycle.
0x2
Two CCLK cycles.
0x3
Three CCLK cycles (POR reset value).
-
11
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
-
© NXP B.V. 2012. All rights reserved.
190 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.21 Static Memory Configuration registers
The EMCStaticConfig0-3 registers configure the static memory configuration. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
Table 136 shows the bit assignments for the EMCStaticConfig0-3 registers. Note that
synchronous burst mode memory devices are not supported.
Table 136. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x2009 C200 (STATICCONFIG0),
0x2009 C220 (STATICCONFIG1), 0x2009 C240 (STATICCONFIG2), 0x2009 C260 (STATICCONFIG3)) bit
description
Bit
Symbol
1:0
MW
Value Description
Reset
Value
Memory width.
0x0
8 bit (POR reset value).
0x1
16 bit.
0x2
32 bit.
0x3
Reserved.
0
2
-
Reserved. Read value is undefined, only zero should be written.
3
PM
Page mode. In page mode the EMC can burst up to four external accesses.
Therefore devices with asynchronous page mode burst four or higher devices
are supported. Asynchronous page mode burst two devices are not supported
and must be accessed normally.
0
Disabled (POR reset value).
1
Asynchronous page mode enabled (page length four).
NA
0
5:4
-
Reserved. Read value is undefined, only zero should be written.
6
PC
Chip select polarity. The value of the chip select polarity on power-on reset is 0.
7
0
Active LOW chip select.
1
Active HIGH chip select.
PB
NA
Byte lane state. The byte lane state bit, PB, enables different types of memory
to be connected. For byte-wide static memories the BLS3:0 signal from the
EMC is usually connected to WE (write enable). In this case for reads all the
BLS3:0 bits must be HIGH. This means that the byte lane state (PB) bit must be
LOW.
0
0
16 bit wide static memory devices usually have the BLS3:0 signals connected to
the UBn and LBn (upper byte and lower byte) signals in the static memory. In
this case a write to a particular byte must assert the appropriate UBn or LBn
signal LOW. For reads, all the UB and LB signals must be asserted LOW so that
the bus is driven. In this case the byte lane state (PB) bit must be HIGH.
UM10562
User manual
0
For reads all the bits in BLS3:0 are HIGH. For writes the respective active bits in
BLS3:0 are LOW (POR reset value).
1
For reads the respective active bits in BLS3:0 are LOW. For writes the
respective active bits in BLS3:0 are LOW.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
191 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
Table 136. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x2009 C200 (STATICCONFIG0),
0x2009 C220 (STATICCONFIG1), 0x2009 C240 (STATICCONFIG2), 0x2009 C260 (STATICCONFIG3)) bit
description
Bit
Symbol
8
EW
18:9
19
20
Value Description
Reset
Value
Extended wait (EW) uses the EMCStaticExtendedWait register to time both the
read and write transfers rather than the EMCStaticWaitRd and
EMCStaticWaitWr registers. This enables much longer transactions.[1]
0
Extended wait disabled (POR reset value).
1
Extended wait enabled.
-
Reserved. Read value is undefined, only zero should be written.
B
Buffer enable
Buffer disabled (POR reset value).
1
Buffer enabled.
P
NA
[2]
0
0
Write protect
0
0
0
Writes not protected (POR reset value).
1
Write protected.
31:21 -
Reserved. Read value is undefined, only zero should be written.
[1]
Extended wait and page mode cannot be selected simultaneously.
[2]
EMC may perform burst read access even when the buffer enable bit is cleared.
NA
9.13.22 Static Memory Write Enable Delay registers
The EMCStaticWaitWen0-3 registers enable you to program the delay from the chip select
to the write enable. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 137. Static Memory Write Enable Delay registers (STATICWAITWEN[0:3], address
0x2009 C204 (STATICWAITWEN0), 0x2009 C224 (STATICWAITWEN1),0x2009 C244
(STATICWAITWEN2), 0x2009 C264 (STATICWAITWEN3)) bit description
UM10562
User manual
Bit
Symbol
Description
3:0
WAITWEN
Wait write enable.
Delay from chip select assertion to write enable.
0x0 = One CCLK cycle delay between assertion of chip select and
write enable (POR reset value).
0x1 - 0xF = (n + 1) CCLK cycle delay. The delay is (WAITWEN +1) x
tCCLK.
0x0
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset
value
© NXP B.V. 2012. All rights reserved.
192 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.23 Static Memory Output Enable Delay registers
The EMCStaticWaitOen0-3 registers enable you to program the delay from the chip select
or address change, whichever is later, to the output enable. It is recommended that these
registers are modified during system initialization, or when there are no current or
outstanding transactions. This can be ensured by waiting until the EMC is idle, and then
entering low-power, or disabled mode. These registers are accessed with one wait state.
Table 138. Static Memory Output Enable delay registers (STATICWAITOEN[0:3], address
0x2009 C208 (STATICWAITOEN0), 0x0x2009 C228 (STATICWAITOEN1), 0x0x2009
C248 (STATICWAITOEN2), 0x0x2009 C268 (STATICWAITOEN3)) bit description
Bit
Symbol
Description
Reset
value
3:0
WAITOEN
Wait output enable.
Delay from chip select assertion to output enable.
0x0 = No delay (POR reset value).
0x1 - 0xF = n cycle delay. The delay is WAITOEN x tCCLK.
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0x0
-
9.13.24 Static Memory Read Delay registers
The EMCStaticWaitRd0-3 registers enable you to program the delay from the chip select
to the read access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. It
is not used if the extended wait bit is enabled in the EMCStaticConfig0-3 registers. These
registers are accessed with one wait state.
Table 139. Static Memory Read Delay registers (STATICWAITRD[0:3], address 0x2009 C20C
(STATICWAITRD0), 0x2009 C22C (STATICWAITRD1), 0x2009 C24C
(STATICWAITRD2), 0x2009 C26C (STATICWAITRD3)) bit description
Bit
Symbol
Description
4:0
WAITRD
Non-page mode read wait states or asynchronous page mode read first 0x1F
[1]
access wait state.
Non-page mode read or asynchronous page mode read, first read only:
0x0 - 0x1E = (n + 1) CCLK cycles for read accesses. For
non-sequential reads, the wait state time is (WAITRD + 1) x tCCLK.
0x1F = 32 CCLK cycles for read accesses (POR reset value).
31:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
[1]
UM10562
User manual
Reset
value
-
The reset value depends on the boot mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
193 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.25 Static Memory Page Mode Read Delay registers
The EMCStaticWaitPage0-3 registers enable you to program the delay for asynchronous
page mode sequential accesses. It is recommended that these registers are modified
during system initialization, or when there are no current or outstanding transactions. This
can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode. This register is accessed with one wait state.
Table 140. Static Memory Page Mode Read Delay registers (STATICWAITPAGE[0:3], address
0x2009 C210 (STATICWAITPAGE0), 2009 C230 (STATICWAITPAGE1), 0x2009 C250
(STATICWAITPAGE2), 0x2009 C270 (STATICWAITPAGE3)) bit description
Bit
Symbol
Description
Reset
value
4:0
WAITPAGE Asynchronous page mode read after the first read wait states.
Number of wait states for asynchronous page mode read accesses
after the first read:
0x0 - 0x1E = (n+ 1) CCLK cycle read access time. For asynchronous
page mode read for sequential reads, the wait state time for page
mode accesses after the first read is (WAITPAGE + 1) x tCCLK.
0x1F = 32 CCLK cycle read access time (POR reset value).
31:5
-
0x1F
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
9.13.26 Static Memory Write Delay registers
The EMCStaticWaitWr0-3 registers enable you to program the delay from the chip select
to the write access. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled
mode.These registers are not used if the extended wait (EW) bit is enabled in the
EMCStaticConfig register. These registers are accessed with one wait state.
Table 141. Static Memory Write Delay registers (STATICWAITWR[0:3], address 0x2009 C214
(STATICWAITWR0), 0x2009 C234 (STATICWAITWR1), 0x2009 C254
(STATICWAITWR2), 0x2009 C274 (STATICWAITWR3)) bit description
UM10562
User manual
Bit
Symbol
Description
Reset
value
4:0
WAITWR
Write wait states.
SRAM wait state time for write accesses after the first read:
0x0 - 0x1E = (n + 2) CCLK cycle write access time. The wait state time
for write accesses after the first read is WAITWR (n + 2) x tCCLK.
0x1F = 33 CCLK cycle write access time (POR reset value).
0x1F
31:5
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
194 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.13.27 Static Memory Turn Round Delay registers
The EMCStaticWaitTurn0-3 registers enable you to program the number of bus
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 142. Static Memory Turn-around Delay registers (STATICWAITTURN[0:3], address
0x2009 C218 (STATICWAITTURN0),0x2009 C238 (STATICWAITTURN1), 0x2009
C258 (STATICWAITTURN2), 0x2009 C278 (STATICWAITTURN3)) bit description
Bit
Symbol
Description
Reset
value
3:0
WAITTURN Bus turn-around cycles.
0x0 - 0xE = (n + 1) CCLK turn-around cycles. Bus turn-around time is
(WAITTURN + 1) x tCCLK.
0xF = 16 CCLK turn-around cycles (POR reset value).
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
0xF
-
To prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
195 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.14 External memory interface
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding EMCStaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
the A1 and/or A0 lines to provide address or non-address function is accomplished using
the IOCON registers (see Section 7.4.1).
Symbol "a_b" in the following figures refers to the highest order address line in the data
bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the
external memory interface.
9.14.1 32-bit wide memory bank connection
CS
OE
BLS[3]
D[31:24]
CE
OE
WE
BLS[2]
IO[7:0]
A[a_m:0]
D[23:16]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[1]
D[15:8]
CE
OE
WE
IO[7:0]
A[a_m:0]
BLS[0]
D[7:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
A[a_b:2]
a. 32 bit wide memory bank interfaced to four 8 bit memory chips
CS
OE
WE
BLS[3]
BLS[2]
D[31:16]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
BLS[1]
BLS[0]
D[15:0]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
A[a_b:2]
b. 32 bit wide memory bank interfaced to two 16 bit memory chips
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
196 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
CS
OE
WE
BLS[3]
BLS[2]
BLS[1]
BLS[0]
D[31:0]
CE
OE
WE
B3
B2
B1
B0
IO[31:0]
A[a_m:0]
A[a_b:2]
c. 32 bit wide memory bank interfaced to one 8 bit memory chip
Fig 18. 32 bit bank external memory interfaces ( bits MW = 10)
9.14.2 16-bit wide memory bank connection
CS
OE
CE
OE
WE
BLS[1]
BLS[0]
IO[7:0]
A[a_m:0]
D[15:8]
D[7:0]
CE
OE
WE
IO[7:0]
A[a_m:0]
A[a_b:1]
a. 16 bit wide memory bank interfaced to two 8 bit memory chips
CS
OE
WE
BLS[1]
BLS[0]
D[15:0]
CE
OE
WE
UB
LB
IO[15:0]
A[a_m:0]
A[a_b:1]
b. 16 bit wide memory bank interfaced to a 16 bit memory chip
Fig 19. 16 bit bank external memory interfaces (bits MW = 01)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
197 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.14.3 8-bit wide memory bank connection
CS
OE
CE
OE
WE
D[7:0]
WE
IO[7:0]
A[a_m:0]
A[a_b:0]
Fig 20. 8 bit bank external memory interface (bits MW = 00)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
198 of 942
UM10562
NXP Semiconductors
Chapter 9: LPC408x/407x External Memory Controller (EMC)
9.14.4 Memory configuration example
A[20:0]
A[20:0]
D[31:0]
A[20:0]
Q[31:0]
D[31:0]
nCE
CS0
nOE
OE
2Mx32 Burst Mask ROM
A[15:0]
D[31:16]
A[15:0]
CS1
IO[15:0]
nCE
nOE
nWE
WE
nUB
nLB
A[15:0]
D[15:0]
A[15:0]
IO[15:0]
nCE
nOE
nWE
nUB
nLB
64Kx16 SRAM, two off
D[31:24]
A[16:0]
A[16:0]
CS2
IO[7:0]
nCE
nOE
BLS3
nWE
D[23:16]
A[16:0]
A[16:0]
IO[7:0]
nCE
nOE
BLS2
nWE
D[15:8]
A[16:0]
A[16:0]
IO[7:0]
nCE
nOE
BLS1
nWE
D[7:0]
A[16:0]
A[16:0]
IO[7:0]
nCE
nOE
BLS0
nWE
128Kx8 SRAM, four off
Fig 21. Typical memory configuration diagram
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
199 of 942
UM10562
Chapter 10: LPC408x/407x Ethernet
Rev. 1 — 13 September 2012
User manual
10.1 Basic configuration
The Ethernet controller is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCENET.
Remark: On reset, the Ethernet block is disabled (PCENET = 0).
2. Clock: See Section 3.3.3.2.
3. Pins: Enable Ethernet pins and select their modes through the IOCON registers, see
Section 7.4.1.
4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from
Power-down mode, see Section 3.12.8.
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. Initialization: See Section 10.13.2.
10.2 Introduction
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix,
it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet
is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be
accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum
bandwidth to the Ethernet function.
The Ethernet block interfaces between an off-chip Ethernet PHY using the MII (Media
Independent Interface) or RMII (reduced MII) protocol and the on-chip MIIM (Media
Independent Interface Management) serial bus, also referred to as MDIO (Management
Data Input/Output).
Table 143. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
Definition
AHB
Advanced High-performance bus
CRC
Cyclic Redundancy Check
DMA
Direct Memory Access
Double-word
64-bit entity
FCS
Frame Check Sequence (CRC)
Fragment
A (part of an) Ethernet frame; one or multiple fragments can add up to a single Ethernet frame.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
200 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 143. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
Definition
Frame
An Ethernet frame consists of destination address, source address, length type field, payload and frame
check sequence.
Half-word
16-bit entity
LAN
Local Area Network
MAC
Media Access Control sublayer
MII
Media Independent Interface
MIIM
MII management
Octet
An 8-bit data entity, used in lieu of "byte" by IEEE 802.3
Packet
A frame that is transported across Ethernet; a packet consists of a preamble, a start of frame delimiter and
an Ethernet frame.
PHY
Ethernet Physical Layer
RMII
Reduced MII
Rx
Receive
TCP/IP
Transmission Control Protocol / Internet Protocol. The most common high-level protocol used with
Ethernet.
Tx
Transmit
VLAN
Virtual LAN
WoL
Wake-up on LAN
Word
32-bit entity
10.3 Features
• Ethernet standards support:
– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– VLAN frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and prefetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic FCS insertion (CRC) for transmit.
– Selectable automatic transmit frame padding.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
201 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision backoff and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through standard Media Independent Interface
(MII) or standard Reduced MII (RMII) interface, software selectable.
– PHY register access is available via the Media Independent Interface Management
(MIIM) interface.
10.4 Architecture and operation
TRANSMIT
DMA
TRANSMIT
RETRY
RECEIVE
DMA
RECEIVE
BUFFER
R MII A DAP TER
TRANSMIT
FLOW
CONTROL
ETH ER N ET MAC
HOST
REGISTERS
RMII
ET HE RN ET PHY
DMA interface
(AHB master)
BU S
IN TER F ACE
register
interface (AHB
slave)
BUS IN T ERF AC E
AH B BU S
Figure 22 shows the internal architecture of the Ethernet block.
MIIM
RECEIVE
FILTER
ETHERNET
BLOCK
Fig 22. Ethernet block diagram
The block diagram for the Ethernet block consists of:
• The host registers module containing the registers in the software view and handling
AHB accesses to the Ethernet block. The host registers connect to the transmit and
receive data path as well as the MAC.
• The DMA to AHB interface. This provides an AHB master connection that allows the
Ethernet block to access on-chip SRAM for reading of descriptors, writing of status,
and reading and writing data buffers.
• The Ethernet MAC, which interfaces to the off-chip PHY via an MII or RMII interface.
• The transmit data path, including:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
202 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
– The transmit DMA manager which reads descriptors and data from memory and
writes status to memory.
– The transmit retry module handling Ethernet retry and abort situations.
– The transmit flow control module which can insert Ethernet pause frames.
• The receive data path, including:
– The receive DMA manager which reads descriptors from memory and writes data
and status to memory.
– The Ethernet MAC which detects frame types by parsing part of the frame header.
– The receive filter which can filter out certain Ethernet frames by applying different
filtering schemes.
– The receive buffer implementing a delay for receive frames to allow the filter to
filter out certain frames before storing them to memory.
10.5 DMA engine functions
The Ethernet block is designed to provide optimized performance via DMA hardware
acceleration. Independent scatter/gather DMA engines connected to the AHB bus off-load
many data transfers from the CPU.
Descriptors, which are stored in memory, contain information about fragments of incoming
or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller
amount of data. Each descriptor contains a pointer to a memory buffer that holds data
associated with a fragment, the size of the fragment buffer, and details of how the
fragment will be transmitted or received.
Descriptors are stored in arrays in memory, which are located by pointer registers in the
Ethernet block. Other registers determine the size of the arrays, point to the next
descriptor in each array that will be used by the DMA engine, and point to the next
descriptor in each array that will be used by the Ethernet device driver.
10.6 Overview of DMA operation
The DMA engine makes use of a Receive descriptor array and a Transmit descriptor array
in memory. All or part of an Ethernet frame may be contained in a memory buffer
associated with a descriptor. When transmitting, the transmit DMA engine uses as many
descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and
sends them out in sequence. When receiving, the receive DMA engine also uses as many
descriptors as needed (one or more) to find places to store (scatter) all of the data in the
received frame.
The base address registers for the descriptor array, registers indicating the number of
descriptor array entries, and descriptor array input/output pointers are contained in the
Ethernet block. The descriptor entries and all transmit and receive packet data are stored
in memory which is not a part of the Ethernet block. The descriptor entries tell where
related frame data is stored in memory, certain aspects of how the data is handled, and
the result status of each Ethernet transaction.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
203 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved
to memory, causes fragment related status to be saved, and advances the hardware
receive pointer for incoming data. Driver software must handle the disposition of received
data, changing of descriptor data addresses (to avoid unnecessary data movement), and
advancing the software receive pointer. The two pointers create a circular queue in the
descriptor array and allow both the DMA hardware and the driver software to know which
descriptors (if any) are available for their use, including whether the descriptor array is
empty or full.
Similarly, driver software must set up pointers to data that will be transmitted by the
Ethernet MAC, giving instructions for each fragment of data, and advancing the software
transmit pointer for outgoing data. Hardware in the DMA engine reads this information and
sends the data to the Ethernet MAC interface when possible, updating the status and
advancing the hardware transmit pointer.
10.7 Ethernet packet
Figure 23 illustrates the different fields in an Ethernet packet.
ethernet packet
PREAMBLE
7 bytes
ETHERNET FRAME
start-of-frame
delimiter
1 byte
DESTINATION
ADDRESS
SOURCE
ADDRESS
OPTIONAL
VLAN
LEN
TYPE
PAYLOAD
DesA
oct6
DesA
oct5
DesA
oct4
DesA
oct3
DesA
oct2
DesA
oct1
SrcA
oct6
SrcA
oct5
LSB
oct(0)
oct(1)
oct(2)
oct(3)
oct(4)
oct(5)
oct(6)
MSB
oct(7)
SrcA
oct4
SrcA
oct3
FCS
SrcA
oct2
SrcA
oct1
time
Fig 23. Ethernet packet fields
A packet consists of a preamble, a start-of-frame delimiter and an Ethernet frame.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
204 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The Ethernet frame consists of the destination address, the source address, an optional
VLAN field, the length/type field, the payload and the frame check sequence.
Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred
starting with the least significant bit.
10.8 Overview
10.8.1 Partitioning
The Ethernet block and associated device driver software offer the functionality of the
Media Access Control (MAC) sublayer of the data link layer in the OSI reference model
(see IEEE std 802.3). The MAC sublayer offers the service of transmitting and receiving
frames to the next higher protocol level, the MAC client layer, typically the Logical Link
Control sublayer. The device driver software implements the interface to the MAC client
layer. It sets up registers in the Ethernet block, maintains descriptor arrays pointing to
frames in memory and receives results back from the Ethernet block through interrupts.
When a frame is transmitted, the software partially sets up the Ethernet frames by
providing pointers to the destination address field, source address field, the length/type
field, the MAC client data field and optionally the CRC in the frame check sequence field.
Preferably concatenation of frame fields should be done by using the scatter/gather
functionality of the Ethernet core to avoid unnecessary copying of data. The hardware
adds the preamble and start frame delimiter fields and can optionally add the CRC, if
requested by software. When a packet is received the hardware strips the preamble and
start frame delimiter and passes the rest of the packet - the Ethernet frame - to the device
driver, including destination address, source address, length/type field, MAC client data
and frame check sequence (FCS).
Apart from the MAC, the Ethernet block contains receive and transmit DMA managers that
control receive and transmit data streams between the MAC and the AHB interface.
Frames are passed via descriptor arrays located in host memory, so that the hardware
can process many frames without software/CPU support. Frames can consist of multiple
fragments that are accessed with scatter/gather DMA. The DMA managers optimize
memory bandwidth using prefetching and buffering.
A receive filter block is used to identify received frames that are not addressed to this
Ethernet station, so that they can be discarded. The Rx filters include a perfect address
filter and a hash filter.
Wake-on-LAN power management support makes it possible to wake the system up from
a power-down state -a state in which some of the clocks are switched off -when wake-up
frames are received over the LAN. Wake-up frames are recognized by the receive filtering
modules or by a Magic Frame detection technology. System wake-up occurs by triggering
an interrupt.
An interrupt logic block raises and masks interrupts and keeps track of the cause of
interrupts. The interrupt block sends an interrupt request signal to the host system.
Interrupts can be enabled, cleared and set by software.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
205 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block.
Receive flow control frames are automatically handled by the MAC. Transmit flow control
frames can be initiated by software. In half duplex mode, the flow control module will
generate back pressure by sending out continuous preamble only, interrupted by pauses
to prevent the jabber limit from being exceeded.
The Ethernet block has both a standard Media Independent Interface (MII) bus and a
Reduced Media Independent Interface (RMII) to connect to an external Ethernet PHY
chip. MII or RMII mode can be selected by the RMII bit in the Command register. The
standard nibble-wide MII interface allows a low speed data connection to the PHY chip:
2.5 MHz at 10 Mbps or 25 MHz at 100 Mbps. The RMII interface allows a low pin count
double clock data connection to the PHY. Registers in the PHY chip are accessed via the
AHB interface through the serial management connection of the MIIM bus, typically
operating at 2.5 MHz.
10.8.2 Example PHY Devices
Some examples of compatible PHY devices are shown in Table 144.
Table 144. Example PHY Devices
UM10562
User manual
Manufacturer
Part Numbers
Broadcom
BCM5221
ICS
ICS1893
Intel
LXT971A
LSI Logic
L80223, L80225, L80227
Micrel
KS8721
National
DP83847, DP83846, DP83843
SMSC
LAN83C185
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
206 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.9 Pin description
Table 145 shows the signals used for connecting the Media Independent Interface (MII),
and Table 146 shows the signals used for connecting the Reduced Media Independent
Interface (RMII) to the external PHY.
Table 145. Ethernet MII pin descriptions
Pin Name
Type
Pin Description
ENET_TX_EN
Output
Transmit data enable, active low.
ENET_TXD3:0
Output
Transmit data, 4 bits.
ENET_TX_ER
Output
Transmit error.
ENET_TX_CLK
Input
Transmitter clock.
ENET_RX_DV
Input
Receive data valid.
ENET_RXD3:0
Input
Receive data, 4 bits.
ENET_RX_ER
Input
Receive error.
ENET_RX_CLK
Input
Receive clock.
ENET_COL
Input
Collision detect.
ENET_CRS
Input
Carrier sense.
Table 146. Ethernet RMII pin descriptions
Pin Name
Type
Pin Description
ENET_TX_EN
Output
Transmit data enable, active low.
ENET_TXD1:0
Output
Transmit data, 2 bits
ENET_RXD1:0
Input
Receive data, 2 bits.
ENET_RX_ER
Input
Receive error.
ENET_CRS
Input
ENET_CRS_DV. Carrier sense/data valid.
ENET_RX_CLK
Input
ENET_REF_CLK. Reference clock.
Table 147 shows the signals used for Media Independent Interface Management (MIIM) to
the external PHY.
Table 147. Ethernet MIIM pin descriptions
Pin Name
UM10562
User manual
Type
Pin Description
ENET_MDC
Output
MIIM clock.
ENET_MDIO
Input/Output
MI data input and output
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
207 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10 Register description
The software interface of the Ethernet block consists of a register view and the format
definitions for the transmit and receive descriptors. These two aspects are addressed in
the next two subsections.
The total AHB address space required for the ethernet is 4 kilobytes.
After a hard reset or a soft reset via the RegReset bit of the Command register all bits in
all registers are reset to 0 unless stated otherwise in the following register descriptions.
Some registers will have unused bits which will return a 0 on a read via the AHB interface.
Writing to unused register bits of an otherwise writable register will not have side effects.
The register map consists of registers in the Ethernet MAC and registers around the core
for controlling DMA transfers, flow control and filtering.
Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to
reserved addresses or reserved bits has no effect.
Reading of write-only registers will return a read error on the AHB interface. Writing of
read-only registers will return a write error on the AHB interface.
Table 148. Register overview: Ethernet (base address 0x2008 4000)
Name
Access Address Description
offset
Reset Value Table
MAC registers
MAC1
R/W
0x000
MAC configuration register 1.
0x8000
149
MAC2
R/W
0x004
MAC configuration register 2.
0
150
IPGT
R/W
0x008
Back-to-Back Inter-Packet-Gap register.
0
152
IPGR
R/W
0x00C
Non Back-to-Back Inter-Packet-Gap register.
0
153
CLRT
R/W
0x010
Collision window / Retry register.
0x370F
154
MAXF
R/W
0x014
Maximum Frame register.
0x0600
155
SUPP
R/W
0x018
PHY Support register.
0
156
TEST
R/W
0x01C
Test register.
0
157
MCFG
R/W
0x020
MII Mgmt Configuration register.
0
158
MCMD
R/W
0x024
MII Mgmt Command register.
0
160
MADR
R/W
0x028
MII Mgmt Address register.
0
161
MWTD
WO
0x02C
MII Mgmt Write Data register.
-
162
MRDD
RO
0x030
MII Mgmt Read Data register.
0
163
MIND
RO
0x034
MII Mgmt Indicators register.
0
164
SA0
R/W
0x040
Station Address 0 register.
0
165
SA1
R/W
0x044
Station Address 1 register.
0
166
SA2
R/W
0x048
Station Address 2 register.
0
167
R/W
0x100
Command register.
0
168
Control registers
COMMAND
STATUS
RO
0x104
Status register.
0
169
RXDESCRIPTOR
R/W
0x108
Receive descriptor base address register.
0
170
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
208 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 148. Register overview: Ethernet (base address 0x2008 4000)
Name
Access Address Description
offset
RXSTATUS
R/W
0x10C
Receive status base address register.
RXDESCRIPTORNUMBER
R/W
0x110
RXPRODUCEINDEX
RO
0x114
RXCONSUMEINDEX
R/W
TXDESCRIPTOR
Reset Value Table
0
171
Receive number of descriptors register.
0
172
Receive produce index register.
0
173
0x118
Receive consume index register.
0
174
R/W
0x11C
Transmit descriptor base address register.
0
175
TXSTATUS
R/W
0x120
Transmit status base address register.
0
176
TXDESCRIPTORNUMBER
R/W
0x124
Transmit number of descriptors register.
0
177
TXPRODUCEINDEX
R/W
0x128
Transmit produce index register.
0
178
TXCONSUMEINDEX
RO
0x12C
Transmit consume index register.
0
179
TSV0
RO
0x158
Transmit status vector 0 register.
0
180
TSV1
RO
0x15C
Transmit status vector 1 register.
0
181
RSV
RO
0x160
Receive status vector register.
0
182
FLOWCONTROLCOUNTER
R/W
0x170
Flow control counter register.
0
183
FLOWCONTROLSTATUS
RO
0x174
Flow control status register.
0
184
RXFILTERCTRL
R/W
0x200
Receive filter control register.
0
185
RXFILTERWOLSTATUS
RO
0x204
Receive filter WoL status register.
0
186
RXFILTERWOLCLEAR
WO
0x208
Receive filter WoL clear register.
-
187
HASHFILTERL
R/W
0x210
Hash filter table LSBs register.
0
188
HASHFILTERH
R/W
0x214
Hash filter table MSBs register.
0
189
Rx filter registers
Module control registers
INTSTATUS
RO
0xFE0
Interrupt status register.
0
190
INTENABLE
R/W
0xFE4
Interrupt enable register.
0
191
INTCLEAR
WO
0xFE8
Interrupt clear register.
-
192
INTSET
WO
0xFEC
Interrupt set register.
-
193
POWERDOWN
R/W
0xFF4
Power-down register.
0
194
The third column in the table lists the accessibility of the register: read-only, write-only,
read/write.
All AHB register write transactions except for accesses to the interrupt registers are
posted i.e. the AHB transaction will complete before write data is actually committed to the
register. Accesses to the interrupt registers will only be completed by accepting the write
data when the data has been committed to the register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
209 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1 Ethernet MAC register definitions
This section defines the bits in the individual registers of the Ethernet block register map.
10.10.1.1 MAC Configuration Register 1
The MAC configuration register 1 (MAC1) has an address of 0x2008 4000. Its bit
definition is shown in Table 149.
Table 149. MAC Configuration register 1 (MAC1 - address 0x2008 4000) bit description
Bit
Symbol
Function
Reset
value
0
RXENABLE
RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC
synchronizes this control bit to the incoming receive stream.
0
1
PARF
PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames
regardless of type (normal vs. Control). When disabled, the MAC does not pass valid
Control frames.
0
2
RXFLOWCTRL RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow
Control frames. When disabled, received PAUSE Flow Control frames are ignored.
0
3
TXFLOWCTRL TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed
to be transmitted. When disabled, Flow Control frames are blocked.
0
4
LOOPBACK
0
Setting this bit will cause the MAC Transmit interface to be looped back to the MAC
Receive interface. Clearing this bit results in normal operation.
7:5
-
Unused
0
8
RESETTX
Setting this bit will put the Transmit Function logic in reset.
0
9
RESETMCSTX Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic
implements flow control.
0
10
RESETRX
0
11
RESETMCSRX Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic
implements flow control.
Setting this bit will put the Ethernet receive logic in reset.
0
13:12 -
Reserved. Read value is undefined, only zero should be written.
0
14
SIMRESET
SIMULATION RESET. Setting this bit will cause a reset to the random number generator
within the Transmit Function.
0
15
SOFTRESET
SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host
Interface.
1
Reserved. Read value is undefined, only zero should be written.
0
31:16 -
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
210 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1.2 MAC Configuration Register 2
Table 150. MAC Configuration register 2 (MAC2 - address 0x2008 4004) bit description
Bit
Symbol
Function
0
FULLDUPLEX
When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the
MAC operates in Half-Duplex mode.
0
1
FLC
FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive
frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported in the
StatusInfo word for each received frame.
0
2
HFEN
HUGE FRAME ENABLE. When enabled (set to 1), frames of any length are transmitted
and received.
0
3
DELAYEDCRC
DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header
information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header
(ignored by the CRC function) are added. When 0, there is no proprietary header.
0
4
CRCEN
CRC ENABLE. Set this bit to append a CRC to every frame whether padding was
required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames
presented to the MAC contain a CRC.
0
5
PADCRCEN
PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if
frames presented to the MAC have a valid length. This bit is used in conjunction with
AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 152 - Pad Operation for
details on the pad function.
0
6
VLANPADEN
VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes
and append a valid CRC. Consult Table 152 - Pad Operation for more information on
the various padding features.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
0
7
AUTODETPADEN AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the
type of frame, either tagged or un-tagged, by comparing the two octets following the
source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 152 - Pad
Operation provides a description of the pad function based on the configuration of this
register.
Note: This bit is ignored if PAD / CRC ENABLE is cleared.
0
8
PPENF
PURE PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC will verify the
content of the preamble to ensure it contains 0x55 and is error-free. A packet with an
incorrect preamble is discarded. When disabled, no preamble checking is performed.
0
9
LPENF
LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows
receive packets which contain preamble fields less than 12 bytes in length. When
disabled, the MAC allows any length preamble as per the Standard.
0
11:10
-
Reserved. Read value is undefined, only zero should be written.
0
12
NOBACKOFF
When enabled (set to 1), the MAC will immediately retransmit following a collision
rather than using the Binary Exponential Backoff algorithm as specified in the Standard.
0
13
BP_NOBACKOFF BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC
incidentally causes a collision during back pressure, it will immediately retransmit
without backoff, reducing the chance of further collisions and ensuring transmit packets
get sent.
0
14
EXCESSDEFER
When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard.
When disabled, the MAC will abort when the excessive deferral limit is reached.
0
31:15
-
Reserved. Read value is undefined, only zero should be written.
0
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
211 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 151. Pad operation
Type
Auto detect pad
VLAN pad
Pad/CRC enable Action
enable MAC2 [7] enable MAC2 [6]
MAC2 [5]
Any
x
x
0
No pad or CRC check
Any
0
0
1
Pad to 60 bytes, append CRC
Any
x
1
1
Pad to 64 bytes, append CRC
Any
1
0
1
If untagged, pad to 60 bytes and append CRC. If VLAN
tagged: pad to 64 bytes and append CRC.
10.10.1.3 Back-to-Back Inter-Packet-Gap Register
Table 152. Back-to-back Inter-packet-gap register (IPGT - address 0x2008 4008) bit description
Bit
Symbol
Function
Reset
value
6:0
BTOBINTEGAP BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the
nibble time offset of the minimum possible period between the end of any transmitted
packet to the beginning of the next. In Full-Duplex mode, the register value should be the
desired period in nibble times minus 3. In Half-Duplex mode, the register value should be
the desired period in nibble times minus 6. In Full-Duplex the recommended setting is
0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also
represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in 10 Mbps mode).
0
31:7
-
0
Reserved. Read value is undefined, only zero should be written.
10.10.1.4 Non Back-to-Back Inter-Packet-Gap Register
Table 153. Non Back-to-back Inter-packet-gap register (IPGR - address 0x2008 400C) bit description
Bit
Symbol
6:0
NBTOBINTEGAP2 NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field
representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12
(18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 µs (in
10 Mbps mode).
0
7
-
0
14:8
NBTOBINTEGAP1 NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field
representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1
'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to
carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing
IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to
medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)
31:15 -
UM10562
User manual
Function
Reset
value
Reserved. Read value is undefined, only zero should be written.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
© NXP B.V. 2012. All rights reserved.
212 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1.5 Collision Window / Retry Register
Table 154. Collision Window / Retry register (CLRT - address 0x2008 4010) bit description
Bit
Symbol
Function
Reset value
3:0
RETRANSMAX RETRANSMISSION MAXIMUM.This is a programmable field specifying the number
of retransmission attempts following a collision before aborting the packet due to
excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See
IEEE 802.3/4.2.3.2.5.
7:4
-
Reserved. Read value is undefined, only zero should be written.
13:8
COLLWIN
COLLISION WINDOW. This is a programmable field representing the slot time or
collision window during which collisions occur in properly configured networks. The
default value of 0x37 (55d) represents a 56 byte window following the preamble and
SFD.
31:14
-
Reserved. Read value is undefined, only zero should be written.
0xF
0
0x37
NA
10.10.1.6 Maximum Frame Register
Table 155. Maximum Frame register (MAXF - address 0x2008 4014) bit description
Bit
Symbol
Function
Reset value
15:0
MAXFLEN MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a
maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is
1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter
maximum length restriction is desired, program this 16-bit field.
31:16
-
Unused
0x0600
0
10.10.1.7 PHY Support Register
The SUPP register provides additional control over the RMII interface.
Table 156. PHY Support register (SUPP - address 0x2008 4018) bit description
Bit
Symbol Function
Reset value
7:0
-
8
SPEED This bit configures the Reduced MII logic for the current operating speed. When set,
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
0
31:9
-
0
Unused
0
Unused
Unused bits in the PHY support register should be left as zeroes.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
213 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1.8 Test Register
Table 157. Test register (TEST - address 0x2008 401C) bit description
Bit
Symbol
Function
Reset
value
0
SCPQ
SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64
byte-times to 1 byte-time.
0
1
TESTPAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE
Receive Control frame with a nonzero pause time parameter was received.
0
2
TESTBP
TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the
link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit
packet from the system will be sent during backpressure.
0
31:3
-
Unused
0
10.10.1.9 MII Mgmt Configuration Register
Table 158. MII Mgmt Configuration register (MCFG - address 0x2008 4020) bit description
Bit
Symbol
Function
Reset
value
0
SCANINC
SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform
read cycles across a range of PHYs. When set, the MII Management hardware will
perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear
this bit to allow continuous reads of the same PHY.
1
SUPPPREAMBLE SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to
perform read/write cycles without the 32-bit preamble field. Clear this bit to cause
normal cycles to be performed. Some PHYs support suppressed preamble.
0
5:2
CLOCKSEL
CLOCK SELECT. This field is used by the clock divide logic in creating the MII
Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz.
Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK)
is divided by the specified amount. Refer to Table 159 below for the definition of values
for this field.
0
14:6
-
Unused
0
0
15
RESETMIIMGMT
RESET MII MGMT. This bit resets the MII Management hardware.
0
31:16
-
Unused
0
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
214 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 159. Clock select encoding
Clock Select
Bit 5
Bit 4
Bit 3
Bit 2
Maximum AHB
clock supported
Host Clock divided by 4
0
0
0
x
10
Host Clock divided by 6
0
0
1
0
15
Host Clock divided by 8
0
0
1
1
20
Host Clock divided by 10
0
1
0
0
25
Host Clock divided by 14
0
1
0
1
35
Host Clock divided by 20
0
1
1
0
50
Host Clock divided by 28
0
1
1
1
70
Host Clock divided by 36
1
0
0
0
80[1]
Host Clock divided by 40
1
0
0
1
90[1]
Host Clock divided by 44
1
0
1
0
100[1]
Host Clock divided by 48
1
0
1
1
120[1]
Host Clock divided by 52
1
1
0
0
130[1]
Host Clock divided by 56
1
1
0
1
140[1]
Host Clock divided by 60
1
1
1
0
150[1]
Host Clock divided by 64
1
1
1
1
160[1]
[1]
The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device.
10.10.1.10 MII Mgmt Command Register
Table 160. MII Mgmt Command register (MCMD - address 0x2008 4024) bit description
Bit
Symbol Function
Reset value
0
READ
This bit causes the MII Management hardware to perform a single Read cycle. The Read
data is returned in Register MRDD (MII Mgmt Read Data).
0
1
SCAN
This bit causes the MII Management hardware to perform Read cycles continuously. This is
useful for monitoring Link Fail for example.
0
31:2
-
Unused
0
10.10.1.11 MII Mgmt Address Register
Table 161. MII Mgmt Address register (MADR - address 0x2008 4028) bit description
Bit
Symbol
4:0
REGADDR REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt
cycles. Up to 32 registers can be accessed.
0
7:5
-
0
12:8
PHYADDR PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to
31 PHYs can be addressed (0 is reserved).
0
31:13
-
0
UM10562
User manual
Function
Reset value
Unused
Unused
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
215 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1.12 MII Mgmt Write Data Register
Table 162. MII Mgmt Write Data register (MWTD - address 0x2008 402C) bit description
Bit
Symbol
Function
15:0
WRITEDATA WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the
pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).
31:16
-
Unused
10.10.1.13 MII Mgmt Read Data Register
Table 163. MII Mgmt Read Data register (MRDD - address 0x2008 4030) bit description
Bit
Symbol
Function
Reset value
15:0
READDATA READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this
location.
0
31:16
-
0
Unused
10.10.1.14 MII Mgmt Indicators Register
Table 164. MII Mgmt Indicators register (MIND - address 0x2008 4034) bit description
Bit
Symbol
Function
Reset value
0
BUSY
When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or
Write cycle.
0
1
SCANNING
When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is
in progress.
0
2
NOTVALID
When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read
Data is not yet valid.
0
3
MIILINKFAIL When 1 is returned - indicates that an MII Mgmt link fail has occurred.
0
31:4
-
0
Unused
Here are two examples to access PHY via the MII Management Controller.
For PHY Write if scan is not used:
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND
For PHY Read if scan is not used:
1. Write 1 to MCMD
2. Write PHY address and register address to MADR
3. Wait for busy bit to be cleared in MIND
4. Write 0 to MCMD
5. Read data from MRDD
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
216 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.1.15 Station Address 0 Register
Table 165. Station Address register (SA0 - address 0x2008 4040) bit description
Bit
Symbol
Function
Reset value
7:0
SADDR2 STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.
0
15:8
SADDR1 STATION ADDRESS, 1st octet. This field holds the first octet of the station address.
0
31:16
-
0
Unused
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 23.
10.10.1.16 Station Address 1 Register
Table 166. Station Address register (SA1 - address 0x2008 4044) bit description
Bit
Symbol
Function
Reset value
7:0
SADDR4 STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.
0
15:8
SADDR3 STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.
0
31:16
-
0
Unused
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 23.
10.10.1.17 Station Address 2 Register
Table 167. Station Address register (SA2 - address 0x2008 4048) bit description
Bit
Symbol
Function
Reset value
7:0
SADDR6 STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.
0
15:8
SADDR5 STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.
0
31:16
-
0
Unused
The station address is used for perfect address filtering and for sending pause control
frames. For the ordering of the octets in the packet please refer to Figure 23.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
217 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.2
Control register definitions
10.10.2.1 Command Register
Table 168. Command register (COMMAND - address 0x2008 4100) bit description
Bit
Symbol
Function
Reset
value
0
RXENABLE
Enable receive.
0
1
TXENABLE
Enable transmit.
0
2
-
Unused
0
3
REGRESET
When a 1 is written, all datapaths and the host registers are reset. The MAC needs
to be reset separately.
0
4
TXRESET
When a 1 is written, the transmit datapath is reset.
-
5
RXRESET
When a 1 is written, the receive datapath is reset.
-
6
PASSRUNTFRAME When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they
have a CRC error. If 0 runt frames are filtered out.
0
7
PASSRXFILTER
0
8
TXFLOWCONTROL Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and
continuous preamble in half duplex.
0
9
RMII
When set to 1 , RMII mode is selected; if 0, MII mode is selected.
0
10
FULLDUPLEX
When set to 1 , indicates full duplex operation.
0
31:11
-
Unused
0
When set to 1 , disables receive filtering i.e. all frames received are written to
memory.
All bits can be written and read. The Tx/RxReset bits are write-only, reading will return a 0.
10.10.2.2 Status Register
The Status register (Status) is a read-only register.
Table 169. Status register (STATUS - address 0x2008 4104) bit description
Bit
Symbol
Function
Reset value
0
RXSTATUS If 1, the receive channel is active. If 0, the receive channel is inactive.
0
1
TXSTATUS If 1, the transmit channel is active. If 0, the transmit channel is inactive.
0
31:2
-
0
Unused
The values represent the status of the two channels/data paths. When the status is 1, the
channel is active, meaning:
• It is enabled and the Rx/TxEnable bit is set in the Command register or it just got
disabled while still transmitting or receiving a frame.
• Also, for the transmit channel, the transmit queue is not empty
i.e. ProduceIndex != ConsumeIndex.
• Also, for the receive channel, the receive queue is not full
i.e. ProduceIndex != ConsumeIndex - 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
218 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The status transitions from active to inactive if the channel is disabled by a software reset
of the Rx/TxEnable bit in the Command register and the channel has committed the status
and data of the current frame to memory. The status also transitions to inactive if the
transmit queue is empty or if the receive queue is full and status and data have been
committed to memory.
10.10.2.3 Receive Descriptor Base Address Register
Table 170. Receive Descriptor Base Address register (RXDESCRIPTOR - address 0x2008 4108) bit description
Bit
Symbol
Function
Reset value
1:0
-
Fixed to 00
31:2
RXDESCRIPTOR MSBs of receive descriptor base address.
0
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
10.10.2.4 Receive Status Base Address Register
The receive descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
Table 171. Receive Status Base Address register (RXSTATUS - address 0x2008 410C) bit description
Bit
Symbol
Function
Reset value
2:0
-
Fixed to 000
31:3
RXSTATUS MSBs of receive status base address.
0
The receive status base address is a byte address aligned to a double word boundary i.e.
LSB 2:0 are fixed to “000”.
10.10.2.5 Receive Number of Descriptors Register
Table 172. Receive Number of Descriptors register (RXDESCRIPTORNUMBER - address 0x2008 4110) bit
description
Bit
Symbol
Function
Reset value
15:0
RXDESCRIPTORN RxDescriptorNumber. Number of descriptors in the descriptor array for which
RxDescriptor is the base address. The number of descriptors is minus one
encoded.
0
31:16
-
0
Unused
The receive number of descriptors register defines the number of descriptors in the
descriptor array for which RxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if the
array has 8 elements, the value in the register should be 7.
10.10.2.6 Receive Produce Index Register
Table 173. Receive Produce Index register (RXPRODUCEINDEX - address 0x2008 4114) bit description
Bit
Symbol
15:0
RXPRODUCEIX Index of the descriptor that is going to be filled next by the receive datapath.
0
31:16
-
0
UM10562
User manual
Function
Reset value
Unused
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
219 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The receive produce index register defines the descriptor that is going to be filled next by
the hardware receive process. After a frame has been received, hardware increments the
index. The value is wrapped to 0 once the value of RxDescriptorNumber has been
reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any
further frames being received will cause a buffer overrun error.
10.10.2.7 Receive Consume Index Register
Table 174. Receive Consume Index register (RXCONSUMEINDEX - address 0x2008 4118) bit description
Bit
Symbol
Function
Reset value
15:0
RXCONSUMEIX Index of the descriptor that is going to be processed next by the receive
31:16
-
Unused
0
The receive consume register defines the descriptor that is going to be processed next by
the software receive driver. The receive array is empty as long as RxProduceIndex equals
RxConsumeIndex. As soon as the array is not empty, software can process the frame
pointed to by RxConsumeIndex. After a frame has been processed by software, software
should increment the RxConsumeIndex. The value must be wrapped to 0 once the value
of RxDescriptorNumber has been reached. If the RxProduceIndex equals
RxConsumeIndex - 1, the array is full and any further frames being received will cause a
buffer overrun error.
10.10.2.8 Transmit Descriptor Base Address Register
Table 175. Transmit Descriptor Base Address register (TXDESCRIPTOR - address 0x2008 411C) bit description
Bit
Symbol Function
Reset value
1:0
-
Fixed to “00”
-
31:2
TXD
TxDescriptor. MSBs of transmit descriptor base address.
0
The transmit descriptor base address is a byte address aligned to a word boundary i.e.
LSB 1:0 are fixed to “00”. The register contains the lowest address in the array of
descriptors.
10.10.2.9 Transmit Status Base Address Register
Table 176. Transmit Status Base Address register (TXSTATUS - address 0x2008 4120) bit description
Bit
Symbol Function
Reset value
1:0
-
31:2
TXSTAT TxStatus. MSBs of transmit status base address.
Fixed to “00”
0
The transmit status base address is a byte address aligned to a word boundary i.e. LSB
1:0 are fixed to “00”. The register contains the lowest address in the array of statuses.
10.10.2.10 Transmit Number of Descriptors Register
Table 177. Transmit Number of Descriptors register (TXDESCRIPTORNUMBER - address 0x2008 4124) bit
description
Bit
Symbol Function
15:0
TXDN
TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor
is the base address. The register is minus one encoded.
0
31:16
-
Unused
0
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
220 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The transmit number of descriptors register defines the number of descriptors in the
descriptor array for which TxDescriptor is the base address. The number of descriptors
should match the number of statuses. The register uses minus one encoding i.e. if the
array has 8 elements, the value in the register should be 7.
10.10.2.11 Transmit Produce Index Register
Table 178. Transmit Produce Index register (TXPRODUCEINDEX - address 0x2008 4128) bit description
Bit
Symbol Function
Reset value
15:0
TXPI
TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit
software driver.
0
31:16
-
Unused
0
The transmit produce index register defines the descriptor that is going to be filled next by
the software transmit driver. The transmit descriptor array is empty as long as
TxProduceIndex equals TxConsumeIndex. If the transmit hardware is enabled, it will start
transmitting frames as soon as the descriptor array is not empty. After a frame has been
processed by software, it should increment the TxProduceIndex. The value must be
wrapped to 0 once the value of TxDescriptorNumber has been reached. If the
TxProduceIndex equals TxConsumeIndex - 1 the descriptor array is full and software
should stop producing new descriptors until hardware has transmitted some frames and
updated the TxConsumeIndex.
10.10.2.12 Transmit Consume Index Register
Table 179. Transmit Consume Index register (TXCONSUMEINDEX - address 0x2008 412C) bit description
Bit
Symbol Function
Reset value
15:0
TXCI
TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit
datapath.
0
31:16
-
Unused
0
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
10.10.2.13 Transmit Status Vector 0 Register
The transmit status vector registers store the most recent transmit status returned by the
MAC. Since the status vector consists of more than 4 bytes, status is distributed over two
registers TSV0 and TSV1. These registers are provided for debug purposes, because the
communication between driver software and the Ethernet block takes place primarily
through the frame descriptors. The status register contents are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
221 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 180. Transmit Status Vector 0 register (TSV0 - address 0x2008 4158) bit description
Bit
Symbol
Function
Reset
value
0
CRCERR
CRC error. The attached CRC in the packet did not match the internally generated
CRC.
0
1
LCE
Length check error. Indicates the frame length field does not match the actual number
of data items and is not a type field.
0
2
LOR
Length out of range. Indicates that frame type/length field was larger than 1500 bytes.
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the
IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the
max length and gives the "Length out of range" error. In fact, this bit is not an error
indication, but simply a statement by the chip regarding the status of the received
frame.
0
3
DONE
Transmission of packet was completed.
0
4
MULTICAST
Packet’s destination was a multicast address.
0
5
BROADCAST
Packet’s destination was a broadcast address.
0
6
PACKETDEFER
Packet was deferred for at least one attempt, but less than an excessive defer.
0
7
EXDF
Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or
24287 bit times in 10 Mbps mode.
0
8
EXCOL
Excessive Collision. Packet was aborted due to exceeding of maximum allowed
number of collisions.
0
9
LCOL
Late Collision. Collision occurred beyond collision window, 512 bit times.
0
10
GIANT
Byte count in frame was greater than can be represented in the transmit byte count
field in TSV1.
0
11
UNDERRUN
Host side caused buffer underrun.
0
27:12
TOTALBYTES
The total number of bytes transferred including collided attempts.
0
28
CONTROLFRAME The frame was a control frame.
0
29
PAUSE
0
30
BACKPRESSURE Carrier-sense method backpressure was previously applied.
0
31
VLAN
0
The frame was a control frame with a valid PAUSE opcode.
Frame’s length/type field contained 0x8100 which is the VLAN protocol identifier.
[1]
UM10562
User manual
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length
out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the
status of the received frame.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
222 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.2.14 Transmit Status Vector 1 Register
The Transmit Status Vector 1 register (TSV1) is a read-only register. The transmit status
vector registers store the most recent transmit status returned by the MAC. Since the
status vector consists of more than 4 bytes, status is distributed over two registers TSV0
and TSV1. These registers are provided for debug purposes, because the communication
between driver software and the Ethernet block takes place primarily through the frame
descriptors. The status register contents are valid as long as the internal status of the
MAC is valid and should typically only be read when the transmit and receive processes
are halted.
Table 181. Transmit Status Vector 1 register (TSV1 - address 0x2008 415C) bit description
Bit
Symbol Function
15:0
TBC
Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.
0
19:16
TCC
Transmit collision count. Number of collisions the current packet incurred during
transmission attempts. The maximum number of collisions (16) cannot be represented.
0
31:20
-
Unused
0
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
223 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.2.15 Receive Status Vector Register
The Receive status vector register (RSV) is a read-only register. The receive status vector
register stores the most recent receive status returned by the MAC. This register is
provided for debug purposes, because the communication between driver software and
the Ethernet block takes place primarily through the frame descriptors. The status register
contents are valid as long as the internal status of the MAC is valid and should typically
only be read when the transmit and receive processes are halted.
Table 182. Receive Status Vector register (RSV - address 0x2008 4160) bit description
Bit
Symbol
Function
Reset
value
15:0
RBC
Received byte count. Indicates length of received frame.
0
16
PPI
Packet previously ignored. Indicates that a packet was dropped.
0
17
RXDVSEEN
RXDV event previously seen. Indicates that the last receive event seen was not long
enough to be a valid packet.
0
18
CESEEN
Carrier event previously seen. Indicates that at some time since the last receive
statistics, a carrier event was detected.
0
19
RCV
Receive code violation. Indicates that received PHY data does not represent a valid
receive code.
0
20
CRCERR
CRC error. The attached CRC in the packet did not match the internally generated
CRC.
0
21
LCERR
Length check error. Indicates the frame length field does not match the actual number
of data items and is not a type field.
0
22
LOR
Length out of range. Indicates that frame type/length field was larger than 1518 bytes.
0
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the
IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the
max length and gives the "Length out of range" error. In fact, this bit is not an error
indication, but simply a statement by the chip regarding the status of the received
frame.
23
ROK
Receive OK. The packet had valid CRC and no symbol errors.
0
24
MULTICAST
The packet destination was a multicast address.
0
25
BROADCAST
The packet destination was a broadcast address.
0
26
DRIBBLENIBBLE
Indicates that after the end of packet another 1-7 bits were received. A single nibble,
called dribble nibble, is formed but not sent out.
0
27
CONTROLFRAME The frame was a control frame.
0
28
PAUSE
The frame was a control frame with a valid PAUSE opcode.
0
29
UO
Unsupported Opcode. The current frame was recognized as a Control Frame but
contains an unknown opcode.
0
30
VLAN
Frame’s length/type field contained 0x8100 which is the VLAN protocol identifier.
0
31
-
Unused
0
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
224 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.2.16 Flow Control Counter Register
Table 183. Flow Control Counter register (FLOWCONTROLCOUNTER - address 0x2008 4170) bit description
Bit
Symbol Function
Reset value
15:0
MC
MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before
re-issuing the Pause control frame.
0
31:16
PT
PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the
pause timer field of a pause flow control frame. In half duplex mode the PauseTimer
specifies the number of backpressure cycles.
0
10.10.2.17 Flow Control Status Register
Table 184. Flow Control Status register (FLOWCONTROLSTATUS - address 0x2008 4174) bit description
Bit
Symbol Function
15:0
MCC
MirrorCounterCurrent. In full duplex mode this register represents the current value of the
datapath’s mirror counter which counts up to the value specified by the MirrorCounter field
in the FlowControlCounter register. In half duplex mode the register counts until it reaches
the value of the PauseTimer bits in the FlowControlCounter register.
0
31:16
-
Unused
0
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
225 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.3 Receive filter register definitions
10.10.3.1 Receive Filter Control Register
Table 185. Receive Filter Control register (RXFILTERCTRL - address 0x2008 4200) bit description
Bit
Symbol Function
Reset value
0
AUE
AcceptUnicastEn. When set to 1, all unicast frames are accepted.
1
ABE
AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.
0
2
AME
AcceptMulticastEn. When set to 1, all multicast frames are accepted.
0
3
AUHE
AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are
accepted.
0
4
AMHE
AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter
are accepted.
0
5
APE
AcceptPerfectEn. When set to 1, the frames with a destination address identical to the
station address are accepted.
0
0
11:6
-
Reserved. Read value is undefined, only zero should be written.
12
MPEW
MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL
interrupt when there is a match.
0
13
RFEW
RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the
imperfect hash filter will generate a WoL interrupt when there is a match.
0
Unused
0
31:14 -
NA
10.10.3.2 Receive Filter WoL Status Register
The Receive Filter Wake-up on LAN Status register (RxFilterWoLStatus) is a read-only
register.
Table 186. Receive Filter WoL Status register (RXFILTERWOLSTATUS - address 0x2008 4204) bit description
Bit
Symbol Function
0
AUW
AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.
0
1
ABW
AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.
0
2
AMW
AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.
0
3
AUHW
AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash
filter caused WoL.
0
4
AMHW
AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect
hash filter caused WoL.
0
5
APW
AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.
0
6
-
Unused
0
7
RFW
RxFilterWoL. When the value is 1, the receive filter caused WoL.
0
8
MPW
MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.
0
Unused
0
31:9 -
Reset value
The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be
cleared by writing the RxFilterWoLClear register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
226 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.3.3 Receive Filter WoL Clear Register
The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear) is a write-only
register.
Table 187. Receive Filter WoL Clear register (RxFilterWoLClear - address 0x2008 4208) bit description
Bit
Symbol
Function
0
AUWCLR
AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
1
ABWCLR
AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
2
AMWCLR
AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
3
AUHWCLR AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
4
AMHWCLR AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
5
APWCLR
AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus
register is cleared.
6
-
Unused
7
RFWCLR
RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is
cleared.
8
MPWCLR
MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register
is cleared.
31:9 -
Unused
The bits in this register are write-only; writing resets the corresponding bits in the
RxFilterWoLStatus register.
10.10.3.4 Hash Filter Table LSBs Register
Details of Hash filter table use can be found in Section 10.13.10 “Receive filtering” on
page 259.
Table 188. Hash Filter Table LSBs register (HASHFILTERL - address 0x2008 4210) bit description
Bit
Symbol
Function
Reset value
31:0
HFL
HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.
0
10.10.3.5 Hash Filter Table MSBs Register
Details of Hash filter table use can be found in Section 10.13.10 “Receive filtering” on
page 259.
Table 189. Hash Filter MSBs register (HASHFILTERH - address 0x2008 4214) bit description
Bit
Symbol
Function
31:0
HFH
Bits 63:32 of the imperfect filter hash table for receive filtering.
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
227 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.4 Module control register definitions
10.10.4.1 Interrupt Status Register
The Interrupt Status register (IntStatus) is a read-only register.Note that all bits are
flip-flops with an asynchronous set in order to be able to generate interrupts if there are
wake-up events while clocks are disabled.
Table 190. Interrupt Status register (INTSTATUS - address 0x2008 4FE0) bit description
Bit
Symbol
Function
Reset
value
0
RXOVERRUNINT
Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be
resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.
0
1
RXERRORINT
Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError,
SymbolError, CRCError or NoDescriptor or Overrun.
0
2
RXFINISHEDINT
Interrupt triggered when all receive descriptors have been processed i.e. on the
transition to the situation where ProduceIndex == ConsumeIndex.
0
3
RXDONEINT
Interrupt triggered when a receive descriptor has been processed while the Interrupt
bit in the Control field of the descriptor was set.
0
4
TXUNDERRUNINT Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should
be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun
error.
0
5
TXERRORINT
Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and
ExcessiveDefer, NoDescriptor or Underrun.
0
6
TXFINISHEDINT
Interrupt triggered when all transmit descriptors have been processed i.e. on the
transition to the situation where ProduceIndex == ConsumeIndex.
0
7
TXDONEINT
Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the
Control field of the descriptor was set.
0
11:8
-
Unused
0
12
SOFTINT
Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.
0
13
WAKEUPINT
Interrupt triggered by a Wake-up event detected by the receive filter.
0
31:14
-
Unused
0
The interrupt status register is read-only. Setting can be done via the IntSet register. Reset
can be accomplished via the IntClear register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
228 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.4.2 Interrupt Enable Register
Table 191. Interrupt Enable register (INTENABLE - address 0x2008 4FE4) bit description
Bit
Symbol
Function
Reset
value
0
RXOVERRUNINTEN
Enable for interrupt trigger on receive buffer overrun or descriptor underrun
situations.
0
1
RXERRORINTEN
Enable for interrupt trigger on receive errors.
0
2
RXFINISHEDINTEN
Enable for interrupt triggered when all receive descriptors have been processed i.e.
on the transition to the situation where ProduceIndex == ConsumeIndex.
0
3
RXDONEINTEN
Enable for interrupt triggered when a receive descriptor has been processed while
the Interrupt bit in the Control field of the descriptor was set.
0
4
TXUNDERRUNINTEN Enable for interrupt trigger on transmit buffer or descriptor underrun situations.
0
5
TXERRORINTEN
Enable for interrupt trigger on transmit errors.
0
6
TXFINISHEDINTEN
Enable for interrupt triggered when all transmit descriptors have been processed
i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
0
7
TXDONEINTEN
Enable for interrupt triggered when a descriptor has been transmitted while the
Interrupt bit in the Control field of the descriptor was set.
0
11:8
-
Unused
0
12
SOFTINTEN
Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by
software writing a 1 to the SoftIntSet bit in the IntSet register.
0
13
WAKEUPINTEN
Enable for interrupt triggered by a Wake-up event detected by the receive filter.
0
31:14
-
Unused
0
10.10.4.3 Interrupt Clear Register
Table 192. Interrupt Clear register (INTCLEAR - address 0x2008 4FE8) bit description
Bit
Symbol
Function
0
RXOVERRUNINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
1
RXERRORINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
2
RXFINISHEDINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
3
RXDONEINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
4
TXUNDERRUNINTCLR Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
5
TXERRORINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
6
TXFINISHEDINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
7
TXDONEINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
11:8
-
Unused
12
SOFTINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
13
WAKEUPINTCLR
Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
31:14
-
Unused
The interrupt clear register is write-only. Writing a 1 to a bit of the IntClear register clears
the corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
229 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.10.4.4 Interrupt Set Register
Table 193. Interrupt Set register (INTSET - address 0x2008 4FEC) bit description
Bit
Symbol
Function
0
RXOVERRUNINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
1
RXERRORINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
2
RXFINISHEDINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
3
RXDONEINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
4
TXUNDERRUNINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
5
TXERRORINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
6
TXFINISHEDINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
7
TXDONEINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
11:8
-
Unused
12
SOFTINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
13
WAKEUPINTSET
Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
31:14
-
Unused
The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
10.10.4.5 Power-Down Register
The Power-Down register (PowerDown) is used to block all AHB accesses except
accesses to the Power-Down register.
Table 194. Power-Down register (POWERDOWN - address 0x2008 4FF4) bit description
Bit
Symbol Function
Reset value
30:0
-
Unused
0
31
PD
PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except
accesses to the Power-Down register.
0
Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the Power-Down register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
230 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.11 Descriptor and status formats
This section defines the descriptor format for the transmit and receive scatter/gather DMA
engines. Each Ethernet frame can consist of one or more fragments. Each fragment
corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for
receive) and gather (for transmit) multiple fragments for a single Ethernet frame.
10.11.1 Receive descriptors and statuses
Figure 24 depicts the layout of the receive descriptors in memory.
RxDescriptor
RxStatus
PACKET
1
DATA BUFFER
CONTROL
PACKET
2
StatusHashCRC
DATA BUFFER
CONTROL
PACKET
3
PACKET
DATA BUFFER
PACKET
DATA BUFFER
PACKET
StatusInfo
StatusHashCRC
DATA BUFFER
CONTROL
RxDescriptorNumber
StatusInfo
StatusHashCRC
CONTROL
5
StatusInfo
StatusHashCRC
CONTROL
4
StatusInfo
StatusInfo
StatusHashCRC
DATA BUFFER
CONTROL
StatusInfo
StatusHashCRC
Fig 24. Receive descriptor memory layout
Receive descriptors are stored in an array in memory. The base address of the array is
stored in the RxDescriptor register, and should be aligned on a 4 byte address boundary.
The number of descriptors in the array is stored in the RxDescriptorNumber register using
a minus one encoding style e.g. if the array has 8 elements the register value should be 7.
Parallel to the descriptors there is an array of statuses. For each element of the descriptor
array there is an associated status field in the status array. The base address of the status
array is stored in the RxStatus register, and must be aligned on an 8 byte address
boundary. During operation (when the receive data path is enabled) the RxDescriptor,
RxStatus and RxDescriptorNumber registers should not be modified.
Two registers, RxConsumeIndex and RxProduceIndex, define the descriptor locations
that will be used next by hardware and software. Both registers act as counters starting at
0 and wrapping when they reach the value of RxDescriptorNumber. The RxProduceIndex
contains the index of the descriptor that is going to be filled with the next frame being
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
231 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
received. The RxConsumeIndex is programmed by software and is the index of the next
descriptor that the software receive driver is going to process. When RxProduceIndex ==
RxConsumeIndex, the receive buffer is empty. When RxProduceIndex ==
RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly
received data would generate an overflow unless the software driver frees up one or more
descriptors.
Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes two words (8 bytes) in memory. Each receive descriptor consists of a
pointer to the data buffer for storing receive data (Packet) and a control word (Control).
The Packet field has a zero address offset, the control field has a 4 byte address offset
with respect to the descriptor address as defined in Table 195.
Table 195. Receive Descriptor Fields
Symbol
Address offset
Bytes
Description
Packet
0x0
4
Base address of the data buffer for storing receive data.
Control
0x4
4
Control information, see Table 196.
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table 196.
Table 196. Receive Descriptor Control Word
Bit
Symbol Description
10:0
Size
30:11 31
Size in bytes of the data buffer. This is the size of the buffer reserved by the device driver for a frame or
frame fragment i.e. the byte size of the buffer pointed to by the Packet field. The size is -1 encoded e.g. if
the buffer is 8 bytes the size field should be equal to 7.
Unused
Interrupt If true generate an RxDone interrupt when the data in this frame or frame fragment and the associated
status information has been committed to memory.
Table 197 lists the fields in the receive status elements from the status array.
Table 197. Receive Status Fields
Symbol
Address offset Bytes Description
StatusInfo
0x0
4
Receive status return flags, see Table 199.
StatusHashCRC
0x4
4
The concatenation of the destination address hash CRC and the source
address hash CRC.
Each receive status consists of two words. The StatusHashCRC word contains a
concatenation of the two 9-bit hash CRCs calculated from the destination and source
addresses contained in the received frame. After detecting the destination and source
addresses, StatusHashCRC is calculated once, then held for every fragment of the same
frame.
The concatenation of the two CRCs is shown in Table 198:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
232 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 198. Receive Status HashCRC Word
Bit
Symbol
Description
8:0
SAHashCRC
Hash CRC calculated from the source address.
15:9
-
Unused
24:16
DAHashCRC
Hash CRC calculated from the destination address.
31:25
-
Unused
The StatusInfo word contains flags returned by the MAC and flags generated by the
receive data path reflecting the status of the reception. Table 199 lists the bit definitions in
the StatusInfo word.
Table 199. Receive status information word
Bit
Symbol
Description
10:0
RxSize
The size in bytes of the actual data transferred into one fragment buffer. In other words, this is the
size of the frame or fragment as actually written by the DMA manager for one descriptor. This may
be different from the Size bits of the Control field in the descriptor that indicate the size of the buffer
allocated by the device driver. Size is -1 encoded e.g. if the buffer has 8 bytes the RxSize value will
be 7.
17:11
-
Unused
18
ControlFrame
Indicates this is a control frame for flow control, either a pause frame or a frame with an
unsupported opcode.
19
VLAN
Indicates a VLAN frame.
20
FailFilter
Indicates this frame has failed the Rx filter. These frames will not normally pass to memory. But due
to the limitation of the size of the buffer, part of this frame may already be passed to memory. Once
the frame is found to have failed the Rx filter, the remainder of the frame will be discarded without
being passed to the memory. However, if the PassRxFilter bit in the Command register is set, the
whole frame will be passed to memory.
21
Multicast
Set when a multicast frame is received.
22
Broadcast
Set when a broadcast frame is received.
23
CRCError
The received frame had a CRC error.
24
SymbolError
The PHY reports a bit error over the PHY interface during reception.
25
LengthError
The frame length field value in the frame specifies a valid length, but does not match the actual
data length.
26
RangeError[1]
The received packet exceeds the maximum packet size.
27
AlignmentError An alignment error is flagged when dribble bits are detected and also a CRC error is detected. This
is in accordance with IEEE std. 802.3/clause 4.3.2.
28
Overrun
Receive overrun. The adapter can not accept the data stream.
29
NoDescriptor
No new Rx descriptor is available and the frame is too long for the buffer size in the current receive
descriptor.
30
LastFlag
When set to 1, indicates this descriptor is for the last fragment of a frame. If the frame consists of a
single fragment, this bit is also set to 1.
31
Error
An error occurred during reception of this frame. This is a logical OR of AlignmentError,
RangeError, LengthError, SymbolError, CRCError, and Overrun.
[1]
UM10562
User manual
The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or
ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range"
error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the
received frame.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
233 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
For multi-fragment frames, the value of the AlignmentError, RangeError, LengthError,
SymbolError and CRCError bits in all but the last fragment in the frame will be 0; likewise
the value of the FailFilter, Multicast, Broadcast, VLAN and ControlFrame bits is undefined.
The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid LastFrag, RxSize, Error, Overrun and
NoDescriptor bits.
10.11.2 Transmit descriptors and statuses
Figure 25 depicts the layout of the transmit descriptors in memory.
TxDescriptor
TxStatus
PACKET
1
DATA BUFFER
StatusInfo
CONTROL
PACKET
2
DATA BUFFER
StatusInfo
CONTROL
PACKET
3
DATA BUFFER
StatusInfo
CONTROL
PACKET
4
DATA BUFFER
StatusInfo
CONTROL
PACKET
5
DATA BUFFER
StatusInfo
CONTROL
TxDescriptorNumber
PACKET
DATA BUFFER
StatusInfo
CONTROL
Fig 25. Transmit descriptor memory layout
Transmit descriptors are stored in an array in memory. The lowest address of the transmit
descriptor array is stored in the TxDescriptor register, and must be aligned on a 4 byte
address boundary. The number of descriptors in the array is stored in the
TxDescriptorNumber register using a minus one encoding style i.e. if the array has 8
elements the register value should be 7. Parallel to the descriptors there is an array of
statuses. For each element of the descriptor array there is an associated status field in the
status array. The base address of the status array is stored in the TxStatus register, and
must be aligned on a 4 byte address boundary. During operation (when the transmit data
path is enabled) the TxDescriptor, TxStatus, and TxDescriptorNumber registers should
not be modified.
Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that
will be used next by hardware and software. Both register act as counters starting at 0 and
wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
234 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
contains the index of the next descriptor that is going to be filled by the software driver.
The TxConsumeIndex contains the index of the next descriptor going to be transmitted by
the hardware. When TxProduceIndex == TxConsumeIndex, the transmit buffer is empty.
When TxProduceIndex == TxConsumeIndex -1 (taking wraparound into account), the
transmit buffer is full and the software driver cannot add new descriptors until the
hardware has transmitted one or more frames to free up descriptors.
Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each
status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a
pointer to the data buffer containing transmit data (Packet) and a control word (Control).
The Packet field has a zero address offset, whereas the control field has a 4 byte address
offset, see Table 200.
Table 200. Transmit descriptor fields
Symbol
Address offset
Bytes
Description
Packet
0x0
4
Base address of the data buffer containing transmit data.
Control
0x4
4
Control information, see Table 201.
The data buffer pointer (Packet) is a 32-bit, byte aligned address value containing the
base address of the data buffer. The definition of the control word bits is listed in
Table 201.
Table 201. Transmit descriptor control word
Bit
Symbol Description
10:0
Size
Size in bytes of the data buffer. This is the size of the frame or fragment as it needs to be fetched by the
DMA manager. In most cases it will be equal to the byte size of the data buffer pointed to by the Packet
field of the descriptor. Size is -1 encoded e.g. a buffer of 8 bytes is encoded as the Size value 7.
25:11
-
Unused
26
Override Per frame override. If true, bits 30:27 will override the defaults from the MAC internal registers. If false,
bits 30:27 will be ignored and the default values from the MAC will be used.
27
Huge
If true, enables huge frame, allowing unlimited frame sizes. When false, prevents transmission of more
than the maximum frame length (MAXF[15:0]).
28
Pad
If true, pad short frames to 64 bytes.
29
CRC
If true, append a hardware CRC to the frame.
30
Last
If true, indicates that this is the descriptor for the last fragment in the transmit frame. If false, the fragment
from the next descriptor should be appended.
31
Interrupt If true, a TxDone interrupt will be generated when the data in this frame or frame fragment has been sent
and the associated status information has been committed to memory.
Table 202 shows the one field transmit status.
Table 202. Transmit status fields
Symbol
StatusInfo
Address offset
Bytes
0x0
4
Description
Transmit status return flags, see Table 203.
The transmit status consists of one word which is the StatusInfo word. It contains flags
returned by the MAC and flags generated by the transmit data path reflecting the status of
the transmission. Table 203 lists the bit definitions in the StatusInfo word.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
235 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Table 203. Transmit status information word
Bit
Symbol
Description
20:0
-
Unused
24:21
CollisionCount
The number of collisions this packet incurred, up to the Retransmission Maximum.
25
Defer
This packet incurred deferral, because the medium was occupied. This is not an error unless
excessive deferral occurs.
26
ExcessiveDefer
This packet incurred deferral beyond the maximum deferral limit and was aborted.
27
ExcessiveCollision Indicates this packet exceeded the maximum collision limit and was aborted.
28
LateCollision
An Out of window Collision was seen, causing packet abort.
29
Underrun
A Tx underrun occurred due to the adapter not producing transmit data.
30
NoDescriptor
The transmit stream was interrupted because a descriptor was not available.
31
Error
An error occurred during transmission. This is a logical OR of Underrun, LateCollision,
ExcessiveCollision, and ExcessiveDefer.
For multi-fragment frames, the value of the LateCollision, ExcessiveCollision,
ExcessiveDefer, Defer and CollissionCount bits in all but the last fragment in the frame will
be 0. The status of the last fragment in the frame will copy the value for these bits from the
MAC. All fragment statuses will have valid Error, NoDescriptor and Underrun bits.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
236 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.12 Ethernet block functional description
This section defines the functions of the DMA capable 10/100 Ethernet MAC. After
introducing the DMA concepts of the Ethernet block, and a description of the basic
transmit and receive functions, this section elaborates on advanced features such as flow
control, receive filtering, etc.
10.12.1 Overview
The Ethernet block can transmit and receive Ethernet packets from an off-chip Ethernet
PHY connected through the MII/RMII interface. MII or RMII mode is selected by software.
Typically during system start-up, the Ethernet block will be initialized. Software
initialization of the Ethernet block should include initialization of the descriptor and status
arrays as well as the receiver fragment buffers.
Remark: when initializing the Ethernet block, it is important to first configure the PHY and
insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both
ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins
and connected to the EMAC module (selecting the appropriate pins using the IOCON
registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become
locked and no further functionality will be possible. This will cause JTAG lose
communication with the target, if debug mode is being used.
To transmit a packet the software driver has to set up the appropriate Control registers
and a descriptor to point to the packet data buffer before transferring the packet to
hardware by incrementing the TxProduceIndex register. After transmission, hardware will
increment TxConsumeIndex and optionally generate an interrupt.
The hardware will receive packets from the PHY and apply filtering as configured by the
software driver. While receiving a packet the hardware will read a descriptor from memory
to find the location of the associated receiver data buffer. Receive data is written in the
data buffer and receive status is returned in the receive descriptor status word. Optionally
an interrupt can be generated to notify software that a packet has been received. Note
that the DMA manager will prefetch and buffer up to three descriptors.
10.12.2 AHB interface
The registers of the Ethernet block connect to an AHB slave interface to allow access to
the registers from the CPU.
The AHB interface has a 32-bit data path, which supports only word accesses and has an
address aperture of 4 kB. Table 148 lists the registers of the Ethernet block.
All AHB write accesses to registers are posted except for accesses to the IntSet, IntClear
and IntEnable registers. AHB write operations are executed in order.
If the PowerDown bit of the PowerDown register is set, all AHB read and write accesses
will return a read or write error except for accesses to the PowerDown register.
Bus Errors
The Ethernet block generates errors for several conditions:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
237 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
• The AHB interface will return a read error when there is an AHB read access to a
write-only register; likewise a write error is returned when there is an AHB write
access to the read-only register. An AHB read or write error will be returned on AHB
read or write accesses to reserved registers. These errors are propagated back to the
CPU. Registers defined as read-only and write-only are identified in Table 148.
• If the PowerDown bit is set all accesses to AHB registers will result in an error
response except for accesses to the PowerDown register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
238 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.13 Interrupts
The Ethernet block has a single interrupt request output to the CPU (via the NVIC).
The interrupt service routine must read the IntStatus register to determine the origin of the
interrupt. All interrupt statuses can be set by software writing to the IntSet register;
statuses can be cleared by software writing to the IntClear register.
The transmit and receive data paths can only set interrupt statuses, they cannot clear
statuses. The SoftInt interrupt cannot be set by hardware and can be used by software for
test purposes.
10.13.1 Direct Memory Access (DMA)
Descriptor arrays
The Ethernet block includes two DMA managers. The DMA managers make it possible to
transfer frames directly to and from memory with little support from the processor and
without the need to trigger an interrupt for each frame.
The DMA managers work with arrays of frame descriptors and statuses that are stored in
memory. The descriptors and statuses act as an interface between the Ethernet hardware
and the device driver software. There is one descriptor array for receive frames and one
descriptor array for transmit frames. Using buffering for frame descriptors, the memory
traffic and memory bandwidth utilization of descriptors can be kept small.
Each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer
containing a frame or a fragment, whereas the second field is a control word related to
that frame or fragment.
The software driver must write the base addresses of the descriptor and status arrays in
the TxDescriptor/RxDescriptor and TxStatus/RxStatus registers. The number of
descriptors/statuses in each array must be written in the
TxDescriptorNumber/RxDescriptorNumber registers. The number of descriptors in an
array corresponds to the number of statuses in the associated status array.
Transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be
aligned on a 4 byte (32bit)address boundary, while the receive status array must be
aligned on a 8 byte (64bit) address boundary.
Ownership of descriptors
Both device driver software and Ethernet hardware can read and write the descriptor
arrays at the same time in order to produce and consume descriptors. A descriptor is
"owned" either by the device driver or by the Ethernet hardware. Only the owner of a
descriptor reads or writes its value. Typically, the sequence of use and ownership of
descriptors and statuses is as follows: a descriptor is owned and set up by the device
driver; ownership of the descriptor/status is passed by the device driver to the Ethernet
block, which reads the descriptor and writes information to the status field; the Ethernet
block passes ownership of the descriptor back to the device driver, which uses the status
information and then recycles the descriptor to be used for another frame. Software must
pre-allocate the memory used to hold the descriptor arrays.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
239 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Software can hand over ownership of descriptors and statuses to the hardware by
incrementing (and wrapping if on the array boundary) the
TxProduceIndex/RxConsumeIndex registers. Hardware hands over descriptors and
status to software by updating the TxConsumeIndex/ RxProduceIndex registers.
After handing over a descriptor to the receive and transmit DMA hardware, device driver
software should not modify the descriptor or reclaim the descriptor by decrementing the
TxProduceIndex/ RxConsumeIndex registers because descriptors may have been
prefetched by the hardware. In this case the device driver software will have to wait until
the frame has been transmitted or the device driver has to soft-reset the transmit and/or
receive data paths which will also reset the descriptor arrays.
Sequential order with wrap-around
When descriptors are read from and statuses are written to the arrays, this is done in
sequential order with wrap-around. Sequential order means that when the Ethernet block
has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is
the one at the next higher, adjacent memory address. Wrap around means that when the
Ethernet block has finished reading/writing the last descriptor/status of the array (with the
highest memory address), the next descriptor/status it reads/writes is the first
descriptor/status of the array at the base address of the array.
Full and Empty state of descriptor arrays
The descriptor arrays can be empty, partially full or full. A descriptor array is empty when
all descriptors are owned by the producer. A descriptor array is partially full if both
producer and consumer own part of the descriptors and both are busy processing those
descriptors. A descriptor array is full when all descriptors (except one) are owned by the
consumer, so that the producer has no more room to process frames. Ownership of
descriptors is indicated with the use of a consume index and a produce index. The
produce index is the first element of the array owned by the producer. It is also the index
of the array element that is next going to be used by the producer of frames (it may
already be busy using it and subsequent elements). The consume index is the first
element of the array that is owned by the consumer. It is also the number of the array
element next to be consumed by the consumer of frames (it and subsequent elements
may already be in the process of being consumed). If the consume index and the produce
index are equal, the descriptor array is empty and all array elements are owned by the
producer. If the consume index equals the produce index plus one, then the array is full
and all array elements (except the one at the produce index) are owned by the consumer.
With a full descriptor array, still one array element is kept empty, to be able to easily
distinguish the full or empty state by looking at the value of the produce index and
consume index. An array must have at least 2 elements to be able to indicate a full
descriptor array with a produce index of value 0 and a consume index of value 1. The
wrap around of the arrays is taken into account when determining if a descriptor array is
full, so a produce index that indicates the last element in the array and a consume index
that indicates the first element in the array, also means the descriptor array is full. When
the produce index and the consume index are unequal and the consume index is not the
produce index plus one (with wrap around taken into account), then the descriptor array is
partially full and both the consumer and producer own enough descriptors to be able to
operate actively on the descriptor array.
Interrupt bit
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
240 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The descriptors have an Interrupt bit, which is programmed by software. When the
Ethernet block is processing a descriptor and finds this bit set, it will allow triggering an
interrupt (after committing status to memory) by passing the RxDoneInt or TxDoneInt bits
in the IntStatus register to the interrupt output pin. If the Interrupt bit is not set in the
descriptor, then the RxDoneInt or TxDoneInt are not set and no interrupt is triggered (note
that the corresponding bits in IntEnable must also be set to trigger interrupts). This offers
flexible ways of managing the descriptor arrays. For instance, the device driver could add
10 frames to the Tx descriptor array, and set the Interrupt bit in descriptor number 5 in the
descriptor array. This would invoke the interrupt service routine before the transmit
descriptor array is completely exhausted. The device driver could add another batch of
frames to the descriptor array, without interrupting continuous transmission of frames.
Frame fragments
For maximum flexibility in frame storage, frames can be split up into multiple frame
fragments with fragments located in different places in memory. In this case one
descriptor is used for each frame fragment. So, a descriptor can point to a single frame or
to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit
frames are gathered from multiple fragments in memory and receive frames can be
scattered to multiple fragments in memory.
By stringing together fragments it is possible to create large frames from small memory
areas. Another use of fragments is to be able to locate a frame header and frame payload
in different places and to concatenate them without copy operations in the device driver.
For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the
last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status
words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor
is a new Ethernet frame.
10.13.2 Initialization
After reset, the Ethernet software driver needs to initialize the Ethernet block. During
initialization the software needs to:
• Remove the soft reset condition from the MAC.
• Configure the PHY via the MIIM interface of the MAC.
Remark: it is important to configure the PHY and insure that reference clocks
(ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK
signals in MII mode) are present at the external pins and connected to the EMAC
module (selecting the appropriate pins using the IOCON registers) prior to continuing
with Ethernet configuration. Otherwise the CPU can become locked and no further
functionality will be possible. This will cause JTAG lose communication with the target,
if debug mode is being used.
•
•
•
•
UM10562
User manual
Select MII or RMII mode
Configure the transmit and receive DMA engines, including the descriptor arrays.
Configure the host registers (MAC1,MAC2 etc.) in the MAC.
Enable the receive and transmit data paths.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
241 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Depending on the PHY, the software needs to initialize registers in the PHY via the MII
Management interface. The software can read and write PHY registers by programming
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the
MWTD register; read data and status information can be read from the MRDD and MIND
registers.
The Ethernet block supports MII and RMII PHYs. During initialization software must select
MII or RMII mode by programming the Command register.
Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be
de-asserted. The clock(s) from the PHY must be running and internally connected during
this operation.
Transmit and receive DMA engines should be initialized by the device driver by allocating
the descriptor and status arrays in memory. Transmit and receive functions have their own
dedicated descriptor and status arrays. The base addresses of these arrays need to be
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The
number of descriptors in an array matches the number of statuses in an array.
Please note that the transmit descriptors, receive descriptors and receive statuses are 8
bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit
statuses need to be aligned on 4 byte boundaries; receive status arrays need to be
aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to
be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding
i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor
array has 4 descriptors the value of the number of descriptors register should be 3.
After setting up the descriptor arrays, frame buffers need to be allocated for the receive
descriptors before enabling the receive data path. The Packet field of the receive
descriptors needs to be filled with the base address of the frame buffer of that descriptor.
Amongst others the Control field in the receive descriptor needs to contain the size of the
data buffer using -1 encoding.
The receive data path has a configurable filtering function for discarding/ignoring specific
Ethernet frames. The filtering function should also be configured during initialization.
After an assertion of the hardware reset, the soft reset bit in the MAC will be asserted. The
soft reset condition must be removed before the Ethernet block can be enabled.
Enabling of the receive function is located in two places. The receive DMA manager
needs to be enabled and the receive data path of the MAC needs to be enabled. To
prevent overflow in the receive DMA engine the receive DMA engine should be enabled
by setting the RxEnable bit in the Command register before enabling the receive data path
in the MAC by setting the RECEIVE ENABLE bit in the MAC1 register.
The transmit DMA engine can be enabled at any time by setting the TxEnable bit in the
Command register.
Before enabling the data paths, several options can be programmed in the MAC, such as
automatic flow control, transmit to receive loop-back for verification, full/half duplex
modes, etc.
Base addresses of descriptor arrays and descriptor array sizes cannot be modified
without a (soft) reset of the receive and transmit data paths.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
242 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.13.3 Transmit process
Overview
This section outlines the transmission process.
Device driver sets up descriptors and data
If the descriptor array is full the device driver should wait for the descriptor arrays to
become not full before writing to a descriptor in the descriptor array. If the descriptor array
is not full, the device driver should use the descriptor numbered TxProduceIndex of the
array pointed to by TxDescriptor.
The Packet pointer in the descriptor is set to point to a data frame or frame fragment to be
transmitted. The Size field in the Command field of the descriptor should be set to the
number of bytes in the fragment buffer, -1 encoded. Additional control information can be
indicated in the Control field in the descriptor (bits Interrupt, Last, CRC, Pad).
After writing the descriptor the descriptor needs to be handed over to the hardware by
incrementing (and possibly wrapping) the TxProduceIndex register.
If the transmit data path is disabled, the device driver should not forget to enable the
transmit data path by setting the TxEnable bit in the Command register.
When there is a multi-fragment transmission for fragments other than the last, the Last bit
in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To
trigger an interrupt when the frame has been transmitted and transmission status has
been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have
the hardware add a CRC in the frame sequence control field of this Ethernet frame, set
the CRC bit in the descriptor. This should be done if the CRC has not already been added
by software. To enable automatic padding of small frames to the minimum required frame
size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits
CRC and Pad are both set to 1.
The device driver can set up interrupts using the IntEnable register to wait for a signal of
completion from the hardware or can periodically inspect (poll) the progress of
transmission. It can also add new frames at the end of the descriptor array, while
hardware consumes descriptors at the start of the array.
The device driver can stop the transmit process by resetting the TxEnable bit in the
Command register to 0. The transmission will not stop immediately; frames already being
transmitted will be transmitted completely and the status will be committed to memory
before deactivating the data path. The status of the transmit data path can be monitored
by the device driver reading the TxStatus bit in the Status register.
As soon as the transmit data path is enabled and the corresponding TxConsumeIndex
and TxProduceIndex are not equal i.e. the hardware still needs to process frames from
the descriptor array, the TxStatus bit in the Status register will return to 1 (active).
Tx DMA manager reads the Tx descriptor array
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
243 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at
the address determined by TxDescriptor and TxConsumeIndex. The number of
descriptors requested is determined by the total number of descriptors owned by the
hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes
memory loading. Read data returned from memory is buffered and consumed as needed.
Tx DMA manager transmits data
After reading the descriptor the transmit DMA engine reads the associated frame data
from memory and transmits the frame. After transfer completion, the Tx DMA manager
writes status information back to the StatusInfo and StatusHashCRC words of the status
field. The value of the TxConsumeIndex is only updated after status information has been
committed to memory, which is checked by an internal tag protocol in the memory
interface. The Tx DMA manager continues to transmit frames until the descriptor array is
empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will
return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the
TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled.
The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the
descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments.
The Tx DMA manager gathers all the fragments from the host memory, visiting a string of
frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.
When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,
this indicates the last fragment of the frame and thus the end of the frame is found.
Update ConsumeIndex
Each time the Tx DMA manager commits a status word to memory it completes the
transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around
into account) to hand the descriptor back to the device driver software. Software can
re-use the descriptor for new transmissions after hardware has handed it back.
The device driver software can keep track of the progress of the DMA manager by reading
the TxConsumeIndex register to see how far along the transmit process is. When the Tx
descriptor array is emptied completely, the TxConsumeIndex register retains its last value.
Write transmission status
After the frame has been transmitted over the MII/RMII bus, the StatusInfo word of the
frame descriptor is updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame transmission, error
flags (Error, LateCollision, ExcessiveCollision, Underrun, ExcessiveDefer, Defer) are set
in the status. The CollisionCount field is set to the number of collisions the frame incurred,
up to the Retransmission Maximum programmed in the Collision window/retry register of
the MAC.
Statuses for all but the last fragment in the frame will be written as soon as the data in the
frame has been accepted by the Tx DMA manager. Even if the descriptor is for a frame
fragment other than the last fragment, the error flags are returned via the AHB interface. If
the Ethernet block detects a transmission error during transmission of a (multi-fragment)
frame, all remaining fragments of the frame are still read via the AHB interface. After an
error, the remaining transmit data is discarded by the Ethernet block. If there are errors
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
244 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
during transmission of a multi-fragment frame the error statuses will be repeated until the
last fragment of the frame. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. These may
include error information if the error is detected early enough. The status for the last
fragment in the frame will only be written after the transmission has completed on the
Ethernet connection. Thus, the status for the last fragment will always reflect any error
that occurred anywhere in the frame.
The status of the last frame transmission can also be inspected by reading the TSV0 and
TSV1 registers. These registers do not report statuses on a fragment basis and do not
store information of previously sent frames. They are provided primarily for debug
purposes, because the communication between driver software and the Ethernet block
takes place through the frame descriptors. The status registers are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
Transmission error handling
If an error occurs during the transmit process, the Tx DMA manager will report the error
via the transmission StatusInfo word written in the Status array and the IntStatus interrupt
status register.
The transmission can generate several types of errors: LateCollision, ExcessiveCollision,
ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the
transmission StatusInfo word. In addition to the separate bits in the StatusInfo word,
LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error
bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the
IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer,
or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus
register.
Underrun errors can have three causes:
• The next fragment in a multi-fragment transmission is not available. This is a nonfatal
error. A NoDescriptor status will be returned on the previous fragment and the TxError
bit in IntStatus will be set.
• The transmission fragment data is not available when the Ethernet block has already
started sending the frame. This is a nonfatal error. An Underrun status will be returned
on transfer and the TxError bit in IntStatus will be set.
• The flow of transmission statuses stalls and a new status has to be written while a
previous status still waits to be transferred across the memory interface. This is a fatal
error which can only be resolved by a soft reset of the hardware.
The first and second situations are nonfatal and the device driver has to re-send the frame
or have upper software layers re-send the frame. In the third case the hardware is in an
undefined state and needs to be soft reset by setting the TxReset bit in the Command
register.
After reporting a LateCollision, ExcessiveCollision, ExcessiveDefer or Underrun error, the
transmission of the erroneous frame will be aborted, remaining transmission data and
frame fragments will be discarded and transmission will continue with the next frame in
the descriptor array.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
245 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Device drivers should catch the transmission errors and take action.
Transmit triggers interrupts
The transmit data path can generate four different interrupt types:
• If the Interrupt bit in the descriptor Control field is set, the Tx DMA will set the
TxDoneInt bit in the IntStatus register after sending the fragment and committing the
associated transmission status to memory. Even if a descriptor (fragment) is not the
last in a multi-fragment frame the Interrupt bit in the descriptor can be used to
generate an interrupt.
• If the descriptor array is empty while the Ethernet hardware is enabled the hardware
will set the TxFinishedInt bit of the IntStatus register.
• If the AHB interface does not consume the transmission statuses at a sufficiently high
bandwidth the transmission may underrun in which case the TxUnderrun bit will be set
in the IntStatus register. This is a fatal error which requires a soft reset of the
transmission queue.
• In the case of a transmission error (LateCollision, ExcessiveCollision, or
ExcessiveDefer) or a multi-fragment frame where the device driver did provide the
initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the
case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus
register.
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Transmit example
Figure 26 illustrates the transmit process in an example transmitting uses a frame header
of 8 bytes and a frame payload of 12 bytes.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
246 of 942
UM10562
NXP Semiconductors
status 0
StatusInfo
status 1
StatusInfo
status 2
StatusInfo
StatusInfo
0x200811F8
0x200811FC
3
Control
0x20081100 1 1 CONTROL
0x2008132B
Packet
0x20081419
0x20081324
0x200810FC
0 0 CONTROL
7
Control
descriptor 2
descriptor array
0x200810F8
Packet
0x20081411
descriptor 1
PACKET 0 PAYLOAD (12 bytes)
0x200810F4
0x20081104
0x20081108
7
0 0 CONTROL
Control
descriptor array
descriptor 3
PACKET 1 HEADER (8 bytes)
Packet
0x20081324
0x20081200
status array
0x2008141C
0x20081419
0 0 CONTROL
Control
7
0x20081411
PACKET 0 HEADER (8 bytes)
Packet
0x20081314
descriptor 0
0x200810F0
TxStatus
0x200811F8
status 3
0x20081314
TxDescriptor
0x200810EC
0x200810EC
0x2008131B
Chapter 10: LPC408x/407x Ethernet
0x20081204
TxProduceIndex
TxConsumeIndex
TxDescriptorNumber
=3
fragment buffers
status array
Fig 26. Transmit example memory and registers
After reset the values of the DMA registers will be zero. During initialization the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
boundary. Since the number of descriptors matches the number of statuses the status
array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address
boundary. The device driver writes the base address of the descriptor array
(0x2008 10EC) to the TxDescriptor register and the base address of the status array
(0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors
and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and
statuses in the arrays need not be initialized, yet.
At this point, the transmit data path may be enabled by setting the TxEnable bit in the
Command register. If the transmit data path is enabled while there are no further frames to
send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load
only the desired interrupts can be enabled by setting the relevant bits in the IntEnable
register.
Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP
protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will
add a header to the frame. The frame header need not be immediately in front of the
payload data in memory. The device driver can program the Tx DMA to collect header and
payload data. To do so, the device driver will program the first descriptor to point at the
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
247 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
frame header; the Last flag in the descriptor will be set to false/0 to indicate a
multi-fragment transmission. The device driver will program the next descriptor to point at
the actual payload data. The maximum size of a payload buffer is 2 kB so a single
descriptor suffices to describe the payload buffer. For the sake of the example though the
payload is distributed across two descriptors. After the first descriptor in the array
describing the header, the second descriptor in the array describes the initial 8 bytes of
the payload; the third descriptor in the array describes the remaining 4 bytes of the frame.
In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last
descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set
in the last fragment of the frame in order to trigger an interrupt after the transmission
completed. The Size field in the descriptor’s Control word is set to the number of bytes in
the fragment buffer, -1 encoded.
Note that in real device drivers, the payload will typically only be split across multiple
descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to
the hardware without the device driver copying it (zero copy device driver).
After setting up the descriptors for the transaction the device driver increments the
TxProduceIndex register by 3 since three descriptors have been programmed. If the
transmit data path was not enabled during initialization the device driver needs to enable
the data path now.
If the transmit data path is enabled the Ethernet block will start transmitting the frame as
soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero
after reset. The Tx DMA will start reading the descriptors from memory. The memory
system will return the descriptors and the Ethernet block will accept them one by one
while reading the transmit data fragments.
As soon as transmission read data is returned from memory, the Ethernet block will try to
start transmission on the Ethernet connection via the MII/RMII interface.
After transmitting each fragment of the frame the Tx DMA will write the status of the
fragment’s transmission. Statuses for all but the last fragment in the frame will be written
as soon as the data in the frame has been accepted by the Tx DMA manager. The status
for the last fragment in the frame will only be written after the transmission has completed
on the Ethernet connection.
Since the Interrupt bit in the descriptor of the last fragment is set, after committing the
status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,
which triggers the device driver to inspect the status information.
In this example the device driver cannot add new descriptors as long as the Ethernet
block has not incremented the TxConsumeIndex because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the hardware commits the status
for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager
can the device driver program the next (the fourth) descriptor. The fourth descriptor can
already be programmed before completely transmitting the first frame.
In this example the hardware adds the CRC to the frame. If the device driver software
adds the CRC, the CRC trailer can be considered another frame fragment which can be
added by doing another gather DMA.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
248 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Each data byte is transmitted across the MII interface as two 4-bit values or the RMII
interface as four 2-bit values. The Ethernet block adds the preamble, frame delimiter
leader, and the CRC trailer if hardware CRC is enabled. Once transmission on the
MII/RMII interface commences the transmission cannot be interrupted without generating
an underrun error, which is why descriptors and data read commands are issued as soon
as possible and pipelined.
Using an MII PHY, the data communication between the Ethernet block and the PHY is
done at a 25 MHz rate. With an RMII PHY, the data communication between the Ethernet
block and the PHY is at a 50 MHz rate. In 10 Mbps mode data will only be transmitted
once every 10 clock cycles.
10.13.4 Receive process
This section outlines the receive process including the activities in the device driver
software.
Device driver sets up descriptors
After initializing the receive descriptor and status arrays to receive frames from the
Ethernet connection, the receive data path should be enabled in the MAC1 register and
the Control register.
During initialization, each Packet pointer in the descriptors is set to point to a data
fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the
descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt
bit allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the initialization and enabling of the receive data path, all descriptors are owned by
the receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of the
receive data path.
Rx DMA manager reads Rx descriptor arrays
When the RxEnable bit in the Command register is set, the Rx DMA manager reads the
descriptors from memory at the address determined by RxDescriptor and
RxProduceIndex. The Ethernet block will start reading descriptors even before actual
receive data arrives on the MII/RMII interface (descriptor prefetching). The block size of
the descriptors to be read is determined by the total number of descriptors owned by the
hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors
minimizes memory load. Read data returned from memory is buffered and consumed as
needed.
RX DMA manager receives data
After reading the descriptor, the receive DMA engine waits for the MAC to return receive
data from the MII/RMII interface that passes the receive filter. Receive frames that do not
match the filtering criteria are not passed to memory. Once a frame passes the receive
filter, the data is written in the fragment buffer associated with the descriptor. The Rx DMA
does not write beyond the size of the buffer. When a frame is received that is larger than a
descriptor’s fragment buffer, the frame will be written to multiple fragment buffers of
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
249 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
consecutive descriptors. In the case of a multi-fragment reception, all but the last fragment
in the frame will return a status where the LastFrag bit is set to 0. Only on the last
fragment of a frame the LastFrag bit in the status will be set to 1. If a fragment buffer is the
last of a frame, the buffer may not be filled completely. The first receive data of the next
frame will be written to the fragment buffer of the next descriptor.
After receiving a fragment, the Rx DMA manager writes status information back to the
StatusInfo and StatusHashCRC words of the status. The Ethernet block writes the size in
bytes of a descriptor’s fragment buffer in the RxSize field of the Status word. The value of
the RxProduceIndex is only updated after the fragment data and the fragment status
information has been committed to memory, which is checked by an internal tag protocol
in the memory interface. The Rx DMA manager continues to receive frames until the
descriptor array is full. If the descriptor array is full, the Ethernet hardware will set the
RxFinishedInt bit of the IntStatus register. The receive data path will still be enabled. If the
receive descriptor array is full any new receive data will generate an overflow error and
interrupt.
Update ProduceIndex
Each time the Rx DMA manager commits a data fragment and the associated status word
to memory, it completes the reception of a descriptor and increments the RxProduceIndex
(taking wrap around into account) in order to hand the descriptor back to the device driver
software. Software can re-use the descriptor for new receptions by handing it back to
hardware when the receive data has been processed.
The device driver software can keep track of the progress of the DMA manager by reading
the RxProduceIndex register to see how far along the receive process is. When the Rx
descriptor array is emptied completely, the RxProduceIndex retains its last value.
Write reception status
After the frame has been received from the MII/RMII bus, the StatusInfo and
StatusHashCRC words of the frame descriptor are updated by the DMA manager.
If the descriptor is for the last fragment of a frame (or for the whole frame if there are no
fragments), then depending on the success or failure of the frame reception, error flags
(Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or
CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually
written to the fragment buffer, -1 encoded. For fragments not being the last in the frame
the RxSize will match the size of the buffer. The hash CRCs of the destination and source
addresses of a packet are calculated once for all the fragments belonging to the same
packet and then stored in every StatusHashCRC word of the statuses associated with the
corresponding fragments. If the reception reports an error, any remaining data in the
receive frame is discarded and the LastFrag bit will be set in the receive status field, so
the error flags in all but the last fragment of a frame will always be 0.
The status of the last received frame can also be inspected by reading the RSV register.
The register does not report statuses on a fragment basis and does not store information
of previously received frames. RSV is provided primarily for debug purposes, because the
communication between driver software and the Ethernet block takes place through the
frame descriptors.
Reception error handling
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
250 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
When an error occurs during the receive process, the Rx DMA manager will report the
error via the receive StatusInfo written in the Status array and the IntStatus interrupt status
register.
The receive process can generate several types of errors: AlignmentError, RangeError,
LengthError, SymbolError, CRCError, Overrun, and NoDescriptor. All have corresponding
bits in the receive StatusInfo. In addition to the separate bits in the StatusInfo,
AlignmentError, RangeError, LengthError, SymbolError, and CRCError are ORed together
into the Error bit of the StatusInfo. Errors are also propagated to the IntStatus register; the
RxError bit in the IntStatus register is set if there is an AlignmentError, RangeError,
LengthError, SymbolError, CRCError, or NoDescriptor error; nonfatal overrun errors are
reported in the RxError bit of the IntStatus register; fatal Overrun errors are report in the
RxOverrun bit of the IntStatus register. On fatal overrun errors, the Rx data path needs to
be soft reset by setting the RxReset bit in the Command register.
Overrun errors can have three causes:
• In the case of a multi-fragment reception, the next descriptor may be missing. In this
case the NoDescriptor field is set in the status word of the previous descriptor and the
RxError in the IntStatus register is set. This error is nonfatal.
• The data flow on the receiver data interface stalls, corrupting the packet. In this case
the overrun bit in the status word is set and the RxError bit in the IntStatus register is
set. This error is nonfatal.
• The flow of reception statuses stalls and a new status has to be written while a
previous status still waits to be transferred across the memory interface. This error will
corrupt the hardware state and requires the hardware to be soft reset. The error is
detected and sets the Overrun bit in the IntStatus register.
The first overrun situation will result in an incomplete frame with a NoDescriptor status
and the RxError bit in IntStatus set. Software should discard the partially received frame.
In the second overrun situation the frame data will be corrupt which results in the Overrun
status bit being set in the Status word while the IntError interrupt bit is set. In the third case
receive errors cannot be reported in the receiver Status arrays which corrupts the
hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The
RxReset bit in the Command register should be used to soft reset the hardware.
Device drivers should catch the above receive errors and take action.
Receive triggers interrupts
The receive data path can generate four different interrupt types:
• If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the
RxDoneInt bit in the IntStatus register after receiving a fragment and committing the
associated data and status to memory. Even if a descriptor (fragment) is not the last in
a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an
interrupt.
• If the descriptor array is full while the Ethernet hardware is enabled, the hardware will
set the RxFinishedInt bit of the IntStatus register.
• If the AHB interface does not consume receive statuses at a sufficiently high
bandwidth, the receive status process may overrun, in which case the RxOverrun bit
will be set in the IntStatus register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
251 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
• If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or
CRCError), or a multi-fragment frame where the device driver did provide descriptors
for the initial fragments but did not provide the descriptors for the rest of the
fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt
bit of the IntStatus register.
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Device driver processes receive data
As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the
device driver can read the descriptors that have been handed over to it by the hardware
(RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words
in the status array to check for multi-fragment receptions and receive errors.
The device driver can forward receive data and status to upper software layers. After
processing of data and status, the descriptors, statuses and data buffers may be recycled
and handed back to hardware by incrementing the RxConsumeIndex.
Receive example
Figure 27 illustrates the receive process in an example receiving a frame of 19 bytes.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
252 of 942
UM10562
NXP Semiconductors
Status 0
Status 1
1 CONTROL 7
0x20081418
0x200810F0
0x20081411
FRAGMENT 0 BUFFER(8 bytes)
PACKET
0x20081409
Descriptor 0
0x200810EC
RxStatus
0x200811F8
StatusInfo
7
0x200811F8
StatusHashCRC
StatusInfo
7
0x20081200
StatusHashCRC
Status 2
Status 3
0x2008141B
0x200810F8 1 CONTROL 7
0x20081419
PACKET
0x20081411
0x20081100 1 CONTROL 7
0x20081325
PACKET
0x20081419
StatusInfo
2
0x20081208
StatusHashCRC
StatusInfo
7
0x20081210
StatusHashCRC
0x2008132C
FRAGMENT 2 BUFFER(3 bytes)
0x200810FC
Descriptor 2
descriptor array
0x200810F4
Descriptor 1
FRAGMENT 1 BUFFER(8 bytes)
status array
RxDescriptor
0x200810EC
0x20081410
0x20081409
Chapter 10: LPC408x/407x Ethernet
FRAGMENT 3 BUFFER(8 bytes)
0x20081108
1 CONTROL 7
descriptor array
RxProduceIndex
Descriptor 3
0x20081104
PACKET
0x20081325
RxConsumeIndex
RxDescriptorNumber= 3
fragment buffers
status array
Fig 27. Receive Example Memory and Registers
After reset, the values of the DMA registers will be zero. During initialization, the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
boundary. Since the number of descriptors matches the number of statuses, the status
array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address
boundary. The device driver writes the base address of the descriptor array
(0x2008 10EC) in the RxDescriptor register, and the base address of the status array
(0x2008 11F8) in the RxStatus register. The device driver writes the number of descriptors
and statuses minus 1 (3) in the RxDescriptorNumber register. The descriptors and
statuses in the arrays need not be initialized yet.
After allocating the descriptors, a fragment buffer needs to be allocated for each of the
descriptors. Each fragment buffer can be between 1 byte and 2 k bytes. The base
address of the fragment buffer is stored in the Packet field of the descriptors. The number
of bytes in the fragment buffer is stored in the Size field of the descriptor Control word.
The Interrupt field in the Control word of the descriptor can be set to generate an interrupt
as soon as the descriptor has been filled by the receive process. In this example the
fragment buffers are 8 bytes, so the value of the Size field in the Control word of the
descriptor is set to 7. Note that in this example, the fragment buffers are actually a
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
253 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
continuous memory space; even when a frame is distributed over multiple fragments it will
typically be in a linear, continuous memory space; when the descriptors wrap at the end of
the descriptor array the frame will not be in a continuous memory space.
The device driver should enable the receive process by writing a 1 to the RxEnable bit of
the Command register, after which the MAC needs to be enabled by writing a 1 to the
‘RECEIVE ENABLE’ bit of the MAC1 configuration register. The Ethernet block will now
start receiving Ethernet frames. To reduce the processor interrupt load, some interrupts
can be disabled by setting the relevant bits in the IntEnable register.
After the Rx DMA manager is enabled, it will start issuing descriptor read commands. In
this example the number of descriptors is 4. Initially the RxProduceIndex and
RxConsumeIndex are 0. Since the descriptor array is considered full if RxProduceIndex
== RxConsumeIndex - 1, the Rx DMA manager can only read (RxConsumeIndex RxProduceIndex - 1 =) 3 descriptors; note the wrapping.
After enabling the receive function in the MAC, data reception will begin starting at the
next frame i.e. if the receive function is enabled while the MII/RMII interface is halfway
through receiving a frame, the frame will be discarded and reception will start at the next
frame. The Ethernet block will strip the preamble and start of frame delimiter from the
frame. If the frame passes the receive filtering, the Rx DMA manager will start writing the
frame to the first fragment buffer.
Suppose the frame is 19 bytes long. Due to the buffer sizes specified in this example, the
frame will be distributed over three fragment buffers. After writing the initial 8 bytes in the
first fragment buffer, the status for the first fragment buffer will be written and the Rx DMA
will continue filling the second fragment buffer. Since this is a multi-fragment receive, the
status of the first fragment will have a 0 for the LastFrag bit in the StatusInfo word; the
RxSize field will be set to 7 (8, -1 encoded). After writing the 8 bytes in the second
fragment the Rx DMA will continue writing the third fragment. The status of the second
fragment will be like the status of the first fragment: LastFrag = 0, RxSize = 7. After writing
the three bytes in the third fragment buffer, the end of the frame has been reached and the
status of the third fragment is written. The third fragment’s status will have the LastFrag bit
set to 1 and the RxSize equal to 2 (3, -1 encoded).
The next frame received from the MII/RMII interface will be written to the fourth fragment
buffer i.e. five bytes of the third buffer will be unused.
The Rx DMA manager uses an internal tag protocol in the memory interface to check that
the receive data and status have been committed to memory. After the status of the
fragments are committed to memory, an RxDoneInt interrupt will be triggered, which
activates the device driver to inspect the status information. In this example, all
descriptors have the Interrupt bit set in the Control word i.e. all descriptors will generate
an interrupt after committing data and status to memory.
In this example the receive function cannot read new descriptors as long as the device
driver does not increment the RxConsumeIndex, because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the device driver has forwarded
the receive data to application software, and after the device driver has updated the
RxConsumeIndex by incrementing it, will the Ethernet block can continue reading
descriptors and receive data. The device driver will probably increment the
RxConsumeIndex by 3, since the driver will forward the complete frame consisting of
three fragments to the application, and hence free up three descriptors at the same time.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
254 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) are
transferred as a byte on the data write interface after being delayed by 128 or 136 cycles
for filtering by the receive filter and buffer modules. The Ethernet block removes
preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the
buffer NoDescriptor error probability, three descriptors are buffered. The value of the
RxProduceIndex is only updated after status information has been committed to memory,
which is checked by an internal tag protocol in the memory interface. The software device
driver will process the receive data, after which the device driver will update the
RxConsumeIndex.
For an RMII PHY the data between the Ethernet block and the PHY is communicated at
half the data-width and twice the clock frequency (50 MHz).
10.13.5 Transmission retry
If a collision on the Ethernet occurs, it usually takes place during the collision window
spanning the first 64 bytes of a frame. If collision is detected, the Ethernet block will retry
the transmission. For this purpose, the first 64 bytes of a frame are buffered, so that this
data can be used during the retry. A transmission retry within the first 64 bytes in a frame
is fully transparent to the application and device driver software.
When a collision occurs outside of the 64 byte collision window, a LateCollision error is
triggered, and the transmission is aborted. After a LateCollision error, the remaining data
in the transmit frame will be discarded. The Ethernet block will set the Error and
LateCollision bits in the frame’s status fields. The TxError bit in the IntStatus register will
be set. If the corresponding bit in the IntEnable register is set, the TxError bit in the
IntStatus register will be propagated to the CPU (via the NVIC). The device driver software
should catch the interrupt and take appropriate actions.
The ‘RETRANSMISSION MAXIMUM’ field of the CLRT register can be used to configure
the maximum number of retries before aborting the transmission.
10.13.6 Status hash CRC calculations
For each received frame, the Ethernet block is able to detect the destination address and
source address and from them calculate the corresponding hash CRCs. To perform the
computation, the Ethernet block features two internal blocks: one is a controller
synchronized with the beginning and the end of each frame, the second block is the CRC
calculator.
When a new frame is detected, internal signaling notifies the controller.The controller
starts counting the incoming bytes of the frame, which correspond to the destination
address bytes. When the sixth (and last) byte is counted, the controller notifies the
calculator to store the corresponding 32-bit CRC into a first inner register. Then the
controller repeats counting the next incoming bytes, in order to get synchronized with the
source address. When the last byte of the source address is encountered, the controller
again notifies the CRC calculator, which freezes until the next new frame. When the
calculator receives this second notification, it stores the present 32-bit CRC into a second
inner register. Then the CRCs remain frozen in their own registers until new notifications
arise.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
255 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The destination address and source address hash CRCs being written in the
StatusHashCRC word are the nine most significant bits of the 32-bit CRCs as calculated
by the CRC calculator.
10.13.7 Duplex modes
The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex
mode needs to be configured by the device driver software during initialization.
For a full duplex connection the FullDuplex bit of the Command register needs to be set to
1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1; for
half duplex the same bits need to be set to 0.
10.13.8 IEE 802.3/Clause 31 flow control
Overview
For full duplex connections, the Ethernet block supports IEEE 802.3/clause 31 flow control
using pause frames. This type of flow control may be used in full-duplex point-to-point
connections. Flow control allows a receiver to stall a transmitter e.g. when the receive
buffers are (almost) full. For this purpose, the receiving side sends a pause frame to the
transmitting side.
Pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles.
Receive flow control
In full-duplex mode, the Ethernet block will suspend its transmissions when the it receives
a pause frame. Rx flow control is initiated by the receiving side of the transmission. It is
enabled by setting the ‘RX FLOW CONTROL’ bit in the MAC1 configuration register. If the
RX FLOW CONTROL’ bit is zero, then the Ethernet block ignores received pause control
frames. When a pause frame is received on the Rx side of the Ethernet block,
transmission on the Tx side will be interrupted after the currently transmitting frame has
completed, for an amount of time as indicated in the received pause frame. The transmit
data path will stop transmitting data for the number of 512 bit slot times encoded in the
pause-timer field of the received pause control frame.
By default the received pause control frames are not forwarded to the device driver. To
forward the receive flow control frames to the device driver, set the ‘PASS ALL RECEIVE
FRAMES’ bit in the MAC1 configuration register.
Transmit flow control
If case device drivers need to stall the receive data e.g. because software buffers are full,
the Ethernet block can transmit pause control frames. Transmit flow control needs to be
initiated by the device driver software; there is no IEEE 802.3/31 flow control initiated by
hardware, such as the DMA managers.
With software flow control, the device driver can detect a situation in which the process of
receiving frames needs to be interrupted by sending out Tx pause frames. Note that due
to Ethernet delays, a few frames can still be received before the flow control takes effect
and the receive stream stops.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
256 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command
register. When the Ethernet block operates in full duplex mode, this will result in
transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is
written to TxFlowControl bit of the Command register.
If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the
Command register will start a pause frame transmission. The value inserted into the
pause-timer value field of transmitted pause frames is programmed via the
PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is
de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically
sent to abort flow control and resume transmission.
When flow control be in force for an extended time, a sequence of pause frames must be
transmitted. This is supported with a mirror counter mechanism. To enable mirror
counting, a nonzero value is written to the MirrorCounter[15:0] bits in the
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame is
transmitted. After sending the pause frame, an internal mirror counter is initialized to zero.
The internal mirror counter starts incrementing one every 512 bit-slot times. When the
internal mirror counter reaches the MirrorCounter value, another pause frame is
transmitted with pause-timer value equal to the PauseTimer field from the
FlowControlCounter register, the internal mirror counter is reset to zero and restarts
counting. The register MirrorCounter[15:0] is usually set to a smaller value than register
PauseTimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send
a new pause frame before the transmission on the other side can resume. By continuing
to send pause frames before the transmitting side finishes counting the pause timer, the
pause can be extended as long as TxFlowControl is asserted. This continues until
TxFlowControl is de-asserted when a final pause frame having a pause-timer value of
0x0000 is automatically sent to abort flow control and resume transmission. To disable the
mirror counter mechanism, write the value 0 to MirrorCounter field in the
FlowControlCounter register. When using the mirror counter mechanism, account for
time-of-flight delays, frame transmission time, queuing delays, crystal frequency
tolerances, and response time delays by programming the MirrorCounter conservatively,
typically about 80% of the PauseTimer value.
If the software device driver sets the MirrorCounter field of the FlowControlCounter
register to zero, the Ethernet block will only send one pause control frame. After sending
the pause frame an internal pause counter is initialized at zero; the internal pause counter
is incremented by one every 512 bit-slot times. Once the internal pause counter reaches
the value of the PauseTimer register, the TxFlowControl bit in the Command register will
be reset. The software device driver can poll the TxFlowControl bit to detect when the
pause completes.
The value of the internal counter in the flow control module can be read out via the
FlowControlStatus register. If the MirrorCounter is nonzero, the FlowControlStatus register
will return the value of the internal mirror counter; if the MirrorCounter is zero the
FlowControlStatus register will return the value of the internal pause counter value.
The device driver is allowed to dynamically modify the MirrorCounter register value and
switch between zero MirrorCounter and nonzero MirrorCounter modes.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
257 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1
configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not
transmit pause control frames, software must not initiate pause frame transmissions, and
the TxFlowControl bit in the Command register should be zero.
Transmit flow control example
Figure 28 illustrates the transmit flow control.
device driver PauseTimer
register MirrorCounter
TxFlowCtl
writes
RMII
transmit
clear
TxFlowCtl
normal
transmission
pause control
frame
transmission
pause control
frame
transmission
normal transimisson
pause control
frame
transmission
MirrorCounter
(1/515 bit
slots)
RMII
receive
0
pause in effect
normal receive
50
100
150
200
250
300
normal receive
350
400
450
500
Fig 28. Transmit Flow Control
In this example, a frame is received while transmitting another frame (full duplex.) The
device driver detects that some buffer might overrun and enables the transmit flow control
by programming the PauseTimer and MirrorCounter fields of the FlowControlCounter
register, after which it enables the transmit flow control by setting the TxFlowControl bit in
the Command register.
As a response to the enabling of the flow control a pause control frame will be sent after
the currently transmitting frame has been transmitted. When the pause frame
transmission completes the internal mirror counter will start counting bit slots; as soon as
the counter reaches the value in the MirrorCounter field another pause frame is
transmitted. While counting the transmit data path will continue normal transmissions.
As soon as software disables transmit flow control a zero pause control frame is
transmitted to resume the receive process.
10.13.9 Half-Duplex mode backpressure
When in half-duplex mode, backpressure can be generated to stall receive packets by
sending continuous preamble that basically jams any other transmissions on the Ethernet
medium. When the Ethernet block operates in half duplex mode, asserting the
TxFlowControl bit in the Command register will result in applying continuous preamble on
the Ethernet wire, effectively blocking traffic from any other Ethernet station on the same
segment.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
258 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent
until TxFlowControl is de-asserted. If the medium is idle, the Ethernet block begins
transmitting preamble, which raises carrier sense causing all other stations to defer. In the
event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the
collision. The colliding station backs off and then defers to the backpressure. If during
backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame
sent and then the backpressure resumed. If TxFlowControl is asserted for longer than
3.3 ms in 10 Mbps mode or 0.33 ms in 100 Mbps mode, backpressure will cease sending
preamble for several byte times to avoid the jabber limit.
10.13.10 Receive filtering
Features of receive filtering
The Ethernet MAC has several receive packet filtering functions that can be configured
from the software driver:
• Perfect address filter: allows packets with a perfectly matching station address to be
identified and passed to the software driver.
• Hash table filter: allows imperfect filtering of packets based on the station address.
• Unicast/multicast/broadcast filtering: allows passing of all unicast, multicast, and/or
broadcast packets.
• Magic packet filter: detection of magic packets to generate a Wake-on-LAN interrupt.
The filtering functions can be logically combined to create complex filtering functions.
Furthermore, the Ethernet block can pass or reject runt packets smaller than 64 bytes; a
promiscuous mode allows all packets to be passed to software.
Overview
The Ethernet block has the capability to filter out receive frames by analyzing the Ethernet
destination address in the frame. This capability greatly reduces the load on the host
system, because Ethernet frames that are addressed to other stations would otherwise
need to be inspected and rejected by the device driver software, using up bandwidth,
memory space, and host CPU time. Address filtering can be implemented using the
perfect address filter or the (imperfect) hash filter. The latter produces a 6-bit hash code
which can be used as an index into a 64 entry programmable hash table. Figure 29
depicts a functional view of the receive filter.
At the top of the diagram the Ethernet receive frame enters the filters. Each filter is
controlled by signals from control registers; each filter produces a ‘Ready’ output and a
‘Match’ output. If ‘Ready’ is 0 then the Match value is ‘don’t care’; if a filter finishes filtering
then it will assert its Ready output; if the filter finds a matching frame it will assert the
Match output along with the Ready output. The results of the filters are combined by logic
functions into a single RxAbort output. If the RxAbort output is asserted, the frame does
not need to be received.
In order to reduce memory traffic, the receive data path has a buffer of 68 bytes. The
Ethernet MAC will only start writing a frame to memory after 68 byte delays. If the RxAbort
signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and
removed from the buffer and not stored to memory at all, not using up receive descriptors,
etc. If the RxAbort signal is asserted after the initial 68 bytes in a frame (probably due to
reception of a Magic Packet), part of the frame is already written to memory and the
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
259 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the
status word of the frame will be set to indicate that the software device driver can discard
the frame immediately.
packet
AcceptUnicastEn
AcceptMulticastEn
StationAddress
IMPERFECT
HASH
FILTER
AcceptUnicastHashEn
AcceptMulticastHashEn
AcceptPerfectEn
PERFECT
ADDRESS
FILTER
PAMatch
PAReady
HFReady
H FMatc h
HashFilter
CRC
OK?
FMatch
RxFilterWoL
RxFilterEnWoL
FReady
RxAbort
Fig 29. Receive filter block diagram
Unicast, broadcast and multicast
Generic filtering based on the type of frame (unicast, multicast or broadcast) can be
programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits
of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and
AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast,
respectively, to be accepted, ignoring the Ethernet destination address in the frame. To
program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1.
Perfect address match
When a frame with a unicast destination address is received, a perfect filter compares the
destination address with the 6 byte station address programmed in the station address
registers SA0, SA1, SA2. If the AcceptPerfectEn bit in the RxFilterCtrl register is set to 1,
and the address matches, the frame is accepted.
Imperfect hash filtering
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
260 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
An imperfect filter is available, based on a hash mechanism. This filter applies a hash
function to the destination address and uses the hash to access a table that indicates if
the frame should be accepted. The advantage of this type of filter is that a small table can
cover any possible address. The disadvantage is that the filtering is imperfect, i.e.
sometimes frames are accepted that should have been discarded.
• Hash function:
– The standard Ethernet cyclic redundancy check (CRC) function is calculated from
the 6 byte destination address in the Ethernet frame (this CRC is calculated
anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access
the hash table: it is used as an index in the 64-bit HashFilter register that has been
programmed with accept values. If the selected accept value is 1, the frame is
accepted.
– The device driver can initialize the hash filter table by writing to the registers
HashFilterL and HashfilterH. HashFilterL contains bits 0 through 31 of the table
and HashFilterH contains bit 32 through 63 of the table. So, hash value 0
corresponds to bit 0 of the HashfilterL register and hash value 63 corresponds to
bit 31 of the HashFilterH register.
• Multicast and unicast
– The imperfect hash filter can be applied to multicast addresses, by setting the
AcceptMulticastHashEn bit in the RxFilter register to 1.
– The same imperfect hash filter that is available for multicast addresses can also be
used for unicast addresses. This is useful to be able to respond to a multitude of
unicast addresses without enabling all unicast addresses. The hash filter can be
applied to unicast addresses by setting the AcceptUnicastHashEn bit in the
RxFilter register to 1.
Enabling and disabling filtering
The filters as defined in the sections above can be bypassed by setting the PassRxFilter
bit in the Command register. When the PassRxFilter bit is set, all receive frames will be
passed to memory. In this case the device driver software has to implement all filtering
functionality in software. Setting the PassRxFilter bit does not affect the runt frame filtering
as defined in the next section.
Runt frames
A frame with less than 64 bytes (or 68 bytes for VLAN frames) is shorter than the
minimum Ethernet frame size and therefore considered erroneous; they might be collision
fragments. The receive data path automatically filters and discards these runt frames
without writing them to memory and using a receive descriptor.
When a runt frame has a correct CRC there is a possibility that it is intended to be useful.
The device driver can receive the runt frames with correct CRC by setting the
PassRuntFrame bit of the Command register to 1.
10.13.11 Power management
The Ethernet block supports power management by means of clock switching. All clocks
in the Ethernet core can be switched off. If Wake-up on LAN is needed, the rx_clk should
not be switched off.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
261 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.13.12 Wake-up on LAN
Overview
The Ethernet block supports power management with remote wake-up over LAN. The
host system can be powered down, even including part of the Ethernet block itself, while
the Ethernet block continues to listen to packets on the LAN. Appropriately formed
packets can be received and recognized by the Ethernet block and used to trigger the
host system to wake up from its power-down state.
Wake-up of the system takes effect through an interrupt. When a wake-up event is
detected, the WakeupInt bit in the IntStatus register is set. The interrupt status will trigger
an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set. This
interrupt should be used by system power management logic to wake up the system.
While in a power-down state the packet that generates a Wake-up on LAN event is lost.
There are two ways in which Ethernet packets can trigger wake-up events: generic
Wake-up on LAN and Magic Packet. Magic Packet filtering uses an additional filter for
Magic Packet detection. In both cases a Wake-up on LAN event is only triggered if the
triggering packet has a valid CRC. Figure 29 shows the generation of the wake-up signal.
The RxFilterWoLStatus register can be read by the software to inspect the reason for a
Wake-up event. Before going to power-down the power management software should
clear the register by writing the RxFilterWolClear register.
NOTE: when entering in power-down mode, a receive frame might be not entirely stored
into the Rx buffer. In this situation, after turning exiting power-down mode, the next
receive frame is corrupted due to the data of the previous frame being added in front of
the last received frame. Software drivers have to reset the receive data path just after
exiting power-down mode.
The following subsections describe the two Wake-up on LAN mechanisms.
Filtering for WoL
The receive filter functionality can be used to generate Wake-up on LAN events. If the
RxFilterEnWoL bit of the RxFilterCtrl register is set, the receive filter will set the WakeupInt
bit of the IntStatus register if a frame is received that passes the filter. The interrupt will
only be generated if the CRC of the frame is correct.
Magic Packet WoL
The Ethernet block supports wake-up using Magic Packet technology (see ‘Magic Packet
technology’, Advanced Micro Devices). A Magic Packet is a specially formed packet solely
intended for wake-up purposes. This packet can be received, analyzed and recognized by
the Ethernet block and used to trigger a wake-up event.
A Magic Packet is a packet that contains in its data portion the station address repeated
16 times with no breaks or interruptions, preceded by 6 Magic Packet synchronization
bytes with the value 0xFF. Other data may be surrounding the Magic Packet pattern in the
data portion of the packet. The whole packet must be a well-formed Ethernet frame.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
262 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The magic packet detection unit analyzes the Ethernet packets, extracts the packet
address and checks the payload for the Magic Packet pattern. The address from the
packet is used for matching the pattern (not the address in the SA0/1/2 registers.) A magic
packet only sets the wake-up interrupt status bit if the packet passes the receive filter as
illustrated in Figure 29: the result of the receive filter is ANDed with the magic packet filter
result to produce the result.
Magic Packet filtering is enabled by setting the MagicPacketEnWoL bit of the RxFilterCtrl
register. Note that when doing Magic Packet WoL, the RxFilterEnWoL bit in the
RxFilterCtrl register should be 0. Setting the RxFilterEnWoL bit to 1 would accept all
packets for a matching address, not just the Magic Packets i.e. WoL using Magic Packets
is more strict.
When a magic packet is detected, apart from the WakeupInt bit in the IntStatus register,
the MagicPacketWoL bit is set in the RxFilterWoLStatus register. Software can reset the
bit writing a 1 to the corresponding bit of the RxFilterWoLClear register.
Example: An example of a Magic Packet with station address 0x11 0x22 0x33 0x44 0x55
0x66 is the following (MISC indicates miscellaneous additional data bytes in the packet):
<DESTINATION> <SOURCE> <MISC>
FF FF FF FF FF FF
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
11 22 33 44 55 66 11 22 33 44
<MISC> <CRC>
55
55
55
55
55
55
55
55
66
66
66
66
66
66
66
66
10.13.13 Enabling and disabling receive and transmit
Enabling and disabling reception
After reset, the receive function of the Ethernet block is disabled. The receive function can
be enabled by the device driver setting the RxEnable bit in the Command register and the
“RECEIVE ENABLE’ bit in the MAC1 configuration register (in that order).
The status of the receive data path can be monitored by the device driver by reading the
RxStatus bit of the Status register. Figure 30 illustrates the state machine for the
generation of the RxStatus bit.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
263 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
ACTIVE
RxStatus = 1
RxEnable = 0 and not busy receiving
OR
RxProduceIndex = RxConsumeIndex - 1
RxEnable = 1
INACTIVE
RxStatus = 0
reset
Fig 30. Receive Active/Inactive state machine
After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is
set in the Command register, the state machine transitions to the ACTIVE state. As soon
as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the
receive data path is busy receiving a packet while the receive data path gets disabled, the
packet will be received completely, stored to memory along with its status before returning
to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will
return to the INACTIVE state.
For the state machine in Figure 30, a soft reset is like a hardware reset assertion, i.e. after
a soft reset the receive data path is inactive until the data path is re-enabled.
Enabling and disabling transmission
After reset, the transmit function of the Ethernet block is disabled. The Tx transmit data
path can be enabled by the device driver setting the TxEnable bit in the Command
register to 1.
The status of the transmit data paths can be monitored by the device driver reading the
TxStatus bit of the Status register. Figure 31 illustrates the state machine for the
generation of the TxStatus bit.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
264 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
ACTIVE
TxStatus = 1
TxEnable = 1
AND
TxProduceIndex <> TxConsumeIndex
TxEnable = 0 and not busy transmitting
OR
TxProduceIndex = TxConsumeIndex
INACTIVE
TxStatus = 0
reset
Fig 31. Transmit Active/Inactive state machine
After reset, the state machine is in the INACTIVE state. As soon as the TxEnable bit is set
in the Command register and the Produce and Consume indices are not equal, the state
machine transitions to the ACTIVE state. As soon as the TxEnable bit is cleared and the
transmit data path has completed all pending transmissions, including committing the
transmission status to memory, the state machine returns to the INACTIVE state. The
state machine will also return to the INACTIVE state if the Produce and Consume indices
are equal again i.e. all frames have been transmitted.
For the state machine in Figure 31, a soft reset is like a hardware reset assertion, i.e. after
a soft reset the transmit data path is inactive until the data path is re-enabled.
10.13.14 Transmission padding and CRC
In the case of a frame of less than 60 bytes (or 64 bytes for VLAN frames), the Ethernet
block can pad the frame to 64 or 68 bytes including a 4 bytes CRC Frame Check
Sequence (FCS). Padding is affected by the value of the ‘AUTO DETECT PAD ENABLE’
(ADPEN), ‘VLAN PAD ENABLE’ (VLPEN) and ‘PAD/CRC ENABLE’ (PADEN) bits of the
MAC2 configuration register, as well as the Override and Pad bits from the transmit
descriptor Control word. CRC generation is affected by the ‘CRC ENABLE’ (CRCE) and
‘DELAYED CRC’ (DCRC) bits of the MAC2 configuration register, and the Override and
CRC bits from the transmit descriptor Control word.
The effective pad enable (EPADEN) is equal to the ‘PAD/CRC ENABLE’ bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise the effective CRC enable
(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from the
descriptor.
If padding is required and enabled, a CRC will always be appended to the padded frames.
A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the frame will not be padded and no CRC will be added unless ECRCE is
set.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
265 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
If EPADEN is 1, then small frames will be padded and a CRC will always be added to the
padded frames. In this case if ADPEN and VLPEN are both 0, then the frames will be
padded to 60 bytes and a CRC will be added creating 64 bytes frames; if VLPEN is 1, the
frames will be padded to 64 bytes and a CRC will be added creating 68 bytes frames; if
ADPEN is 1, while VLPEN is 0 VLAN frames will be padded to 64 bytes, non VLAN
frames will be padded to 60 bytes, and a CRC will be added to padded frames, creating
64 or 68 bytes padded frames.
If CRC generation is enabled, CRC generation can be delayed by four bytes by setting the
DELAYED CRC bit in the MAC2 register, in order to skip proprietary header information.
10.13.15 Huge frames and frame length checking
The ‘HUGE FRAME ENABLE’ bit in the MAC2 configuration register can be set to 1 to
enable transmission and reception of frames of any length. Huge frame transmission can
be enabled on a per frame basis by setting the Override and Huge bits in the transmit
descriptor Control word.
When enabling huge frames, the Ethernet block will not check frame lengths and report
frame length errors (RangeError and LengthError). If huge frames are enabled, the
received byte count in the RSV register may be invalid because the frame may exceed the
maximum size; the RxSize fields from the receive status arrays will be valid.
Frame lengths are checked by comparing the length/type field of the frame to the actual
number of bytes in the frame. A LengthError is reported by setting the corresponding bit in
the receive StatusInfo word.
The MAXF register allows the device driver to specify the maximum number of bytes in a
frame. The Ethernet block will compare the actual receive frame to the MAXF value and
report a RangeError in the receive StatusInfo word if the frame is larger.
10.13.16 Statistics counters
Generally, Ethernet applications maintain many counters that track Ethernet traffic
statistics. There are a number of standards specifying such counters, such as IEEE std
802.3 / clause 30. Other standards are RFC 2665 and RFC 2233.
The approach taken here is that by default all counters are implemented in software. With
the help of the StatusInfo field in frame statuses, many of the important statistics events
listed in the standards can be counted by software.
10.13.17 MAC status vectors
Transmit and receive status information as detected by the MAC are available in registers
TSV0, TSV1 and RSV so that software can poll them. These registers are normally of
limited use because the communication between driver software and the Ethernet block
takes place primarily through frame descriptors. Statistical events can be counted by
software in the device driver. However, for debug purposes the transmit and receive status
vectors are made visible. They are valid as long as the internal status of the MAC is valid
and should typically only be read when the transmit and receive processes are halted.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
266 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.13.18 Reset
The Ethernet block has a hard reset input which is connected to the chip reset, as well as
several soft resets which can be activated by setting the appropriate bits in registers. All
registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise
specified.
Hard reset
After a hard reset, all registers will be set to their default value.
Soft reset
Parts of the Ethernet block can be soft reset by setting bits in the Command register and
the MAC1 configuration register.The MAC1 register has six different reset bits:
• SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the
MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a
hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware
reset.
• SIMULATION RESET: Resets the random number generator in the Transmit
Function. The value after a hardware reset assertion is 0.
• RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the receive function in the MAC. The value after a hardware reset assertion
is 0.
• RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a
hardware reset assertion is 0.
• RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the transmit function in the MAC. The value after a hardware reset
assertion is 0.
• RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after
a hardware reset assertion is 0.
The above reset bits must be cleared by software.
The Command register has three different reset bits:
• TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit data path, excluding the
MAC portions, including all (read-only) registers in the transmit data path, as well as
the TxProduceIndex register in the host registers module. A soft reset of the transmit
data path will abort all AHB transactions of the transmit data path. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Tx data path will clear
the TxStatus bit in the Status register.
• RxReset: Writing a ‘1’ to the RxReset bit will reset the receive data path, excluding the
MAC portions, including all (read-only) registers in the receive data path, as well as
the RxConsumeIndex register in the host registers module. A soft reset of the receive
data path will abort all AHB transactions of the receive data path. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Rx data path will clear
the RxStatus bit in the Status register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
267 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
• RegReset: Resets all of the data paths and registers in the host registers module,
excluding the registers in the MAC. A soft reset of the registers will also abort all AHB
transactions of the transmit and receive data path. The reset bit will be cleared
autonomously by the Ethernet block.
To do a full soft reset of the Ethernet block, device driver software must:
•
•
•
•
Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
Set the RegReset bit in the Command register, this bit clears automatically.
Re-initialize the MAC registers (0x000 to 0x0FC).
Reset the ‘SOFT RESET’ bit in the MAC1 register to 0.
To reset just the transmit data path, the device driver software has to:
• Set the ‘RESET MCS/Tx’ bit in the MAC1 register to 1.
• Disable the Tx DMA managers by setting the TxEnable bits in the Command register
to 0.
• Set the TxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Tx’ bit in the MAC1 register to 0.
To reset just the receive data path, the device driver software has to:
• Disable the receive function by resetting the ‘RECEIVE ENABLE’ bit in the MAC1
configuration register and resetting of the RxEnable bit of the Command register.
• Set the ‘RESET MCS/Rx’ bit in the MAC1 register to 1.
• Set the RxReset bit in the Command register, this bit clears automatically.
• Reset the ‘RESET MCS/Rx’ bit in the MAC1 register to 0.
10.13.19 Ethernet errors
The Ethernet block generates errors for the following conditions:
• A reception can cause an error: AlignmentError, RangeError, LengthError,
SymbolError, CRCError, NoDescriptor, or Overrun. These are reported back in the
receive StatusInfo and in the interrupt status register (IntStatus).
• A transmission can cause an error: LateCollision, ExcessiveCollision,
ExcessiveDefer, NoDescriptor, or Underrun. These are reported back in the
transmission StatusInfo and in the interrupt status register (IntStatus).
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
268 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.14 AHB bandwidth
The Ethernet block is connected to an AHB bus which must carry all of the data and
control information associated with all Ethernet traffic in addition to the CPU accesses
required to operate the Ethernet block and deal with message contents.
10.14.1 DMA access
Assumptions
By making some assumptions, the bandwidth needed for each type of AHB transfer can
be calculated and added in order to find the overall bandwidth requirement.
The flexibility of the descriptors used in the Ethernet block allows the possibility of defining
memory buffers in a range of sizes. In order to analyze bus bandwidth requirements,
some assumptions must be made about these buffers. The "worst case" is not addressed
since that would involve all descriptors pointing to single byte buffers, with most of the
memory occupied in holding descriptors and very little data. It can easily be shown that
the AHB cannot handle the huge amount of bus traffic that would be caused by such a
degenerate (and illogical) case.
For this analysis, an Ethernet packet is assumed to consist of a 64 byte frame.
Continuous traffic is assumed on both the transmit and receive channels.
This analysis does not reflect the flow of Ethernet traffic over time, which would include
inter-packet gaps in both the transmit and receive channels that reduce the bandwidth
requirements over a larger time frame.
Types of DMA access and their bandwidth requirements
The interface to an external Ethernet PHY is via RMII. RMII operates at 50 MHz,
transferring a byte in 4 clock cycles. The data transfer rate is 12.5 Mbps.
The interface to an external Ethernet PHY is via either MII or RMII. An interface MII
operates at 25 MHz, transferring a byte in 2 clock cycles. An RMII interface operates at 50
MHz, transferring a byte in 4 clock cycles. The data transfer rate is the same in both
cases: 12.5 Mbps.
The Ethernet block initiates DMA accesses for the following cases:
• Tx descriptor read:
– Transmit descriptors occupy 2 words (8 bytes) of memory and are read once for
each use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
• Rx descriptor read:
– Receive descriptors occupy 2 words (8 bytes) of memory and are read once for
each use of a descriptor.
– Two word read happens once every 64 bytes (16 words) of received data.
– This gives 1/8th of the data rate, which = 1.5625 Mbps.
• Tx status write:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
269 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
– Transmit status occupies 1 word (4 bytes) of memory and is written once for each
use of a descriptor.
– One word write happens once every 64 bytes (16 words) of transmitted data.
– This gives 1/16th of the data rate, which = 0.7813 Mbps.
• Rx status write:
– Receive status occupies 2 words (8 bytes) of memory and is written once for each
use of a descriptor.
– Two word write happens once every 64 bytes (16 words) of received data.
– This gives 1/8 of the data rate, which = 1.5625 Mbps.
• Tx data read:
– Data transmitted in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
• Rx data write:
– Data to be received in an Ethernet frame, the size is variable.
– Basic Ethernet rate = 12.5 Mbps.
This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function.
10.14.2 Types of CPU access
• Accesses that mirror each of the DMA access types:
– All or part of status values must be read, and all or part of descriptors need to be
written after each use, transmitted data must be stored in the memory by the CPU,
and eventually received data must be retrieved from the memory by the CPU.
– This gives roughly the same or slightly lower rate as the combined DMA functions,
which = 30.5 Mbps.
• Access to registers in the Ethernet block:
– The CPU must read the RxProduceIndex, TxConsumeIndex, and IntStatus
registers, and both read and write the RxConsumeIndex and TxProduceIndex
registers.
– 7 word read/writes once every 64 bytes (16 words) of transmitted and received
data.
– This gives 7/16 of the data rate, which = 5.4688 Mbps.
This gives a total rate of 36 Mbps for the traffic generated by the Ethernet DMA function.
10.14.3 Overall bandwidth
Overall traffic on the AHB is the sum of DMA access rates and CPU access rates, which
comes to approximately 66.5 MB/s.
The peak bandwidth requirement can be somewhat higher due to the use of small
memory buffers, in order to hold often used addresses (e.g. the station address) for
example. Driver software can determine how to build frames in an efficient manner that
does not overutilize the AHB.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
270 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
The bandwidth available on the AHB bus depends on the system clock frequency. As an
example, assume that the system clock is set at 60 MHz. All or nearly all of bus accesses
related to the Ethernet will be word transfers. The raw AHB bandwidth can be
approximated as 4 bytes per two system clocks, which equals 2 times the system clock
rate. With a 60 MHz system clock, the bandwidth is 120 MB/s, giving about 55% utilization
for Ethernet traffic during simultaneous transmit and receive operations. This shows that it
is not necessary to use the maximum CPU frequency for the Ethernet to work with plenty
of bandwidth headroom.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
271 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
10.15 CRC calculation
The calculation is used for several purposes:
• Generation the FCS at the end of the Ethernet frame.
• Generation of the hash table index for the hash table filtering.
• Generation of the destination and source address hash CRCs.
The C pseudocode function below calculates the CRC on a frame taking the frame
(without FCS) and the number of bytes in the frame as arguments. The function returns
the CRC as a 32-bit integer.
int crc_calc(char frame_no_fcs[], int frame_len) {
int i;
// iterator
int j;
// another iterator
char byte; // current byte
int crc; // CRC result
int q0, q1, q2, q3; // temporary variables
crc = 0xFFFFFFFF;
for (i = 0; i < frame_len; i++) {
byte = *frame_no_fcs++;
for (j = 0; j < 2; j++) {
if (((crc >> 28) ^ (byte >> 3)) & 0x00000001)
q3 = 0x04C11DB7;
} else {
q3 = 0x00000000;
}
if (((crc >> 29) ^ (byte >> 2)) & 0x00000001)
q2 = 0x09823B6E;
} else {
q2 = 0x00000000;
}
if (((crc >> 30) ^ (byte >> 1)) & 0x00000001)
q1 = 0x130476DC;
} else {
q1 = 0x00000000;
}
if (((crc >> 31) ^ (byte >> 0)) & 0x00000001)
q0 = 0x2608EDB8;
} else {
q0 = 0x00000000;
}
crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
byte >>= 4;
}
}
return crc;
}
{
{
{
{
For FCS calculation, this function is passed a pointer to the first byte of the frame and the
length of the frame without the FCS.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
272 of 942
UM10562
NXP Semiconductors
Chapter 10: LPC408x/407x Ethernet
For hash filtering, this function is passed a pointer to the destination address part of the
frame and the CRC is only calculated on the 6 address bytes. The hash filter uses bits
[28:23] for indexing the 64-bits { HashFilterH, HashFilterL } vector. If the corresponding bit
is set the packet is passed, otherwise it is rejected by the hash filter.
For obtaining the destination and source address hash CRCs, this function calculates first
both the 32-bit CRCs, then the nine most significant bits from each 32-bit CRC are
extracted, concatenated, and written in every StatusHashCRC word of every fragment
status.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
273 of 942
UM10562
Chapter 11: LPC408x/407x LCD controller
Rev. 1 — 13 September 2012
User manual
11.1 How to read this chapter
The LCD controller is available on some LPC408x/407x devices, see Section 1.4 for
details.
11.2 Basic configuration
The LCD controller is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCLCD.
Remark: The LCD is disabled on reset (PCLCD = 0).
Also see Section 11.6.12 for power-up procedure.
2. Clock: See Table 224 and Table 34.
3. Pins: Select LCD pins and pin modes through the relevant IOCON registers
(Section 7.4.1).
4. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
5. The LCD clock divider is configured in the system configuration block
(Section 3.3.7.2) and the CLKSEL bit in the LCD_POL register (Section 11.7.3).
11.3 Introduction
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
274 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.4 Features
•
•
•
•
AHB bus master interface to access frame buffer.
Setup and control via a separate AHB slave interface.
Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4 or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320x200, 320x240,
640x200, 640x240, 640x480, 800x600, and 1024x768.
•
•
•
•
•
•
•
•
•
•
•
•
Hardware cursor support for single-panel displays.
15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.
1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
16 bpp true-color non-palettized, for color STN and TFT.
24 bpp true-color non-palettized, for color TFT.
Programmable timing for different display panels.
256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM.
Frame, line, and pixel clock signals.
AC bias signal for STN, data enable signal for TFT panels.
Supports little and big-endian, and Windows CE data formats.
LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
11.4.1 Programmable parameters
The following key display and controller parameters can be programmed:
•
•
•
•
•
•
•
•
•
•
•
•
•
UM10562
User manual
Horizontal front and back porch
Horizontal synchronization pulse width
Number of pixels per line
Vertical front and back porch
Vertical synchronization pulse width
Number of lines per panel
Number of pixel clocks per line
Hardware cursor control.
Signal polarity, active HIGH or LOW
AC panel bias
Panel clock frequency
Bits-per-pixel
Display type: STN monochrome, STN color, or TFT
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
275 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
•
•
•
•
STN 4 or 8-bit interface mode
STN dual or single panel mode
Little-endian, big-endian, or Windows CE mode
Interrupt generation event
11.4.2 Hardware cursor support
The hardware cursor feature reduces software overhead associated with maintaining a
cursor image in the LCD frame buffer.
Without this feature, software needed to:
• Save an image of the area under the next cursor position.
• Update the area with the cursor image.
• Repair the last cursor position with a previously saved image.
In addition, the LCD driver had to check whether the graphics operation had overwritten
the cursor, and correct it. With a cursor size of 64x64 and 24-bit color, each cursor move
involved reading and writing approximately 75 kB of data.
The hardware cursor removes the requirement for this management by providing a
completely separate image buffer for the cursor, and superimposing the cursor image on
the LCD output stream at the current cursor (X,Y) coordinate.
To move the hardware cursor, the software driver supplies a new cursor coordinate. The
frame buffer requires no modification. This significantly reduces software overhead.
The cursor image is held in the LCD controller in an internal 256x32-bit buffer memory.
11.4.3 Types of LCD panels supported
The LCD controller supports the following types of LCD panel:
•
•
•
•
•
Active matrix TFT panels with up to 24-bit bus interface.
Single-panel monochrome STN panels (4-bit and 8-bit bus interface).
Dual-panel monochrome STN panels (4-bit and 8-bit bus interface per panel).
Single-panel color STN panels, 8-bit bus interface.
Dual-panel color STN panels, 8-bit bus interface per panel.
11.4.4 TFT panels
TFT panels support one or more of the following color modes:
•
•
•
•
•
UM10562
User manual
1 bpp, palettized, 2 colors selected from available colors.
2 bpp, palettized, 4 colors selected from available colors.
4 bpp, palettized, 16 colors selected from available colors.
8 bpp, palettized, 256 colors selected from available colors.
12 bpp, direct 4:4:4 RGB.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
276 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
• 16 bpp, direct 5:5:5 RGB, with 1 bpp not normally used. This pixel is still output, and
can be used as a brightness bit to connect to the Least Significant Bit (LSB) of RGB
components of a 6:6:6 TFT panel.
• 16 bpp, direct 5:6:5 RGB.
• 24 bpp, direct 8:8:8 RGB, providing over 16 million colors.
Each 16-bit palette entry is composed of 5 bpp (RGB), plus a common intensity bit. This
provides better memory utilization and performance compared with a full 6 bpp structure.
The total number of colors supported can be doubled from 32K to 64K if the intensity bit is
used and applied to all three color components simultaneously.
Alternatively, the 16 signals can be used to drive a 5:6:5 panel with the extra bit only
applied to the green channel.
11.4.5 Color STN panels
Color STN panels support one or more of the following color modes:
•
•
•
•
•
1 bpp, palettized, 2 colors selected from 3375.
2 bpp, palettized, 4 colors selected from 3375.
4 bpp, palettized, 16 colors selected from 3375.
8 bpp, palettized, 256 colors selected from 3375.
16 bpp, direct 4:4:4 RGB, with 4 bpp not being used.
11.4.6 Monochrome STN panels
Monochrome STN panels support one or more of the following modes:
• 1 bpp, palettized, 2 gray scales selected from 15.
• 2 bpp, palettized, 4 gray scales selected from 15.
• 4 bpp, palettized, 16 gray scales selected from 15.
More than 4 bpp for monochrome panels can be programmed, but using these modes has
no benefit because the maximum number of gray scales supported on the display is 15.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
277 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.5 Pin description
The largest configuration for the LCD controller uses 31 pins. There are many variants
using as few as 10 pins for a monochrome STN panel. Pins are allocated in groups based
on the selected configuration. All LCD functions are shared with other chip functions. In
Table 204, only the LCD related portion of the pin name is shown.
Remark: To connect the LCD controller to necessary pins, see Section 7.3.
Table 204. LCD controller pins
Pin name
Type
Function
LCD_PWR
output
LCD panel power enable.
LCD_DCLK
output
LCD panel clock. Each level on this pin must be at least 1 PCLK in duration in order to be
sampled. The maximum frequency must therefore be less than PCLK/2.
LCD_ENAB_M
output
STN AC bias drive or TFT data enable output.
LCD_FP
output
Frame pulse (STN). Vertical synchronization pulse (TFT)
LCD_LE
output
Line end signal
LCD_LP
output
Line synchronization pulse (STN). Horizontal synchronization pulse (TFT)
LCD_VD[23:0]
output
LCD panel data. Bits used depend on the panel configuration.
LCD_CLKIN
input
Optional clock input.
11.5.1 Signal usage
The signals that are used for various display types are identified in the following sections.
11.5.1.1 Signals used for single panel STN displays
The signals used for single panel STN displays are shown in Table 205. UD refers to
upper panel data.
Table 205. Pins used for single panel STN displays
Pin name
4-bit Monochrome 8-bit Monochrome
(10 pins)
(14 pins)
Color
(14 pins)
LCD_PWR
Y
Y
Y
LCD_DCLK
Y
Y
Y
LCD_ENAB_M
Y
Y
Y
LCD_FP
Y
Y
Y
LCD_LE
Y
Y
Y
LCD_LP
Y
Y
Y
LCD_VD[3:0]
UD[3:0]
UD[3:0]
UD[3:0]
LCD_VD[7:4]
-
UD[7:4]
UD[7:4]
LCD_VD[23:8]
-
-
-
11.5.1.2 Signals used for dual panel STN displays
The signals used for dual panel STN displays are shown in Table 206. UD refers to upper
panel data, and LD refers to lower panel data.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
278 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 206. Pins used for dual panel STN displays
Pin name
4-bit Monochrome 8-bit Monochrome
(14 pins)
(22 pins)
Color
(22 pins)
LCD_PWR
Y
Y
Y
LCD_DCLK
Y
Y
Y
LCD_ENAB_M
Y
Y
Y
LCD_FP
Y
Y
Y
LCD_LE
Y
Y
Y
LCD_LP
Y
Y
Y
LCD_VD[3:0]
UD[3:0]
UD[3:0]
UD[3:0]
LCD_VD[7:4]
-
UD[7:4]
UD[7:4]
LCD_VD[11:8]
LD[3:0]
LD[3:0]
LD[3:0]
LCD_VD[15:12]
-
LD[7:4]
LD[7:4]
LCD_VD[23:16]
-
-
-
11.5.1.3 Signals used for TFT displays
The signals used for TFT displays are shown in Table 207.
Table 207. Pins used for TFT displays
Pin name
12-bit, 4:4:4
mode
16-bit, 5:6:5
mode
16-bit, 1:5:5:5
mode
(18 pins)
(22 pins)
(24 pins)
LCD_PWR
Y
Y
Y
Y
LCD_DCLK
Y
Y
Y
Y
LCD_ENAB_M
Y
Y
Y
Y
LCD_FP
Y
Y
Y
Y
LCD_LE
Y
Y
Y
Y
LCD_LP
Y
Y
Y
Y
LCD_VD[1:0]
-
-
-
RED[1:0]
LCD_VD[2]
-
-
Intensity
RED[2]
LCD_VD[3]
-
RED[0]
RED[0]
RED[3]
LCD_VD[7:4]
RED[3:0]
RED[4:1]
RED[4:1]
RED[7:4]
LCD_VD[9:8]
-
-
-
GREEN[1:0]
LCD_VD[10]
-
GREEN[0]
Intensity
GREEN[2]
LCD_VD[11]
-
GREEN[1]
GREEN[0]
GREEN[3]
LCD_VD[15:12]
GREEN[3:0]
GREEN[5:2]
GREEN[4:1]
GREEN[7:4]
LCD_VD[17:16]
-
-
-
BLUE[1:0]
LCD_VD[18]
-
-
Intensity
BLUE[2]
LCD_VD[19]
-
BLUE[0]
BLUE[0]
BLUE[3]
BLUE[3:0]
BLUE[4:1]
BLUE[4:1]
BLUE[7:4]
LCD_VD[23:20]
UM10562
User manual
24-bit
(30 pins)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
279 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.6 LCD controller functional description
The LCD controller performs translation of pixel-coded data into the required formats and
timings to drive a variety of single or dual panel monochrome and color LCDs.
Packets of pixel coded data are fed using the AHB interface, to two independent,
programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers.
The buffered pixel coded data is then unpacked using a pixel serializer.
Depending on the LCD type and mode, the unpacked data can represent:
• An actual true display gray or color value.
• An address to a 256x16 bit wide palette RAM gray or color value.
In the case of STN displays, either a value obtained from the addressed palette location,
or the true value is passed to the gray scaling generators. The hardware-coded gray scale
algorithm logic sequences the activity of the addressed pixels over a programmed number
of frames to provide the effective display appearance.
For TFT displays, either an addressed palette value or true color value is passed directly
to the output display drivers, bypassing the gray scaling algorithmic logic.
In addition to data formatting, the LCD controller provides a set of programmable display
control signals, including:
•
•
•
•
LCD panel power enable.
Pixel clock.
Horizontal and vertical synchronization pulses.
Display bias.
The LCD controller generates individual interrupts for:
•
•
•
•
Upper or lower panel DMA FIFO underflow.
Base address update signification.
Vertical compare.
Bus error.
There is also a single combined interrupt that is asserted when any of the individual
interrupts become active.
Figure 32 shows a simplified block diagram of the LCD controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
280 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
AHB
slave
interface
Timing
controller
Panel clock
generator
AHB Bus
Upper
panel
DMA
FIFO
AHB
master
interface
LCD control
signals
LCD panel
clock
LCDCLKIN
Input
FIFO
control
Pixel
serializer
RAM
palette
(128x32)
Upper
panel
formatter
Upper
panel
output
FIFO
Upper
STN
Lower
panel
formatter
Lower
panel
output
FIFO
Lower
STN
Gray
scaler
Lower
panel
DMA
FIFO
Hardware
Cursor
STN/TFT
data
select
FIFO underflow
AHB error
Interrupt
generation
LCD panel
data
Interrupt
Fig 32. LCD controller block diagram
11.6.1 AHB interfaces
The LCD controller includes two separate AHB interfaces. The first, an AHB slave
interface, is used primarily by the CPU to access control and data registers within the LCD
controller. The second, an AHB master interface, is used by the LCD controller for DMA
access to display data stored in memory elsewhere in the system. The LCD DMA
controller can only access the Peripheral SRAMs and the external memory.
11.6.1.1 AMBA AHB slave interface
The AHB slave interface connects the LCD controller to the AHB bus and provides CPU
accesses to the registers and palette RAM.
11.6.1.2 AMBA AHB master interface
The AHB master interface transfers display data from a selected slave (memory) to the
LCD controller DMA FIFOs. It can be configured to obtain data from the Peripheral
SRAMs, various types of off-chip static memory, or off-chip SDRAM.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
281 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single
DMA request. In single panel mode, the DMA FIFOs are filled up in a sequential fashion
from a single DMA request.
The inherent AHB master interface state machine performs the following functions:
• Loads the upper panel base address into the AHB address incrementer on
recognition of a new frame.
• Monitors both the upper and lower DMA FIFO levels and asserts a DMA request to
request display data from memory, filling them to above the programmed watermark.
the DMA request is reasserted when there are at least four locations available in
either FIFO (dual panel mode).
• Checks for 1 kB boundaries during fixed-length bursts, appropriately adjusting the
address in such occurrences.
• Generates the address sequences for fixed-length and undefined bursts.
• Controls the handshaking between the memory and DMA FIFOs. It inserts busy
cycles if the FIFOs have not completed their synchronization and updating sequence.
• Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single
DMA request.
• Asserts the a bus error interrupt if an error occurs during an active burst.
• Responds to retry commands by restarting the failed access. This introduces some
busy cycles while it re-synchronizes.
11.6.2 Dual DMA FIFOs and associated control logic
The pixel data accessed from memory is buffered by two DMA FIFOs that can be
independently controlled to cover single and dual-panel LCD types. Each FIFO is 16
words deep by 64 bits wide and can be cascaded to form an effective 32-Dword deep
FIFO in single panel mode.
Synchronization logic transfers the pixel data from the AHB clock domain to the LCD
controller clock domain. The water level marks in each FIFO are set such that each FIFO
requests data when at least four locations become available.
An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs
when they are empty (an underflow condition has occurred).
11.6.3 Pixel serializer
This block reads the 32-bit wide LCD data from the output port of the DMA FIFO and
extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The
LCD controller supports big-endian, little-endian, and Windows CE data formats.
Depending on the mode of operation, the extracted data can be used to point to a color or
gray scale value in the palette RAM or can actually be a true color value that can be
directly applied to an LCD panel input.
Table 208 through Table 210 show the structure of the data in each DMA FIFO word
corresponding to the endianness and bpp combinations. For each of the three supported
data formats, the required data for each panel display pixel must be extracted from the
data word.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
282 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 208. FIFO bits for Little-endian Byte, Little-endian Pixel order
UM10562
User manual
FIFO bit
1 bpp
0
p0
1
p1
2
p2
3
p3
4
p4
5
p5
6
p6
7
p7
8
p8
9
p9
10
p10
11
p11
12
p12
13
p13
14
p14
15
p15
16
p16
17
p17
18
p18
19
p19
20
p20
21
p21
22
p22
23
p23
24
p24
25
p25
26
p26
27
p27
28
p28
29
p29
30
p30
31
p31
2 bpp
4 bpp
8 bpp
16 bpp
24 bpp
p0
p0
p1
p0
p2
p1
p3
p0
p4
p2
p5
p1
p0
p6
p3
p7
p8
p4
p9
p2
p10
p5
p11
p1
p12
p6
p13
p3
p14
p7
p15
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
283 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 209. FIFO bits for Big-endian Byte, Big-endian Pixel order
FIFO bit
UM10562
User manual
1 bpp
0
p31
1
p30
2
p29
3
p28
4
p27
5
p26
6
p25
7
p24
8
p23
9
p22
10
p21
11
p20
12
p19
13
p18
14
p17
15
p16
16
p15
17
p14
18
p13
19
p12
20
p11
21
p10
22
p9
23
p8
24
p7
25
p6
26
p5
27
p4
28
p3
29
p2
30
p1
31
p0
2 bpp
4 bpp
8 bpp
16 bpp
24 bpp
p15
p7
p14
p3
p13
p6
p12
p1
p11
p5
p10
p2
p0
p9
p4
p8
p7
p3
p6
p1
p5
p2
p4
p0
p3
p1
p2
p0
p1
p0
p0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
284 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 210. FIFO bits for Little-endian Byte, Big-endian Pixel order
FIFO bit
1 bpp
0
p7
1
p6
2
p5
3
p4
4
p3
5
p2
6
p1
7
p0
8
p15
9
p14
10
p13
11
p12
12
p11
13
p10
14
p9
15
p8
16
p23
17
p22
18
p21
19
p20
20
p19
21
p18
22
p17
23
p16
24
p31
25
p30
26
p29
27
p28
28
p27
29
p26
30
p25
31
p24
2 bpp
4 bpp
8 bpp
16 bpp
24 bpp
p3
p1
p2
p0
p1
p0
p0
p0
p7
p3
p6
p1
p0
p5
p2
p4
p11
p5
p10
p2
p9
p4
p8
p1
p15
p7
p14
p3
p13
p6
p12
Table 211 shows the structure of the data in each DMA FIFO word in RGB mode.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
285 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 211. RGB mode data formats
FIFO data 24-bit RGB
16-bit (1:5:5:5 RGB) 16-bit (5:6:5 RGB)
16-bit (4:4:4 RGB)
0
p0, Red 0
p0, Red 0
p0, Red 0
p0, Red 0
1
p0, Red 1
p0, Red 1
p0, Red 1
p0, Red 1
2
p0, Red 2
p0, Red 2
p0, Red 2
p0, Red 2
3
p0, Red 3
p0, Red 3
p0, Red 3
p0, Red 3
4
p0, Red 4
p0, Red 4
p0, Red 4
p0, Green 0
5
p0, Red 5
p0, Green 0
p0, Green 0
p0, Green 1
6
p0, Red 6
p0, Green 1
p0, Green 1
p0, Green 2
7
p0, Red 7
p0, Green 2
p0, Green 2
p0, Green 3
8
p0, Green 0
p0, Green 3
p0, Green 3
p0, Blue 0
9
p0, Green 1
p0, Green 4
p0, Green 4
p0, Blue 1
10
p0, Green 2
p0, Blue 0
p0, Green 5
p0, Blue 2
11
p0, Green 3
p0, Blue 1
p0, Blue 0
p0, Blue 3
12
p0, Green 4
p0, Blue 2
p0, Blue 1
-
13
p0, Green 5
p0, Blue 3
p0, Blue 2
-
14
p0, Green 6
p0, Blue 4
p0, Blue 3
-
15
p0, Green 7
p0 intensity bit
p0, Blue 4
-
16
p0, Blue 0
p1, Red 0
p1, Red 0
p1, Red 0
17
p0, Blue 1
p1, Red 1
p1, Red 1
p1, Red 1
18
p0, Blue 2
p1, Red 2
p1, Red 2
p1, Red 2
19
p0, Blue 3
p1, Red 3
p1, Red 3
p1, Red 3
20
p0, Blue 4
p1, Red 4
p1, Red 4
p1, Green 0
21
p0, Blue 5
p1, Green 0
p1, Green 0
p1, Green 1
22
p0, Blue 6
p1, Green 1
p1, Green 1
p1, Green 2
23
p0, Blue 7
p1, Green 2
p1, Green 2
p1, Green 3
24
-
p1, Green 3
p1, Green 3
p1, Blue 0
25
-
p1, Green 4
p1, Green 4
p1, Blue 1
26
-
p1, Blue 0
p1, Green 5
p1, Blue 2
27
-
p1, Blue 1
p1, Blue 0
p1, Blue 3
28
-
p1, Blue 2
p1, Blue 1
-
29
-
p1, Blue 3
p1, Blue 2
-
30
-
p1, Blue 4
p1, Blue 3
-
31
-
p1 intensity bit
p1, Blue 4
-
11.6.4 RAM palette
The RAM-based palette is a 256 x 16 bit dual-port RAM physically structured as 128 x 32
bits. Two entries can be written into the palette from a single word write access. The Least
Significant Bit (LSB) of the serialized pixel data selects between upper and lower halves of
the palette RAM. The half that is selected depends on the byte ordering mode. In
little-endian mode, setting the LSB selects the upper half, but in big-endian mode, the
lower half of the palette is selected.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
286 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Pixel data values can be written and verified through the AHB slave interface. For
information on the supported colors, refer to the section on the related panel type earlier in
this chapter.
The palette RAM is a dual port RAM with independent controls and addresses for each
port. Port1 is used as a read/write port and is connected to the AHB slave interface. The
palette entries can be written and verified through this port. Port2 is used as a read-only
port and is connected to the unpacker and gray scaler. For color modes of less than 16
bpp, the palette enables each pixel value to be mapped to a 16-bit color:
• For TFT displays, the 16-bit value is passed directly to the pixel serializer.
• For STN displays, the 16-bit value is first converted by the gray scaler.
Table 212 shows the bit representation of the palette data. The palette 16-bit output uses
the TFT 1:5:5:5 data format. In 16 and 24 bpp TFT mode, the palette is bypassed and the
output of the pixel serializer is used as the TFT panel data.
Table 212. Palette data storage for TFT modes.
Bit(s)
Name
Description
Name
Description
(RGB format)
(RGB format)
(BGR format)
(BGR format)
4:0
R[4:0]
Red palette data
B[4:0]
Blue palette data
9:5
G[4:0]
Green palette data
G[4:0]
Green palette data
14:10
B[4:0]
Blue palette data
R[4:0]
Red palette data
15
I
Intensity / unused
I
Intensity / unused
20:16
R[4:0]
Red palette data
B[4:0]
Blue palette data
25:21
G[4:0]
Green palette data
G[4:0]
Green palette data
30:26
B[4:0]
Blue palette data
R[4:0]
Red palette data
31
I
Intensity / unused
I
Intensity / unused
The red and blue pixel data can be swapped to support BGR data format using a control
register bit 8 (BGR). See the LCD_CTRL register description for more information.
Table 213 shows the bit representation of the palette data for the STN color modes.
Table 213. Palette data storage for STN color modes.
Bit(s)
UM10562
User manual
Name
Description
Name
Description
(RGB format)
(RGB format)
(BGR format)
(BGR format)
0
R[0]
Unused
B[0]
Unused
4:1
R[4:1]
Red palette data
B[4:1]
Blue palette data
5
G[0]
Unused
G[0]
Unused
9:6
G[4:1]
Green palette data
G[4:1]
Green palette data
10
B[0]
Unused
R[0]
Unused
14:11
B[4:1]
Blue palette data
R[4:1]
Red palette data
15
I
Unused
I
Unused
16
-
Unused
-
Unused
20:17
R[3:0]
Red palette data
B[3:0]
Blue palette data
21
-
Unused
-
Unused
25:22
G[3:0]
Green palette data
G[3:0]
Green palette data
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
287 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 213. Palette data storage for STN color modes.
Bit(s)
Name
Description
Name
Description
(RGB format)
(RGB format)
(BGR format)
(BGR format)
26
-
Unused
-
Unused
30:27
B[3:0]
Blue palette data
R[3:0]
Red palette data
31
-
Unused
-
Unused
For monochrome STN mode, only the red palette field bits [4:1] are used. However, in
STN color mode the green and blue [4:1] are also used. Only 4 bits per color are used,
because the gray scaler only supports 16 different shades per color.
Table 214 shows the bit representation of the palette data for the STN monochrome
mode.
Table 214. Palette data storage for STN monochrome mode.
Bit(s)
Name
Description
0
-
Unused
4:1
Y[3:0]
Intensity data
16:5
-
Unused
20:17
Y[3:0]
Intensity data
31:21
-
Unused
11.6.5 Hardware cursor
The hardware cursor is an integral part of the LCD controller. It uses the LCD timing
module to provide an indication of the current scan position coordinate, and intercepts the
pixel stream between the palette logic and the gray scale/output multiplexer.
All cursor programming registers are accessed through the LCD slave interface. This also
provides a read/write port to the cursor image RAM.
11.6.5.1 Cursor operation
The hardware cursor is contained in a dual port RAM. It is programmed by software
through the AHB slave interface. The AHB slave interface also provides access to the
hardware cursor control registers. These registers enable you to modify the cursor
position and perform various other functions.
When enabled, the hardware cursor uses the horizontal and vertical synchronization
signals, along with a pixel clock enable and various display parameters to calculate the
current scan coordinate.
When the display point is inside the bounds of the cursor image, the cursor replaces
frame buffer pixels with cursor pixels.
When the last cursor pixel is displayed, an interrupt is generated that software can use as
an indication that it is safe to modify the cursor image. This enables software controlled
animations to be performed without flickering for frame synchronized cursors.
11.6.5.2 Cursor sizes
Two cursor sizes are supported, as shown in Table 215.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
288 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 215. Palette data storage for STN monochrome mode.
X Pixels
Y Pixels
Bits per pixel
Words per line
Words in cursor image
32
32
2
2
64
64
64
2
4
256
11.6.5.3 Cursor movement
The following descriptions assume that both the screen and cursor origins are at the top
left of the visible screen (the first visible pixel scanned each frame). Figure 33 shows how
each pixel coordinate is assumed to be the top left corner of the pixel.
CRSR_XY(X)
CRSR_XY(Y)
(0,0)
Fig 33. Cursor movement
11.6.5.4 Cursor XY positioning
The CRSR_XY register controls the cursor position on the cursor overlay (see Cursor XY
Position register). This provides separate fields for X and Y ordinates.
The CRSR_CFG register (see Cursor Configuration register) provides a FrameSync bit
controlling the visible behavior of the cursor.
With FrameSync inactive, the cursor responds immediately to any change in the
programmed CRSR_XY value. Some transient smearing effects may be visible if the
cursor is moved across the LCD scan line.
With FrameSync active, the cursor only updates its position after a vertical
synchronization has occurred. This provides clean cursor movement, but the cursor
position only updates once a frame.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
289 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.6.5.5 Cursor clipping
The CRSR_XY register (see Cursor XY Position register) is programmed with positive
binary values that enable the cursor image to be located anywhere on the visible screen
image. The cursor image is clipped automatically at the screen limits when it extends
beyond the screen image to the right or bottom (see X1,Y1 in Figure 34). The checked
pattern shows the visible portion of the cursor.
Because the CRSR_XY register values are positive integers, to emulate cursor clipping
on the left and top of screen, a Clip Position register, CRSR_CLIP, is provided. This
controls which point of the cursor image is positioned at the CRSR_CLIP coordinate. For
clipping functions on the Y axis, CRSR_XY(X) is zero, and Clip(X) is programmed to
provide the offset into the cursor image (X2 and X3). The equivalent function is provided
to clip on the X axis at the top of the display (Y2).
For cursors that are not clipped at the X=0 or Y=0 lines, program the Clip Position register
X and Y fields with zero to display the cursor correctly. See Clip(X4,Y4) for the effect of
incorrect programming.
Cursor(X5)
Clip(X3)
Cursor(Y1)
Clip(Y4)
Cursor(Y5)
Clip(Y2)
Clip(X2)
Clip(X4)
Cursor(X1)
Fig 34. Cursor clipping
11.6.5.6 Cursor image format
The LCD frame buffer supports three packing formats, but the hardware cursor image
requirement has been simplified to support only LBBP. This is little-endian byte,
big-endian pixel for Windows CE mode.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
290 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
The Image RAM start address is offset by 0x800 from the LCD base address, as shown in
the register description in this chapter.
The displayed cursor coordinate system is expressed in terms of (X,Y). 64 x 64 is an
extension of the 32 x 32 format shown in Figure 35.
TOP
(0, 0)
(1, 0)
(2, 0)
(29, 0)
(30, 0)
(31, 0)
(0, 1)
(1, 1)
(2, 1)
(29, 1)
(30, 1)
(31, 1)
(0, 2)
(1, 2)
(2, 2)
(29, 2)
(30, 2)
(31, 2)
LEFT
RIGHT
(0, 29)
(1, 29)
(2, 29)
(29, 29)
(30, 29)
(31, 29)
(0, 30)
(1, 30)
(2, 30)
(29, 30)
(30, 30)
(31, 30)
(0, 31)
(1, 31)
(2, 31)
(29, 31)
(30, 31)
(31, 31)
BOTTOM
Fig 35. Cursor image format
32 by 32 pixel format
Four cursors are held in memory, each with the same pixel format. Table 216 lists the
base addresses for the four cursors.
Table 216. Addresses for 32 x 32 cursors
Address
Description
0x2008 8800
Cursor 0 start address.
0x2008 8900
Cursor 1 start address.
0x2008 8A00
Cursor 2 start address.
0x2008 8B00
Cursor 3 start address.
Table 217 shows the buffer to pixel mapping for Cursor 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
291 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 217. Buffer to pixel mapping for 32 x 32 pixel cursor format
Offset into cursor memory
Data bits
0
4
(8 * y)
(8 * y) +4
F8
FC
1:0
(3, 0)
(19, 0)
(3, y)
(19, y)
(3, 31)
(19, 31)
3:2
(2, 0)
(18, 0)
(2, y)
(18, y)
(2, 31)
(18, 31)
5:4
(1, 0)
(17, 0)
(1, y)
(17, y)
(1, 31)
(17, 31)
7:6
(0, 0)
(16, 0)
(0, y)
(16, y)
(0, 31)
(16, 31)
9:8
(7, 0)
(23, 0)
(7, y)
(23, y)
(7, 31)
(23, 31)
11:10
(6, 0)
(22, 0)
(6, y)
(22, y)
(6, 31)
(22, 31)
13:12
(5, 0)
(21, 0)
(5, y)
(21, y)
(5, 31)
(21, 31)
15:14
(4, 0)
(20, 0)
(4, y)
(20, y)
(4, 31)
(20, 31)
17:16
(11, 0)
(27, 0)
(11, y)
(27, y)
(11, 31)
(27, 31)
19:18
(10, 0)
(26, 0)
(10, y)
(26, y)
(10, 31)
(26, 31)
21:20
(9, 0)
(25, 0)
(9, y)
(25, y)
(9, 31)
(25, 31)
23:22
(8, 0)
(24, 0)
(8, y)
(24, y)
(8, 31)
(24, 31)
25:24
(15, 0)
(31, 0)
(15, y)
(31, y)
(15, 31)
(31, 31)
27:26
(14, 0)
(30, 0)
(14, y)
(30, y)
(14, 31)
(30, 31)
29:28
(13, 0)
(29, 0)
(13, y)
(29, y)
(13, 31)
(29, 31)
31:30
(12, 0)
(28, 0)
(12, y)
(28, y)
(12, 31)
(28,31)
64 by 64 pixel format
Only one cursor fits in the memory space in 64 x 64 mode, as detailed in Table 218.
Table 218. Buffer to pixel mapping for 64 x 64 pixel cursor format
Offset into cursor memory
Data bits
0
4
8
12
(16 * y)
(16 * y) +4
(16 * y) + 8
(16 * y) + 12
FC
1:0
(3, 0)
(19, 0)
(35, 0)
(51, 0)
(3, y)
(19, y)
(35, y)
(51, y)
(51, 63)
3:2
(2, 0)
(18, 0)
(34, 0)
(50, 0)
(2, y)
(18, y)
(34, y)
(50, y)
(50, 63)
5:4
(1, 0)
(17, 0)
(33, 0)
(49, 0)
(1, y)
(17, y)
(33, y)
(49, y)
(49, 63)
7:6
(0, 0)
(16, 0)
(32, 0)
(48, 0)
(0, y)
(16, y)
(32, y)
(48, y)
(48, 63)
9:8
(7, 0)
(23, 0)
(39, 0)
(55, 0)
(7, y)
(23, y)
(39, y)
(55, y)
(55, 63)
11:10
(6, 0)
(22, 0)
(38, 0)
(54, 0)
(6, y)
(22, y)
(38, y)
(54, y)
(54, 63)
13:12
(5, 0)
(21, 0)
(37, 0)
(53, 0)
(5, y)
(21, y)
(37, y)
(53, y)
(53, 63)
15:14
(4, 0)
(20, 0)
(36, 0)
(52, 0)
(4, y)
(20, y)
(36, y)
(52, y)
(52, 63)
17:16
(11, 0)
(27, 0)
(43, 0)
(59, 0)
(11, y)
(27, y)
(43, y)
(59, y)
(59, 63)
19:18
(10, 0)
(26, 0)
(42, 0)
(58, 0)
(10, y)
(26, y)
(42, y)
(58, y)
(58, 63)
21:20
(9, 0)
(25, 0)
(41, 0)
(57, 0)
(9, y)
(25, y)
(41, y)
(57, y)
(57, 63)
23:22
(8, 0)
(24, 0)
(40, 0)
(56, 0)
(8, y)
(24, y)
(40, y)
(56, y)
(56, 63)
25:24
(15, 0)
(31, 0)
(47, 0)
(63, 0)
(15, y)
(31, y)
(47, y)
(63, y)
(63, 63)
27:26
(14, 0)
(30, 0)
(46, 0)
(62, 0)
(14, y)
(30, y)
(46, y)
(62, y)
(62, 63)
29:28
(13, 0)
(29, 0)
(45, 0)
(61, 0)
(13, y)
(29, y)
(45, y)
(61, y)
(61, 63)
31:30
(12, 0)
(28, 0)
(44, 0)
(60, 0)
(12, y)
(28, y)
(44, y)
(60, y)
(60, 63)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
292 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Cursor pixel encoding
Each pixel of the cursor requires two bits of information. These are interpreted as Color0,
Color1, Transparent, and Transparent inverted.
In the coding scheme, bit 1 selects between color and transparent (AND mask) and bit 0
selects variant (XOR mask).
Table 219 shows the pixel encoding bit assignments.
Table 219. Pixel encoding
Value
Description
00
Color0. The cursor color is displayed according to the Red-Green-Blue (RGB) value programmed into the
CRSR_PAL0 register.
01
Color1. The cursor color is displayed according to the RGB value programmed into the CRSR_PAL1 register.
10
Transparent. The cursor pixel is transparent, so is displayed unchanged. This enables the visible cursor to assume
shapes that are not square.
11
Transparent inverted. The cursor pixel assumes the complementary color of the frame pixel that is displayed. This
can be used to ensure that the cursor is visible regardless of the color of the frame buffer image.
11.6.6 Gray scaler
A patented gray scale algorithm drives monochrome and color STN panels. This provides
15 gray scales for monochrome displays. For STN color displays, the three color
components (RGB) are gray scaled simultaneously. This results in 3375 (15x15x15)
colors being available. The gray scaler transforms each 4-bit gray value into a sequence
of activity-per-pixel over several frames, relying to some degree on the display
characteristics, to give the representation of gray scales and color.
11.6.7 Upper and lower panel formatters
Formatters are used in STN mode to convert the gray scaler output to a parallel format as
required by the display. For monochrome displays, this is either 4 or 8 bits wide, and for
color displays, it is 8 bits wide. Table 220 shows a color display driven with 2 2/3 pixels
worth of data in a repeating sequence.
Table 220. Color display driven with 2 2/3 pixel data
Byte
CLD[7]
CLD[6]
CLD[5]
CLD[4]
CLD[3]
CLD[2]
CLD[1]
CLD[0]
0
P2[Green]
P2[Red]
P1[Blue]
P1[Green]
P1[Red]
P0[Blue]
P0[Green]
P0[Red]
1
P5[Red]
P4q[Blue]
P4[Green]
P4[Red]
P3[Blue]
P3[Green]
P3[Red]
P2[Blue]
2
P7[Blue]
P7[Green]
P7[Red]
P6[Blue]
P6[Green]
P6[Red]
P5[Blue]
P5[Green]
Each formatter consists of three 3-bit (RGB) shift left registers. RGB pixel data bit values
from the gray scaler are concurrently shifted into the respective registers. When enough
data is available, a byte is constructed by multiplexing the registered data to the correct bit
position to satisfy the RGB data pattern of LCD panel. The byte is transferred to the 3-byte
FIFO, which has enough space to store eight color pixels.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
293 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.6.8 Panel clock generator
The output of the panel clock generator block is the panel clock, pin LCD_DCLK. The
panel clock can be based on either the peripheral clock for the LCD block or the external
clock input for the LCD, pin LCD_CLKIN. Whichever source is selected can be divided
down in order to produce the internal LCD clock, LCDCLK.
The panel clock generator can be programmed to output the LCD panel clock in the range
of LCDCLK/2 to LCDCLK/1025 to match the bpp data rate of the LCD panel being used.
The CLKSEL bit in the LCD_POL register determines whether the base clock used is
CCLK or the LCD_CLKIN pin.
11.6.9 Timing controller
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides the panel bias and enable signals. These timings are
all register-programmable.
11.6.10 STN and TFT data select
Support is provided for passive Super Twisted Nematic (STN) and active Thin Film
Transistor (TFT) LCD display types:
11.6.10.1 STN displays
STN display panels require algorithmic pixel pattern generation to provide pseudo gray
scaling on monochrome displays, or color creation on color displays.
11.6.10.2 TFT displays
TFT display panels require the digital color value of each pixel to be applied to the display
data inputs.
11.6.11 Interrupt generation
Four interrupts are generated by the LCD controller, and a single combined interrupt. The
four interrupts are:
•
•
•
•
Master bus error interrupt.
Vertical compare interrupt.
Next base address update interrupt.
FIFO underflow interrupt.
Each of the four individual maskable interrupts is enabled or disabled by changing the
mask bits in the LCD_INT_MSK register. These interrupts are also combined into a single
overall interrupt, which is asserted if any of the individual interrupts are both asserted and
unmasked. Provision of individual outputs in addition to a combined interrupt output
enables use of either a global interrupt service routine, or modular device drivers to
handle interrupts.
The status of the individual interrupt sources can be read from the LCD_INTRAW register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
294 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.6.11.1 Master bus error interrupt
The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it. When the respective interrupt service routine is complete, the
master bus error interrupt may be cleared by writing a 1 to the BERIC bit in the
LCD_INTCLR register. This action releases the master interface from its ERROR state to
the start of FRAME state, and enables fresh frame of data display to be initiated.
11.6.11.2 Vertical compare interrupt
The vertical compare interrupt asserts when one of four vertical display regions, selected
using the LCD_CTRL register, is reached. The interrupt can be made to occur at the start
of:
•
•
•
•
Vertical synchronization.
Back porch.
Active video.
Front porch.
The interrupt may be cleared by writing a 1 to the VcompIC bit in the LCD_INTCLR
register.
11.6.11.2.1 Next base address update interrupt
The LCD next base address update interrupt asserts when either the LCDUPBASE or
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE registers with new frame base addresses if required.
The interrupt can be cleared by writing a 1 to the LNBUIC bit in the LCD_INTCLR register
11.6.11.2.2 FIFO underflow interrupt
The FIFO underflow interrupt asserts when internal data is requested from an empty DMA
FIFO. Internally, upper and lower panel DMA FIFO underflow interrupt signals are
generated.
The interrupt can be cleared by writing a 1 to the FUFIC bit in the LCD_INTCLR register.
11.6.12 LCD power-up and power-down sequence
The LCD controller requires the following power-up sequence to be performed:
1. When power is applied, the following signals are held LOW:
•
•
•
•
•
•
UM10562
User manual
LCD_LP
LCD_DCLK
LCD_FP
LCD_ENAB_M
LCD_VD[23:0]
LCD_LE
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
295 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the LCD_CTRL register.
This enables the following signals into their active states:
•
•
•
•
•
LCD_LP
LCD_DCLK
LCD_FP
LCD_ENAB_M
LCD_LE
The LCD_VD[23:0] signals remain in an inactive state.
3. When the signals in step 2 have stabilized, the contrast voltage (not controlled or
supplied by the LCD controller) is applied to the LCD panel.
4. If required, a software or hardware timer can be used to provide the minimum display
specific delay time between application of the control signals and power to the panel
display. On completion of the time interval, power is applied to the panel by writing a 1 to
the LcdPwr bit within the LCD_CTRL register that, in turn, sets the LCD_PWR signal high
and enables the LCD_VD[23:0] signals into their active states. The LCD_PWR signal is
intended to be used to gate the power to the LCD panel.
The power-down sequence is the reverse of the above four steps and must be strictly
followed, this time, writing the respective register bits with 0.
Figure 36 shows the power-up and power-down sequences.
LCD on sequence
LCD off sequence
Minimum 0 ms
Minimum 0 ms
LCD Power
Minimum 0 ms
Minimum 0 ms
LCDLP, LCDCP,
LCDFP, LCDAC,
LCDLE
Contrast Voltage
LCDPWR,
LCD[23:0]
Display specific delay
Display specific delay
Fig 36. Power-up and power-down sequences
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
296 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7 Register description
For LCD configuration and clocking control, see Table 34.
Table 221. Register overview: LCD controller (base address 0x2008 8000)
Name
Access Address offset
Description
Reset Table
value [1]
TIMH
R/W
0x000
Horizontal Timing Control register
0
222
TIMV
R/W
0x004
Vertical Timing Control register
0
223
POL
R/W
0x008
Clock and Signal Polarity Control register
0
224
LE
R/W
0x00C
Line End Control register
0
225
UPBASE
R/W
0x010
Upper Panel Frame Base Address register
0
226
LPBASE
R/W
0x014
Lower Panel Frame Base Address register
0
227
CTRL
R/W
0x018
LCD Control register
0
228
INTMSK
R/W
0x01C
Interrupt Mask register
0
229
INTRAW
RO
0x020
Raw Interrupt Status register
0
230
INTSTAT
RO
0x024
Masked Interrupt Status register
0
231
INTCLR
WO
0x028
Interrupt Clear register
-
232
UPCURR
RO
0x02C
Upper Panel Current Address Value register
0
233
LPCURR
RO
0x030
Lower Panel Current Address Value register
0
234
PAL0
R/W
0x200
256x16-bit Color Palette registers
0
235
...
to
PAL127
0x3FC
256x16-bit Color Palette registers
0
235
0x800
Cursor Image registers
0
236
Cursor Image registers
0
236
CRSR_IMG0
R/W
...
to
CRSR_IMG255
0xBFC
CRSR_CTRL
R/W
0xC00
Cursor Control register
0
237
CRSR_CFG
R/W
0xC04
Cursor Configuration register
0
238
CRSR_PAL0
R/W
0xC08
Cursor Palette register 0
0
239
CRSR_PAL1
R/W
0xC0C
Cursor Palette register 1
0
240
CRSR_XY
R/W
0xC10
Cursor XY Position register
0
241
CRSR_CLIP
R/W
0xC14
Cursor Clip Position register
0
242
CRSR_INTMSK
R/W
0xC20
Cursor Interrupt Mask register
0
243
CRSR_INTCLR
WO
0xC24
Cursor Interrupt Clear register
-
244
CRSR_INTRAW
RO
0xC28
Cursor Raw Interrupt Status register
0
245
CRSR_INTSTAT
RO
0xC2C
Cursor Masked Interrupt Status register
0
246
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
297 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.1 Horizontal Timing register
The LCD_TIMH register controls the Horizontal Synchronization pulse Width (HSW), the
Horizontal Front Porch (HFP) period, the Horizontal Back Porch (HBP) period, and the
Pixels-Per-Line (PPL).
Table 222. Horizontal Timing register (TIMH, address 0x2008 8000) bit description
Bits
Symbol
Description
Reset
value
1:0
-
Reserved. Read value is undefined, only zero should be written.
-
7:2
PPL
Pixels-per-line. The PPL bit field specifies the number of pixels in each line or row of the screen.
PPL is a 6-bit value that represents between 16 and 1024 pixels per line. PPL counts the
number of pixel clocks that occur before the HFP is applied.
0
Program the value required divided by 16, minus 1. Actual pixels-per-line = 16 * (PPL + 1). For
example, to obtain 320 pixels per line, program PPL as (320/16) -1 = 19.
15:8
HSW
Horizontal synchronization pulse width. The 8-bit HSW field specifies the pulse width of the line
clock in passive mode, or the horizontal synchronization pulse in active mode. Program with
desired value minus 1.
0
23:16
HFP
Horizontal front porch. The 8-bit HFP field sets the number of pixel clock intervals at the end of
each line or row of pixels, before the LCD line clock is pulsed. When a complete line of pixels is
transmitted to the LCD driver, the value in HFP counts the number of pixel clocks to wait before
asserting the line clock. HFP can generate a period of 1-256 pixel clock cycles. Program with
desired value minus 1.
0
31:24
HBP
Horizontal back porch. The 8-bit HBP field is used to specify the number of pixel clock periods
inserted at the beginning of each line or row of pixels. After the line clock for the previous line
has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting
the next display line. HBP can generate a delay of 1-256 pixel clock cycles. Program with
desired value minus 1.
0
11.7.1.1 Horizontal timing restrictions
DMA requests new data at the start of a horizontal display line. Some time must be
allowed for the DMA transfer and for data to propagate down the FIFO path in the LCD
interface. The data path latency forces some restrictions on the usable minimum values
for horizontal porch width in STN mode. The minimum values are HSW = 2 and HBP = 2.
Single panel mode:
•
•
•
•
HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
Panel Clock Divisor (PCD) = 1 (LCDCLK / 3)
Dual panel mode:
•
•
•
•
UM10562
User manual
HSW = 3 pixel clock cycles
HBP = 5 pixel clock cycles
HFP = 5 pixel clock cycles
PCD = 5 (LCDCLK / 7)
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
298 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10,
data does not corrupt for PCD = 4, the minimum value.
11.7.2 Vertical Timing register
The LCD_TIMV register controls the Vertical Synchronization pulse Width (VSW), the
Vertical Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the
Lines-Per-Panel (LPP).
Table 223. Vertical Timing register (TIMV, address 0x2008 8004) bit description
Bits
Symbol Description
Reset
value
9:0
LPP
Lines per panel. This is the number of active lines per screen. The LPP field specifies the total
number of lines or rows on the LCD panel being controlled. LPP is a 10-bit value allowing
between 1 and 1024 lines. Program the register with the number of lines per LCD panel, minus 1.
For dual panel displays, program the register with the number of lines on each of the upper and
lower panels.
0
15:10
VSW
Vertical synchronization pulse width. This is the number of horizontal synchronization lines. The
6-bit VSW field specifies the pulse width of the vertical synchronization pulse. Program the
register with the number of lines required, minus one.
0
The number of horizontal synchronization lines must be small (for example, program to zero) for
passive STN LCDs. The higher the value the worse the contrast on STN LCDs.
23:16
VFP
Vertical front porch. This is the number of inactive lines at the end of a frame, before the vertical
synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end
of each frame. When a complete frame of pixels is transmitted to the LCD display, the value in
VFP is used to count the number of line clock periods to wait.
0
After the count has elapsed, the vertical synchronization signal, LCD_FP, is asserted in active
mode, or extra line clocks are inserted as specified by the VSW bit-field in passive mode. VFP
generates 0–255 line clock cycles. Program to zero on passive displays for improved contrast.
31:24
VBP
UM10562
User manual
Vertical back porch. This is the number of inactive lines at the start of a frame, after the vertical
synchronization period. The 8-bit VBP field specifies the number of line clocks inserted at the
beginning of each frame. The VBP count starts immediately after the vertical synchronization
signal for the previous frame has been negated for active mode, or the extra line clocks have
been inserted as specified by the VSW bit field in passive mode. After this has occurred, the count
value in VBP sets the number of line clock periods inserted before the next frame. VBP generates
0 to 255 extra line clock cycles. Program to zero on passive displays for improved contrast.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
299 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.3 Clock and Signal Polarity register
The LCD_POL register controls various details of clock timing and signal polarity.
Table 224. Clock and Signal Polarity register (POL, address 0x2008 8008) bit description
Bits
Symbol
Description
Reset
value
4:0
PCD_LO Lower five bits of panel clock divisor. The ten-bit PCD field, comprising PCD_HI (bits 31:27 of this
register) and PCD_LO, is used to derive the LCD panel clock frequency LCD_DCLK from the
input clock, LCD_DCLK = LCDCLK/(PCD+2).
0
For monochrome STN displays with a 4 or 8-bit interface, the panel clock is a factor of four and
eight down from the actual individual pixel clock rate. For color STN displays, 22/3 pixels are
output per LCD_DCLK cycle, so the panel clock is 0.375 times the pixel rate.
For TFT displays, the pixel clock divider can be bypassed by setting the BCD bit in this register.
Note: data path latency forces some restrictions on the usable minimum values for the panel
clock divider in STN modes:
Single panel color mode, PCD = 1 (LCD_DCLK = LCDCLK/3).
Dual panel color mode, PCD = 4 (LCD_DCLK = LCDCLK/6).
Single panel monochrome 4-bit interface mode, PCD = 2(LCD_DCLK = LCDCLK/4).
Dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface
mode, PCD = 6(LCD_DCLK = LCDCLK/8).
Dual panel monochrome 8-bit interface mode, PCD = 14(LCD_DCLK = LCDCLK/16).
5
CLKSEL Clock Select. This bit controls the selection of the source for LCDCLK.
0
0 = the clock source for the LCD block is CCLK.
1 = the clock source for the LCD block is LCD_CLKIN (external clock input for the LCD).
10:6
ACB
11
IVS
AC bias pin frequency. The AC bias pin frequency is only applicable to STN displays. These
require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge
accumulation. Program this field with the required value minus one to apply the number of line
clocks between each toggle of the AC bias pin, LCD_ENAB_M. This field has no effect if the LCD
is operating in TFT mode, when the LCD_ENAB_M pin is used as a data enable signal.
0
Invert vertical synchronization. The IVS bit inverts the polarity of the LCD_FP signal.
0
0 = LCD_FP pin is active HIGH and inactive LOW.
1 = LCD_FP pin is active LOW and inactive HIGH.
12
IHS
Invert horizontal synchronization. The IHS bit inverts the polarity of the LCD_LP signal.
0
0 = LCD_LP pin is active HIGH and inactive LOW.
1 = LCD_LP pin is active LOW and inactive HIGH.
13
IPC
Invert panel clock. The IPC bit selects the edge of the panel clock on which pixel data is driven
out onto the LCD data lines.
0
0 = Data is driven on the LCD data lines on the rising edge of LCD_DCLK.
1 = Data is driven on the LCD data lines on the falling edge of LCD_DCLK.
14
IOE
Invert output enable. This bit selects the active polarity of the output enable signal in TFT mode.
In this mode, the LCD_ENAB_M pin is used as an enable that indicates to the LCD panel when
valid display data is available. In active display mode, data is driven onto the LCD data lines at
the programmed edge of LCD_DCLK when LCD_ENAB_M is in its active state.
0
0 = LCD_ENAB_M output pin is active HIGH in TFT mode.
1 = LCD_ENAB_M output pin is active LOW in TFT mode.
15
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
300 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 224. Clock and Signal Polarity register (POL, address 0x2008 8008) bit description
Bits
Symbol
Description
Reset
value
25:16
CPL
Clocks per line. This field specifies the number of actual LCD_DCLK clocks to the LCD panel on
each line. This is the number of PPL divided by either 1 (for TFT), 4 or 8 (for monochrome
passive), 2 2/3 (for color passive), minus one. This must be correctly programmed in addition to
the PPL bit in the LCD_TIMH register for the LCD display to work correctly.
0
26
BCD
Bypass pixel clock divider.
0
Setting this to 1 bypasses the pixel clock divider logic. This is mainly used for TFT displays.
31:27
PCD_HI
Upper five bits of panel clock divisor.
0
See description for PCD_LO, in bits [4:0] of this register.
11.7.4 Line End Control register
The LCD_LE register controls the enabling of line-end signal LCD_LE. When enabled, a
positive pulse, four LCDCLK periods wide, is output on LCD_LE after a programmable
delay, LED, from the last pixel of each display line. If the line-end signal is disabled it is
held permanently LOW.
Table 225. Line End Control register (LE, address 0x2008 800C) bit description
Bits
Symbol
Description
Reset
value
6:0
LED
Line-end delay. Controls Line-end signal delay from the rising-edge of the last panel clock,
LCD_DCLK. Program with the number of LCDCLK clock periods minus 1.
0
15:7
-
Reserved. Read value is undefined, only zero should be written.
-
16
LEE
LCD Line end enable.
0
0 = LCD_LE disabled (held LOW).
1 = LCD_LE signal active.
31:17
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
301 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.5 Upper Panel Frame Base Address register
The LCD_UPBASE register is the color LCD upper panel DMA base address register, and
is used to program the base address of the frame buffer for the upper panel. LCDUPBase
(and LCDLPBase for dual panels) must be initialized before enabling the LCD controller.
The base address must be doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
Table 226. Upper Panel Frame Base register (UPBASE, address 0x2008 8010) bit description
Bits
Symbol
Description
Reset
value
2:0
-
Reserved. Read value is undefined, only zero should be written.
-
31:3
LCDUPBASE
LCD upper panel base address. This is the start address of the upper panel frame data in
memory and is doubleword aligned.
0
11.7.6 Lower Panel Frame Base Address register
The LCD_LPBASE register is the color LCD lower panel DMA base address register, and
is used to program the base address of the frame buffer for the lower panel. LCDLPBase
must be initialized before enabling the LCD controller. The base address must be
doubleword aligned.
Optionally, the value may be changed mid-frame to create double-buffered video displays.
These registers are copied to the corresponding current registers at each LCD vertical
synchronization. This event causes the LNBU bit and an optional interrupt to be
generated. The interrupt can be used to reprogram the base address when generating
double-buffered video.
The contents of the LCD_LPBASE register are described in Table 227.
Table 227. Lower Panel Frame Base register (LPBASE, address 0x2008 8014) bit description
Bits
Symbol
Description
2:0
-
Reserved. Read value is undefined, only zero should be written.
-
31:3
LCDLPBASE
LCD lower panel base address. This is the start address of the lower panel frame data in
memory and is doubleword aligned.
0
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
302 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.7 LCD Control register
The LCD_CTRL register controls the LCD operating mode and the panel pixel
parameters.
The contents of the LCD_CTRL register are described in Table 228.
Table 228. LCD Control register (CTRL, address 0x2008 8018) bit description
Bits
Symbol
Description
Reset
value
0
LCDEN
LCD enable control bit.
0
0 = LCD disabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are
low.
1 = LCD enabled. Signals LCD_LP, LCD_DCLK, LCD_FP, LCD_ENAB_M, and LCD_LE are
high.
See LCD power-up and power-down sequence for details on LCD power sequencing.
3:1
LCDBPP
0
LCD bits per pixel. Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.
4
LCDBW
STN LCD monochrome/color selection.
0
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.
5
LCDTFT
LCD panel TFT type selection.
0
0 = LCD is an STN display. Use gray scaler.
1 = LCD is a TFT display. Do not use gray scaler.
6
LCDMONO8
Monochrome LCD interface width. Controls whether a monochrome STN LCD uses a 4 or
8-bit parallel interface. It has no meaning in other modes and must be programmed to zero.
0
0 = monochrome LCD uses a 4-bit interface.
1 = monochrome LCD uses a 8-bit interface.
7
LCDDUAL
Single or Dual LCD panel selection. STN LCD interface is:
0
0 = single-panel.
1 = dual-panel.
8
BGR
Color format selection.
0
0 = RGB: normal output.
1 = BGR: red and blue swapped.
9
BEBO
Big-endian Byte Order. Controls byte ordering in memory:
0
0 = little-endian byte order.
1 = big-endian byte order.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
303 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 228. LCD Control register (CTRL, address 0x2008 8018) bit description
Bits
Symbol
Description
Reset
value
10
BEPO
Big-Endian Pixel Ordering. Controls pixel ordering within a byte:
0
0 = little-endian ordering within a byte.
1 = big-endian pixel ordering within a byte.
The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display
modes, it has no effect on 8 or 16 bpp pixel formats. See Pixel serializer for more
information on the data format.
11
LCDPWR
LCD power enable.
0
0 = power not gated through to LCD panel and LCD_VD[23:0] signals disabled, (held LOW).
1 = power gated through to LCD panel and LCD_VD[23:0] signals enabled, (active).
See LCD power-up and power-down sequence for details on LCD power sequencing.
13:12 LCDVCOMP
0
LCD Vertical Compare Interrupt. Generate VComp interrupt at:
00 = start of vertical synchronization.
01 = start of back porch.
10 = start of active video.
11 = start of front porch.
15:14 16
Reserved. Read value is undefined, only zero should be written.
-
WATERMARK LCD DMA FIFO watermark level. Controls when DMA requests are generated:
0
0 = An LCD DMA request is generated when either of the DMA FIFOs have four or more
empty locations.
1 = An LCD DMA request is generated when either of the DMA FIFOs have eight or more
empty locations.
31:17 -
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
304 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.8 Interrupt Mask register
The LCD_INTMSK register controls whether various LCD interrupts occur.Setting bits in
this register enables the corresponding raw interrupt LCD_INTRAW status bit values to be
passed to the LCD_INTSTAT register for processing as interrupts.
The contents of the LCD_INTMSK register are described in Table 229.
Table 229. Interrupt Mask register (INTMSK, address 0x2008 801C) bit description
Bits
Symbol
Description
Reset
value
0
-
Reserved. Read value is undefined, only zero should be written.
-
1
FUFIM
FIFO underflow interrupt enable.
0
0: The FIFO underflow interrupt is disabled.
1: Interrupt will be generated when the FIFO underflows.
2
LNBUIM
0
LCD next base address update interrupt enable.
0: The base address update interrupt is disabled.
1: Interrupt will be generated when the LCD base address registers have been updated
from the next address registers.
3
VCOMPIM
Vertical compare interrupt enable.
0
0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as defined by LcdVComp
field in the LCD_CTRL register) is reached.
4
BERIM
AHB master error interrupt enable.
0
0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
31:5
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
305 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.9 Raw Interrupt Status register
The LCD_INTRAW register contains status flags for various LCD controller events. These
flags can generate an interrupts if enabled by mask bits in the LCD_INTMSK register.
Table 230. Raw Interrupt Status register (INTRAW, address 0x2008 8020) bit description
Bits
Symbol
Description
Reset
value
0
-
Reserved. Read value is undefined, only zero should be written.
1
FUFRIS
FIFO underflow raw interrupt status. Set when either the upper or lower DMA FIFOs have
been read accessed when empty causing an underflow condition to occur. Generates an
interrupt if the FUFIM bit in the LCD_INTMSK register is set.
2
LNBURIS
LCD next address base update raw interrupt status. Mode dependent. Set when the
current base address registers have been successfully updated by the next address
registers. Signifies that a new next address can be loaded if double buffering is in use.
Generates an interrupt if the LNBUIM bit in the LCD_INTMSK register is set.
0
3
VCOMPRIS
Vertical compare raw interrupt status. Set when one of the four vertical regions is reached,
as selected by the LcdVComp bits in the LCD_CTRL register. Generates an interrupt if the
VCompIM bit in the LCD_INTMSK register is set.
0
4
BERRAW
AHB master bus error raw interrupt status. Set when the AHB master interface receives a
bus error response from a slave. Generates an interrupt if the BERIM bit in the
LCD_INTMSK register is set.
0
31:5
-
Reserved. Read value is undefined, only zero should be written.
-
-
11.7.10 Masked Interrupt Status register
The LCD_INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the
LCD_INTRAW register and the LCD_INTMASK register. A logical OR of all interrupts is
provided to the system interrupt controller.
Table 231. Masked Interrupt Status register (INTSTAT, address 0x2008 8024) bit description
Bits
Symbol
Description
0
-
Reserved. The value read from a reserved bit is not defined.
-
1
FUFMIS
FIFO underflow masked interrupt status. Set when the both the FUFRIS bit in the
LCD_INTRAW register and the FUFIM bit in the LCD_INTMSK register are set.
0
2
LNBUMIS
LCD next address base update masked interrupt status. Set when the both the LNBURIS
bit in the LCD_INTRAW register and the LNBUIM bit in the LCD_INTMSK register are set.
0
3
VCOMPMIS
Vertical compare masked interrupt status. Set when the both the VCompRIS bit in the
LCD_INTRAW register and the VCompIM bit in the LCD_INTMSK register are set.
0
4
BERMIS
AHB master bus error masked interrupt status. Set when the both the BERRAW bit in the
LCD_INTRAW register and the BERIM bit in the LCD_INTMSK register are set.
0
31:5
-
Reserved. Read value is undefined, only zero should be written.
-
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
306 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.11 Interrupt Clear register
The LCD_INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the
corresponding interrupt.
Table 232. Interrupt Clear register (INTCLR, address 0x2008 8028) bit description
Bits
Symbol
Description
0
-
Reserved. Read value is undefined, only zero should be written.
1
FUFIC
FIFO underflow interrupt clear. Writing a 1 to this bit clears the FIFO underflow interrupt.
2
LNBUIC
LCD next address base update interrupt clear. Writing a 1 to this bit clears the LCD next address
base update interrupt.
3
VCOMPIC
Vertical compare interrupt clear. Writing a 1 to this bit clears the vertical compare interrupt.
4
BERIC
AHB master error interrupt clear. Writing a 1 to this bit clears the AHB master error interrupt.
31:5
-
Reserved. Read value is undefined, only zero should be written.
11.7.12 Upper Panel Current Address register
The LCD_UPCURR register is Read-Only, and contains an approximate value of the
upper panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
Table 233. Upper Panel Current Address register (UPCURR, address 0x2008 802C) bit description
Bits
Symbol
Description
Reset
value
31:0
LCDUPCURR
LCD Upper Panel Current Address. Contains the current LCD upper panel data DMA
address.
0
11.7.13 Lower Panel Current Address register
The LCD_LPCURR register is Read-Only, and contains an approximate value of the lower
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
Table 234. Lower Panel Current Address register (LPCURR, address 0x2008 8030) bit description
Bits
Symbol
Description
31:0
LCDLPCURR
LCD Lower Panel Current Address. Contains the current LCD lower panel data DMA
address.
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
307 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.14 Color Palette registers
The LCD_PAL register contain 256 palette entries organized as 128 locations of two
entries per word.
Each word location contains two palette entries. This means that 128 word locations are
used for the palette. When configured for little-endian byte ordering, bits [15:0] are the
lower numbered palette entry and [31:16] are the higher numbered palette entry. When
configured for big-endian byte ordering this is reversed, because bits [31:16] are the low
numbered palette entry and [15:0] are the high numbered entry.
Note: Only TFT displays use all of the palette entry bits.
Table 235. Color Palette registers (PAL[0:127], address 0x2008 8200 (PAL0) to 0x2008 83FC (PAL127)) bit
description
Bits
Symbol Description
Reset
value
4:0
R04_0
Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome
displays only the red palette data is used. All of the palette registers have the same bit fields.
0
9:5
G04_0
Green palette data.
0
14:10
B04_0
Blue palette data.
0
15
I0
Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display,
doubling the number of colors to 64K, where each color has two different intensities.
0
20:16
R14_0
Red palette data. For STN displays, only the four MSBs, bits [4:1], are used. For monochrome
displays only the red palette data is used. All of the palette registers have the same bit fields.
0
25:21
G14_0
Green palette data.
0
30:26
B14_0
Blue palette data.
0
31
I1
Intensity / unused bit. Can be used as the LSB of the R, G, and B inputs to a 6:6:6 TFT display,
doubling the number of colors to 64K, where each color has two different intensities.
0
11.7.15 Cursor Image registers
The CRSR_IMG register area contains 256-word wide values which are used to define
the image or images overlaid on the display by the hardware cursor mechanism. The
image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as
described in Section 11.6.5.6. Two bits are used to encode color and transparency for
each pixel in the cursor.
Depending on the state of bit 0 in the CRSR_CFG register (see Cursor Configuration
register description), the cursor image RAM contains either four 32x32 cursor images, or
a single 64x64 cursor image.
The two colors defined for the cursor are mapped onto values from the CRSR_PAL0 and
CRSR_PAL0 registers (see Cursor Palette register descriptions).
Table 236. Cursor Image registers (CRSR_IMG[0:255], address 0x2008 8800 (CRSR_IMG0) to 0x2008 8BFC
(CRSR_IMG255)) bit description
Bits
Symbol
Description
31:0
CRSR_IMG
Cursor Image data. The 256 words of the cursor image registers define the appearance of
either one 64x64 cursor, or 4 32x32 cursors.
UM10562
User manual
Reset
value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
308 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.16 Cursor Control register
The CRSR_CTRL register provides access to frequently used cursor functions, such as
the display on/off control for the cursor, and the cursor number.
If a 32x32 cursor is selected, one of four 32x32 cursors can be enabled. The images each
occupy one quarter of the image memory, with Cursor0 from location 0, followed by
Cursor1 from address 0x100, Cursor2 from 0x200 and Cursor3 from 0x300. If a 64x64
cursor is selected only one cursor fits in the image buffer, and no selection is possible.
Similar frame synchronization rules apply to the cursor number as apply to the cursor
coordinates. If CrsrFramesync is 1, the displayed cursor image is only changed during the
vertical frame blanking period. If CrsrFrameSync is 0, the cursor image index is changed
immediately, even if the cursor is currently being scanned.
Table 237. Cursor Control register (CRSR_CTRL, address 0x2008 8C00) bit description
Bits
Symbol
Description
Reset value
0
CRSRON
Cursor enable.
0
0 = Cursor is not displayed.
1 = Cursor is displayed.
3:1
-
Reserved. Read value is undefined, only zero should be written.
0
5:4
CRSRNUM1_0
Cursor image number. If the selected cursor size is 6x64, this field has no effect. If
the selected cursor size is 32x32:
0
00 = Cursor0.
01 = Cursor1.
10 = Cursor2.
11 = Cursor3.
31:6
-
Reserved. Read value is undefined, only zero should be written.
0
11.7.17 Cursor Configuration register
The CRSR_CFG register provides overall configuration information for the hardware
cursor.
Table 238. Cursor Configuration register (CRSR_CFG, address 0x2008 8C04) bit description
Bits
Symbol
Description
Reset value
0
CRSRSIZE
Cursor size selection.
0
0 = 32x32 pixel cursor. Allows for 4 defined cursors.
1 = 64x64 pixel cursor.
1
FRAMESYNC Cursor frame synchronization type.
0
0 = Cursor coordinates are asynchronous.
1 = Cursor coordinates are synchronized to the frame synchronization pulse.
31:2
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
309 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.18 Cursor Palette register 0
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color0 maps through CRSR_PAL0.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
Table 239. Cursor Palette register 0 (CRSR_PAL0, address 0x2008 8C08) bit description
Bits
Symbol
Description
Reset value
7:0
RED
Red color component
0
15:8
GREEN
Green color component
0
23:16
BLUE
Blue color component.
0
31:24
-
Reserved. Read value is undefined, only zero should be written.
-
11.7.19 Cursor Palette register 1
The cursor palette registers provide color palette information for the visible colors of the
cursor. Color1 maps through CRSR_PAL1.
The register provides 24-bit RGB values that are displayed according to the abilities of the
LCD panel in the same way as the frame-buffers palette output is displayed.
In monochrome STN mode, only the upper 4 bits of the Red field are used. In STN color
mode, the upper 4 bits of the Red, Blue, and Green fields are used. In 24 bits per pixel
mode, all 24 bits of the palette registers are significant.
Table 240. Cursor Palette register 1 (CRSR_PAL1, address 0x2008 8C0C) bit description
Bits
Symbol
Description
7:0
RED
Red color component
0
15:8
GREEN
Green color component
0
23:16
BLUE
Blue color component.
0
31:24
-
Reserved. Read value is undefined, only zero should be written.
-
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
310 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.20 Cursor XY Position register
The CRSR_XY register defines the distance of the top-left edge of the cursor from the
top-left side of the cursor overlay. refer to the section on Cursor Clipping for more details.
If the FrameSync bit in the CRSR_CFG register is 0, the cursor position changes
immediately, even if the cursor is currently being scanned. If Framesync is 1, the cursor
position is only changed during the next vertical frame blanking period.
Table 241. Cursor XY Position register (CRSR_XY, address 0x2008 8C10) bit description
Bits
Symbol
Description
Reset value
9:0
CRSRX
X ordinate of the cursor origin measured in pixels. When 0, the left edge of the cursor is
at the left of the display.
0
15:10
-
Reserved. Read value is undefined, only zero should be written.
-
25:16
CRSRY
Y ordinate of the cursor origin measured in pixels. When 0, the top edge of the cursor is
at the top of the display.
0
31:26
-
Reserved. Read value is undefined, only zero should be written.
-
11.7.21 Cursor Clip Position register
The CRSR_CLIP register defines the distance from the top-left edge of the cursor image,
to the first displayed pixel in the cursor image.
Different synchronization rules apply to the Cursor Clip registers than apply to the cursor
coordinates. If the FrameSync bit in the CRSR_CFG register is 0, the cursor clip point is
changed immediately, even if the cursor is currently being scanned.
If the Framesync bit in the CRSR_CFG register is 1, the displayed cursor image is only
changed during the vertical frame blanking period, providing that the cursor position has
been updated since the Clip register was programmed. When programming, the Clip
register must be written before the Position register (ClcdCrsrXY) to ensure that in a given
frame, the clip and position information is coherent.
The contents of the CRSR_CLIP register are described in Table 242.
Table 242. Cursor Clip Position register (CRSR_CLIP, address 0x2008 8C14) bit description
Bits
Symbol
Description
Reset value
5:0
CRSRCLIPX
Cursor clip position for X direction. Distance from the left edge of the cursor image to
the first displayed pixel in the cursor.
0
When 0, the first pixel of the cursor line is displayed.
7:6
-
Reserved. Read value is undefined, only zero should be written.
-
13:8
CRSRCLIPY
Cursor clip position for Y direction. Distance from the top of the cursor image to the
first displayed pixel in the cursor.
0
When 0, the first displayed pixel is from the top line of the cursor image.
31:14
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
311 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.22 Cursor Interrupt Mask register
The CRSR_INTMSK register is used to enable or disable the cursor from interrupting the
processor.
Table 243. Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0x2008 8C20)
Bits
Symbol
Description
0
CRSRIM
Cursor interrupt mask. When clear, the cursor never interrupts the processor. When set,
the cursor interrupts the processor immediately after reading of the last word of cursor
image.
Reset value
0
31:1
-
Reserved. Read value is undefined, only zero should be written.
-
11.7.23 Cursor Interrupt Clear register
The CRSR_INTCLR register is used by software to clear the cursor interrupt status and
the cursor interrupt signal to the processor.
Table 244. Cursor Interrupt Clear register (CRSR_INTCLR, address 0x2008 8C24) bit description
Bits
Symbol
Description
0
CRSRIC
Cursor interrupt clear.
Writing a 0 to this bit has no effect.
Writing a 1 to this bit causes the cursor interrupt status to be cleared.
31:1
-
Reserved. Read value is undefined, only zero should be written.
11.7.24 Cursor Raw Interrupt Status register
The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the
CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt
controller.
Table 245. Cursor Raw Interrupt Status register (CRSR_INTRAW, address 0x2008 8C28) bit description
Bits
Symbol
0
CRSRRIS Cursor raw interrupt status. The cursor interrupt status is set immediately after the last
data is read from the cursor image for the current frame. This bit is cleared by writing to
the CrsrIC bit in the CRSR_INTCLR register.
0
31:1
-
-
UM10562
User manual
Description
Reset value
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
312 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.7.25 Cursor Masked Interrupt Status register
The CRSR_INTSTAT register is set to indicate a cursor interrupt providing that the
interrupt is not masked in the CRSR_INTMSK register.
Table 246. Cursor Masked Interrupt Status register (CRSR_INTSTAT, address 0x2008 8C2C) bit description
Bits
Symbol
Description
Reset
value
0
CRSRMIS
Cursor masked interrupt status. The cursor interrupt status is set immediately after the last
data read from the cursor image for the current frame, providing that the corresponding bit in
the CRSR_INTMSK register is set.
0
The bit remains clear if the CRSR_INTMSK register is clear.
This bit is cleared by writing to the CRSR_INTCLR register.
31:1
-
UM10562
User manual
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
© NXP B.V. 2012. All rights reserved.
313 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.8 LCD timing diagrams
one horizontal line
pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(line synch
pulse)
LCDDCLK
(panel clock)
suppressed
during LCDLP
LCD_TIMH (HBP)
16  LCD_TIMH(PPL)  1
horizontal back porch
(defined in pixel clocks)
LCD_TIMH (HFP)
horizontal front porch
(defined in pixel clocks)
LCDVD[15:0]
(panel data)
one horizontal line of LCD data
(1) The active data lines will vary with the type of STN panel (4-bit, 8-bit, color, mono) and with single or dual frames.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCD_LP signal is controlled by the HSW field in the LCD_TIMH register.
(4) The Polarity of the LCD_LP signal is determined by the IHS bit in the LCD_POL register.
Fig 37. Horizontal timing for STN displays
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
314 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
one frame
LCDDCLK
(panel clock)
panel data clock active
LCD_TIMV (VSW)
LCDFP
(vertical synch
pulse)
LCD_TIMV (VBP)
LCD_TIMV(LPP)
LCD_TIMV (VFP)
back porch
(defined in line clocks)
all horizontal lines for one frame
front porch
(defined in line clocks)
pixel data
and horizontal
controls for one
frame
see horizontal timing for STN displays
(1) Signal polarities may vary for some displays.
Fig 38. Vertical timing for STN displays
one horizontal line
pixel clock
(internal)
LCD_TIMH (HSW)
LCDLP
(lhorizontal
synch pulse)
LCDDCLK
(panel clock)
LCD_TIMH (HBP)
LCD_TIMH(PPL)
LCD_TIMH (HFP)
LCDENAB
horizontal back porch
(defined in pixel clocks)
horizontal front porch
(defined in pixel clocks)
LCDVD[23:0]
(panel data)
one horizontal line of LCD data
(1) The active data lines will vary with the type of TFT panel.
(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.
(3) The duration of the LCD_LP is controlled by the HSW field in the LCD_TIMH register.
(4) The polarity of the LCD_LP signal is determined by the IHS bit in the LCD_POL register.
Fig 39. Horizontal timing for TFT displays
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
315 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
one frame
LCDDCLK
(panel clock)
panel data clock active
LCDENA
(data enable)
data enable
LCD_TIMV (VSW)
LCDFP
(vertical synch
pulse)
LCD_TIMV (VBP)
LCD_TIMV(LPP)
LCD_TIMV (VFP)
back porch
(defined in line clocks)
all horizontal lines for one frame
front porch
(defined in line clocks)
pixel data
and horizontal
control signals
for one frame
see horizontal timing for TFT displays
(1) Polarities may vary for some displays.
Fig 40. Vertical timing for TFT displays
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
316 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
11.9 LCD panel signal usage
Table 247. LCD panel connections for STN single panel mode
External pin
4-bit mono STN single panel
pin used
LCD function
8-bit mono STN single panel
pin used
LCD function
pin used
-
-
-
LCD_VD[7]
-
-
P4[29]
UD[7]
P4[29]
UD[7]
LCD_VD[6]
-
-
P4[28]
UD[6]
P4[28]
UD[6]
LCD_VD[5]
-
-
P2[13]
UD[5]
P2[13]
UD[5]
LCD_VD[4]
-
-
P2[12]
UD[4]
P2[12]
UD[4]
LCD_VD[3]
P2[9]
UD[3]
P2[9]
UD[3]
P2[9]
UD[3]
LCD_VD[2]
P2[8]
UD[2]
P2[8]
UD[2]
P2[8]
UD[2]
LCD_VD[1]
P2[7]
UD[1]
P2[7]
UD[1]
P2[7]
UD[1]
LCD_VD[0]
P2[6]
UD[0]
P2[6]
UD[0]
P2[6]
UD[0]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
LCD_ENAB_M
P2[4]
LCD_ENAB_M
P2[4]
LCD_ENAB_M
P2[4]
LCD_ENAB_M
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
LCD_DCLK
P2[2]
LCD_DCLK
P2[2]
LCD_DCLK
P2[2]
LCD_DCLK
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
LCD_CLKIN
P2[11]
LCD_CLKIN
P2[11]
LCD_CLKIN
P2[0]
LCD_PWR
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
-
LCD function
LCD_VD[8] LCD_VD[23]
UM10562
-
Color STN single panel
-
© NXP B.V. 2012. All rights reserved.
317 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 248. LCD panel connections for STN dual panel mode
External pin
4-bit mono STN dual panel
8-bit mono STN dual panel
Color STN dual panel
pin used
LCD function
pin used
LCD function
pin used
LCD function
LCD_VD[16] LCD_VD[23]
-
-
-
-
-
-
LCD_VD[15]
-
-
P1[29]
LD[7]
P1[29]
LD[7]
LCD_VD[14]
-
-
P1[28]
LD[6]
P1[28]
LD[6]
LCD_VD[13]
-
-
P1[27]
LD[5]
P1[27]
LD[5]
-
P1[26]
LD[4]
P1[26]
LD[4]
LD[3]
P1[25]
LD[3]
P1[25]
LD[3]
LCD_VD[12]
LCD_VD[11]
P4[29]
LCD_VD[10]
P4[28]
LD[2]
P1[24]
LD[2]
P1[24]
LD[2]
LCD_VD[9]
P2[13]
LD[1]
P1[23]
LD[1]
P1[23]
LD[1]
LCD_VD[8]
P2[12]
LD[0]
P1[22]
LD[0]
P1[22]
LD[0]
LCD_VD[7]
-
-
P1[21]
UD[7]
P1[21]
UD[7]
LCD_VD[6]
-
-
P1[20]
UD[6]
P1[20]
UD[6]
LCD_VD[5]
-
-
P2[13]
UD[5]
P2[13]
UD[5]
LCD_VD[4]
-
-
P2[12]
UD[4]
P2[12]
UD[4]
LCD_VD[3]
P2[9]
UD[3]
P2[9]
UD[3]
P2[9]
UD[3]
LCD_VD[2]
P2[8]
UD[2]
P2[8]
UD[2]
P2[8]
UD[2]
LCD_VD[1]
P2[7]
UD[1]
P2[7]
UD[1]
P2[7]
UD[1]
LCD_VD[0]
P2[6]
UD[0]
P2[6]
UD[0]
P2[6]
UD[0]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
LCD_ENAB_M
P2[4]
LCD_ENAB_M
P2[4]
LCD_ENAB_M
P2[4]
LCD_ENAB_M
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
LCD_DCLK
P2[2]
LCD_DCLK
P2[2]
LCD_DCLK
P2[2]
LCD_DCLK
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD-PWR
LCD_CLKIN
P2[11]
LCD_CLKIN
P2[11]
LCD_CLKIN
P2[11]
LCD_CLKIN
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
318 of 942
UM10562
NXP Semiconductors
Chapter 11: LPC408x/407x LCD controller
Table 249. LCD panel connections for TFT panels
External pin
TFT 12 bit (4:4:4 mode)
TFT 16 bit (5:6:5 mode)
TFT 16 bit (1:5:5:5
mode)
TFT 24 bit
pin used
LCD
function
pin used
LCD
function
pin used
LCD
function
pin used
LCD
function
LCD_VD[23]
P1[29]
BLUE3
P1[29]
BLUE4
P1[29]
BLUE4
P1[29]
BLUE7
LCD_VD[22]
P1[28]
BLUE2
P1[28]
BLUE3
P1[28]
BLUE3
P1[28]
BLUE6
LCD_VD[21]
P1[27]
BLUE1
P1[27]
BLUE2
P1[27]
BLUE2
P1[27]
BLUE5
LCD_VD[20]
P1[26]
BLUE0
P1[26]
BLUE1
P1[26]
BLUE1
P1[26]
BLUE4
LCD_VD[19]
-
-
P2[13]
BLUE0
P2[13]
BLUE0
P2[13]
BLUE3
LCD_VD[18]
-
-
-
-
P2[12]
intensity
P2[12]
BLUE2
LCD_VD[17]
-
-
-
-
-
-
P0[9]
BLUE1
LCD_VD[16]
-
-
-
-
-
-
P0[8]
BLUE0
LCD_VD[15]
P1[25]
GREEN3
P1[25]
GREEN5
P1[25]
GREEN4
P1[25]
GREEN7
LCD_VD[14]
P1[24]
GREEN2
P1[24]
GREEN4
P1[24]
GREEN3
P1[24]
GREEN6
LCD_VD[13]
P1[23]
GREEN1
P1[23]
GREEN3
P1[23]
GREEN2
P1[23]
GREEN5
LCD_VD[12]
P1[22]
GREEN0
P1[22]
GREEN2
P1[22]
GREEN1
P1[22]
GREEN4
LCD_VD[11]
-
-
P1[21]
GREEN1
P1[21]
GREEN0
P1[21]
GREEN3
LCD_VD[10]
-
-
P1[20]
GREEN0
P1[20]
intensity
P1[20]
GREEN2
LCD_VD[9]
-
-
-
-
-
-
P0[7]
GREEN1
LCD_VD[8]
-
-
-
-
-
-
P0[6]
GREEN0
LCD_VD[7]
P2[9]
RED3
P2[9]
RED4
P2[9]
RED4
P2[9]
RED7
LCD_VD[6]
P2[8]
RED2
P2[8]
RED3
P2[8]
RED3
P2[8]
RED6
LCD_VD[5]
P2[7]
RED1
P2[7]
RED2
P2[7]
RED2
P2[7]
RED5
LCD_VD[4]
P2[6]
RED0
P2[6]
RED1
P2[6]
RED1
P2[6]
RED4
LCD_VD[3]
-
-
P2[12]
RED0
P4[29]
RED0
P4[29]
RED3
LCD_VD[2]
-
-
-
-
P4[28]
intensity
P4[28]
RED2
LCD_VD[1]
-
-
-
-
-
-
P0[5]
RED1
LCD_VD[0]
-
-
-
-
-
-
P0[4]
RED0
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
P2[5]
LCD_LP
LCD_
ENAB_M
P2[4]
LCD_
ENAB_M
P2[4]
LCD_
ENAB_M
P2[4]
LCD_
ENAB_M
P2[4]
LCD_
ENAB_M
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
P2[3]
LCD_FP
LCD_DCLK
P2[2]
LCD_DCLK P2[2]
LCD_DCLK P2[2]
LCD_DCLK P2[2]
LCD_DCLK
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
P2[1]
LCD_LE
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
P2[0]
LCD_PWR
LCD_CLKIN
P2[11]
LCD_CLKIN P2[11]
UM10562
User manual
LCD_CLKIN P2[11]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
LCD_CLKIN P2[11]
LCD_CLKIN
© NXP B.V. 2012. All rights reserved.
319 of 942
UM10562
Chapter 12: LPC408x/407x USB device controller
Rev. 1 — 13 September 2012
User manual
12.1 How to read this chapter
This chapter describes the USB device controller which is present on LPC408x/407x
family devices. On some family devices, the USB controller can also be configured for
Host or OTG operation (see Section 1.4 for details).
12.2 Basic configuration
The USB controller is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCUSB.
Remark: On reset, the USB block is disabled (PCUSB = 0).
2. Clock: The USB block can be used with either the Main PLL (PLL0), or with the
alternate PLL (PLL1) to obtain the USB clock. See Section 3.10.
3. Pins: Select the required USB pins and their modes in the relevant IOCON registers
(Section 7.4.1).
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
Power-down mode, see Section 3.12.8.
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. The USB global interrupt status is visible in the USBINTSTAT register (Table 37).
7. Initialization: See Section 12.13.
12.3 Introduction
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame
(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 16 logical or 32 physical endpoints. There are four types of
transfers defined for the endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the
rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no
error correction.
For more information on the Universal Serial Bus, see the USB Implementers Forum
website.
The USB device controller enables full-speed (12 Mb/s) data exchange with a USB host
controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
320 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Table 250. USB related acronyms, abbreviations, and definitions used in this chapter
Acronym/abbreviation
Description
AHB
Advanced High-performance bus
ATLE
Auto Transfer Length Extraction
ATX
Analog Transceiver
DD
DMA Descriptor
DDP
DMA Description Pointer
DMA
Direct Memory Access
EOP
End-Of-Packet
EP
Endpoint
EP_RAM
Endpoint RAM
FS
Full Speed
LED
Light Emitting Diode
LS
Low Speed
MPS
Maximum Packet Size
NAK
Negative Acknowledge
PLL
Phase Locked Loop
RAM
Random Access Memory
SOF
Start-Of-Frame
SIE
Serial Interface Engine
SRAM
Synchronous RAM
UDCA
USB Device Communication Area
USB
Universal Serial Bus
12.4 Features
•
•
•
•
•
Fully compliant with the USB 2.0 specification (full speed).
•
•
•
•
Supports SoftConnect and GoodLink features.
Supports 32 physical (16 logical) endpoints.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports DMA transfers on all non-control endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
12.5 Fixed endpoint configuration
Table 251 shows the supported endpoint configurations. Endpoints are realized and
configured at run time using the Endpoint realization registers, documented in
Section 12.10.4 “Endpoint realization registers”.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
321 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Table 251. Fixed endpoint configuration
UM10562
User manual
Logical
endpoint
Physical
endpoint
Endpoint type
Direction
Packet size
(bytes)
Double
buffer
0
0
Control
Out
8, 16, 32, 64
No
0
1
Control
In
8, 16, 32, 64
No
1
2
Interrupt
Out
1 to 64
No
1
3
Interrupt
In
1 to 64
No
2
4
Bulk
Out
8, 16, 32, 64
Yes
2
5
Bulk
In
8, 16, 32, 64
Yes
3
6
Isochronous
Out
1 to 1023
Yes
3
7
Isochronous
In
1 to 1023
Yes
4
8
Interrupt
Out
1 to 64
No
4
9
Interrupt
In
1 to 64
No
5
10
Bulk
Out
8, 16, 32, 64
Yes
5
11
Bulk
In
8, 16, 32, 64
Yes
6
12
Isochronous
Out
1 to 1023
Yes
6
13
Isochronous
In
1 to 1023
Yes
7
14
Interrupt
Out
1 to 64
No
7
15
Interrupt
In
1 to 64
No
8
16
Bulk
Out
8, 16, 32, 64
Yes
8
17
Bulk
In
8, 16, 32, 64
Yes
9
18
Isochronous
Out
1 to 1023
Yes
9
19
Isochronous
In
1 to 1023
Yes
10
20
Interrupt
Out
1 to 64
No
10
21
Interrupt
In
1 to 64
No
11
22
Bulk
Out
8, 16, 32, 64
Yes
11
23
Bulk
In
8, 16, 32, 64
Yes
12
24
Isochronous
Out
1 to 1023
Yes
12
25
Isochronous
In
1 to 1023
Yes
13
26
Interrupt
Out
1 to 64
No
13
27
Interrupt
In
1 to 64
No
14
28
Bulk
Out
8, 16, 32, 64
Yes
14
29
Bulk
In
8, 16, 32, 64
Yes
15
30
Bulk
Out
8, 16, 32, 64
Yes
15
31
Bulk
In
8, 16, 32, 64
Yes
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
322 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.6 Functional description
The architecture of the USB device controller is shown below in Figure 41.
VBUS
BUS
MASTER
INTERFACE
DMA
ENGINE
USB_CONNECT1
USB_CONNECT2
REGISTER
INTERFACE
EP_RAM
ACCESS
CONTROL
SERIAL
INTERFACE
ENGINE
USB ATX
AHB BUS
DMA interface
(AHB master)
USB_D+1,
USB_D+2
USB_D-1,
USB_D-2
USB_UP_LED1,
USB_UP_LED2
register
interface
(AHB slave)
EP_RAM
(4K)
USB DEVICE
BLOCK
Fig 41. USB device controller block diagram
12.6.1 Analog transceiver
The USB Device Controller has a built-in analog transceiver (ATX). The USB ATX
sends/receives the bidirectional D+ and D- signals of the USB bus.
12.6.2 Serial Interface Engine (SIE)
The SIE implements the full USB protocol layer. It is completely hardwired for speed and
needs no firmware intervention. It handles transfer of data between the endpoint buffers in
EP_RAM and the USB bus. The functions of this block include: synchronization pattern
recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation,
PID verification/generation, address recognition, and handshake evaluation/generation.
12.6.3 Endpoint RAM (EP_RAM)
Each endpoint buffer is implemented as an SRAM based FIFO. The SRAM dedicated for
this purpose is called the EP_RAM. Each realized endpoint has a reserved space in the
EP_RAM. The total EP_RAM space required depends on the number of realized
endpoints, the maximum packet size of the endpoint, and whether the endpoint supports
double buffering.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
323 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.6.4 EP_RAM access control
The EP_RAM Access Control logic handles transfer of data from/to the EP_RAM and the
three sources that can access it: the CPU (via the Register Interface), the SIE, and the
DMA Engine.
12.6.5 DMA engine and bus master interface
When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB
bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all
endpoints. When transferring data, the DMA Engine functions as a master on the AHB
bus through the bus master interface.
12.6.6 Register interface
The Register Interface allows the CPU to control the operation of the USB Device
Controller. It also provides a way to write transmit data to the controller and read receive
data from the controller.
12.6.7 SoftConnect
The connection to the USB is accomplished by bringing D+ (for a full-speed device) HIGH
through a 1.5 kOhm pull-up resistor. The SoftConnect feature can be used to allow
software to finish its initialization sequence before deciding to establish connection to the
USB. Re-initialization of the USB bus connection can also be performed without having to
unplug the cable.
To use the SoftConnect feature, the CONNECT signal should control an external switch
that connects the 1.5 kOhm resistor between D+ and +3.3V. Software can then control the
CONNECT signal by writing to the CON bit using the SIE Set Device Status command.
12.6.8 GoodLink
Good USB connection indication is provided through GoodLink technology. When the
device is successfully enumerated and configured, the LED indicator will be permanently
ON. During suspend, the LED will be OFF.
This feature provides a user-friendly indicator on the status of the USB device. It is a
useful field diagnostics tool to isolate faulty equipment.
To use the GoodLink feature the UP_LED signal should control an LED. The UP_LED
signal is controlled using the SIE Configure Device command.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
324 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.7 Operational overview
Transactions on the USB bus transfer data between device endpoints and the host. The
direction of a transaction is defined with respect to the host. OUT transactions transfer
data from the host to the device. IN transactions transfer data from the device to the host.
All transactions are initiated by the host controller.
For an OUT transaction, the USB ATX receives the bidirectional D+ and D- signals of the
USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and
converts it into a parallel data stream. The parallel data is written to the corresponding
endpoint buffer in the EP_RAM.
For IN transactions, the SIE reads the parallel data from the endpoint buffer in EP_RAM,
converts it into serial data, and transmits it onto the USB bus using the USB ATX.
Once data has been received or sent, the endpoint buffer can be read or written. How this
is accomplished depends on the endpoint’s type and operating mode. The two operating
modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface. See Section 12.14 “Slave mode operation” for a detailed description of
this mode.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer. See
Section 12.15 “DMA operation” for a detailed description of this mode.
12.8 Pin description
Table 252. USB external interface
Name
Direction Description
VBUS
I
VBUS status input. When this input function is not enabled via the
corresponding IOCON register, it is driven HIGH internally.
USB_CONNECT1, USB_CONNECT2
O
SoftConnect control signal.
USB_UP_LED1, USB_UP_LED2
O
GoodLink LED control signal.
USB_D+1, USB_D+2
I/O
Positive differential data.
USB_D-1, USB_D-2
I/O
Negative differential data.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
325 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.9 Clocking and power management
This section describes the clocking and power management features of the USB Device
Controller.
12.9.1 Power requirements
The USB protocol insists on power management by the device. This becomes very critical
if the device draws power from the bus (bus-powered device). The following constraints
should be met by a bus-powered device:
1. A device in the non-configured state should draw a maximum of 100 mA from the bus.
2. A configured device can draw only up to what is specified in the Max Power field of
the configuration descriptor. The maximum value is 500 mA.
3. A suspended device can draw a maximum of 500 µA.
12.9.2 Clocks
The USB device controller clocks are shown in Table 253
Table 253. USB device controller clock sources
Clock source
Description
AHB master clock
Clock for the AHB master bus interface and DMA
AHB slave clock
Clock for the AHB slave interface
usbclk
48 MHz clock from the dedicated Alt PLL (PLL1) or the Main PLL (PLL0),
used to recover the 12 MHz clock from the USB bus
12.9.3 Power management support
To help conserve power, the USB device controller automatically disables the AHB master
clock and usbclk when not in use.
When the USB Device Controller goes into the suspend state (bus is idle for 3 ms), the
usbclk input to the device controller is automatically disabled, helping to conserve power.
However, if software wishes to access the device controller registers, usbclk must be
active. To allow access to the device controller registers while in the suspend state, the
USBClkCtrl and USBClkSt registers are provided.
When software wishes to access the device controller registers, it should first ensure
usbclk is enabled by setting DEV_CLK_EN in the USBClkCtrl register, and then poll the
corresponding DEV_CLK_ON bit in USBClkSt until set. Once set, usbclk will remain
enabled until DEV_CLK_EN is cleared by software.
When a DMA transfer occurs, the device controller automatically turns on the AHB master
clock. Once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure
that DMA throughput is not affected by turning off the AHB master clock. 2 ms after the
last DMA access, the AHB master clock is automatically disabled to help conserve power.
If desired, software also has the capability of forcing this clock to remain enabled using the
USBClkCtrl register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
326 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Note that the AHB slave clock is always enabled as long as the PCUSB bit of PCONP is
set. When the device controller is not in use, all of the device controller clocks may be
disabled by clearing PCUSB.
The USB_NEED_CLK signal is used to facilitate going into and waking up from chip
Power-down mode. USB_NEED_CLK is asserted if any of the bits of the USBClkSt
register are asserted.
After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the
DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off.
When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put
into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK
can be read from the USBIntSt register.
Any bus activity in the suspend state will cause the USB_NEED_CLK signal to be
asserted. When the chip is in Power-down mode and the USB interrupt is enabled, the
assertion of USB_NEED_CLK causes the chip to wake up from Power-down mode.
12.9.4 Remote wake-up
The USB device controller supports software initiated remote wake-up. Remote wake-up
involves resume signaling on the USB bus initiated from the device. This is done by
clearing the SUS bit in the SIE Set Device Status register. Before writing into the register,
all the clocks to the device controller have to be enabled using the USBClkCtrl register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
327 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10 Register description
Table 254 shows the USB Device Controller registers directly accessible by the CPU. The
Serial Interface Engine (SIE) has other registers that are indirectly accessible via the SIE
command registers. See Section 12.12 “Serial interface engine command description” for
more info.
The USB interrupt status is captured in the USBINTSTAT register in the syscon block.
Reading WO register will return an invalid value.
Table 254. Register overview: USB device controller (base address 0x2008 C000)
Name
Access
Address
offset
Description
Reset Table
value[1]
Port select register
PORTSEL
R/W
0x110
USB Port Select. This register is also used for OTG
configuration. In device-only operations only bits 0 and 1 of
this register are used to control the routing of USB pins to
Port 1 or Port 2.
0
255
Device interrupt registers
DEVINTST
RO
0x200
USB Device Interrupt Status
0x10
256
DEVINTEN
R/W
0x204
USB Device Interrupt Enable
0
257
DEVINTCLR
WO
0x208
USB Device Interrupt Clear
-
258
DEVINTSET
WO
0x20C
USB Device Interrupt Set
-
259
DEVINTPRI
WO
0x22C
USB Device Interrupt Priority
0
260
Endpoint interrupt registers
EPINTST
RO
0x230
USB Endpoint Interrupt Status
0
262
EPINTEN
R/W
0x234
USB Endpoint Interrupt Enable
0
263
EPINTCLR
WO
0x238
USB Endpoint Interrupt Clear
-
264
EPINTSET
WO
0x23C
USB Endpoint Interrupt Set
-
265
EPINTPRI
WO
0x240
USB Endpoint Priority
0
266
0x3
267
Endpoint realization registers
REEP
R/W
0x244
USB Realize Endpoint
EPIN
WO
0x248
USB Endpoint Index
0
268
MAXPSIZE
R/W
0x24C
USB MaxPacketSize
0x8
269
USB transfer registers
RXDATA
RO
0x218
USB Receive Data
0
270
RXPLEN
RO
0220
USB Receive Packet Length
0
271
TXDATA
WO
0x21C
USB Transmit Data
-
272
TXPLEN
WO
0x224
USB Transmit Packet Length
0
273
CTRL
R/W
0x228
USB Control
0
274
SIE Command registers
CMDCODE
WO
0x210
USB Command Code
0
275
CMDDATA
RO
0x214
USB Command Data
0
276
RO
0x250
USB DMA Request Status
0
277
DMA registers
DMARST
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
328 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Table 254. Register overview: USB device controller (base address 0x2008 C000)
Name
Access
Address
offset
WO
0x254
USB DMA Request Clear
DMARSET
WO
0x258
UDCAH
R/W
0x280
EPDMAST
RO
EPDMAEN
DMARCLR
Description
Reset Table
value[1]
-
278
USB DMA Request Set
-
279
USB UDCA Head
0
280
0x284
USB Endpoint DMA Status
0
281
WO
0x288
USB Endpoint DMA Enable
-
282
EPDMADIS
WO
0x28C
USB Endpoint DMA Disable
-
283
DMAINTST
RO
0x290
USB DMA Interrupt Status
0
284
DMAINTEN
R/W
0x294
USB DMA Interrupt Enable
0
285
EOTINTST
RO
0x2A0
USB End of Transfer Interrupt Status
0
286
EOTINTCLR
WO
0x2A4
USB End of Transfer Interrupt Clear
-
287
EOTINTSET
WO
0x2A8
USB End of Transfer Interrupt Set
-
288
NDDRINTST
RO
0x2AC
USB New DD Request Interrupt Status
0
289
NDDRINTCLR
WO
0x2B0
USB New DD Request Interrupt Clear
-
290
NDDRINTSET
WO
0x2B4
USB New DD Request Interrupt Set
-
291
SYSERRINTST
RO
0x2B8
USB System Error Interrupt Status
0
292
SYSERRINTCLR
WO
0x2BC
USB System Error Interrupt Clear
-
293
SYSERRINTSET
WO
0x2C0
USB System Error Interrupt Set
-
294
Clock control registers
CLKCTRL
R/W
0xFF4
USB Clock Control
0
295
CLKST
RO
0xFF8
USB Clock Status
0
296
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
329 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.1 Port select register
12.10.1.1 USB Port Select register
This register selects the USB port pins that the USB device signals are routed to.
USBPortSel is a read/write register.
Table 255. USB Port Select register (PORTSEL - address 0x2008 C110) bit description
Bit
Symbol
1:0
PORTSEL
31:2
-
Value Description
Reset value
Selects which USB port the device controller signals are mapped to. Other
values are reserved.
0x0
The USB device controller signals are mapped to the U1 port:
USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1.
0x3
The USB device controller signals are mapped to the U2 port:
USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.
0
Reserved. Read value is undefined, only zero should be written.
NA
12.10.2 Device interrupt registers
12.10.2.1 USB Device Interrupt Status register
The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and
1 indicates the presence of the interrupt. USBDevIntSt is a read-only register.
Table 256. USB Device Interrupt Status register (DEVINTST - address 0x2008 C200) bit description
Bit
Symbol
Description
0
FRAME
The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
0
1
EP_FAST
Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the
corresponding endpoint interrupt will be routed to this bit.
0
2
EP_SLOW
Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set,
the corresponding endpoint interrupt will be routed to this bit.
0
3
DEV_STAT
Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to
Section 12.12.6 “Set Device Status (Command: 0xFE, Data: write 1 byte)” on page 360.
0
4
CCEMPTY
The command code register (USBCmdCode) is empty (New command can be written).
1
5
CDFULL
Command data register (USBCmdData) is full (Data can be read now).
0
6
RxENDPKT
The current packet in the endpoint buffer is transferred to the CPU.
0
7
TxENDPKT
The number of data bytes transferred to the endpoint buffer equals the number of bytes
programmed in the TxPacket length register (USBTxPLen).
0
8
EP_RLZED
Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize
register (USBMaxPSize) is updated and the corresponding operation is completed.
0
9
ERR_INT
Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 12.12.9 “Read
Error Status (Command: 0xFB, Data: read 1 byte)” on page 362
0
31:10 -
UM10562
User manual
Reset
value
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
330 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.2.2 USB Device Interrupt Enable register
Writing a one to a bit in this register enables the corresponding bit in USBDevIntSt to
generate an interrupt on one of the interrupt lines when set. By default, the interrupt is
routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME
interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of
USBDevIntPri. USBDevIntEn is a read/write register.
Table 257. USB Device Interrupt Enable register (DEVINTEN - address 0x2008 C204) bit description
Bit
Symbol
Description
Reset
value
0
FRAMEEN
0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
1
EP_FASTEN
0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
2
EP_SLOWEN
0
0 = No interrupt is generated.
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
3
DEV_STATEN 0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
4
CCEMPTYEN
0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
5
CDFULLEN
0
0 = No interrupt is generated.
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
6
RxENDPKTEN 0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
7
0
TxENDPKTEN 0 = No interrupt is generated.
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
331 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Table 257. USB Device Interrupt Enable register (DEVINTEN - address 0x2008 C204) bit description
Bit
Symbol
Description
Reset
value
8
EP_RLZEDEN 0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256)) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
9
ERR_INTEN
0 = No interrupt is generated.
0
1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status
(DevIntSt) register (Table 256) is set. By default, the interrupt is routed to the
USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may
be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
31:10 -
Reserved
-
12.10.2.3 USB Device Interrupt Clear register
Writing one to a bit in this register clears the corresponding bit in USBDevIntSt. Writing a
zero has no effect. USBDevIntClr is a write-only register.
Remark: Before clearing the EP_SLOW or EP_FAST interrupt bits, the corresponding
endpoint interrupts in USBEpIntSt should be cleared.
Table 258. USB Device Interrupt Clear register (DEVINTCLR - address 0x2008 C208) bit description
Bit
Symbol
Description
0
FRAMECLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
1
EP_FASTCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
2
EP_SLOWCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
3
DEV_STATCLR
0 = No effect.
4
CCEMPTYCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
5
CDFULLCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
6
RxENDPKTCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
7
TxENDPKTCLR
0 = No effect.
8
EP_RLZEDCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
9
ERR_INTCLR
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is cleared.
31:10 -
UM10562
User manual
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
332 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.2.4 USB Device Interrupt Set register
Writing one to a bit in this register sets the corresponding bit in the USBDevIntSt. Writing a
zero has no effect. USBDevIntSet is a write-only register.
Table 259. USB Device Interrupt Set register (DEVINTSET - address 0x2008 C20C) bit description
Bit
Symbol
Description
0
FRAMESET
0 = No effect.
1
EP_FASTSET
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
2
EP_SLOWSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
3
DEV_STATSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
4
CCEMPTYSET
0 = No effect.
5
CDFULLSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
6
RxENDPKTSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
7
TxENDPKTSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
8
EP_RLZEDSET
0 = No effect.
9
ERR_INTSET
0 = No effect.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
1 = The corresponding bit in USBDevIntSt (Section 12.10.2.1) is set.
31:10 -
UM10562
User manual
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
333 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.2.5 USB Device Interrupt Priority register
Writing one to a bit in this register causes the corresponding interrupt to be routed to the
USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the
USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed
to USB_INT_REQ_HP, but not both. If the software attempts to set both bits to one, no
interrupt will be routed to USB_INT_REQ_HP. USBDevIntPri is a write-only register.
Table 260. USB Device Interrupt Priority register (DEVINTPRI - address 0x2008 C22C) bit description
Bit
Symbol
0
FRAME
1
31:2
Value Description
Frame interrupt routing
0
FRAME interrupt is routed to USB_INT_REQ_LP.
1
FRAME interrupt is routed to USB_INT_REQ_HP.
EP_FAST
-
UM10562
User manual
Reset value
Fast endpoint interrupt routing
0
EP_FAST interrupt is routed to USB_INT_REQ_LP.
1
EP_FAST interrupt is routed to USB_INT_REQ_HP.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
-
© NXP B.V. 2012. All rights reserved.
334 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.3 Endpoint interrupt registers
The registers in this group facilitate handling of endpoint interrupts. Endpoint interrupts are
used in Slave mode operation.
Table 261. USB Endpoint registers bit allocation
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
31
30
29
28
27
26
25
24
EPx31 =
EP15TX
EPx30 =
EP15RX
EPx29 =
EP14TX
EPx28 =
EP14RX
EPx27 =
EP13TX
EPx26 =
EP13RX
EPx25 =
EP12TX
EPx24 =
EP12RX
23
22
21
20
19
18
17
16
EPx23 =
EP11TX
EPx22 =
EP11RX
EPx21 =
EP10TX
EPx20 =
EP10RX
EPx19 =
EP9TX
EPx18 =
EP9RX
EPx17 =
EP8TX
EPx16 =
EP8RX
15
14
13
12
11
10
9
8
EPx15 =
EP7TX
EPx14 =
EP7RX
EPx13 =
EP6TX
EPx12 =
EP6RX
EPx11 =
EP5TX
EPx10 =
EP5RX
EPx9 =
EP4TX
EPx8 =
EP4RX
7
6
5
4
3
2
1
0
EPx7 =
EP3TX
EPx6 =
EP3RX
EPx5 =
EP2TX
EPx4 =
EP2RX
EPx3 =
EP1TX
EPx2 =
EP1RX
EPx1 =
EP0TX
EPx0 =
EP0RX
12.10.3.1 USB Endpoint Interrupt Status register
Each physical non-isochronous endpoint is represented by a bit in this register to indicate
that it has generated an interrupt. All non-isochronous OUT endpoints generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet is successfully transmitted, or when a NAK
handshake is sent on the bus and the interrupt on NAK feature is enabled (see
Section 12.12.3 “Set Mode (Command: 0xF3, Data: write 1 byte)” on page 358). A bit set
to one in this register causes either the EP_FAST or EP_SLOW bit of USBDevIntSt to be
set depending on the value of the corresponding bit of USBEpDevIntPri. USBEpIntSt is a
read-only register.
Note that for Isochronous endpoints, handling of packet data is done when the FRAME
interrupt occurs.
Table 262. USB Endpoint Interrupt Status register (EPINTST - address 0x2008 C230) bit description
Bit
Symbol
Description
31:0
EPST
1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31)
Interrupt received.
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
335 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.3.2 USB Endpoint Interrupt Enable register
Setting a bit to 1 in this register causes the corresponding bit in USBEpIntSt to be set
when an interrupt occurs for the associated endpoint. Setting a bit to 0 causes the
corresponding bit in USBDMARSt to be set when an interrupt occurs for the associated
endpoint. USBEpIntEn is a read/write register.
Table 263. USB Endpoint Interrupt Enable register (EPINTEN - address 0x2008 C234) bit description
Bit
Symbol
Description
Reset
value
31:0
EPEN
0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint.
0
1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this
endpoint. Implies Slave mode for this endpoint.
12.10.3.3 USB Endpoint Interrupt Clear register
Writing a one to this a bit in this register causes the SIE Select Endpoint/Clear Interrupt
command to be executed (Table 304) for the corresponding physical endpoint. Writing
zero has no effect. Before executing the Select Endpoint/Clear Interrupt command, the
CDFULL bit in USBDevIntSt is cleared by hardware. On completion of the command, the
CDFULL bit is set, USBCmdData contains the status of the endpoint, and the
corresponding bit in USBEpIntSt is cleared.
Notes:
• When clearing interrupts using USBEpIntClr, software should wait for CDFULL to be
set to ensure the corresponding interrupt has been cleared before proceeding.
• While setting multiple bits in USBEpIntClr simultaneously is possible, it is not
recommended; only the status of the endpoint corresponding to the least significant
interrupt bit cleared will be available at the end of the operation.
• Alternatively, the SIE Select Endpoint/Clear Interrupt command can be directly
invoked using the SIE command registers, but using USBEpIntClr is recommended
because of its ease of use.
Each physical endpoint has its own reserved bit in this register. The bit field definition is
the same as that of EpIntSt shown in Table 262. EpIntClr is a write-only register.
Table 264. USB Endpoint Interrupt Clear register (EPINTCLR - address 0x2008 C238) bit
description
Bit
Symbol
Description
31:0
EPCLR
0 = No effect.
1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select
Endpoint/Clear Interrupt command for this endpoint.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
336 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.3.4 USB Endpoint Interrupt Set register
Writing a one to a bit in this register sets the corresponding bit in USBEpIntSt. Writing zero
has no effect. Each endpoint has its own bit in this register. USBEpIntSet is a write-only
register.
Table 265. USB Endpoint Interrupt Set register (EPINTSET - address 0x2008 C23C) bit
description
Bit
Symbol
Description
31:0
EPSET
0 = No effect.
1 = Sets the corresponding bit in USBEpIntSt.
12.10.3.5 USB Endpoint Interrupt Priority register
This register determines whether an endpoint interrupt is routed to the EP_FAST or
EP_SLOW bits of USBDevIntSt. If a bit in this register is set to one, the interrupt is routed
to EP_FAST, if zero it is routed to EP_SLOW. Routing of multiple endpoints to EP_FAST
or EP_SLOW is possible.
Note that the USBDevIntPri register determines whether the EP_FAST interrupt is routed
to the USB_INT_REQ_HP or USB_INT_REQ_LP interrupt line.
USBEpIntPri is a write-only register.
Table 266. USB Endpoint Interrupt Priority register (EPINTPRI - address 0x2008 C240) bit description
Bit
Symbol
31:0
EPPRI
Description
Reset value
0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt
0
1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
337 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.4 Endpoint realization registers
The registers in this group allow realization and configuration of endpoints at run time.
12.10.4.1 EP RAM requirements
The USB device controller uses a RAM based FIFO for each endpoint buffer. The RAM
dedicated for this purpose is called the Endpoint RAM (EP_RAM). Each endpoint has
space reserved in the EP_RAM. The EP_RAM space required for an endpoint depends
on its MaxPacketSize and whether it is double buffered. 32 words of EP_RAM are used by
the device for storing the endpoint buffer pointers. The EP_RAM is word aligned but the
MaxPacketSize is defined in bytes hence the RAM depth has to be adjusted to the next
word boundary. Also, each buffer has one word header showing the size of the packet
length received.
The EP_ RAM space (in words) required for the physical endpoint can be expressed as
MaxPacketSize + 3
EPRAMspace =  -------------------------------------------------- + 1  dbstatus


4
where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint.
Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is
N
TotalEPRAMspace = 32 +

EPRAMspace  n 
n=0
where N is the number of realized endpoints. Total EP_RAM space should not exceed
4096 bytes (4 kB, 1 kwords).
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
338 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.4.2 USB Realize Endpoint register
Writing one to a bit in this register causes the corresponding endpoint to be realized.
Writing zeros causes it to be unrealized. This register returns to its reset state when a bus
reset occurs. USBReEp is a read/write register.
Table 267. USB Realize Endpoint register (REEP - address 0x2008 C244) bit description
Bit
Symbol
Description
31:0
EPR
0 = Endpoint EPxx is not realized.
Reset value
0
1 = Endpoint EPxx is realized.
On reset, only the control endpoints are realized. Other endpoints, if required, are realized
by programming the corresponding bits in USBReEp. To calculate the required EP_RAM
space for the realized endpoints, see Section 12.10.4.1.
Realization of endpoints is a multi-cycle operation. Pseudo code for endpoint realization is
shown below.
Clear EP_RLZED bit in USBDevIntSt;
for every endpoint to be realized,
{
/* OR with the existing value of the Realize Endpoint register */
USBReEp |= (UInt32) ((0x1 << endpt));
/* Load Endpoint index Reg with physical endpoint no.*/
USBEpIn = (UInt32) endpointnumber;
/* load the max packet size Register */
USBEpMaxPSize = MPS;
/* check whether the EP_RLZED bit in the Device Interrupt Status register is set
*/
while (!(USBDevIntSt & EP_RLZED))
{
/* wait until endpoint realization is complete */
}
/* Clear the EP_RLZED bit */
Clear EP_RLZED bit in USBDevIntSt;
}
The device will not respond to any transactions to unrealized endpoints. The SIE
Configure Device command will only cause realized and enabled endpoints to respond to
transactions. For details see Table 299.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
339 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.4.3 USB Endpoint Index register
Each endpoint has a register carrying the MaxPacketSize value for that endpoint. This is
in fact a register array. Hence before writing, this register is addressed through the
USBEpIn register.
The USBEpIn register will hold the physical endpoint number. Writing to USBMaxPSize
will set the array element pointed to by USBEpIn. USBEpIn is a write-only register.
Table 268. USB Endpoint Index register (EPIN - address 0x2008 C248) bit description
Bit
Symbol
Description
Reset value
4:0
PHY_EP
Physical endpoint number (0-31)
31:5
-
Reserved. Read value is undefined, only zero should be written.
0
NA
12.10.4.4 USB MaxPacketSize register
On reset, the control endpoint is assigned the maximum packet size of 8 bytes. Other
endpoints are assigned 0. Modifying USBMaxPSize will cause the endpoint buffer
addresses within the EP_RAM to be recalculated. This is a multi-cycle process. At the
end, the EP_RLZED bit will be set in USBDevIntSt (Table 256). USBMaxPSize array
indexing is shown in Figure 42. USBMaxPSize is a read/write register.
Table 269. USB MaxPacketSize register (MAXPSIZE - address 0x2008 C24C) bit description
Bit
Symbol
Description
9:0
MPS
The maximum packet size value.
31:10 -
Reset value
0x008[1]
Reserved. Read value is undefined, only zero should be written.
[1]
NA
Reset value for EP0 and EP1. All other endpoints have a reset value of 0x0.
MPS_EP0
ENDPOINT INDEX
MPS_EP31
The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the
USBMaxPSize register.
Fig 42. USB MaxPacketSize register array indexing
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
340 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.5 USB transfer registers
The registers in this group are used for transferring data between endpoint buffers and
RAM in Slave mode operation. See Section 12.14 “Slave mode operation”.
12.10.5.1 USB Receive Data register
For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before
reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register
should be set appropriately. On reading this register, data from the selected endpoint
buffer is fetched. The data is in little endian format: the first byte received from the USB
bus will be available in the least significant byte of USBRxData. USBRxData is a read-only
register.
Table 270. USB Receive Data register (RXDATA - address 0x2008 C218) bit description
Bit
Symbol
Description
31:0
RX_DATA
Data received.
Reset value
0
12.10.5.2 USB Receive Packet Length register
This register contains the number of bytes remaining in the endpoint buffer for the current
packet being read via the USBRxData register, and a bit indicating whether the packet is
valid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the
USBCtrl register should be set appropriately. This register is updated on each read of the
USBRxData register. USBRxPLen is a read-only register.
Table 271. USB Receive Packet Length register (RXPLEN - address 0x2008 C220) bit description
Bit
Symbol
9:0
PKT_LNGTH
10
DV
11
PKT_RDY
31:12 -
UM10562
User manual
Value Description
-
Reset value
The remaining number of bytes to be read from the currently selected
endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be
set in USBDevIntSt.
0
Data valid. This bit is useful for isochronous endpoints. Non-isochronous
endpoints do not raise an interrupt when an erroneous data packet is
received. But invalid data packet can be produced with a bus reset. For
isochronous endpoints, data transfer will happen even if an erroneous packet
is received. In this case DV bit will not be set for the packet.
0
0
Data is invalid.
1
Data is valid.
The PKT_LNGTH field is valid and the packet is ready for reading.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
341 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.5.3 USB Transmit Data register
For an IN transaction, the CPU writes the endpoint data into this register. Before writing to
this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be
set appropriately, and the packet length should be written to the USBTxPlen register. On
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write-only register.
Table 272. USB Transmit Data register (TXDATA - address 0x2008 C21C) bit description
Bit
Symbol
Description
31:0
TX_DATA
Transmit Data.
12.10.5.4 USB Transmit Packet Length register
This register contains the number of bytes transferred from the CPU to the selected
endpoint buffer. Before writing data to USBTxData, software should first write the packet
length (MaxPacketSize) to this register. After each write to USBTxData, hardware
decrements USBTxPLen by 4. The WR_EN bit and LOG_ENDPOINT field of the USBCtrl
register should be set to select the desired endpoint buffer before starting this process.
For data buffers larger than the endpoint’s MaxPacketSize, software should submit data in
packets of MaxPacketSize, and send the remaining extra bytes in the last packet. For
example, if the MaxPacketSize is 64 bytes and the data buffer to be transferred is of
length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes
in the last packet. So, a total of 3 packets are sent on USB. USBTxPLen is a write-only
register.
Table 273. USB Transmit Packet Length register (TXPLEN - address 0x2008 C224) bit description
Bit
Symbol
Description
9:0
PKT_LNGTH
The remaining number of bytes to be written to the selected endpoint buffer. This field
is decremented by 4 by hardware after each write to USBTxData. When this field
decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
31:10 -
UM10562
User manual
Reset value
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
342 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.5.5 USB Control register
This register controls the data transfer operation of the USB device. It selects the endpoint
buffer that is accessed by the USBRxData and USBTxData registers, and enables
reading and writing them. USBCtrl is a read/write register.
Table 274. USB Control register (CTRL - address 0x2008 C228) bit description
Bit
Symbol
0
RD_EN
1
Value Description
Reset value
Read mode control. Enables reading data from the OUT endpoint buffer
for the endpoint specified in the LOG_ENDPOINT field using the
USBRxData register. This bit is cleared by hardware when the last word of
the current packet is read from USBRxData.
0
Disabled.
1
Enabled.
WR_EN
Write mode control. Enables writing data to the IN endpoint buffer for the
endpoint specified in the LOG_ENDPOINT field using the USBTxData
register. This bit is cleared by hardware when the number of bytes in
USBTxLen have been sent.
0
Disabled.
1
Enabled.
5:2
LOG_ENDPOINT
Logical Endpoint number.
31:6
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
0
NA
© NXP B.V. 2012. All rights reserved.
343 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.6 SIE command code registers
The SIE command code registers are used for communicating with the Serial Interface
Engine. See Section 12.12 “Serial interface engine command description” for more
information.
12.10.6.1 USB Command Code register
This register is used for sending the command and write data to the SIE. The commands
written here are propagated to the SIE and executed there. After executing the command,
the register is empty, and the CCEMPTY bit of USBDevIntSt register is set. See
Section 12.12 for details. USBCmdCode is a write-only register.
Table 275. USB Command Code register (CMDCODE - address 0x2008 C210) bit description
Bit
Symbol
Value
Description
7:0
-
Reserved. Read value is undefined, only zero should be written.
15:8
CMD_PHASE
The command phase:
0x02
Read
0x01
Write
0x05
Command
23:16 CMD_CODE_WDATA
This is a multi-purpose field. When CMD_PHASE is Command or Read, this field
contains the code for the command (CMD_CODE). When CMD_PHASE is Write,
this field contains the command write data (CMD_WDATA).
31:24 -
Reserved. Read value is undefined, only zero should be written.
12.10.6.2 USB Command Data register
This register contains the data retrieved after executing a SIE command. When the data is
ready to be read, the CD_FULL bit of the USBDevIntSt register is set. See Table 256 for
details. USBCmdData is a read-only register.
Table 276. USB Command Data register (CMDDATA - address 0x2008 C214) bit description
Bit
Symbol
Description
7:0
CMD_RDATA
Command Read Data.
31:8
-
Reserved. The value read from a reserved bit is not defined.
UM10562
User manual
Reset value
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
344 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7 DMA registers
The registers in this group are used for the DMA mode of operation (see Section 12.15
“DMA operation”)
12.10.7.1 USB DMA Request Status register
A bit in this register associated with a non-isochronous endpoint is set by hardware when
an endpoint interrupt occurs (see the description of USBEpIntSt) and the corresponding
bit in USBEpIntEn is 0. A bit associated with an isochronous endpoint is set when the
corresponding bit in USBEpIntEn is 0 and a FRAME interrupt occurs. A set bit serves as a
flag for the DMA engine to start the data transfer if the DMA is enabled for the
corresponding endpoint in the USBEpDMASt register. The DMA cannot be enabled for
control endpoints (EP0 and EP1). USBDMARSt is a read-only register.
Table 277. USB DMA Request Status register (DMARST - address 0x2008 C250) bit description
Bit
Symbol Description
Reset
value
0
EPRST0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
0
1
EPRST1 Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).
0
31:2
EPRST
Endpoint xx (2 xx 31) DMA request.
0
0 = DMA not requested by endpoint xx.
1 = DMA requested by endpoint xx.
[1]
DMA can not be enabled for this endpoint and the corresponding bit in the USBDMARSt must be 0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
345 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.2 USB DMA Request Clear register
Writing one to a bit in this register will clear the corresponding bit in the USBDMARSt
register. Writing zero has no effect.
This register is intended for initialization prior to enabling the DMA for an endpoint. When
the DMA is enabled for an endpoint, hardware clears the corresponding bit in
USBDMARSt on completion of a packet transfer. Therefore, software should not clear the
bit using this register while the endpoint is enabled for DMA operation.
USBDMARClr is a write-only register.
The USBDMARClr bit allocation is identical to the USBDMARSt register (Table 277).
Table 278. USB DMA Request Clear register (DMARCLR - address 0x2008 C254) bit description
Bit
Symbol
Description
0
EPRCLR0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
1
EPRCLR1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
31:2
EPRCLR
Clear the endpoint xx (2 xx 31) DMA request.
0 = No effect
1 = Clear the corresponding bit in USBDMARSt.
12.10.7.3 USB DMA Request Set register
Writing one to a bit in this register sets the corresponding bit in the USBDMARSt register.
Writing zero has no effect.
This register allows software to raise a DMA request. This can be useful when switching
from Slave to DMA mode of operation for an endpoint: if a packet to be processed in DMA
mode arrives before the corresponding bit of USBEpIntEn is cleared, the DMA request is
not raised by hardware. Software can then use this register to manually start the DMA
transfer.
Software can also use this register to initiate a DMA transfer to proactively fill an IN
endpoint buffer before an IN token packet is received from the host.
USBDMARSet is a write-only register.
The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 277).
Table 279. USB DMA Request Set register (DMARSET - address 0x2008 C258) bit description
Bit
Symbol
0
EPRSET0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
Description
1
EPRSET1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
31:2
EPRSET
Set the endpoint xx (2 xx 31) DMA request.
0 = No effect
1 = Set the corresponding bit in DMARSt.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
346 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.4 USB UDCA Head register
The UDCA (USB Device Communication Area) Head register maintains the address
where the UDCA is located in the RAM. Refer to Section 12.15.2 “USB device
communication area” and Section 12.15.4 “The DMA descriptor” for more details on the
UDCA and DMA descriptors. UDCAH is a read/write register.
Table 280. USB UDCA Head register (UDCAH - address 0x2008 C280) bit description
Bit
Symbol
Description
6:0
-
Reserved. Read value is undefined, only zero should be written. The UDCA is
aligned to 128-byte boundaries.
Reset value
0
31:7
UDCA_ADDR
Start address of the UDCA.
0
12.10.7.5 USB EP DMA Status register
Bits in this register indicate whether DMA operation is enabled for the corresponding
endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in
this register. EpDMASt is a read-only register.
Table 281. USB EP DMA Status register (EPDMAST - address 0x2008 C284) bit description
Bit
Symbol
Description
Reset value
0
EP_DMA_ST0
Control endpoint OUT (DMA cannot be enabled for this endpoint and the
EP0_DMA_ENABLE bit must be 0).
0
1
EP_DMA_ST1
Control endpoint IN (DMA cannot be enabled for this endpoint and the
EP1_DMA_ENABLE bit must be 0).
0
31:2
EP_DMA_ST
Endpoint xx (2 xx 31) DMA enabled bit.
0
0 = The DMA for endpoint EPxx is disabled.
1 = The DMA for endpoint EPxx is enabled.
12.10.7.6 USB EP DMA Enable register
Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. EpDMAEn is a write-only register.
Table 282. USB EP DMA Enable register (EPDMAEN - address 0x2008 C288) bit description
Bit
Symbol
Description
0
EP_DMA_EN0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit
value must be 0).
1
EP_DMA_EN1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit
must be 0).
31:2
EP_DMA_EN
Endpoint xx(2 xx 31) DMA enable control bit.
0 = No effect.
1 = Enable the DMA operation for endpoint EPxx.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
347 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.7 USB EP DMA Disable register
Writing a one to a bit in this register clears the corresponding bit in EpDMASt. Writing zero
has no effect on the corresponding bit of EpDMASt. Any write to this register clears the
internal DMA_PROCEED flag. Refer to Section 12.15.5.4 “Optimizing descriptor fetch” for
more information on the DMA_PROCEED flag. If a DMA transfer is in progress for an
endpoint when its corresponding bit is cleared, the transfer is completed before the DMA
is disabled. When an error condition is detected during a DMA transfer, the corresponding
bit is cleared by hardware. EpDMADis is a write-only register.
Table 283. USB EP DMA Disable register (EPDMADIS - address 0x2008 C28C) bit description
Bit
Symbol
Description
0
EP_DMA_DIS0 Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit
value must be 0).
1
EP_DMA_DIS1 Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit
value must be 0).
31:2
EP_DMA_DIS
Endpoint xx (2 xx 31) DMA disable control bit.
0 = No effect.
1 = Disable the DMA operation for endpoint EPxx.
12.10.7.8 USB DMA Interrupt Status register
Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. DMAIntSt is a read-only register.
Table 284. USB DMA Interrupt Status register (DMAINTST - address 0x2008 C290) bit description
Bit
Symbol
0
EOT
1
2
Value Description
End of Transfer Interrupt bit.
0
All bits in the EoTIntSt register are 0.
1
At least one bit in the EoTIntSt is set.
NDDR
New DD Request Interrupt bit.
0
All bits in the NDDRIntSt register are 0.
1
At least one bit in the NDDRIntSt is set.
ERR
System Error Interrupt bit.
0
1
31:3
-
UM10562
User manual
Reset value
0
0
0
All bits in the SysErrIntSt register are 0.
At least one bit in the SysErrIntSt is set.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
348 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.9 USB DMA Interrupt Enable register
Writing a one to a bit in this register enables the corresponding bit in DMAIntSt to generate
an interrupt on the USB_INT_REQ_DMA interrupt line when set. DMAIntEn is a read/write
register.
Table 285. USB DMA Interrupt Enable register (DMAINTEN - address 0x2008 C294) bit description
Bit
Symbol
0
EOT
Value Description
0
1
1
2
31:3
NDDR
0
Disabled.
Enabled.
New DD Request Interrupt enable bit.
0
Disabled.
1
Enabled.
0
Disabled.
1
Enabled.
ERR
-
Reset value
End of Transfer Interrupt enable bit.
0
System Error Interrupt enable bit.
0
Reserved. Read value is undefined, only zero should be written.
NA
12.10.7.10 USB End of Transfer Interrupt Status register
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
EoTIntSt is a read-only register.
Table 286. USB End of Transfer Interrupt Status register (EOTINTST - address 0x2008 C2A0) bit description
Bit
Symbol
Description
31:0
EPTXINTST
Endpoint xx (2 xx 31) End of Transfer Interrupt request.
Reset value
0
0 = There is no End of Transfer interrupt request for endpoint xx.
1 = There is an End of Transfer Interrupt request for endpoint xx.
12.10.7.11 USB End of Transfer Interrupt Clear register
Writing one to a bit in this register clears the corresponding bit in the EoTIntSt register.
Writing zero has no effect. EoTIntClr is a write-only register.
Table 287. USB End of Transfer Interrupt Clear register (EOTINTCLR - address 0x2008 C2A4) bit description
Bit
Symbol
Description
31:0
EPTXINTCLR
Clear endpoint xx (2 xx 31) End of Transfer Interrupt request.
0 = No effect.
1 = Clear the EPxx End of Transfer Interrupt request in the EoTIntSt register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
349 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.12 USB End of Transfer Interrupt Set register
Writing one to a bit in this register sets the corresponding bit in the EoTIntSt register.
Writing zero has no effect. EoTIntSet is a write-only register.
Table 288. USB End of Transfer Interrupt Set register (EOTINTSET - address 0x2008 C2A8) bit description
Bit
Symbol
Description
31:0
EPTXINTSET
Set endpoint xx (2 xx 31) End of Transfer Interrupt request.
0 = No effect.
1 = Set the EPxx End of Transfer Interrupt request in the EoTIntSt register.
12.10.7.13 USB New DD Request Interrupt Status register
A bit in this register is set when a transfer is requested from the USB device and no valid
DD is detected for the corresponding endpoint. NDDRIntSt is a read-only register.
Table 289. USB New DD Request Interrupt Status register (NDDRINTST - address 0x2008 C2AC) bit description
Bit
Symbol
Description
Reset value
31:0
EPNDDINTST
Endpoint xx (2 xx 31) new DD interrupt request.
0
0 = There is no new DD interrupt request for endpoint xx.
1 = There is a new DD interrupt request for endpoint xx.
12.10.7.14 USB New DD Request Interrupt Clear register
Writing one to a bit in this register clears the corresponding bit in the NDDRIntSt register.
Writing zero has no effect. NDDRIntClr is a write-only register.
Table 290. USB New DD Request Interrupt Clear register (NDDRINTCLR - address 0x2008 C2B0) bit description
Bit
Symbol
Description
31:0
EPNDDINTCLR
Clear endpoint xx (2 xx 31) new DD interrupt request.
0 = No effect.
1 = Clear the EPxx new DD interrupt request in the NDDRIntSt register.
12.10.7.15 USB New DD Request Interrupt Set register
Writing one to a bit in this register sets the corresponding bit in the NDDRIntSt register.
Writing zero has no effect. NDDRIntSet is a write-only register
Table 291. USB New DD Request Interrupt Set register (NDDRINTSET - address 0x2008 C2B4) bit description
Bit
Symbol
Description
31:0
EPNDDINTSET
Set endpoint xx (2 xx 31) new DD interrupt request.
0 = No effect.
1 = Set the EPxx new DD interrupt request in the NDDRIntSt register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
350 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.7.16 USB System Error Interrupt Status register
If a system error (AHB bus error) occurs when transferring the data or when fetching or
updating the DD the corresponding bit is set in this register. SysErrIntSt is a read-only
register.
Table 292. USB System Error Interrupt Status register (SYSERRINTST - address 0x2008 C2B8) bit description
Bit
Symbol
Description
31:0
EPERRINTST
Endpoint xx (2 xx 31) System Error Interrupt request.
Reset value
0
0 = There is no System Error Interrupt request for endpoint xx.
1 = There is a System Error Interrupt request for endpoint xx.
12.10.7.17 USB System Error Interrupt Clear register
Writing one to a bit in this register clears the corresponding bit in the SysErrIntSt register.
Writing zero has no effect. SysErrIntClr is a write-only register.
Table 293. USB System Error Interrupt Clear register (SYSERRINTCLR - address 0x2008 C2BC) bit description
Bit
Symbol
Description
31:0
EPERRINTCLR
Clear endpoint xx (2 xx 31) System Error Interrupt request.
0 = No effect.
1 = Clear the EPxx System Error Interrupt request in the SysErrIntSt register.
12.10.7.18 USB System Error Interrupt Set register
Writing one to a bit in this register sets the corresponding bit in the SysErrIntSt register.
Writing zero has no effect. SysErrIntSet is a write-only register.
Table 294. USB System Error Interrupt Set register (SYSERRINTSET - address 0x2008 C2C0) bit description
Bit
Symbol
Description
31:0
EPERRINTSET
Set endpoint xx (2 xx 31) System Error Interrupt request.
0 = No effect.
1 = Set the EPxx System Error Interrupt request in the SysErrIntSt register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
351 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.10.8 Clock control registers
12.10.8.1 USB Clock Control register
This register controls the clocking of the USB Device Controller. Whenever software
wants to access the device controller registers, both DEV_CLK_EN and AHB_CLK_EN
must be set. The PORTSEL_CLK_EN bit need only be set when accessing the PortSel
register.
The software does not have to repeat this exercise for every register access, provided that
the corresponding ClkCtrl bits are already set. Note that this register is functional only
when the PCUSB bit of PCONP is set; when PCUSB is cleared, all clocks to the device
controller are disabled irrespective of the contents of this register. ClkCtrl is a read/write
register.
Table 295. ClkCtrl register (CLKCTRL - address 0x2008 CFF4) bit description
Bit
Symbol
Description
Reset value
0
-
Reserved. Read value is undefined, only zero should be written.
1
DEV_CLK_EN
Device clock enable. Enables the usbclk input to the device controller
2
-
Reserved. Read value is undefined, only zero should be written.
NA
3
PORTSEL_CLK_EN
Port select register clock enable.
NA
4
AHB_CLK_EN
AHB clock enable
31:5
-
Reserved. Read value is undefined, only zero should be written.
NA
0
0
NA
12.10.8.2 USB Clock Status register
This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via ClkCtrl, software should
poll the corresponding bit in ClkSt. If it is set, then software can go ahead with the register
access. Software does not have to repeat this exercise for every access, provided that the
ClkCtrl bits are not disturbed. ClkSt is a read-only register.
Table 296. USB Clock Status register (CLKST - address 0x2008 CFF8) bit description
Bit
Symbol
Description
Reset value
0
-
Reserved. Read value is undefined, only zero should be written.
1
DEV_CLK_ON
Device clock on. The usbclk input to the device controller is active.
2
-
Reserved. Read value is undefined, only zero should be written.
NA
3
PORTSEL_CLK_ON
Port select register clock on.
NA
4
AHB_CLK_ON
AHB clock on.
31:5
-
Reserved. The value read from a reserved bit is not defined.
UM10562
User manual
NA
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
352 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.11 Interrupt handling
This section describes how an interrupt event on any of the endpoints is routed to the
Nested Vectored Interrupt Controller (NVIC). For a diagram showing interrupt event
handling, see Figure 43.
All non-isochronous OUT endpoints (control, bulk, and interrupt endpoints) generate an
interrupt when they receive a packet without an error. All non-isochronous IN endpoints
generate an interrupt when a packet has been successfully transmitted or when a NAK
signal is sent and interrupts on NAK are enabled by the SIE Set Mode command, see
Section 12.12.3. For isochronous endpoints, a frame interrupt is generated every 1 ms.
The interrupt handling is different for Slave and DMA mode.
Slave mode
If an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the
EpIntEn register, the corresponding status bit in the EpIntSt is set. For non-isochronous
endpoints, all endpoint interrupt events are divided into two types by the corresponding
EpIntPri[n] registers: fast endpoint interrupt events and slow endpoint interrupt events. All
fast endpoint interrupt events are ORed and routed to bit EP_FAST in the DevIntSt
register. All slow endpoint interrupt events are ORed and routed to the EP_SLOW bit in
DevIntSt.
For isochronous endpoints, the FRAME bit in DevIntSt is set every 1 ms.
The DevIntSt register holds the status of all endpoint interrupt events as well as the status
of various other interrupts (see Section 12.10.2.1). By default, all interrupts (if enabled in
DevIntEn) are routed to the USB_INT_REQ_LP bit in the IntSt register to request low
priority interrupt handling. However, the DevIntPri register can route either the FRAME or
the EP_FAST bit to the USB_INT_REQ_HP bit in the IntSt register.
Only one of the EP_FAST and FRAME interrupt events can be routed to the
USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both
interrupt events are routed to USB_INT_REQ_LP.
Slow endpoint interrupt events are always routed directly to the USB_INT_REQ_LP bit for
low priority interrupt handling by software.
The final interrupt signal to the NVIC is gated by the EN_USB_INTS bit in the IntSt
register. The USB interrupts are routed to the NVIC only if EN_USB_INTS is set.
DMA mode
If an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not
enabled in the EpIntEn register, the corresponding status bit in the DMARSt is set by
hardware. This serves as a flag for the DMA engine to transfer data if DMA transfer is
enabled for the corresponding endpoint in the EpDMASt register.
Three types of interrupts can occur for each endpoint for data transfers in DMA mode: End
of transfer interrupt, new DD request interrupt, and system error interrupt. These interrupt
events set a bit for each endpoint in the respective registers EoTIntSt, NDDRIntSt, and
SysErrIntSt. The End of transfer interrupts from all endpoints are then ORed and routed to
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
353 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
the EOT bit in DMAIntSt. Likewise, all New DD request interrupts and system error
interrupt events are routed to the NDDR and ERR bits respectively in the DMAStInt
register.
The EOT, NDDR, and ERR bits (if enabled in DMAIntEn) are ORed to set the
USB_INT_REQ_DMA bit in the IntSt register. If the EN_USB_INTS bit is set in IntSt, the
interrupt is routed to the NVIC.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
354 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
interrupt
event on
EPn
Slave mode
USBEpIntSt
from other
Endpoints
.
.
.
.
FRAME
EP_FAST
EP_SLOW
.
.
.
.
n
USBEpIntEn[n]
USBDevIntSt
USBDevIntPri[0]
.
.
.
.
.
.
.
.
.
USBEpIntPri[n] ..
.
.
.
.
.
USBDevIntPri[1]
ERR_INT
USBIntSt
USBDMARSt
USB_INT_REQ_HP
USB_INT_REQ_LP
USB_INT_REQ_DMA
to NVIC
to DMA engine
n
EN_USB_INTS
USBEoTIntST
DMA Mode
0
.
.
.
.
31
USBNDDRIntSt
0
USBDMAIntSt
.
.
.
.
EOT
NDDR
ERR
31
USBSysErrIntSt
0
.
.
.
.
31
For simplicity, DevIntEn and DMAIntEn are not shown.
Fig 43. Interrupt event handling
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
355 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12 Serial interface engine command description
The functions and registers of the Serial Interface Engine (SIE) are accessed using
commands, which consist of a command code followed by optional data bytes (read or
write action). The CmdCode (Table 275) and CmdData (Table 276) registers are used for
these accesses.
A complete access consists of two phases:
1. Command phase: the CmdCode register is written with the CMD_PHASE field set to
the value 0x05 (Command), and the CMD_CODE field set to the desired command
code. On completion of the command, the CCEMPTY bit of DevIntSt is set.
2. Data phase (optional): for writes, the CmdCode register is written with the
CMD_PHASE field set to the value 0x01 (Write), and the CMD_WDATA field set with
the desired write data. On completion of the write, the CCEMPTY bit of DevIntSt is
set. For reads, CmdCode register is written with the CMD_PHASE field set to the
value 0x02 (Read), and the CMD_CODE field set with command code the read
corresponds to. On completion of the read, the CDFULL bit of DevInSt will be set,
indicating the data is available for reading in the CmdData register. In the case of
multi-byte registers, the least significant byte is accessed first.
An overview of the available commands is given in Table 297.
Here is an example of the Read Current Frame Number command (reading 2 bytes):
DevIntClr = 0x30;
CmdCode = 0x00F50500;
while (!(DevIntSt & 0x10));
DevIntClr = 0x10;
CmdCode = 0x00F50200;
while (!(DevIntSt & 0x20));
DevIntClr = 0x20;
CurFrameNum = CmdData;
CmdCode = 0x00F50200;
while (!(DevIntSt & 0x20));
Temp = CmdData;
DevIntClr = 0x20;
CurFrameNum = CurFrameNum |
// Clear both CCEMPTY & CDFULL
// CMD_CODE=0xF5, CMD_PHASE=0x05(Command)
// Wait for CCEMPTY.
// Clear CCEMPTY interrupt bit.
// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
// Wait for CDFULL.
// Clear CDFULL.
// Read Frame number LSB byte.
// CMD_CODE=0xF5, CMD_PHASE=0x02(Read)
// Wait for CDFULL.
// Read Frame number MSB byte
// Clear CDFULL interrupt bit.
(Temp << 8);
Here is an example of the Set Address command (writing 1 byte):
DevIntClr = 0x10;
CmdCode = 0x00D00500;
while (!(DevIntSt & 0x10));
DevIntClr = 0x10;
CmdCode = 0x008A0100;
Clear CCEMPTY.
CMD_CODE=0xD0, CMD_PHASE=0x05(Command)
Wait for CCEMPTY.
Clear CCEMPTY.
CMD_WDATA=0x8A(DEV_EN=1, DEV_ADDR=0xA),
// CMD_PHASE=0x01(Write)
while (!(DevIntSt & 0x10)); // Wait for CCEMPTY.
DevIntClr = 0x10;
// Clear CCEMPTY.
UM10562
User manual
//
//
//
//
//
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
356 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Table 297. SIE command code table
Command name
Recipient
Code (Hex) Data phase
Set Address
Device
D0
Write 1 byte
Configure Device
Device
D8
Write 1 byte
Set Mode
Device
F3
Write 1 byte
Read Current Frame Number
Device
F5
Read 1 or 2 bytes
Read Test Register
Device
FD
Read 2 bytes
Set Device Status
Device
FE
Write 1 byte
Get Device Status
Device
FE
Read 1 byte
Get Error Code
Device
FF
Read 1 byte
Read Error Status
Device
FB
Read 1 byte
Endpoint 0
00
Read 1 byte (optional)
Device commands
Endpoint Commands
Select Endpoint
Endpoint 1
01
Read 1 byte (optional)
Endpoint xx
xx
Read 1 byte (optional)
Select Endpoint/Clear Interrupt Endpoint 0
40
Read 1 byte
Endpoint 1
41
Read 1 byte
Set Endpoint Status
Endpoint xx
xx  40
Read 1 byte
Endpoint 0
40
Write 1 byte
Endpoint 1
41
Write 1 byte
Endpoint xx
xx  40
Write 1 byte
Clear Buffer
Selected Endpoint F2
Read 1 byte (optional)
Validate Buffer
Selected Endpoint FA
None
12.12.1 Set Address (Command: 0xD0, Data: write 1 byte)
The Set Address command is used to set the USB assigned address and enable the
(embedded) function. The address set in the device will take effect after the status stage
of the control transaction. After a bus reset, DEV_ADDR is set to 0x00, and DEV_EN is
set to 1. The device will respond to packets for function address 0x00, endpoint 0 (default
endpoint).
Table 298. Set Address command bit description
Bit
Symbol
Description
Reset value
6:0
DEV_ADDR
Device address set by the software. After a bus reset this field is set to 0x00.
0
7
DEV_EN
Device Enable. After a bus reset this bit is set to 1.
0
0: Device will not respond to any packets.
1: Device will respond to packets for function address DEV_ADDR.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
357 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.2 Configure Device (Command: 0xD8, Data: write 1 byte)
A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled and
respond even if the device is not configured, in the default state.
Table 299. Configure Device command bit description
Bit
Symbol
Description
Reset value
0
CONF_DEVICE
Device is configured. All enabled non-control endpoints will respond. This bit is
cleared by hardware when a bus reset occurs. When set, the UP_LED signal is
driven LOW if the device is not in the suspended state (SUS=0).
7:1
-
Reserved. Read value is undefined, only zero should be written.
0
NA
12.12.3 Set Mode (Command: 0xF3, Data: write 1 byte)
Table 300. Set Mode command bit description
Bit
Symbol
0
AP_CLK
1
2
3
4
5
6
7
Value Description
Always PLL Clock.
USB_NEED_CLK is functional; the 48 MHz clock can be stopped when the
device enters suspend state.
1
USB_NEED_CLK is fixed to 1; the 48 MHz clock cannot be stopped when the
device enters suspend state.
Interrupt on NAK for Control IN endpoint.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed IN transactions generate interrupts.
INAK_CO
0
Interrupt on NAK for Control OUT endpoint.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed OUT transactions generate interrupts.
INAK_II
0
Interrupt on NAK for Interrupt IN endpoint.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed IN transactions generate interrupts.
INAK_IO[1]
0
Interrupt on NAK for Interrupt OUT endpoints.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed OUT transactions generate interrupts.
INAK_BI
0
Interrupt on NAK for Bulk IN endpoints.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed IN transactions generate interrupts.
0
Only successful transactions generate an interrupt.
1
Both successful and NAKed OUT transactions generate interrupts.
INAK_BO[2]
0
Interrupt on NAK for Bulk OUT endpoints.
-
User manual
0
0
INAK_CI
UM10562
Reset value
0
Reserved. Read value is undefined, only zero should be written.
NA
[1]
This bit should be reset to 0 if the DMA is enabled for any of the Interrupt OUT endpoints.
[2]
This bit should be reset to 0 if the DMA is enabled for any of the Bulk OUT endpoints.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
358 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2
bytes)
Returns the frame number of the last successfully received SOF. The frame number is
eleven bits wide. The frame number returns least significant byte first. In case the user is
only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
• In case no SOF was received by the device at the beginning of a frame, the frame
number returned is that of the last successfully received SOF.
• In case the SOF frame number contained a CRC error, the frame number returned will
be the corrupted frame number as received by the device.
12.12.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
The test register is 16 bits wide. It returns the value of 0xA50F if the USB clocks (usbclk
and AHB slave clock) are running.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
359 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
The Set Device Status command sets bits in the Device Status Register.
Table 301. Set Device Status command bit description
Bit
Symbol
0
CON
1
2
3
Value Description
Reset
value
The Connect bit indicates the current connect status of the device. It controls the
CONNECT output pin, used for SoftConnect. Reading the connect bit returns the current
connect status. This bit is cleared by hardware when the VBUS status input is LOW for
more than 3 ms. The 3 ms delay filters out temporary dips in the VBUS voltage.
0
Writing a 0 will make the CONNECT pin go HIGH.
1
Writing a 1 will make the CONNECT pin go LOW.
CON_CH
Connect Change.
0
0
This bit is cleared when read.
1
This bit is set when the device’s pull-up resistor is disconnected because VBUS
disappeared. The DEV_STAT interrupt is generated when this bit is 1.
SUS
Suspend: The Suspend bit represents the current suspend state.
When the device is suspended (SUS = 1) and the CPU writes a 0 into it, the device will
generate a remote wake-up. This will only happen when the device is connected
(CON = 1). When the device is not connected or not suspended, writing a 0 has no effect.
Writing a 1 to this bit has no effect.
0
This bit is reset to 0 on any activity.
1
This bit is set to 1 when the device hasn’t seen any activity on its upstream port for more
than 3 ms.
SUS_CH
Suspend (SUS) bit change indicator. The SUS bit can toggle because:
•
•
•
0
0
0
The device goes into the suspended state.
The device is disconnected.
The device receives resume signalling on its upstream port.
This bit is cleared when read.
4
0
SUS bit not changed.
1
SUS bit changed. At the same time a DEV_STAT interrupt is generated.
RST
Bus Reset bit. On a bus reset, the device will automatically go to the default state. In the
default state:
•
•
•
•
•
•
•
•
0
Device is unconfigured.
Will respond to address 0.
Control endpoint will be in the Stalled state.
All endpoints are unrealized except control endpoints EP0 and EP1.
Data toggling is reset for all endpoints.
All buffers are cleared.
There is no change to the endpoint interrupt status.
DEV_STAT interrupt is generated.
Note: Bus resets are ignored when the device is not connected (CON=0).
7:5
-
UM10562
User manual
0
This bit is cleared when read.
1
This bit is set when the device receives a bus reset. A DEV_STAT interrupt is generated.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
360 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.7 Get Device Status (Command: 0xFE, Data: read 1 byte)
The Get Device Status command returns the Device Status Register. Reading the device
status returns 1 byte of data. The bit field definition is same as the Set Device Status
Register as shown in Table 301.
Remark: To ensure correct operation, the DEV_STAT bit of DevIntSt must be cleared
before executing the Get Device Status command.
12.12.8 Get Error Code (Command: 0xFF, Data: read 1 byte)
Different error conditions can arise inside the SIE. The Get Error Code command returns
the last error code that occurred. The 4 least significant bits form the error code.
Table 302. Get Error Code command bit description
Bit
Symbol
3:0
EC
4
EA
7:5
-
UM10562
User manual
Value
Description
Reset value
Error Code.
0
0000
No Error.
0001
PID Encoding Error.
0010
Unknown PID.
0011
Unexpected Packet - any packet sequence violation from the specification.
0100
Error in Token CRC.
0101
Error in Data CRC.
0110
Time Out Error.
0111
Babble.
1000
Error in End of Packet.
1001
Sent/Received NAK.
1010
Sent Stall.
1011
Buffer Overrun Error.
1100
Sent Empty Packet (ISO Endpoints only).
1101
Bitstuff Error.
1110
Error in Sync.
1111
Wrong Toggle Bit in Data PID, ignored data.
-
The Error Active bit will be reset once this register is read.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
361 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
This command reads the 8-bit Error register from the USB device. This register records
which error events have recently occurred in the SIE. If any of these bits are set, the
ERR_INT bit of DevIntSt is set. The error bits are cleared after reading this register.
Table 303. Read Error Status command bit description
Bit
Symbol
Description
0
PID_ERR
PID encoding error or Unknown PID or Token CRC.
0
1
UEPKT
Unexpected Packet - any packet sequence violation from the specification.
0
2
DCRC
Data CRC error.
0
3
TIMEOUT
Time out error.
0
4
EOP
End of packet error.
0
5
B_OVRN
Buffer Overrun.
0
6
BTSTF
Bit stuff error.
0
7
TGL_ERR
Wrong toggle bit in data PID, ignored data.
0
UM10562
User manual
Reset value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
362 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
The Select Endpoint command initializes an internal pointer to the start of the selected
buffer in EP_RAM. Optionally, this command can be followed by a data read, which
returns some additional information on the packet(s) in the endpoint buffer(s). The
command code of the Select Endpoint command is equal to the physical endpoint
number. In the case of a single buffered endpoint the B_2_FULL bit is not valid.
Table 304. Select Endpoint command bit description
Bit
Symbol
0
FE
1
2
3
4
5
6
7
Value Description
Full/Empty. This bit indicates the full or empty status of the endpoint buffer(s). For IN
endpoints, the FE bit gives the ANDed result of the B_1_FULL and B_2_FULL bits.
For OUT endpoints, the FE bit gives ORed result of the B_1_FULL and B_2_FULL
bits. For single buffered endpoints, this bit simply reflects the status of B_1_FULL.
0
For an IN endpoint, at least one write endpoint buffer is empty.
1
For an OUT endpoint, at least one endpoint read buffer is full.
ST
Stalled endpoint indicator.
0
The selected endpoint is not stalled.
1
The selected endpoint is stalled.
STP
0
The STP bit is cleared by doing a Select Endpoint/Clear Interrupt on this endpoint.
1
The last received packet for the selected endpoint was a SETUP packet.
0
The PO bit is cleared by the ‘Select Endpoint/Clear Interrupt’ command.
1
The previously received packet was over-written by a SETUP packet.
Packet over-written bit.
EPN
0
The EPN bit is reset after the device has sent an ACK after an OUT packet or when
the device has seen an ACK after sending an IN packet.
1
The EPN bit is set when a NAK is sent and the interrupt on NAK feature is enabled.
The buffer 1 status.
0
Buffer 1 is empty.
1
Buffer 1 is full.
B_2_FULL
UM10562
User manual
Buffer 2 is empty.
1
Buffer 2 is full.
0
0
The buffer 2 status.
0
0
0
EP NAKed bit indicates sending of a NAK. If the host sends an OUT packet to a
filled OUT buffer, the device returns NAK. If the host sends an IN token packet to an
empty IN buffer, the device returns NAK.
B_1_FULL
0
0
SETUP bit: the value of this bit is updated after each successfully received packet
(i.e. an ACKed package on that particular physical endpoint).
PO
-
Reset value
0
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
363 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1
byte)
Commands 0x40 to 0x5F are identical to their Select Endpoint equivalents, with the
following differences:
• They clear the bit corresponding to the endpoint in the EpIntSt register.
• In case of a control OUT endpoint, they clear the STP and PO bits in the
corresponding Select Endpoint Register.
• Reading one byte is obligatory.
Remark: This command may be invoked by using the CmdCode and CmdData registers,
or by setting the corresponding bit in EpIntClr. For ease of use, using the EpIntClr register
is recommended.
12.12.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte
(optional))
The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The
Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical
endpoint number in hex. Not all bits can be set for all types of endpoints.
Table 305. Set Endpoint Status command bit description
Bit
Symbol
0
ST
4:1
-
5
DA
6
7
Value Description
Stalled endpoint bit. A Stalled control endpoint is automatically unstalled when it
receives a SETUP token, regardless of the content of the packet. If the endpoint
should stay in its stalled state, the CPU can stall it again by setting this bit. When a
stalled endpoint is unstalled - either by the Set Endpoint Status command or by
receiving a SETUP token - it is also re-initialized. This flushes the buffer: in case of an
OUT buffer it waits for a DATA 0 PID; in case of an IN buffer it writes a DATA 0 PID.
There is no change of the interrupt status of the endpoint. When already unstalled,
writing a zero to this bit initializes the endpoint. When an endpoint is stalled by the
Set Endpoint Status command, it is also re-initialized.
0
The endpoint is unstalled.
1
The endpoint is stalled.
Reserved. Read value is undefined, only zero should be written.
User manual
0
The endpoint is enabled.
1
The endpoint is disabled.
Rate Feedback Mode.
0
0
Interrupt endpoint is in the Toggle mode.
1
Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes
place without data toggle bit.
CND_ST
0
NA
Disabled endpoint bit.
0
RF_MO
UM10562
Reset value
Conditional Stall bit.
0
0
Unstalls both control endpoints.
1
Stall both control endpoints, unless the STP bit is set in the Select Endpoint register.
It is defined only for control OUT endpoints.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
364 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.12.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
When an OUT packet sent by the host has been received successfully, an internal
hardware FIFO status Buffer_Full flag is set. All subsequent packets will be refused by
returning a NAK. When the device software has read the data, it should free the buffer by
issuing the Clear Buffer command. This clears the internal Buffer_Full flag. When the
buffer is cleared, new packets will be accepted.
When bit 0 of the optional data byte is 1, the previously received packet was over-written
by a SETUP packet. The Packet over-written bit is used only in control transfers.
According to the USB specification, a SETUP packet should be accepted irrespective of
the buffer status. The software should always check the status of the PO bit after reading
the SETUP data. If it is set then it should discard the previously read data, clear the PO bit
by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and
again check the status of the PO bit.
See Section 12.14 “Slave mode operation” for a description of when this command is
used.
Table 306. Clear Buffer command bit description
Bit
Symbol
0
PO
7:1
-
Value Description
Reset value
Packet over-written bit. This bit is only applicable to the control endpoint EP0.
0
The previously received packet is intact.
1
The previously received packet was over-written by a later SETUP packet.
Reserved. Read value is undefined, only zero should be written.
0
NA
12.12.14 Validate Buffer (Command: 0xFA, Data: none)
When the CPU has written data into an IN buffer, software should issue a Validate Buffer
command. This tells hardware that the buffer is ready for sending on the USB bus.
Hardware will send the contents of the buffer when the next IN token packet is received.
Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See Section 12.14 “Slave mode operation” for a description of when this command is
used.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
365 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.13 USB device controller initialization
The USB device controller initialization includes the following steps:
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk and
the desired frequency for cclk. For the procedure for determining the PLL setting and
configuration, see Section 3.10.5 “Procedure for determining PLL settings”.
3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits
in the ClkCtrl register. Poll the respective clock bits in the ClkSt register until they are
set.
4. Select the desired USB port pins using the PortSel register. The PORTSEL_CLK_EN
bit must be set in ClkCtrl before accessing PortSel and should be cleared after
accessing PortSel.
5. Enable the USB pin functions by writing to the corresponding IOCON registers.
6. Disable the pull-ups and pull-downs on the VBUS pin using the corresponding IOCON
register by putting the pin in the “plain-input” mode. See Section 7.4.1 “I/O
configuration register contents (IOCON)”.
7. Set EpIn and MaxPSize registers for EP0 and EP1, and wait until the EP_RLZED bit
in DevIntSt is set so that EP0 and EP1 are realized.
8. Enable endpoint interrupts (Slave mode):
– Clear all endpoint interrupts using EpIntClr.
– Clear any device interrupts using DevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
EpIntEn.
– Set the priority of each enabled interrupt using EpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using DevIntEn (normally DEV_STAT, EP_SLOW, and
possibly EP_FAST).
9. Configure the DMA (DMA mode):
– Disable DMA operation for all endpoints using EpDMADis.
– Clear any pending DMA requests using DMARClr.
– Clear all DMA interrupts using EoTIntClr, NDDRIntClr, and SysErrIntClr.
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to UDCAH.
– Enable the desired endpoints for DMA operation using EpDMAEn.
– Set EOT, DDR, and ERR bits in DMAIntEn.
10. Install USB interrupt handler in the NVIC by writing its address to the appropriate
vector table location and enabling the USB interrupt in the NVIC.
11. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
command. A bus reset will also cause this to happen.
12. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
command.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
366 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
367 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.14 Slave mode operation
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.
12.14.1 Interrupt generation
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the EpIntEn
register, and are observable in the EpIntSt register.
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
DevIntSt) occurs.
12.14.2 Data transfer for OUT endpoints
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the Ctrl
register. The control logic will fetch the packet length to the RxPLen register, and set the
PKT_RDY bit (Table 271).
Software can now start reading the data from the RxData register (Table 270). When the
end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in the
DevSt register. Software now issues a Clear Buffer (refer to Table 306) command. The
endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the next
packet will be received irrespective of whether the buffer has been cleared. Any data not
read from the buffer before the end of the frame is lost. See Section 12.16 “Double
buffered endpoint operation” for more details.
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
12.14.3 Data transfer for IN endpoints
When writing data to an endpoint buffer, WR_EN (Section 12.10.5.5 “USB Control
register”) is set and software writes to the number of bytes it is going to send in the packet
to the TxPLen register (Section 12.10.5.4). It can then write data continuously in the
TxData register.
When the number of bytes programmed in TxPLen have been written to TxData, the
WR_EN bit is cleared, and the TxENDPKT bit is set in the DevIntSt register. Software
issues a Validate Buffer (Section 12.12.14 “Validate Buffer (Command: 0xFA, Data:
none)”) command. The endpoint is now ready to send the packet. For IN isochronous
endpoints, the data in the buffer will be sent only if the buffer is validated before the next
FRAME interrupt occurs; otherwise, an empty packet will be sent in the next frame. If the
software clears WR_EN before the entire packet is written, writing will start again from the
beginning the next time WR_EN is set for this endpoint.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
368 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
369 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.15 DMA operation
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections Section 12.15.2 “USB device communication area” and Section 12.15.3
“Triggering the DMA engine”. The fields of the DMA Descriptor are described in
Section 12.15.4 “The DMA descriptor”. The last three sections describe DMA operation:
Section 12.15.5 “Non-isochronous endpoint operation”, Section 12.15.6 “Isochronous
endpoint operation”, and Section 12.15.7 “Auto Length Transfer Extraction (ATLE) mode
operation”.
12.15.1 Transfer terminology
Within this section three types of transfers are mentioned:
1. USB transfers – transfer of data over the USB bus. The USB 2.0 specification refers
to these simply as transfers. Within this section they are referred to as USB transfers
to distinguish them from DMA transfers. A USB transfer is composed of transactions.
Each transaction is composed of packets.
2. DMA transfers – the transfer of data between an endpoint buffer and system memory
(RAM).
3. Packet transfers – in this section, a packet transfer refers to the transfer of a packet of
data between an endpoint buffer and system memory (RAM). A DMA transfer is
composed of one or more packet transfers.
12.15.2 USB device communication area
The CPU and DMA controller communicate through a common area of memory, called the
USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA
Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP
points to the start address of a DMA Descriptor, if one is defined for the endpoint. DDPs
for unrealized endpoints and endpoints disabled for DMA operation are ignored and can
be set to a NULL (0x0) value.
The start address of the UDCA is stored in the UDCAH register. The UDCA can reside at
any 128-byte boundary of RAM that is accessible to both the CPU and DMA controller.
Figure 44 illustrates the UDCA and its relationship to the UDCA Head (UDCAH) register
and DMA Descriptors.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
370 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
UDCA
0
NULL
NULL
1
NULL
Next_DD_pointer
Next_DD_pointer
Next_DD_pointer
DD-EP2-a
DD-EP2-b
DD-EP2-c
2
DDP-EP2
NULL
UDCA HEAD
REGISTER
NULL
Next_DD_pointer
Next_DD_pointer
DD-EP16-a
DD-EP16-b
16
DDP-EP16
31
DDP-EP31
Fig 44. UDCA Head register and DMA Descriptors
12.15.3 Triggering the DMA engine
An endpoint raises a DMA request when Slave mode is disabled by setting the
corresponding bit in the EpIntEn register to 0 (Section 12.10.3.2) and an endpoint
interrupt occurs (see Section 12.10.7.1 “USB DMA Request Status register”).
A DMA transfer for an endpoint starts when the endpoint is enabled for DMA operation in
EpDMASt, the corresponding bit in DMARSt is set, and a valid DD is found for the
endpoint.
All endpoints share a single DMA channel to minimize hardware overhead. If more than
one DMA request is active in DMARSt, the endpoint with the lowest physical endpoint
number is processed first.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command
(Section 12.12.3).
12.15.4 The DMA descriptor
DMA transfers are described by a data structure called the DMA Descriptor (DD).
DDs are placed in RAM. These descriptors can be located anywhere in on-chip RAM at
word-aligned addresses.
DDs for non-isochronous endpoints are four words long. DDs for isochronous endpoints
are five words long.
The parameters associated with a DMA transfer are:
• The start address of the DMA buffer
• The length of the DMA buffer
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
371 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
•
•
•
•
The start address of the next DMA descriptor
Control information
Count information (number of bytes transferred)
Status information
Table 307 lists the DMA descriptor fields.
Table 307. DMA descriptor
Word
position
Access
(H/W)
Access
(S/W)
Bit
position
0
R
R/W
31:0
Next_DD_pointer
1
Description
R
R/W
1:0
DMA_mode (00 -Normal; 01 - ATLE)
R
R/W
2
Next_DD_valid (1 - valid; 0 - invalid)
-
-
3
Reserved. Read value is undefined, only zero should be written.
R
R/W
4
Isochronous_endpoint (1 - isochronous; 0 - non-isochronous)
R
R/W
15:5
R/W[1]
R/W
31:16
Max_packet_size
DMA_buffer_length
This value is specified in bytes for non-isochronous endpoints and in
number of packets for isochronous endpoints.
2
R/W
R/W
31:0
3
R/W
R/I
0
W
R/I
4:1
DMA_buffer_start_addr
DD_retired (To be initialized to 0)
DD_status (To be initialized to 0000):
0000 - NotServiced
0001 - BeingServiced
0010 - NormalCompletion
0011 - DataUnderrun (short packet)
1000 - DataOverrun
1001 - SystemError
4
W
R/I
5
Packet_valid (To be initialized to 0)
W
R/I
6
LS_byte_extracted (ATLE mode) (To be initialized to 0)
W
R/I
7
MS_byte_extracted (ATLE mode) (To be initialized to 0)
R
W
13:8
Message_length_position (ATLE mode)
-
-
15:14
Reserved. Read value is undefined, only zero should be written.
R/W
R/I
31:16
Present_DMA_count (To be initialized to 0)
R/W
R/W
31:0
Isochronous_packetsize_memory_address
[1]
Write-only in ATLE mode
Legend: R - Read; W - Write; I - Initialize
12.15.4.1 Next_DD_pointer
Pointer to the memory location from where the next DMA descriptor will be fetched.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
372 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.15.4.2 DMA_mode
Specifies the DMA mode of operation. Two modes have been defined: Normal and
Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes
the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is
extracted from the incoming data. See Section 12.15.7 “Auto Length Transfer Extraction
(ATLE) mode operation” on page 378 for more details.
12.15.4.3 Next_DD_valid
This bit indicates whether the software has prepared the next DMA descriptor. If set, the
DMA engine fetches the new descriptor when it is finished with the current one.
12.15.4.4 Isochronous_endpoint
When set, this bit indicates that the descriptor belongs to an isochronous endpoint. Hence
5 words have to be read when fetching it.
12.15.4.5 Max_packet_size
The maximum packet size of the endpoint. This parameter is used while transferring the
data for IN endpoints from the memory. It is used for OUT endpoints to detect the short
packet. This is applicable to non-isochronous endpoints only. This field should be set to
the same MPS value that is assigned for the endpoint using the MaxPSize register.
12.15.4.6 DMA_buffer_length
This indicates the depth of the DMA buffer allocated for transferring the data. The DMA
engine will stop using this descriptor when this limit is reached and will look for the next
descriptor.
In Normal mode operation, software sets this value for both IN and OUT endpoints. In
ATLE mode operation, software sets this value for IN endpoints only. For OUT endpoints,
hardware sets this value using the extracted length of the data stream.
For isochronous endpoints, DMA_buffer_length is specified in number of packets, for
non-isochronous endpoints in bytes.
12.15.4.7 DMA_buffer_start_addr
The address where the data is read from or written to. This field is updated each time the
DMA engine finishes transferring a packet.
12.15.4.8 DD_retired
This bit is set by hardware when the DMA engine finishes the current descriptor. This
happens when the end of the buffer is reached, a short packet is transferred
(non-isochronous endpoints), or an error condition is detected.
12.15.4.9 DD_status
The status of the DMA transfer is encoded in this field. The following codes are defined:
• NotServiced - No packet has been transferred yet.
• BeingServiced - At least one packet is transferred.
• NormalCompletion - The DD is retired because the end of the buffer is reached and
there were no errors. The DD_retired bit is also set.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
373 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
• DataUnderrun - Before reaching the end of the DMA buffer, the USB transfer is
terminated because a short packet is received. The DD_retired bit is also set.
• DataOverrun - The end of the DMA buffer is reached in the middle of a packet
transfer. This is an error situation. The DD_retired bit is set. The present DMA count
field is equal to the value of DMA_buffer_length. The packet must be re-transmitted
from the endpoint buffer in another DMA transfer. The corresponding
EPxx_DMA_ENABLE bit in EpDMASt is cleared.
• SystemError - The DMA transfer being serviced is terminated because of an error on
the AHB bus. The DD_retired bit is not set in this case. The corresponding
EPxx_DMA_ENABLE in EpDMASt is cleared. Since a system error can happen while
updating the DD, the DD fields in RAM may be unreliable.
12.15.4.10 Packet_valid
This bit is used for isochronous endpoints. It indicates whether the last packet transferred
to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was
received without errors. See Section 12.15.6 “Isochronous endpoint operation” on page
376 for isochronous endpoint operation.
This bit is unnecessary for non-isochronous endpoints because a DMA request is
generated only for packets without errors, and thus Packet_valid will always be set when
the request is generated.
12.15.4.11 LS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.
12.15.4.12 MS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.
12.15.4.13 Present_DMA_count
The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.
For isochronous endpoints, Present_DMA_count is the number of packets transferred; for
non-isochronous endpoints, Present_DMA_count is the number of bytes.
12.15.4.14 Message_length_position
Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.
12.15.4.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See Figure 45. This is applicable to isochronous
endpoints only.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
374 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.15.5 Non-isochronous endpoint operation
12.15.5.1 Setting up DMA transfers
Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled
for DMA transfer. These DDs are present in on-chip RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the EpDMAEn register (Section 12.10.7.6).The DMA_mode bit field in the descriptor is set
to ‘00’ for normal mode operation. All other DD fields are initialized as specified in
Table 307.
DMA operation is not supported for physical endpoints 0 and 1 (default control endpoints).
12.15.5.2 Finding DMA Descriptor
When there is a trigger for a DMA transfer for an endpoint, the DMA engine will first
determine whether a new descriptor has to the fetched or not. A new descriptor does not
have to be fetched if the last packet transferred was for the same endpoint and the DD is
not yet in the retired state. An internal flag called DMA_PROCEED is used to identify this
condition (see Section 12.15.5.4 “Optimizing descriptor fetch” on page 375).
If a new descriptor has to be read, the DMA engine will calculate the location of the DDP
for this endpoint and will fetch the start address of the DD from this location. A DD start
address at location zero is considered invalid. In this case the NDDR interrupt is raised.
All other word-aligned addresses are considered valid.
When the DD is fetched, the DD status word (word 3) is read first and the status of the
DD_retired bit is checked. If not set, DDP points to a valid DD. If DD_retired is set, the
DMA engine will read the control word (word 1) of the DD.
If Next_DD_valid bit is set, the DMA engine will fetch the Next_DD_pointer field (word 0)
of the DD and load it to the DDP. The new DDP is written to the UDCA area.
The full DD (4 words) will then be fetched from the address in the DDP. The DD will give
the details of the DMA transfer to be done. The DMA engine will load its hardware
resources with the information fetched from the DD (start address, DMA count etc.).
If Next_DD_valid is not set and DD_retired bit is set, the DMA engine raises the NDDR
interrupt for this endpoint and clears the corresponding EPxx_DMA_ENABLE bit.
12.15.5.3 Transferring the data
For OUT endpoints, the current packet is read from the EP_RAM by the DMA Engine and
transferred to on-chip RAM memory locations starting from DMA_buffer_start_addr. For
IN endpoints, the data is fetched from on-chip RAM at DMA_buffer_start_addr and written
to the EP_RAM. The DMA_buffer_start_addr and Present_DMA_count fields are updated
after each packet is transferred.
12.15.5.4 Optimizing descriptor fetch
A DMA transfer normally involves multiple packet transfers. Hardware will not re-fetch a
new DD from memory unless the endpoint changes. To indicate an ongoing multi-packet
transfer, hardware sets an internal flag called DMA_PROCEED.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
375 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
The DMA_PROCEED flag is cleared after the required number of bytes specified in the
DMA_buffer_length field is transferred. It is also cleared when the software writes into the
EpDMADis register. The ability to clear the DMA_PROCEED flag allows software to force
the DD to be re-fetched for the next packet transfer. Writing all zeros into the EpDMADis
register clears the DMA_PROCEED flag without disabling DMA operation for any
endpoint.
12.15.5.5 Ending the packet transfer
On completing a packet transfer, the DMA engine writes back the DD with updated status
information to the same memory location from where it was read. The
DMA_buffer_start_addr, Present_DMA_count, and the DD_status fields in the DD are
updated.
A DD can have the following types of completion:
Normal completion - If the current packet is fully transferred and the
Present_DMA_count field equals the DMA_buffer_length, the DD has completed
normally. The DD will be written back to memory with DD_retired set and DD_status set
to NormalCompletion. The EOT interrupt is raised for this endpoint.
USB transfer end completion - If the current packet is fully transferred and its size is
less than the Max_packet_size field, and the end of the DMA buffer is still not reached,
the USB transfer end completion occurs. The DD will be written back to the memory
with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT
interrupt is raised for this endpoint.
Error completion - If the current packet is partially transferred i.e. the end of the DMA
buffer is reached in the middle of the packet transfer, an error situation occurs. The DD
is written back with DD_retired set and DD_status set to the DataOverrun status code.
The EOT interrupt is raised for this endpoint and the corresponding bit in EpDMASt
register is cleared. The packet will be re-sent from the endpoint buffer to memory when
the corresponding EPxx_DMA_ENABLE bit is set again using the EpDMAEn register.
12.15.5.6 No_Packet DD
For an IN transfer, if the system does not have any data to send for a while, it can respond
to an NDDR interrupt by programming a No_Packet DD. This is done by setting both the
Max_packet_size and DMA_buffer_length fields in the DD to 0. On processing a
No_Packet DD, the DMA engine clears the DMA request bit in DMARSt corresponding to
the endpoint without transferring a packet. The DD is retired with a status code of
NormalCompletion. This can be repeated as often as necessary. The device will respond
to IN token packets on the USB bus with a NAK until a DD with a data packet is
programmed and the DMA transfers the packet into the endpoint buffer.
12.15.6 Isochronous endpoint operation
For isochronous endpoints, the packet size can vary for each packet. There is one packet
per isochronous endpoint for each frame.
12.15.6.1 Setting up DMA transfers
Software sets the isochronous endpoint bit to 1 in the DD, and programs the initial value of
the Isochronous_packetsize_memory_address field. All other fields are initialized the
same as for non-isochronous endpoints.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
376 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
For isochronous endpoints, the DMA_buffer_length and Present_DMA_count fields are in
frames rather than bytes.
12.15.6.2 Finding the DMA Descriptor
Finding the descriptors is done in the same way as that for a non-isochronous endpoint.
A DMA request will be placed for DMA-enabled isochronous endpoints on every FRAME
interrupt. On processing the request, the DMA engine will fetch the descriptor and if
Isochronous_endpoint is set, will fetch the Isochronous_packetsize_memory_address
from the fifth word of the DD.
12.15.6.3 Transferring the Data
The data is transferred to or from the memory location DMA_buffer_start_addr. After the
end of the packet transfer the Present_DMA_count value is incremented by 1.
The isochronous packet size is stored in memory as shown in Figure 45. Each word in the
packet size memory shown is divided into fields: Frame_number (bits 31 to 17),
Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet
size memory for a given DD should be DMA_buffer_length words in size – one word for
each packet to transfer.
OUT endpoints
At the completion of each frame, the packet size is written to the address location in
Isochronous_packet_size_memory_address, and
Isochronous_packet_size_memory_address is incremented by 4.
IN endpoints
Only the Packet_length field of the isochronous packet size word is used. For each frame,
an isochronous data packet of size specified by this field is transferred from the USB
device to the host, and Isochronous_packet_size_memory_address is incremented by 4
at the end of the packet transfer. If Packet_length is zero, an empty packet will be sent by
the USB device.
12.15.6.4 DMA descriptor completion
DDs for isochronous endpoints can only end with a status code of NormalCompletion
since there is no short packet on Isochronous endpoints, and the USB transfer continues
indefinitely until a SystemError occurs. There is no DataOverrun detection for isochronous
endpoints.
12.15.6.5 Isochronous OUT Endpoint Operation Example
Assume that an isochronous endpoint is programmed for the transfer of 10 frames and
that the transfer begins when the frame number is 21. After transferring four frames with
packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map
appear as shown in Figure 45.
The_total_number_of_bytes_transferred = 0x0A + 0x0F + 0x08 + 0x14 = 0x35.
The Packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
377 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
Next_DD_Pointer
W0
NULL
DMA_buffer_length
W1
Max_packet_size
0x000A
Isochronous_endpoint
0x0
Next_DD_Valid
1
DMA_mode
0
0
DMA_buffer_start_addr
W2
0x80000000
Present_DMA_Count
ATLE settings
Packet_Valid
DD_Status
0x0
NA
NA
0x0
DD_Retired
W3
0
Isocronous_packetsize_memory_address
W4
0x60000000
after 4 packets
W0
0x0
W1
0x000A0010
FULL
0x80000035
W2
W3
0x4
- -
0x1
0
frame_ number Packet_Valid Packet_Length
W4
0x60000010
31
15
16
21
22
23
24
1
1
1
1
0
EMPTY
10
15
8
20
data memory
packet size memory
Fig 45. Isochronous OUT endpoint operation example
12.15.7 Auto Length Transfer Extraction (ATLE) mode operation
Some host drivers such as NDIS (Network Driver Interface Specification) host drivers are
capable of concatenating small USB transfers (delta transfers) to form a single large USB
transfer. For OUT USB transfers, the device hardware has to break up this concatenated
transfer back into the original delta transfers and transfer them to separate DMA buffers.
This is achieved by setting the DMA mode to Auto Transfer Length Extraction (ATLE)
mode in the DMA descriptor. ATLE mode is supported for Bulk endpoints only.
OUT transfers in ATLE mode
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
378 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
data to be sent
data in packets
data to be stored in
by host driver
as seen on USB
RAM by DMA engine
160 bytes
64 bytes
DMA_buffer_start_addr
of DD1
160 bytes
64 bytes
32 bytes
32 bytes
100 bytes
100 bytes
64 bytes
DMA_buffer_start_addr
of DD2
4 bytes
Fig 46. Data transfer in ATLE mode
Figure 46 shows a typical OUT USB transfer in ATLE mode, where the host concatenates
two USB transfers of 160 bytes and 100 bytes, respectively. Given a MaxPacketSize of
64, the device hardware interprets this USB transfer as four packets of 64 bytes and a
short packet of 4 bytes. The third and fourth packets are concatenated. Note that in
Normal mode, the USB transfer would be interpreted as packets of 64, 64, 32, and 64 and
36 bytes.
It is now the responsibility of the DMA engine to separate these two USB transfers and put
them in the memory locations in the DMA_buffer_start_addr field of DMA Descriptor 1
(DD1) and DMA Descriptor 2 (DD2).
Hardware reads the two-byte-wide DMA_buffer_length at the offset (from the start of the
USB transfer) specified by Message_length_position from the incoming data packets and
writes it in the DMA_buffer_length field of the DD. To ensure that both bytes of the
DMA_buffer_length are extracted in the event they are split between two packets, the
flags LS_byte_extracted and MS_byte_extracted are set by hardware after the respective
byte is extracted. After the extraction of the MS byte, the DMA transfer continues as in the
normal mode.
The flags LS_byte_extracted and MS_byte_extracted are set to 0 by software when
preparing a new DD. Therefore, once a DD is retired, the transfer length is extracted again
for the next DD.
If DD1 is retired during the transfer of a concatenated packet (such as the third packet in
Figure 46), and DD2 is not programmed (Next_DD_valid field of DD1 is 0), then DD1 is
retired with DD_status set to the DataOverrun status code. This is treated as an error
condition and the corresponding EPxx_DMA_ENABLE bit of EpDMASt is cleared by
hardware.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
379 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
In ATLE mode, the last buffer length to be transferred always ends with a short or empty
packet indicating the end of the USB transfer. If the concatenated transfer lengths are
such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host
will send an empty packet to mark the end of the USB transfer.
IN transfers in ATLE mode
For IN USB transfers from the device to the host, DMA_buffer_length is set by the device
software as in normal mode.
In ATLE mode, the device concatenates data from multiple DDs to form a single USB
transfer. If a DD is retired in the middle of a packet (packet size is less than
MaxPacketSize), the next DD referenced by Next_DD_pointer is fetched, and the
remaining bytes to form a packet of MaxPacketSize are transferred from the next DD’s
buffer.
If the next DD is not programmed (i.e. Next_DD_valid field in DD is 0), and the DMA buffer
length for the current DD has completed before the MaxPacketSize packet boundary, then
the available bytes from current DD are sent as a short packet on USB, which marks the
end of the USB transfer for the host.
If the last buffer length completes on a MaxPacketSize packet boundary, the device
software must program the next DD with DMA_buffer_length field 0, so that an empty
packet is sent by the device to mark the end of the USB transfer for the host.
12.15.7.1 Setting up the DMA transfer
For OUT endpoints, the host hardware needs to set the field Message_length_position in
the DD. This indicates the start location of the message length in the incoming data
packets. Also the device software has to set the DMA_buffer_length field to 0 for OUT
endpoints because this field is updated by the device hardware after the extraction of the
buffer length.
For IN endpoints, descriptors are set in the same way as in normal mode operation.
Since a single packet can be split between two DDs, software should always keep two
DDs ready, except for the last DMA transfer which ends with a short or empty packet.
12.15.7.2 Finding the DMA Descriptor
DMA descriptors are found in the same way as the normal mode operation.
12.15.7.3 Transferring the Data
OUT endpoints
If the LS_byte_extracted or MS_byte_extracted bit in the status field is not set, the
hardware will extract the transfer length from the data stream and program
DMA_buffer_length. Once the extraction is complete both the LS_byte_extracted and
MS_byte_extracted bits will be set.
IN endpoints
The DMA transfer proceeds as in normal mode and continues until the number of bytes
transferred equals the DMA_buffer_length.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
380 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.15.7.4 Ending the packet transfer
The DMA engine proceeds with the transfer until the number of bytes specified in the field
DMA_buffer_length is transferred to or from on-chip RAM. Then the EOT interrupt will be
generated. If this happens in the middle of the packet, the linked DD will get loaded and
the remaining part of the packet gets transferred to or from the address pointed by the
new DD.
OUT endpoints
If the linked DD is not valid and the packet is partially transferred to memory, the DD ends
with DataOverrun status code set, and the DMA will be disabled for this endpoint.
Otherwise DD_status will be updated with the NormalCompletion status code.
IN endpoints
If the linked DD is not valid and the packet is partially transferred to USB, the DD ends
with a status code of NormalCompletion in the DD_status field. This situation corresponds
to the end of the USB transfer, and the packet will be sent as a short packet. Also, when
the linked DD is valid and buffer length is 0, an empty packet will be sent to indicate the
end of the USB transfer.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
381 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
12.16 Double buffered endpoint operation
The Bulk and Isochronous endpoints of the USB Device Controller are double buffered to
increase data throughput.
When a double-buffered endpoint is realized, enough space for both endpoint buffers is
automatically allocated in the EP_RAM. See Section 12.10.4.1.
For the following discussion, the endpoint buffer currently accessible to the CPU or DMA
engine for reading or writing is said to be the active buffer.
12.16.1 Bulk endpoints
For Bulk endpoints, the active endpoint buffer is switched by the SIE Clear Buffer or
Validate Buffer commands.
The following example illustrates how double buffering works for a Bulk OUT endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty, and that the active buffer is
B_1.
1. The host sends a data packet to the endpoint. The device hardware puts the packet
into B_1, and generates an endpoint interrupt.
2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
While B_1 is still being read, the host sends a second packet, which device hardware
places in B_2, and generates an endpoint interrupt.
3. Software is still reading from B_1 when the host attempts to send a third packet. Since
both B_1 and B_2 are full, the device hardware responds with a NAK.
4. Software finishes reading the first packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
5. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. Software finds that the active buffer (B_2) has data
(FE=1). Software clears the endpoint interrupt and begins reading the contents of
B_2.
6. The host re-sends the third packet which device hardware places in B_1. An endpoint
interrupt is generated.
7. Software finishes reading the second packet from B_2 and sends a SIE Clear Buffer
command to free B_2 to receive another packet. B_1 becomes the active buffer.
Software waits for the next endpoint interrupt to occur (it already has been generated
back in step 6).
8. Software responds to the endpoint interrupt by clearing it and begins reading the third
packet from B_1.
9. Software finishes reading the third packet from B_1 and sends a SIE Clear Buffer
command to free B_1 to receive another packet. B_2 becomes the active buffer.
10. Software tests the FE bit and finds that the active buffer (B_2) is empty (FE=0).
11. Both B_1 and B_2 are empty. Software waits for the next endpoint interrupt to occur.
The active buffer is now B_2. The next data packet sent by the host will be placed in
B_2.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
382 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
The following example illustrates how double buffering works for a Bulk IN endpoint in
Slave mode:
Assume that both buffer 1 (B_1) and buffer 2 (B_2) are empty and that the active buffer is
B_1. The interrupt on NAK feature is enabled.
1. The host requests a data packet by sending an IN token packet. The device responds
with a NAK and generates an endpoint interrupt.
2. Software clears the endpoint interrupt. The device has three packets to send.
Software fills B_1 with the first packet and sends a SIE Validate Buffer command. The
active buffer is switched to B_2.
3. Software sends the SIE Select Endpoint command to read the Select Endpoint
Register and test the FE bit. It finds that B_2 is empty (FE=0) and fills B_2 with the
second packet. Software sends a SIE Validate Buffer command, and the active buffer
is switched to B_1.
4. Software waits for the endpoint interrupt to occur.
5. The device successfully sends the packet in B_1 and clears the buffer. An endpoint
interrupt occurs.
6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and
validates it using the SIE Validate Buffer command. The active buffer is switched to
B_2.
7. The device successfully sends the second packet from B_2 and generates an
endpoint interrupt.
8. Software has no more packets to send, so it simply clears the interrupt.
9. The device successfully sends the third packet from B_1 and generates an endpoint
interrupt.
10. Software has no more packets to send, so it simply clears the interrupt.
11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by
software will go into B_2.
In DMA mode, switching of the active buffer is handled automatically in hardware. For
Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double
buffering can be accomplished by manually starting a packet transfer using the DMARSet
register.
12.16.2 Isochronous endpoints
For isochronous endpoints, the active data buffer is switched by hardware when the
FRAME interrupt occurs. The SIE Clear Buffer and Validate Buffer commands do not
cause the active buffer to be switched.
Double buffering allows the software to make full use of the frame interval writing or
reading a packet to or from the active buffer, while the packet in the other buffer is being
sent or received on the bus.
For an OUT isochronous endpoint, any data not read from the active buffer before the end
of the frame is lost when it switches.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
383 of 942
UM10562
NXP Semiconductors
Chapter 12: LPC408x/407x USB device controller
For an IN isochronous endpoint, if the active buffer is not validated before the end of the
frame, an empty packet is sent on the bus when the active buffer is switched, and its
contents will be overwritten when it becomes active again.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
384 of 942
UM10562
Chapter 13: LPC408x/407x USB Host controller
Rev. 1 — 13 September 2012
User manual
13.1 How to read this chapter
This chapter describes the USB host controller which is present on some LPC408x/407x
devices (see Section 1.4 for details). On these devices, the USB controller can be
configured for device, Host, or OTG operation.
13.2 Basic configuration
The USB controller is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCUSB.
Remark: On reset, the USB block is disabled (PCUSB = 0).
2. Clock: The USB block can be used with the Alt PLL (PLL1) to obtain the USB clock or
with the Main PLL (PLL0). See Section 3.10.
3. Pins: Select USB pins and their modes in the relevant IOCON registers
(Section 7.4.1).
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
Power-down mode, see Section 3.12.8.
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. Initialization: see Section 14.11.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
385 of 942
UM10562
NXP Semiconductors
Chapter 13: LPC408x/407x USB Host controller
13.3 Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller, and I2C interface. The
I2C interface controls the external OTG ATX.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
Table 308. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation
Description
AHB
Advanced High-Performance Bus
ATX
Analog Transceiver
DMA
Direct Memory Access
FS
Full Speed
LS
Low Speed
OHCI
Open Host Controller Interface
USB
Universal Serial Bus
13.3.1 Features
• OHCI compliant.
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
386 of 942
UM10562
NXP Semiconductors
Chapter 13: LPC408x/407x USB Host controller
13.3.2 Architecture
The architecture of the USB host controller is shown below in Figure 47.
register
interface
(AHB slave)
REGISTER
INTERFACE
U1
port
USB
ATX
AHB bus
port 1
DMA interface
(AHB master)
HOST
CONTROLLER
port 2
BUS
MASTER
INTERFACE
ATX
CONTROL
LOGIC/
PORT
MUX
USB
ATX
U2
port
USB HOST BLOCK
Fig 47. USB Host controller block diagram
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
387 of 942
UM10562
NXP Semiconductors
Chapter 13: LPC408x/407x USB Host controller
13.4 Interfaces
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.
13.4.1 Pin description
Table 309. USB OTG port pins
Pin name
VBUS
Direction
I
Description
Pin category
VBUS status input. When this function is not enabled via
its corresponding IOCON register, it is driven HIGH
internally.
USB Connector
Port U1
USB_D+1
I/O
Positive differential data
USB Connector
USB_D1
I/O
Negative differential data
USB Connector
USB_CONNECT1
O
SoftConnect control signal
Control
USB_UP_LED1
O
GoodLink LED control signal
Control
USB_INT1
I
OTG ATX interrupt
External OTG transceiver
I/O
I2C
serial clock
External OTG transceiver
USB_SDA1
I/O
I2C
serial data
USB_TX_E1
O
Transmit enable
External OTG transceiver
USB_TX_DP1
O
D+ transmit data
External OTG transceiver
USB_TX_DM1
O
D transmit data
External OTG transceiver
USB_RCV1
I
Differential receive data
External OTG transceiver
USB_RX_DP1
I
D+ receive data
External OTG transceiver
USB_RX_DM1
I
D receive data
External OTG transceiver
USB_LS1
O
Low speed status (applies to host functionality only)
External OTG transceiver
USB_SCL1
External OTG transceiver
USB_SSPND1
O
Bus suspend status
External OTG transceiver
USB_PPWR1
O
Port power enable
Host power switch
USB_PWRD1
I
Port power status
Host power switch
USB_OVRCR1
I
Over-current status
Host power switch
USB_HSTEN1
O
Host enabled status
USB_D+2
I/O
Positive differential data
USB Connector
USB_D2
I/O
Negative differential data
USB Connector
Port U2
USB_CONNECT2
O
SoftConnect control signal
Control
USB_UP_LED2
O
GoodLink LED control signal
Control
USB_PPWR2
O
Port power enable
Host power switch
USB_PWRD2
I
Port power status
Host power switch
USB_OVRCR2
I
Over-current status
Host power switch
USB_HSTEN2
O
Host enabled status
Control
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
388 of 942
UM10562
NXP Semiconductors
Chapter 13: LPC408x/407x USB Host controller
13.4.1.1 USB host usage note
Both ports can be configured as USB hosts. For details on how to connect the USB ports,
see the USB OTG chapter, Section 14.7.
The USB device/host/OTG controller is disabled after RESET and must be enabled by
writing a 1 to the PCUSB bit in the PCONP register, see Section 3.3.2.2.
13.4.2 Software interface
The software interface of the USB host block consists of a register view and the format
definitions for the endpoint descriptors. For details on these two aspects see the OHCI
specification. The register map is shown in the next subsection.
13.4.2.1 Register map
The following registers are located in the AHB clock ‘cclk’ domain. They can be accessed
directly by the processor. All registers are 32 bits wide and aligned in the word address
boundaries.
Table 310. USB Host register address definitions
Function
HcRevision
BCD representation of the version of the HCI specification that
is implemented by the Host Controller.
0x2008 C000
R
0x10
HcControl
Defines the operating modes of the HC.
0x2008 C004
R/W
0
HcCommandStatus
This register is used to receive the commands from the Host
Controller Driver (HCD). It also indicates the status of the HC.
0x2008 C008
R/W
0
HcInterruptStatus
Indicates the status on various events that cause hardware
interrupts by setting the appropriate bits.
0x2008 C00C
R/W
0
HcInterruptEnable
Controls the bits in the HcInterruptStatus register and indicates
which events will generate a hardware interrupt.
0x2008 C010
R/W
0
HcInterruptDisable
The bits in this register are used to disable corresponding bits
in the HCInterruptStatus register and in turn disable that event
leading to hardware interrupt.
0x2008 C014
R/W
0
HcHCCA
Contains the physical address of the host controller
communication area.
0x2008 C018
R/W
0
HcPeriodCurrentED
Contains the physical address of the current isochronous or
interrupt endpoint descriptor.
0x2008 C01C
R
0
HcControlHeadED
Contains the physical address of the first endpoint descriptor of
the control list.
0x2008 C020
R/W
0
HcControlCurrentED Contains the physical address of the current endpoint
descriptor of the control list
0x2008 C024
R/W
0
HcBulkHeadED
Contains the physical address of the first endpoint descriptor of
the bulk list.
0x2008 C028
R/W
0
HcBulkCurrentED
Contains the physical address of the current endpoint
descriptor of the bulk list.
0x2008 C02C
R/W
0
HcDoneHead
Contains the physical address of the last transfer descriptor
added to the ‘Done’ queue.
0x2008 C030
R
0
HcFmInterval
Defines the bit time interval in a frame and the full speed
maximum packet size which would not cause an overrun.
0x2008 C034
R/W
0x2EDF
HcFmRemaining
A 14-bit counter showing the bit time remaining in the current
frame.
0x2008 C038
R
0
UM10562
User manual
Address
R/W[1] Reset value
Name
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
389 of 942
UM10562
NXP Semiconductors
Chapter 13: LPC408x/407x USB Host controller
Table 310. USB Host register address definitions …continued
Address
R/W[1] Reset value
Name
Function
HcFmNumber
Contains a 16-bit counter and provides the timing reference
among events happening in the HC and the HCD.
0x2008 C03C
R
0
HcPeriodicStart
Contains a programmable 14-bit value which determines the
earliest time HC should start processing a periodic list.
0x2008 C040
R/W
0
HcLSThreshold
Contains 11-bit value which is used by the HC to determine
whether to commit to transfer a maximum of 8-byte LS packet
before EOF.
0x2008 C044
R/W
0x628h
HcRhDescriptorA
First of the two registers which describes the characteristics of
the root hub.
0x2008 C048
R/W
0xFF000902
HcRhDescriptorB
Second of the two registers which describes the characteristics 0x2008 C04C
of the Root Hub.
R/W
0x60000h
HcRhStatus
This register is divided into two parts. The lower D-word
represents the hub status field and the upper word represents
the hub status change field.
R/W
0
0x2008 C050
HcRhPortStatus[1]
Controls and reports the port events on a per-port basis.
0x2008 C054
R/W
0
HcRhPortStatus[2]
Controls and reports the port events on a per port basis.
0x2008 C058
R/W
0
Module_ID/
Ver_Rev_ID
IP number, where yy (0x00) is unique version number and zz
(0x00) is a unique revision number.
0x2008 C0FC
R
0x3505yyzz
[1]
The R/W column lists the accessibility of the register:
a) Registers marked ‘R’ for access will return their current value when read.
b) Registers marked ‘R/W’ allow both read and write.
13.4.2.2 USB Host Register Definitions
Refer to the OHCI specification document on the Compaq website for register definitions.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
390 of 942
UM10562
Chapter 14: LPC408x/407x USB OTG controller
Rev. 1 — 13 September 2012
User manual
14.1 How to read this chapter
This chapter describes the USB OTG controller which is present on some LPC408x/407x
devices (see Section 1.4 for details). On these devices, the USB controller can be
configured for device, Host, or OTG operation.
14.2 Basic configuration
The USB controller is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PCUSB.
Remark: On reset, the USB block is disabled (PCUSB = 0).
2. Clock: The USB clock can generated using the Alt PLL (PLL1) or with the Main PLL
(PLL0). See Section 3.10.
3. Pins: Select USB pins and their modes in the relevant IOCON registers
(Section 7.4.1).
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
Power-down mode (see Section 14.10.2 and Section 3.12.8).
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. The USB global interrupt status is visible in the USBINTSTAT register (Table 37).
7. Initialization: see Section 14.11.
14.3 Introduction
This chapter describes the OTG and I2C portions of the USB 2.0 OTG dual role device
controller which integrates the (OHCI) host controller, device controller, and I2C. The I2C
interface that is part of the USB block is intended to control an external OTG transceiver,
and is not the same as the I2C peripherals described in Section 22.1.
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality for
connection to USB peripherals. The specification and more information on USB OTG can
be found on the USB Implementers Forum web site.
14.4 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and SRP.
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
391 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.5 Architecture
The architecture of the USB OTG controller is shown below in the block diagram.
The host, device, OTG, and I2C controllers can be programmed through the register
interface. The OTG controller enables dynamic switching between host and device roles
through the HNP protocol. One port may be connected to an external OTG transceiver to
support an OTG connection. The communication between the register interface and an
external OTG transceiver is handled through an I2C interface and through the external
OTG transceiver interrupt signal.
For USB connections that use the device or host controller only (not OTG), the ports use
an embedded USB Analog Transceiver (ATX).
OTG
TRANSCEIVER
register
interface
(AHB slave)
I2C
CONTROLLER
REGISTER
INTERFACE
U1
port
AHB bus
OTG
CONTROLLER
DMA interface
(AHB master)
ATX
port 1 CONTROL
LOGIC/
PORT
MUX
port 1
DEVICE
CONTROLLER
BUS
MASTER
INTERFACE
USB
ATX
HOST
CONTROLLER
USB
ATX
port 2
U2
port
USB OTG BLOCK
EP_RAM
Fig 48. USB OTG controller block diagram
14.6 Modes of operation
The OTG controller is capable of operating in the following modes:
• One dual-role OTG port and optionally another Host port (see Figure 49 and
Figure 50)
• Two Host ports (see Figure 51)
• One Host port and one Device port (see Figure 52)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
392 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.7 Pin configuration
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.
Table 311. USB OTG port 1 pins
Pin name
VBUS
Direction
I
Description
Pin category
VBUS status input. When this function is not enabled via its
corresponding IOCON register, it is driven HIGH internally.
USB Connector
Port U1
USB_D+1
I/O
Positive differential data
USB Connector
USB_D1
I/O
Negative differential data
USB Connector
USB_CONNECT1
O
SoftConnect control signal
Control
USB_UP_LED1
O
GoodLink LED control signal
Control
USB_INT1
I
OTG ATX interrupt
External OTG transceiver
I/O
I2C
serial clock
External OTG transceiver
serial data
External OTG transceiver
USB_SCL1
USB_SDA1
I/O
I2C
USB_TX_E1
O
Transmit enable
External OTG transceiver
USB_TX_DP1
O
D+ transmit data
External OTG transceiver
USB_TX_DM1
O
D transmit data
External OTG transceiver
USB_RCV1
I
Differential receive data
External OTG transceiver
USB_RX_DP1
I
D+ receive data
External OTG transceiver
USB_RX_DM1
I
D receive data
External OTG transceiver
USB_LS1
O
Low speed status (applies to host functionality only)
External OTG transceiver
USB_SSPND1
O
Bus suspend status
External OTG transceiver
USB_PPWR1
O
Port power enable
Host power switch
USB_PWRD1
I
Port power status
Host power switch
USB_OVRCR1
I
Over-current status
Host power switch
USB_HSTEN1
O
Host enabled status
USB_D+2
I/O
Positive differential data
USB Connector
USB_D2
I/O
Negative differential data
USB Connector
Port U2
USB_CONNECT2
O
SoftConnect control signal
Control
USB_UP_LED2
O
GoodLink LED control signal
Control
USB_PPWR2
O
Port power enable
Host power switch
USB_PWRD2
I
Port power status
Host power switch
USB_OVRCR2
I
Over-current status
Host power switch
USB_HSTEN2
O
Host enabled status
Control
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
393 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.7.1 Using port U1 for OTG operation
The following figures show different ways to realize connections to a USB device using
ports U1 and U2. The example described here uses an ISP1302 (ST-Ericsson) for the
external OTG transceiver and the USB Host power switch LM3526-L (National
Semiconductors). There are two ways to connect the OTG transceiver:
1. Use the internal USB transceiver for USB signalling and use the external OTG
transceiver for OTG functionality only (see Figure 49). This option uses the internal
transceiver in VP/VM mode.
2. Use the external OTG transceiver in VP/VM mode for OTG functionality and USB
signalling (see Figure 50).
In both cases port U2 is connected as a host. Solution one uses fewer pins.
VDD
R1
R2
R3
RSTOUT
R4
RESET_N
VBUS
ADR/PSW
ID
OE_N/INT_N
VDD
SPEED
SUSPEND
R4
R5
DP
33 
DM
33 
ISP1302
R6
VSS
SCL
USB_SCL1
Mini-AB
connector
SDA
USB_SDA1
USB_INT1
INT_N
USB_D+1
USB_D-1
VDD
USB_UP_LED1
Microcontroller
R7
5V
VDD
IN
USB_PPWR2
ENA
LM3526-L
OUTA
FLAGA
USB_OVRCR2
VBUS
USB_PWRD2
USB_D+2
33 
USB_D-2
33 
D+
USB-A
connector
D15
k
VSS
15
k
VDD
USB_UP_LED2
R8
002aac708
Fig 49. USB OTG port configuration: port U1 OTG dual-role device, port U2 host
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
394 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
VDD
RSTOUT
RESET_N
OE_N/INT_N
USB_TX_E1
USB_TX_DP1
DAT_VP
USB_TX_DM1
SE0_VM
RCV
USB_RCV1
USB_RX_DP1
USB_RX_DM1
VP
VBUS
VM
ID
VDD
ISP1302
Microcontroller
ADR/PSW
DP
33 
DM
33 
USB MINI-AB
connector
VSS
SPEED
SUSPEND
USB_SCL1
SCL
USB_SDA1
SDA
INT_N
USB_INT1
VDD
USB_UP_LED1
002aac711
Fig 50. USB OTG port configuration: VP_VM mode
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
395 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.7.2 Using both ports U1 and U2 for host operation
Both ports U1 and U2 are connected as hosts using an embedded USB transceiver. There
is no OTG functionality on the port.
VDD
USB_UP_LED1
USB_D+1
33 
D+
USB_D-1
33 
D15
k
15
k
VBUS
USB_PWRD1
VSS
USB_OVRCR1
USB_PPWR1
FLAGA
ENA
OUTA
5V
IN
Microcontroller
USB-A
connector
VDD
USB_PPWR2
LM3526-L
ENB
VDD
OUTB
FLAGB
USB_OVRCR2
VBUS
USB_PWRD2
USB_D+2
33 
D+
USB_D-2
33 
D15
k
USB-A
connector
VSS
15
k
VDD
USB_UP_LED2
002aac709
Fig 51. USB host port configuration: port U1 and U2 as hosts
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
396 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.7.3 Using U1 for host operation and U2 for device operation
Port U2 is connected as device, and port U1 is connected as host. Both ports use
embedded USB transceivers. There is no OTG functionality on either USB port.
VDD
USB_UP_LED1
USB_D+1
33 
D+
USB_D-1
33 
D15
k
15
k
USB-A
connector
VDD
VBUS
USB_PWRD1
USB_OVRCR1
VSS
USB_PPWR1
FLAGA
ENA
5V
IN
LM3526-L
OUTA
Microcontroller
VDD
USB_UP_LED2
VDD
USB_CONNECT2
USB_D+2
33 
D+
USB_D-2
33 
D-
VBUS
USB-B
connector
VBUS
VSS
002aac710
Fig 52. USB device port configuration: port U1 host and port U2 device
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
397 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8 Register description
The OTG and I2C registers are summarized in the following table.
The Device and Host registers are explained in Table 254 and Table 310 in the USB
Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide
and aligned to word address boundaries.
The USB interrupt status is captured in the USBINTSTAT register in the syscon block.
Bits 0 and 1 of the StCtrl register are used to control the routing of the USB pins to ports 1
and 2 in device-only applications (see Section 12.10.1).
Table 312. Register overview: USB OTG controller (base address 0x2008 C000)
Name
Access
Address
offset
Description
Reset value
Table
INTST
RO
0x100
0
313
INTEN
R/W
0x104
OTG Interrupt Enable
INTSET
WO
0x108
OTG Interrupt Set
0
313
NA
313
INTCLR
WO
0x10C
OTG Interrupt Clear
NA
313
PORTSEL
R/W
0x110
OTG Status and Control
and USB port select
0
317
TMR
R/W
0x114
OTG Timer
0xFFFF
318
I2C_RX
RO
0x300
I2C Receive
NA
319
I2C_TX
WO
0x300
I2C Transmit
NA
320
I2C_STS
RO
0x304
I2C Status
0x0A00
321
0x308
I2 C
Control
0
322
OTG registers
I2C
OTG Interrupt Status
registers
I2C_CTL
R/W
I2C_CLKHI
R/W
0x30C
I2 C
Clock High
0xB9
323
I2C_CLKLO
R/W
0x310
I2C Clock Low
0xB9
324
Clock control registers
CLKCTRL
R/W
0xFF4
OTG clock controller
0
325
CLKST
RO
0xFF8
OTG clock status
0
326
14.8.1 OTG Interrupt Status Register
Bits in this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See Section 14.9 for more information on when these bits are set.
Table 313. OTG Interrupt Status register (INTST - address 0x2008 C100) bit description
Bit
Symbol
Description
0
TMR
Timer time-out.
0
1
REMOVE_PU
Remove pull-up. This bit is set by hardware to indicate that software needs to disable the
D+ pull-up resistor.
0
UM10562
User manual
Reset
Value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
398 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Table 313. OTG Interrupt Status register (INTST - address 0x2008 C100) bit description
Bit
Symbol
Description
Reset
Value
2
HNP_FAILURE
HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.
0
3
HNP_SUCCESS
HNP succeeded. This bit is set by hardware to indicate that the HNP switching has
succeeded.
0
31:4
-
Reserved. Read value is undefined, only zero should be written.
NA
14.8.2 OTG Interrupt Enable Register
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
Table 314. OTG Interrupt enable register (INTEN - address 0x2008 C104) bit description
Bit
Symbol
Description
Reset
Value
0
TMR_EN
1 = enable the corresponding bit in the IntSt register.
0
1
REMOVE_PU_EN
1 = enable the corresponding bit in the IntSt register.
0
2
HNP_FAILURE_EN
1 = enable the corresponding bit in the IntSt register.
0
3
HNP_SUCCES_EN
1 = enable the corresponding bit in the IntSt register.
0
31:4
-
Reserved. Read value is undefined, only zero should be written.
NA
14.8.3 OTG Interrupt Set Register
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
Table 315. OTG Interrupt enable register (INTSET - address 0x2008 C108) bit description
Bit
Symbol
Description
Reset
Value
0
TMR_SET
0 = no effect.
1 = set the corresponding bit in the IntSt register.
0
1
REMOVE_PU_SET
0 = no effect.
1 = set the corresponding bit in the IntSt register.
0
2
HNP_FAILURE_SET
0 = no effect.
1 = set the corresponding bit in the IntSt register.
0
3
HNP_SUCCES_SET
0 = no effect.
1 = set the corresponding bit in the IntSt register.
0
31:4
-
Reserved. Read value is undefined, only zero should be written.
NA
14.8.4 OTG Interrupt Clear Register
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
399 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Table 316. OTG Interrupt enable register (INTCLR - address 0x2008 C10C) bit description
Bit
Symbol
Description
0
TMR_CLR
0 = no effect.
1 = clear the corresponding bit in the IntSt register.
0
1
REMOVE_PU_CLR
0 = no effect.
1 = clear the corresponding bit in the IntSt register.
0
2
HNP_FAILURE_CLR
0 = no effect.
1 = clear the corresponding bit in the IntSt register.
0
3
HNP_SUCCES_CLR
0 = no effect.
1 = clear the corresponding bit in the IntSt register.
0
31:4
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
Reset
Value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
400 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.5 OTG Status and Control Register
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 14.8.6 “OTG Timer Register”), the TMR bit is set in OTGIntSt, and the timer
will be disabled.
2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 14.8.6 “OTG Timer Register”), the TMR bit is set, and the timer value is
reloaded into the counter. The timer is not disabled in this mode.
Table 317. OTG Status Control register (STCTRL - address 0x2008 C110) bit description
Bit
Symbol
Description
Reset
Value
1:0
PORT_FUNC
Controls connection of USB functions (see Figure 53). Bit 0 is set or cleared by hardware
when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9.
-
00: U1 = device (OTG), U2 = host
01: U1 = host (OTG), U2 = host
10: Reserved
11: U1 = host, U2 = device
3:2
TMR_SCALE
0
Timer scale selection. This field determines the duration of each timer count.
00: 10 s (100 KHz)
01: 100 s (10 KHz)
10: 1000 s (1 KHz)
11: Reserved
4
TMR_MODE
Timer mode selection.
0
0: monoshot
1: free running
5
TMR_EN
Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.
0
6
TMR_RST
Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit
control for the software to restart the timer when the timer is enabled.
0
7
-
Reserved. Read value is undefined, only zero should be written.
8
B_HNP_TRACK
Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit
when HNP_SUCCESS or HNP_FAILURE is set.
0
9
A_HNP_TRACK
Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit
when HNP_SUCCESS or HNP_FAILURE is set.
0
10
PU_REMOVED
When the B-device changes its role from peripheral to host, software sets this bit when it
removes the D+ pull-up, see Section 14.9. Hardware clears this bit when
HNP_SUCCESS or HNP_FAILURE is set.
0
15:11 -
Reserved. Read value is undefined, only zero should be written.
31:16 TMR_CNT
Current timer count value.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
NA
0
© NXP B.V. 2012. All rights reserved.
401 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
OTGStCtrl
PORT_FUNC[0] = 0
DEVICE
CONTROLLER
PORT_FUNC[1] = 0
port1
U1
U2
port1
HOST
CONTROLLER
port2
Fig 53. Port selection for PORT_FUNC bit 0 = 0 and PORT_FUNC bit 1 = 0
14.8.6 OTG Timer Register
Table 318. OTG Timer register (TMR - address 0x2008 C114) bit description
Bit
Symbol
Description
15:0
TIMEOUT_CNT
The TMR interrupt is set when TMR_CNT reaches this value.
31:16 -
Reset Value
Reserved. Read value is undefined, only zero should be written.
0xFFFF
NA
14.8.7 I2C Receive Register
This register is the top byte of the receive FIFO. The receive FIFO is 4 bytes deep. The Rx
FIFO is flushed by a hard reset or by a soft reset (I2C_CTL bit 7). Reading an empty FIFO
gives unpredictable data results.
Table 319. I2C Receive register (I2C_RX - address 0x2008 C300) bit description
Bit
Symbol
Description
Reset Value
7:0
RX Data
Receive data.
-
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
402 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.8 I2C Transmit Register
This register is the top byte of the transmit FIFO. The transmit FIFO is 4 bytes deep.
The Tx FIFO is flushed by a hard reset, soft reset (I2C_CTL bit 7) or if an arbitration failure
occurs (I2C_STS bit 3). Data writes to a full FIFO are ignored.
I2C_TX must be written for both write and read operations to transfer each byte. Bits [7:0]
are ignored for master-receive operations. The master-receiver must write a dummy byte
to the TX FIFO for each byte it expects to receive in the RX FIFO. When the STOP bit is
set or the START bit is set to cause a RESTART condition on a byte written to the TX
FIFO (master-receiver), then the byte read from the slave is not acknowledged. That is,
the last byte of a master-receive operation is not acknowledged.
Table 320. I2C Transmit register (I2C_TX - address 0x2008 C300) bit description
Bit
Symbol
Description
7:0
TX Data
Transmit data.
8
START
When 1, issue a START condition before transmitting this byte.
-
9
STOP
When 1, issue a STOP condition after transmitting this byte.
-
Reserved. Read value is undefined, only zero should be written.
-
31:10 -
Reset Value
-
14.8.9 I2C Status Register
The I2C_STS register provides status information on the TX and RX blocks as well as the
current state of the external buses. Individual bits are enabled as interrupts by the
I2C_CTL register and routed to the I2C_USB_INT bit in USBIntSt.
Table 321. I2C status register (I2C_STS - address 0x2008 C304) bit description
Bit
Symbol Value Description
0
TDI
1
2
Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is
cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.
0
Transaction has not completed.
1
Transaction completed.
AFI
Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high,
then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure
bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.
0
No arbitration failure on last transmission.
1
Arbitration failure occurred on last transmission.
NAI
UM10562
User manual
Reset
Value
No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an
acknowledge from the receiver. This bit is set if the acknowledge is not received. It is
cleared when a byte is written to the master TX FIFO.
0
Last transmission received an acknowledge.
1
Last transmission did not receive an acknowledge.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
0
© NXP B.V. 2012. All rights reserved.
403 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Table 321. I2C status register (I2C_STS - address 0x2008 C304) bit description
Bit
Symbol Value Description
3
DRMI
4
Reset
Value
Master Data Request Interrupt. Once a transmission is started, the transmitter must have
data to transmit as long as it isn’t followed by a stop condition or it will hold SCL low until
more data is available. The Master Data Request bit is set when the master transmitter is
data-starved. If the master TX FIFO is empty and the last byte did not have a STOP
condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit
is cleared when a byte is written to the master TX FIFO.
0
Master transmitter does not need data.
1
Master transmitter needs data.
DRSI
0
Slave Data Request Interrupt. Once a transmission is started, the transmitter must have
data to transmit as long as it isn’t followed by a STOP condition or it will hold SCL low until
more data is available. The Slave Data Request bit is set when the slave transmitter is
data-starved. If the slave TX FIFO is empty and the last byte transmitted was
acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit
is cleared when a byte is written to the slave Tx FIFO.
0
Slave transmitter does not need data.
1
Slave transmitter needs data.
0
5
Active
Indicates whether the bus is busy. This bit is set when a START condition has been seen.
It is cleared when a STOP condition is seen..
0
6
SCL
The current value of the SCL signal.
-
7
SDA
The current value of the SDA signal.
-
8
RFF
Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any
more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive
FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.
0
9
10
11
0
RX FIFO is not full
1
RX FIFO is full
RFE
Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX
FIFO contains valid data.
0
RX FIFO contains data.
1
RX FIFO is empty
TFF
Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO
is not full.
0
TX FIFO is not full.
1
TX FIFO is full
TFE
31:12 -
UM10562
User manual
Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX
FIFO contains valid data.
0
TX FIFO contains valid data.
1
TX FIFO is empty
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
1
0
1
NA
© NXP B.V. 2012. All rights reserved.
404 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.10 I2C Control Register
The I2C_CTL register is used to enable interrupts and reset the I2C state machine.
Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set.
Table 322. I2C Control register (I2C_CTL - address 0x2008 C308) bit description
Bit
Symbol
0
TDIE
1
2
3
4
5
6
7
Value Description
Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C
issued a STOP condition.
0
Disable the TDI interrupt.
1
Enable the TDI interrupt.
AFIE
Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is
asserted during transmission when trying to set SDA high, but the bus is driven low by
another device.
0
Disable the AFI.
1
Enable the AFI.
NAIE
Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling
that transmitted byte was not acknowledged.
0
Disable the NAI.
1
Enable the NAI.
DRMIE
Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which
signals that the master transmitter has run out of data, has not issued a STOP, and is
holding the SCL line low.
0
Disable the DRMI interrupt.
1
Enable the DRMI interrupt.
DRSIE
Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
0
Disable the DRSI interrupt.
1
Enable the DRSI interrupt.
REFIE
Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to
indicate that the receive FIFO cannot accept any more data.
0
Disable the RFFI.
1
Enable the RFFI.
RFDAIE
Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that
data is available in the receive FIFO (i.e. not empty).
0
Disable the DAI.
1
Enable the DAI.
TFFIE
UM10562
User manual
Reset
Value
Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt
to indicate that the more data can be written to the transmit FIFO. Note that this is not full.
It is intended help the CPU to write to the I2C block only when there is room in the FIFO
and do this without polling the status register.
0
Disable the TFFI.
1
Enable the TFFI.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
0
0
0
0
0
0
© NXP B.V. 2012. All rights reserved.
405 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Table 322. I2C Control register (I2C_CTL - address 0x2008 C308) bit description
Bit
Symbol
8
SRST
31:9 -
Value Description
Reset
Value
Soft reset. This is only needed in unusual circumstances. If a device issues a start
condition without issuing a stop condition. A system timer may be used to reset the I2C if
the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx
FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset
to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are
NOT modified by a soft reset.
0
See the text.
1
Reset the I2C to idle state. Self clearing.
Reserved. Read value is undefined, only zero should be written.
0
NA
14.8.11 I2C Clock High Register
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
high period of the slower I2C serial clock, SCL.
Table 323. I2C_CLKHI register (I2C_CLKHI - address 0x2008 C30C) bit description
Bit
Symbol Description
Reset
Value
7:0
CDHI
Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.
0xB9
31:8
-
Reserved. Read value is undefined, only zero should be written.
NA
14.8.12 I2C Clock Low Register
The CLK register holds a terminal count for counting 48 MHz clock cycles to create the
low period of the slower I2C serial clock, SCL.
Table 324. I2C_CLKLO register (I2C_CLKLO - address 0x2008 C310) bit description
Bit
Symbol Description
Reset
Value
7:0
CDLO
Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.
0xB9
31:8
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
406 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.13 OTG Clock Control Register
This register controls the clocking of the OTG controller. Whenever software wants to
access the registers, the corresponding clock control bit needs to be set. The software
does not have to repeat this exercise for every register access, provided that the
corresponding OTGClkCtrl bits are already set.
Table 325. OTG clock control register (CLKCTRL - address 0x2008 CFF4) bit description
Bit
Symbol
0
HOST_CLK_EN
1
2
Value Description
Host clock enable
0
Disable the Host clock.
1
Enable the Host clock.
DEV_CLK_EN
0
Disable the Device clock.
1
Enable the Device clock.
31:5
OTG_CLK_EN
UM10562
User manual
Disable the
I2C
clock.
Enable the
I2C
clock.
0
OTG clock enable. In device-only applications, this bit enables access to
the PORTSEL register.
0
Disable the OTG clock.
1
Enable the OTG clock.
AHB_CLK_EN
-
0
I2C clock enable
I2C_CLK_EN
1
4
0
Device clock enable
0
3
Reset Value
AHB master clock enable
0
Disable the AHB clock.
1
Enable the AHB clock.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
NA
© NXP B.V. 2012. All rights reserved.
407 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.14 OTG Clock Status Register
This register holds the clock availability status. When enabling a clock via OTGClkCtrl,
software should poll the corresponding bit in this register. If it is set, then software can go
ahead with the register access. Software does not have to repeat this exercise for every
access, provided that the OTGClkCtrl bits are not disturbed.
Table 326. OTG clock status register (CLKST - address 0x2008 CFF8) bit description
Bit
Symbol
0
HOST_CLK_ON
1
2
3
4
31:5
Value Description
Host clock status.
0
Host clock is not available.
1
Host clock is available.
DEV_CLK_ON
Device clock status.
0
Device clock is not available.
1
Device clock is available.
I2C clock status.
I2C_CLK_ON
0
I2C
clock is not available.
1
I2C
clock is available.
OTG_CLK_ON
OTG clock status.
0
OTG clock is not available.
1
OTG clock is available.
0
AHB clock is not available.
1
AHB clock is available.
AHB_CLK_ON
-
UM10562
User manual
Reset Value
AHB master clock status.
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
0
0
0
0
NA
© NXP B.V. 2012. All rights reserved.
408 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.8.15 Interrupt handling
The interrupts set in the OTGIntSt register are set and cleared during HNP switching. All
OTG related interrupts, if enabled, are routed to the USB_OTG_INT bit in the USBIntSt
register.
I2C related interrupts are set in the I2C_STS register and routed, if enabled by I2C_CTL,
to the USB_I2C_INT bit.
For more details on the interrupts created by device controller, see the USB device
chapter. For interrupts created by the host controllers, see the OHCI specification.
The EN_USB_INTS bit in the USBIntSt register enables the routing of any of the USB
related interrupts to the NVIC controller (see Figure 54).
Remark: During the HNP switching between host and device with the OTG stack active,
an action may raise several levels of interrupts. It is advised to let the OTG stack initiate
any actions based on interrupts and ignore device and host level interrupts. This means
that during HNP switching, the OTG stack provides the communication to the host and
device controllers.
USBIntSt
USB_INT_REQ_HP
USB_INT_REQ_LP
USB_INT_REQ_DMA
USB DEVICE
INTERRUPTS
to NVIC
USB_HOST_INT
USB_OTG_INT
USB HOST
INTERRUPTS
USB_I2C_INT
OTGIntSt
TMR
REMOVE_PU
HNP_SUCCESS
HNP_FAILURE
USB_NEED_CLOCK
EN_USB_INTS
USB I2C
INTERRUPTS
Fig 54. USB OTG interrupt handling
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
409 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.9 HNP support
This section describes the hardware support for the Host Negotiation Protocol (HNP)
provided by the OTG controller.
When two dual-role OTG devices are connected to each other, the plug inserted into the
mini-AB receptacle determines the default role of each device. The device with the mini-A
plug inserted becomes the default Host (A-device), and the device with the mini-B plug
inserted becomes the default Peripheral (B-device).
Once connected, the default Host (A-device) and the default Peripheral (B-device) can
switch Host and Peripheral roles using HNP.
The context of the OTG controller operation is shown in Figure 55. Each controller (Host,
Device, or OTG) communicates with its software stack through a set of status and control
registers and interrupts. In addition, the OTG software stack communicates with the
external OTG transceiver through the I2C interface and the external transceiver interrupt
signal.
The OTG software stack is responsible for implementing the HNP state machines as
described in the On-The-Go Supplement to the USB 2.0 Specification.
The OTG controller hardware provides support for some of the state transitions in the
HNP state machines as described in the following subsections.
The USB state machines, the HNP switching, and the communications between the USB
controllers are described in more detail in the following documentation:
•
•
•
•
UM10562
User manual
USB OHCI specification
USB OTG supplement, version 1.2
USB 2.0 specification
ISP1302 data sheet and user manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
410 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
OHCI
STACK
HOST
CONTROLLER
OTG
CONTROLLER
OTG
STACK
USB BUS
MUX
DEVICE
CONTROLLER
DEVICE
STACK
I2C
CONTROLLER
ISP1302
Fig 55. USB OTG controller with software stack
14.9.1 B-device: peripheral to host switching
In this case, the default role of the OTG controller is peripheral (B-device), and it switches
roles from Peripheral to Host.
The On-The-Go Supplement defines the behavior of a dual-role B-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role B-Device State Diagram.
The OTG controller hardware provides support for the state transitions between the states
b_peripheral, b_wait_acon, and b_host in the Dual-Role B-Device state diagram. Setting
B_HNP_TRACK in the OTGStCtrl register enables hardware support for the B-device
switching from peripheral to host. The hardware actions after setting this bit are shown in
Figure 56.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
411 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
idle
B_HNP_TRACK = 0
no
B_HNP_TRACK = 1 ?
set HNP_FAILURE,
clear B_HNP_TRACK,
clear PU_REMOVED
no
bus suspended ?
no
disconnect device controller from U1
set REMOVE_PU
yes
PU_REMOVED set?
PU_REMOVED set?
reconnect port U1 to the
device controller
bus reset/resume detected?
yes
no
reconnect port U1 to the
device controller
wait 25 s for bus to settle
yes
yes
bus reset/resume detected?
connect from A-device detected?
no
set HNP_SUCCESS
set PORT_FUNC[0]
drive J on internal host controller port
and SE0 on U1
no
yes
SE0 sent by host?
connect U1 to host controller
clear B_HNP_TRACK
clear PU_REMOVED
no
Fig 56. Hardware support for B-device switching from peripheral state to host state
Figure 57 shows the actions that the OTG software stack should take in response to the
hardware actions setting REMOVE_PU, HNP_SUCCESS, AND HNP_FAILURE. The
relationship of the software actions to the Dual-Role B-Device states is also shown.
B-device states are in bold font with a circle around them.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
412 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
b_peripheral
when host sends SET_FEATURE
with b_hnp_enable,
set B_HNP_TRACK
no
REMOVE_PU set?
yes
remove D+ pull-up,
set PU_REMOVED
go to
go to
b_wait_acon
b_peripheral
HNP_FAILURE set?
yes
add D+ pull-up
no
no
HNP_SUCCESS set?
yes
go to
b_host
Fig 57. State transitions implemented in software during B-device switching from peripheral to host
Note that only the subset of B-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 57 may appear to imply that the interrupt bits such as REMOVE_PU should be
polled, but this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in Figure 57 are accomplished.
The examples assume that ISP1302 is being used as the external OTG transceiver.
Remove D+ pull-up
/* Remove D+ pull-up through ISP1302 */
OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0
OTG_I2C_TX = 0x007; // Send OTG Control (Clear) register address
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
413 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
OTG_I2C_TX = 0x201; // Clear DP_PULLUP bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
Add D+ pull-up
/* Add D+ pull-up through ISP1302 */
OTG_I2C_TX = 0x15A; // Send ISP1302 address, R/W=0
OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address
OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
14.9.2 A-device: host to peripheral HNP switching
In this case, the role of the OTG controller is host (A-device), and the A-device switches
roles from host to peripheral.
The On-The-Go Supplement defines the behavior of a dual-role A-device during HNP
using a state machine diagram. The OTG software stack is responsible for implementing
all of the states in the Dual-Role A-Device State Diagram.
The OTG controller hardware provides support for the state transitions between a_host,
a_suspend, a_wait_vfall, and a_peripheral in the Dual-Role A-Device state diagram.
Setting A_HNP_TRACK in the OTGStCtrl register enables hardware support for switching
the A-device from the host state to the device state. The hardware actions after setting
this bit are shown in Figure 58.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
414 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
idle
A_HNP_TRACK = 0
no
A_HNP_TRACK = 1 ?
set HNP_FAILURE,
clear A_HNP_TRACK
disconnect host controller from U1
no
no
bus suspended ?
resume detected ?
yes
yes
connnect host controller back to U1
yes
yes
bus reset detected?
resume detected?
no
no
no
OTG timer expired?
(TMR =1 )
yes
clear A_HNP_TRACK
set HNP_SUCCESS
connect device to U1 by clearing
PORT_FUNC[0]
Fig 58. Hardware support for A-device switching from host state to peripheral state
Figure 59 shows the actions that the OTG software stack should take in response to the
hardware actions setting TMR, HNP_SUCCESS, and HNP_FAILURE. The relationship of
the software actions to the Dual-Role A-Device states is also shown. A-device states are
shown in bold font with a circle around them.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
415 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
a_host
when host sends SET_FEATURE
with a_hnp_enable,
set A_HNP_TRACK
set BDIS_ACON_EN
in external OTG transceiver
load and enable OTG timer
suspend host on port 1
go to
a_suspend
no
no
no
TMR set?
HNP_SUCCESS set?
yes
HNP_FAILURE set?
yes
yes
clear BDIS_ACON_EN
bit in external OTG transceiver
discharge VBUS
stop OTG timer
stop the OTG timer
go to
a_peripheral
clear BDIS_ACON_EN
bit in external OTG transceiver
go to
go to
a_wait_vfall
a_host
Fig 59. State transitions implemented in software during A-device switching from host to peripheral
Note that only the subset of A-device HNP states and state transitions supported by
hardware are shown. Software is responsible for implementing all of the HNP states.
Figure 59 may appear to imply that the interrupt bits such as TMR should be polled, but
this is not necessary if the corresponding interrupt is enabled.
Following are code examples that show how the actions in Figure 59 are accomplished.
The examples assume that ISP1302 is being used as the external OTG transceiver.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
416 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Set BDIS_ACON_EN in external OTG transceiver
/* Set BDIS_ACON_EN
OTG_I2C_TX = 0x15A;
OTG_I2C_TX = 0x004;
OTG_I2C_TX = 0x210;
in
//
//
//
ISP1302 */
Send ISP1302 address, R/W=0
Send Mode Control 1 (Set) register address
Set BDIS_ACON_EN bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
Clear BDIS_ACON_EN in external OTG transceiver
/* Set BDIS_ACON_EN
OTG_I2C_TX = 0x15A;
OTG_I2C_TX = 0x005;
OTG_I2C_TX = 0x210;
in
//
//
//
ISP1302 */
Send ISP1302 address, R/W=0
Send Mode Control 1 (Clear) register address
Clear BDIS_ACON_EN bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
Discharge VBUS
/* Clear the
OTG_I2C_TX =
OTG_I2C_TX =
OTG_I2C_TX =
VBUS_DRV bit in ISP1302 */
0x15A; // Send ISP1302 address, R/W=0
0x007; // Send OTG Control (Clear) register address
0x220; // Clear VBUS_DRV bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
/* Set the
OTG_I2C_TX
OTG_I2C_TX
OTG_I2C_TX
VBUS_DISCHRG bit in ISP1302 */
= 0x15A; // Send ISP1302 address, R/W=0
= 0x006; // Send OTG Control (Set) register address
= 0x240; // Set VBUS_DISCHRG bit, send STOP condition
/* Wait for TDI to be set */
while (!(OTG_I2C_STS & TDI));
/* Clear TDI */
OTG_I2C_STS = TDI;
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
417 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
Load and enable OTG timer
/* The following assumes that the OTG timer has previously been */
/* configured for a time scale of 1 ms (TMR_SCALE = “10”)
*/
/* and monoshot mode (TMR_MODE = 0)
*/
/* Load the timeout value to implement the a_aidl_bdis_tmr timer */
/*
the minimum value is 200 ms
*/
OTG_TIMER = 200;
/* Enable the timer */
OTG_STAT_CTRL |= TMR_EN;
Stop OTG timer
/* Disable the timer – causes TMR_CNT to be reset to 0 */
OTG_STAT_CTRL &= ~TMR_EN;
/* Clear TMR interrupt */
OTG_INT_CLR = TMR;
Suspend host on port 1
/* Write to PortSuspendStatus bit to suspend host port 1 –
*/
/* this example demonstrates the low-level action software needs to take. */
/* The host stack code where this is done will be somewhat more involved. */
HC_RH_PORT_STAT1 = PSS;
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
418 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.10 Clocking and power management
The OTG controller clocking is shown in Figure 60.
A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.
To conserve power, the clocks to the Device, Host, OTG, and I2C controllers can be
disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl
register. When the entire USB block is not in use, all of its clocks can be disabled by
clearing the PCUSB bit in the PCONP register.
When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
419 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
ahb_slave_clk
cclk
PCUSB
REGISTER
INTERFACE
ahb_master_clk
CLOCK
SWITCH
EN
AHB_CLK_ON
ahb_need_clk
AHB_CLK_EN
USB CLOCK
DIVIDER
usbclk
(48 MHz)
CLOCK
SWITCH
EN
DEV_CLK_ON
DEVICE
CONTROLLER
dev_dma_need_clk
dev_need_clk
DEV_CLK_EN
CLOCK
SWITCH
EN
host_dma_need_clk
HOST_CLK_ON
HOST
CONTROLLER
host_need_clk
HOST_CLK_EN
CLOCK
SWITCH
EN
OTG_CLK_ON
OTG
CONTROLLER
USB_NEED_CLK
OTG_CLK_EN
CLOCK
SWITCH
EN
I2C_CLK_ON
I2C
CONTROLLER
I2C_CLK_EN
Fig 60. Clocking and power control
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
420 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.10.1 Device clock request signals
The Device controller has two clock request signals, dev_need_clk and
dev_dma_need_clk. When asserted, these signals turn on the device’s 48 MHz clock and
ahb_master_clk respectively.
The dev_need_clk signal is asserted while the device is not in the suspend state, or if the
device is in the suspend state and activity is detected on the USB bus. The dev_need_clk
signal is de-asserted if a disconnect is detected (CON bit is cleared in the SIE Get Device
Status register – Section 12.10.6). This signal allows DEV_CLK_EN to be cleared during
normal operation when software does not need to access the Device controller registers –
the Device will continue to function normally and automatically shut off its clock when it is
suspended or disconnected.
The dev_dma_need_clk signal is asserted on any Device controller DMA access to
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA
throughput is not affected by any latency associated with re-enabling ahb_master_clk.
2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve
power. This signal allows AHB_CLK_EN to be cleared during normal operation.
14.10.1.1 Host clock request signals
The Host controller has two clock request signals, host_need_clk and
host_dma_need_clk. When asserted, these signals turn on the host’s 48 MHz clock and
ahb_master_clk respectively.
The host_need_clk signal is asserted while the Host controller functional state is not
UsbSuspend, or if the functional state is UsbSuspend and resume signaling or a
disconnect is detected on the USB bus. This signal allows HOST_CLK_EN to be cleared
during normal operation when software does not need to access the Host controller
registers – the Host will continue to function normally and automatically shut off its clock
when it goes into the UsbSuspend state.
The host_dma_need_clk signal is asserted on any Host controller DMA access to
memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA
throughput is not affected by any latency associated with re-enabling ahb_master_clk.
2 ms after the last DMA access, host_dma_need_clk is de-asserted to help conserve
power. This signal allows AHB_CLK_EN to be cleared during normal operation.
14.10.2 Power-down mode support
The CPU can be configured to wake up from Power-down mode on any USB bus activity.
When the chip is in Power-down mode and the USB interrupt is enabled, the assertion of
USB_NEED_CLK causes the chip to wake up from Power-down mode.
Before Power-down mode can be entered when the USB activity interrupt is enabled,
USB_NEED_CLK must be de-asserted. This is accomplished by clearing all of the
CLK_EN bits in OTGClkCtrl and putting the Host controller into the UsbSuspend
functional state. If it is necessary to wait for either of the dma_need_clk signals or the
dev_need_clk to be de-asserted, the status of USB_NEED_CLK can be polled in the
USBIntSt register to determine when they have all been de-asserted.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
421 of 942
UM10562
NXP Semiconductors
Chapter 14: LPC408x/407x USB OTG controller
14.11 USB OTG controller initialization
The OTG device controller initialization includes the following steps:
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the Alt PLL (PLL1) or Main PLL (PLL0) to provide 48 MHz for
usbclk and the desired frequency for cclk. For the procedure for determining the PLL
setting and configuration, see Section 3.10.5.
3. Enable the desired controller clocks by setting their respective CLK_EN bits in the
USBClkCtrl register. Poll the corresponding CLK_ON bits in the USBClkSt register
until they are set.
4. Enable the desired USB pin functions by writing to the corresponding IOCON
registers.
5. Follow the appropriate steps in Section 12.13 “USB device controller initialization” to
initialize the device controller.
6. Follow the guidelines given in the OpenHCI specification for initializing the host
controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
422 of 942
UM10562
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
Rev. 1 — 13 September 2012
User manual
15.1 Basic configuration
The SPIFI peripheral is configured using the following registers:
1. Power: In the PCONP register (see Section 3.3.2.2), set bit PCSPIFI.
Remark: On reset, the SPIFI is disabled (PCSPIFI = 0).
2. SPIFI clock: see Section 3.3.3.6.
3. Pins: Select SPIFI pins and pin modes through the relevant IOCON registers
(Section 7.4.1).
15.2 Features
• Quad SPI Flash Interface (SPIFI) interface to external flash.
• Transfer rates of up to SPIFI_CLK/2 bytes per second.
• Code in the serial flash memory can be executed as if it was in the CPU’s internal
memory space. This is accomplished by mapping the external flash memory directly
into the CPU memory space.
• Supports 1-, 2-, and 4-bit bidirectional serial protocols.
• Half-duplex protocol compatible with various vendors and devices (see Table 329).
• Using the SPIFI, as described in this chapter, accomplished with a driver library
available from NXP Semiconductors.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
423 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.3 General description
The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected to
the CPU with little performance penalty compared to parallel flash devices with higher pin
count.
A driver API included in on-chip ROM handles setup, programming and erasure. After an
initialize call to the SPIFI driver, the flash content is accessible as normal memory using
byte, halfword, and word accesses by the processor and/or DMA.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization. Quad devices then use a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices, and includes extensions to help insure compatibility with
future devices.
Serial flash devices respond to commands sent by software or automatically sent by the
SPIFI when software reads either of the two read-only serial flash regions in the memory
map (see Table 327).
Table 327. SPIFI flash memory map
Memory
Address
SPIFI data 0x2800 0000 to 0x28FF FFFF
Remark: This is the address space allocated to the SPIFI. The area allocated allows a maximum of 16 MB of
SPI flash to be mapped into the CPU memory space. In practice, the usable space is limited to the size of the
connected device
15.4 Pin description
Table 328. SPIFI Pin description
Pin function
Direction Description
SPIFI_SCK
O
Serial clock for the flash memory, switched only during active bits on the MOSI/IO0,
MISO/IO1, and IO3:2 lines.
SPIFI_CS
O
Chip select for the flash memory, driven low while a command is in progress, and high
between commands. In the typical case of one serial slave, this signal can be connected
directly to the device. If more than one serial slave is connected, software and off-chip
hardware should use general-purpose I/O signals in combination with this signal to
generate the chip selects for the various slaves.
SPIFI_MOSI or IO0
I/O
This is an output except in quad/dual input data fields. After a quad/dual input data field, it
becomes an output again one serial clock period after CS goes high.
SPIFI_MISO or IO1
I/O
This is an output in quad/dual opcode, address, intermediate, and output data fields, and
an input in SPI mode and in quad/dual input data fields. After an input data field in
quad/dual mode, it becomes an output again one serial clock period after CS goes high.
SPIFI_SIO[3:2]
I/O
These are outputs in quad opcode, address, intermediate, and output data fields, and
inputs in quad input data fields. If the flash memory does not have quad capability, these
pins can be assigned to GPIO or other functions.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
424 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.5 Supported devices
Serial flash devices with the following features are supported:
• Read JDEC ID
• Page programming
• at least one command with uniform erase size throughout the device
Table 329 shows a list of vendor QSPI devices which are verified to support the SPIFI
API. Other devices can be used and will run in basic single SPI mode at lower speed.
Remark: All QSPI devices have been tested at an operating voltage of 3.3 V.
Table 329. Supported QSPI devices
Manufacturer Device name
AMIC
A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032
Atmel
AT25F512B, AT25DF021, AT25DF041A, AT25DF081A, AT25DF161, AT25DQ161, AT25DF321A,
AT25DF641
Chingis
Pm25LD256, Pm25LD512, Pm25LD010, Pm25LD020, Pm25LD040, Pm25LQ032
Elite (ESMT)
F25L08P, F25L16P, F25L32P, F25L32Q
Eon
EN25F10, EN25F20, EN25F40, EN25Q40, EN25F80, EN25Q80, EN25QH16, EN25Q32, EN25Q64,
EN25Q128
Gigadevice
GD25Q512, GD25Q10, GD25Q20, GD25Q40, GD25Q80, GD25Q16, GD25Q32, GD25Q64
Macronix
MX25L8006, MX25L8035, MX25L8036, MX25U8035[1], MX25L1606, MX25L1633, MX25L1635,
MX25L1636, MX25U1635[1], MX25L3206, MX25L3235, MX25L3236, MX25U3235[1], MX25L6436,
MX25L6445, MX25L6465, MX25L12836, MX25L12845, MX25L12865, MX25L25635, MX25L25735
Numonyx
M25P10, M25P20, M25P40, M25P80, M25PX80, M25P16, M25PX16, M25P32, M25PX32, M25P64,
M25PX64, N25Q032, N25Q064, N25Q128
Spansion
S25FL004K, S25FL008K, S25FL016K, S25FL032K, S25FL032P, S25FL064K, S25FL064P, S25FL129P
SST
SST26VF016, SST26VF032, SST25VF064
Winbond
W25Q40, W25Q80, W25Q16, W25Q32, W25Q64
[1]
Level translation circuitry, which might affect performance, is required for these parts.
The following devices lack one or more of these features and are not supported:
• Elite: F25L004, F25L008, F25L016.
• Eon: 25B64.
• SST: 25VF512, 25WF512, 25VF010, 25WF010, 25LF020, 25VF020, 25WF020,
25VF040, 25WF040, 25VF080, 25WF080, 25VF016, 25VF032.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
425 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.6 SPIFI hardware
The SPIFI has a base address for the registers and a base address for the memory area
in which the serial Flash connected to the SPIFI can be read.
The first operation with the serial Flash is Read JEDEC ID, which is implemented by most
serial Flash devices. Depending on the device identity code returned by the serial Flash in
this operation, device-specific commands are used for further operation. Programming
and other operations on the serial Flash are performed by API calls as described in this
document.
15.7 SPIFI software library
15.7.1 SPIFI function allocation
Table 330 shows an overview of the SPIFI API calls. For details see Section 15.7.2.
Table 330. SPIFI function allocation
Function
Description
spifi_init
This call sends the standardized JEDEC ID command to the attached serial flash device. If a serial flash
responds with an ID known to the SPIFI API, it is set up for operation as standard memory.
Parameter0 - Pointer to SPIFIobj
Parameter1 - (minimum clock cycles with CS pin HIGH) - 1
Parameter2 - SPIFI options
Parameter3 - Serial clock rate
Return - SPIFI error code
spifi_program This call programs length bytes in the serial flash. obj must point to the object returned by the preceding
spifi_init call.
Parameter0 - Pointer to the object returned by the preceding spifi_init call.
Parameter1 - Source address (in RAM or other memory) of the data to be programmed.
Parameter2 - Number of bytes to be programmed.
Return - SPIFI error code.
spifi_erase
This command can be used to erase sections of the serial flash. It is not needed for re-programing because
spifi_program automatically erases as necessary in order to accomplish required programming. obj should
point to the object returned by the preceding spifi_init call.
Parameter0 - Pointer to the object returned by the preceding spifi_init call.
Parameter1 - SPIFI memory area to be erased.
Return - SPIFI error code
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
426 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.7.2 SPIFI function calls
15.7.2.1 Calling the SPIFI driver
Remark: Compile any module that calls the SPIFI API with the compiler set for ARM ABI
compatibility. This is the default in most compilers.
15.7.2.2 SPIFI initialization call spifi_init
The SPIFI initialization API call sends the standardized Read JEDEC ID command to the
attached serial flash device. If a serial flash responds, it is set up for reading in ARM
memory space.
int spifi_init (SPIFIobj *obj, unsigned csHigh, unsigned options, uclnsigned MHz)
After a spifi_init call that returns one of the unknown error codes (0x20009 to 0x20006,
see Table 332), the caller can read and check the SPIFI memory area but should not
issue any spifi_program or spifi_erase calls because not enough is known about the
device to accomplish these tasks.
spifi_init can be called repeatedly in order to change some of its operands. The
subsequent call need not use the same SPIFIobj , and need not use the same version of
the driver as the preceding call. The only case in which problems should arise with
reusing spifi_init is if the SPIFI and microcontroller hardware has been reset but the
serial flash hardware has not (since most serial flashes don't have a Reset pin).
Parameter0 obj
obj points to an area of memory large enough to receive the object created by spifi_init.
The space required for the SPIFI object is 192 bytes.
Parameter1 csHigh
csHigh is one less than the minimum number of clock cycles with the CS pin HIGH, that
the SPIFI should maintain between commands. Compute this parameter from the SPIFI
clock period and the minimum HIGH time of CS from the serial flash data sheet:
csHigh = ceiling(min CS HIGH / SPIFI_CLK ) - 1
where ceiling means round up to the next higher integer if the argument isn't an integer.
Parameter2 options
options contains 10 bits controlling the binary choices shown in Table 331. options can be
0 or any AND or OR combination of the bits represented in Table 331. An optional use of
names for the enumeration of bit values is also shown.
Table 331. Bit values for spifi_init options parameter
Bit
Value Description
0
Name
SCL output mode
0
SCL is low when a frame/command is not in progress.
S_MODE0
1
The SCL output is high when a frame/ command is not in progress. Note that S_MODE3+
S_FULLCLK+S_RCVCLK is not allowed. Use S_MODE0 or S_INTCLK.
S_MODE3
1
SPIFI read mode
0
The fastest read operation provided by the device will be used.
S_MAXIMAL
1
SPI mode and the slowest, most basic/ compatible read operation will be used.
S_MINIMAL
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
427 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
Table 331. Bit values for spifi_init options parameter
Bit
5:2
Value Description
0
Reserved
-
Sampling edge
-
0
Data from the serial flash is sampled on rising edges of the SCL output, as in classic SPI
applications. Suitable for slower clock rates.
S_HALFCLK
1
Data from the serial flash is sampled on falling edges on the SCL output, allowing a full clock S_FULLCLK
period for the serial flash to present each bit or group of bits.
0
Data is sampled using the internal clock from which the SCL pin is driven.
S_INTCLK
1
Data is sampled using the SCL clock fed back from the pin. This allows more time for the
serial flash to present each bit or group of bits, but when used with S_FULLCLK can
endanger hold time for data from the flash.
S_RCVCLK
6
7
Sampling clock
8
9
Name
SPIFI mode
0
If the device can operate in quad mode, quad mode will be used, else SPI mode.
-
1
If the connected device can operate in dual mode (2 bits per clock), dual mode will be used,
else SPI mode.
S_DUAL
0
Reserved
-
Parameter3 MHz
MHz is the serial clock rate divided by 1000000, rounded to an integer. It is used for devices
that allow a variable number of dummy bytes between the address and the read data in a
memory read command. This operand is only required for some Numonyx and Winbond
quad devices, but it is good practice to include it in all spifi_init calls.
Return
A return value of zero indicates success. Non-zero error codes are listed in Table 332
Table 332. Error codes for spifi_init
Error code Description
UM10562
User manual
0x2000A
No operative serial flash (JEDEC ID all zeroes or all ones)
0x20009
Unknown manufacturer code
0x20008
Unknown device type code
0x20007
Unknown device ID code
0x20006
Unknown extended device ID value
0x20005
Device status error
0x20004
Operand error: S_MODE3 + S_FULLCLK + S_RCVCLK selected in options
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
428 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.7.2.3 SPIFI program call spifi_program
The SPIFI program API call programs opers.length bytes in the serial flash.
int spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers)
A spifi_program call with source equal to opers.dest and opers.options not including
S_FORCE_ERASE will not do any erasing nor programming, since the data at opers.dest
is equal to the data at source. Such a call can be used to protect or unprotect sectors
depending on the value of opers.protect .
Parameter0 obj
obj points to the object returned by the preceding spifi_init call.
Parameter1 source
source is the address in RAM or other memory of the data to be programmed.
Parameter2 opers
Parameter2 is defined through the SPIFIopers C struct (see Section 15.7.2.5).
opers.length is the length of bytes to be programmed in the serial flash. opers.dest is the
destination address of the data in the SPIFI memory, and opers.options defines the
options for programming the SPIFI.
Return
spifi_program does not return until programming and erasure have been completed or an
error is encountered. A return value of zero indicates success. Non-zero error codes are
listed in Table 333.
Table 333. Error codes for spifi_program and spifi_erase
Error code Description
0x20007
Programming and erasure cannot be done because the serial flash was not identified in the spifi_init
operation.
0x20005
Device status error
0x20004
Operand error: the dest and/or length operands were out of range. See <tbd>Address operands and checking
below.
0x20003
Time-out waiting for program or erase to begin: protection could not be removed.
0x20002
Internal error in API code.
0x2000B
S_CALLER_ERASE is included in options, and erasure is required.
other
Other non-zero values can occur if options selects verification. They will be the address in the SPIFI memory
area at which the first discrepancy was found.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
429 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.7.2.4 SPIFI erase call spifi_erase
The spifi_erase call can be used instead of the spifi_program call to speed up erasing
large memory areas. Since erasing is also done by spifi_program , the spifi_erase call is
not strictly necessary.
int spifi_erase (SPIFIobj *obj, SPIFIopers *opers)
Parameter0 obj
obj points to the object returned by the preceding spifi_init call.
Parameter1 opers
Parameter1 is defined through the SPIFIopers C struct (see Section 15.7.2.5).
The code will use the largest units of erasure it can to accomplish the indicated operation
and will use the opers.scratch area only when required by a starting or ending address
that is not a multiple of the smallest available erase size. The driver will attempt to remove
any protection on the sectors indicated by opers.dest and opers.length. If this removal
succeeds, the opers.protect value determines the protection of the sectors on return, as
described in Section 15.7.2.7.
Return
Return values are the same as for spifi_program. A return value of zero indicates success.
Non-zero error codes are listed in Table 333
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
430 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.7.2.5 SPIFI operands for program and erase
SPIFIopers is a C struct that contains operands for the spifi_program and spifi_erase calls.
typedef struct {
char *dest; /* starting address for programming or erasing */
unsigned length; /* number of bytes to be programmed or erased */
char *scratch; /* address of work area or NULL */
int protect; /* protection to apply after programming/erasing is done */
unsigned options; /* see the table below */
} SPIFIopers;
dest specifies the first address to be programmed or erased, either in the SPIFI memory
area or as a zero-based device address. If dest is not a multiple of the smallest sector size
that's uniformly available throughout the serial flash, the first part of the first sector is one
of the following:
• Preserved if a scratch address is provided and/or an erase isn't needed for the first
sector.
• Erased to all ones if scratch is NULL and an erase is needed for the first sector.
Similarly, if dest plus length is not a multiple of the sector size, the last part of the last
sector is one of the following:
• Preserved if scratch is non-zero and/or an erase isn't needed for the last sector.
• Erased to all ones if scratch is zero and an erase is needed for the last sector.
For either spifi_program or spifi_erase , scratch should be NULL or the address of an area
of RAM that the SPIFI driver can use to save data during erase operations. If provided, the
scratch area should be as large as the smallest erase size that is available throughout the
serial flash device. If scratch is NULL (zero) and an erase is necessary, any bytes in the
first erase block before dest are left in erased state (all ones), as are any bytes in the last
erase block after dest + length .
The driver uses the least number of bytes possible in the scratch area. If dest and
dest + length - 1 are in separate erase blocks, the driver will use the larger of (the
number of bytes before dest in the first erase block) and (the number of bytes after
(dest + length ) in the last erase block). If only one erase block is involved, the driver will
use the sum of these two numbers.
options contains 10 bits controlling the binary choices shown in Table 334. options can be
0 or any AND or OR combination of the bits represented in Table 334. An optional use of
names for the enumeration of bit values is also shown.
Unless options includes S_CALLER_PROT, the driver attempts to remove
write-protection on the sectors implied by dest and length .
The protect operand indicates whether the driver should protect the sectors after
programming is completed. See Section 15.7.2.7 for details of the protect value.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
431 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
Table 334. Bit values for SPIFIopers options parameter
Bit
1:0
Value Description
0
Reserved
-
Erase mode
-
0
Erasing is done when necessary.
S_ERASE_AS_REQD
1
All sectors in dest to dest + length will be erased.
S_FORCE_ERASE
0
Erasing is done when necessary.
S_ERASE_AS_REQD
1
Erasing is handled by the caller not by the driver.
S_CALLER_ERASE
Verify program
-
0
No reading or checking will be done.
S_NO_VERIFY
1
Data will be read back and checked after programming.
S_VERIFY_PROG
Verify erase
-
No reading or checking will be done.
S_NO_VERIFY
1
Sectors will be read back and checked for 0xFF after erasing
S_VERIFY_ERASE
0
Reserved
-
Write protection
-
0
The driver removes protection before the operation and sets it as specified
afterward.
S_DRIVER_PROT
1
Write protection is handled by the caller not by the driver.
S_CALLER_PROT
2
3
Erase mode
4
5
0
8:6
Name
9
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
432 of 942
UM10562
NXP Semiconductors
Chapter 15: LPC408x/407x SPI flash interface (SPIFI)
15.7.2.6 Address operands and checking
For both spifi_program and spifi_erase , the opers.dest value can be either the
(zero-based) address within the serial flash or an address in the SPIFI memory area.
opers.dest and opers.length operands are always checked against the device size; when
verification is requested, they are also checked against the allocated size of the SPIFI
memory area.
15.7.2.7 Protection
Serial flash devices provide write-protection in several ways. Most devices simply have 2
to 5 bits in their status registers that specify what fraction of the device is write protected,
possibly in conjunction with a bit that specifies whether the fraction is at top or bottom
and/or a bit that specifies whether the fraction is protected or unprotected. For such
devices, at the start of spifi_program or spifi_erase the driver simply saves the status
byte, then clears all of the 2 to 5 bits, so that the whole device is write-enabled.
The opers.protect value of a spifi_program or spifi_erase on such a device can be 0 to
leave the device fully write-enabled, -1 to restore the protection status saved at the start of
the call, or any other non-zero value to set the protection status to that value. (Consult the
device data sheet for the content of the latter value.)
Some serial flash devices use individual protection bits for each sector. These include
SST quad devices, Atmel devices, and Macronix devices that provide a WPSEL
command and on which such a command has been executed (Setting WPSEL is an
irrevocable operation). Similarly to devices which include status register protection, -1 in
the opers.protect value makes the driver restore protection to the state in effect before the
call. 0 leaves the programmed/erased sectors write-enabled, and 1 write-protects them.
For small (high and low) sectors on SST quad devices only, opers.protect can be 3 to
read- and write-protect the sectors, or 2 to read-protect but write-enable them (Write Only
Memory!). 2 and 3 work like 0 and 1 respectively for other sectors and other devices.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
433 of 942
UM10562
Chapter 16: LPC408x/407x SD card interface
Rev. 1 — 13 September 2012
User manual
16.1 How to read this chapter
The SD card interface is available on most LPC408x/407x devices, see Section 1.4 for
details.
16.2 Basic configuration
The SD card interface (also known as MCI or Multimedia card interface) is configured
using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bit PC_SD.
Remark: On reset, the SD card interface is disabled (PCSD = 0).
2. Peripheral clock: The SD card interface operates from the common PCLK that clocks
both the bus interface and functional portion of most APB peripherals. See
Section 3.3.3.5.
3. Pins: Select SD card interface pins and their modes through the relevant IOCON
registers (Section 7.4.1).
4. Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
16.3 Introduction
The Secure Digital card interface is an interface between the Advanced Peripheral Bus
(APB) system bus and multimedia and/or secure digital memory cards. It consists of two
parts:
• The SD card interface provides all functions specific to the Secure Digital memory
card, such as the clock generation unit, power management control, command and
data transfer. The interface also supports the Multimedia Card Interface.
• The APB interface accesses SD card interface registers, and generates interrupt and
DMA request signals.
16.4 Features
The following features are provided by the SD card interface:
• Conformance to Secure Digital Memory Card Physical Layer Specification, v0.96.
• Conformance to Multimedia Card Specification v2.11.
• Use as a multimedia card bus or a secure digital memory card bus host. It can be
connected to several multimedia cards, or a single secure digital memory card.
• DMA supported through the General Purpose DMA Controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
434 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.5 Pin description
Table 335. SD/MMC card interface pin description
Pin Name
Type
Description
SD_CLK
Output
Clock output
SD_CMD
Input
Command input/output.
SD_DAT[3:0]
Output
Data lines. Only SD_DAT[0] is used for Multimedia cards.
SD_PWR
Output
Power Supply Enable for external card power supply.
16.6 Functional overview
The SD card interface may be used as a secure digital memory card bus host (see
Section 16.6.1 “Secure digital memory card”) or as a multimedia card bus host (see
Section 16.6.2 “Multimedia card”). A single secure digital memory card or up to 4
multimedia cards (depending on board loading) may be connected.
16.6.1 Secure digital memory card
Figure 61 shows the secure digital memory card connection.
CLK
SECURE
DIGITAL
MEMORY CARD
CONTROLLER
CMD
D[3:0]
SECURE
DIGITAL
MEMORY CARD
Fig 61. Secure digital memory card connection
16.6.1.1 Secure digital memory card bus signals
The following signals are used on the secure digital memory card bus:
• SD_CLK Host to card clock signal
• SD_CMD Bidirectional command/response signal
• SD_DAT[3:0] Bidirectional data signals
16.6.2 Multimedia card
Figure 62 shows the multimedia card system.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
435 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
MULTIMEDIA
CARD
INTERFACE
POWER
SUPPLY
MULTIMEDIA CARD BUS
CARD
CARD
CARD
MULTIMEDIA CARD STACK
Fig 62. Multimedia card system
Multimedia cards are grouped into three types according to their function:
• Read Only Memory (ROM) cards, containing pre-programmed data
• Read/Write (R/W) cards, used for mass storage
• Input/Output (I/O) cards, used for communication
The multimedia card system transfers commands and data using three signal lines:
• CLK: One bit is transferred on both command and data lines with each clock cycle.
The clock frequency varies between 0 MHz and 20 MHz (for a multimedia card) or
0 MHz and 25 MHz (for a secure digital memory card).
• CMD: Bidirectional command channel that initializes a card and transfers commands.
CMD has two operational modes:
– Open-drain for initialization
– Push-pull for command transfer
• DAT: Bidirectional data channel, operating in push-pull mode
16.6.3 SD card interface details
Figure 63 shows a simplified block diagram of the SD card interface.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
436 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
MULTIMEDIA CARD INTERFACE
SD_CLK
CONTROL
UNIT
APB
INTERFACE
APB BUS
ADAPTER
REGISTERS
SD_PWR
COMMAND
PATH
DATA PATH
SD_CMD
SD_DATA [3:0]
FIFO
Fig 63. SD card interface
The SD card interface is a secure digital/multimedia memory card bus master that
provides an interface to a multimedia card stack or to a secure digital memory card. It
consists of five subunits:
•
•
•
•
•
Adapter register block
Control unit
Command path
Data path
Data FIFO
16.6.3.1 Adapter register block
The adapter register block contains all system registers. This block also generates the
signals that clear the static flags in the multimedia card. The clear signals are generated
when 1 is written into the corresponding bit location of the MCIClear register.
16.6.3.2 Control unit
The control unit contains the power management functions and the clock divider for the
memory card clock.
There are three power phases:
• Power-off
• Power-up
• Power-on
The power management logic controls an external power supply unit, and disables the
card bus output signals during the power-off or power-up phases. The power-up phase is
a transition phase between the power-off and power-on phases, and allows an external
power supply to reach the card bus operating voltage. A device driver is used to ensure
that the interface remains in the power-up phase until the external power supply reaches
the operating voltage.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
437 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
The clock management logic generates and controls the SD_CLK signal. The SD_CLK
output can use either a clock divide or clock bypass mode. The clock output is inactive:
• after reset
• during the power-off or power-up phases
• if the power saving mode is enabled and the card bus is in the IDLE state (eight clock
periods after both the command and data path subunits enter the IDLE phase)
16.6.3.3 Command path
The command path subunit sends commands to and receives responses from the cards.
16.6.3.4 Command path state machine
When the command register is written to and the enable bit is set, command transfer
starts. When the command has been sent, the Command Path State Machine (CPSM)
sets the status flags and enters the IDLE state if a response is not required. If a response
is required, it waits for the response (see Figure 64). When the response is received, the
received CRC code and the internally generated code are compared, and the appropriate
status flags are set.
IDLE
Response received
or disabled or
command CRC failed
Enabled and
Pending command
Disabled
RECEIVE
Disabled or
no response
PEND
Disabled
or timeout
Enabled and
command start
Response
started
LastData
SEND
WAIT
Wait for
response
Fig 64. Command path state machine
When the WAIT state is entered, the command timer starts running. If the timeout1 is
reached before the CPSM moves to the RECEIVE state, the timeout flag is set and the
IDLE2 state is entered.
If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits
for an interrupt request from one of the cards. If a pending bit is set in the command
register, the CPSM enters the PEND state, and waits for a CmdPend signal from the data
path subunit. When CmdPend is detected, the CPSM moves to the SEND state. This
enables the data counter to trigger the stop command transmission.
1.
The timeout period has a fixed value of 64 SD_CLK clocks period.
2.
The CPSM remains in the IDLE state for at least eight SD_CLK periods to meet Ncc and Nrc timing constraints.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
438 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
Figure 65 shows the command transfer.
min 8
SD_CLK
SD_CLK
COMMAND
RESPONSE
COMMAND
State
IDLE
SEND
WAIT
RECEIVE
IDLE
SEND
SD_CMD
HI-Z
controller drives
HI-Z
card drives
HI-Z
controller drives
Fig 65. Command transfer
16.6.3.5 Command format
The command path operates in a half-duplex mode, so that commands and responses
can either be sent or received. If the CPSM is not in the SEND state, the SD_CMD output
is in HI-Z state, as shown in Figure 65. Data on SD_CMD is synchronous to the rising
SD_CLK edge. All commands have a fixed length of 48 bits. Table 336 shows the
command format.
Table 336. Command format
Bit Position
Width
Value
Description
0
1
1
End bit.
7:1
7
-
CRC7
39:8
32
-
Argument.
45:40
6
-
Command index.
46
1
1
Transmission bit.
47
1
0
Stat bit.
The SD card interface supports two response types. Both use CRC error checking:
• 48 bit short response (see Table 337)
• 136 bit long response (see Table 338)
Note: If the response does not contain CRC (CMD1 response), the device driver must
ignore the CRC failed status.
Table 337. Simple response format
UM10562
User manual
Bit Position
Width
Value
0
1
1
End bit.
Description
7:1
7
-
CRC7 (or 1111111).
39:8
32
-
Argument.
45:40
6
-
Command index.
46
1
0
Transmission bit.
47
1
0
Start bit.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
439 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
Table 338. Long response format
Bit Position
Width
Value
Description
0
1
1
End bit.
127:1
127
-
CID or CSD (including internal CRC7).
133:128
6
111111
134
1
1
Transmission bit.
135
1
0
Start bit.
Reserved.
The command register contains the command index (six bits sent to a card) and the
command type. These determine whether the command requires a response, and
whether the response is 48 or 136 bits long (see Section 16.7.4 “Command Register” for
more information). The command path implements the status flags shown in Table 339
(see Section 16.7.11 “Status Register” for more information).
Table 339. Command path status flags
Flag
Description
CmdRespEnd
Set if response CRC is OK.
CmdCrcFail
Set if response CRC fails.
CmdSent
Set when command (that does not require response) is sent.
CmdTimeOut
Response timeout.
CmdActive
Command transfer in progress.
The CRC generator calculates the CRC checksum for all bits before the CRC code. This
includes the start bit, transmitter bit, command index, and command argument (or card
status). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long
response format. Note that the start bit, transmitter bit and the six reserved bits are not
used in the CRC calculation.
The CRC checksum is a 7 bit value:
CRC[6:0] = Remainder [(M(x)  x7 ) / G(x)]
G(x) = x7 + x3 + 1
M(x) = (start bit)  x39 + … + (last bit before CRC)  x0 , or
M(x) = (start bit)  x119 + … + (last bit before CRC)  x0
16.6.3.6 Data path
The card data bus width can be programmed using the clock control register. If the wide
bus mode is enabled, data is transferred at four bits per clock cycle over all four data
signals (SD_DAT[3:0]). If the wide bus mode is not enabled, only one bit per clock cycle is
transferred over SD_DAT[0].
Depending on the transfer direction (send or receive), the Data Path State Machine
(DPSM) moves to the WAIT_S or WAIT_R state when it is enabled:
• Send: The DPSM moves to the WAIT_S state. If there is data in the send FIFO, the
DPSM moves to the SEND state, and the data path subunit starts sending data to a
card.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
440 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
• Receive: The DPSM moves to the WAIT_R state and waits for a start bit. When it
receives a start bit, the DPSM moves to the RECEIVE state, and the data path subunit
starts receiving data from a card.
16.6.3.7 Data path state machine
The DPSM operates at SD_CLK frequency. Data on the card bus signals is synchronous
to the rising edge of SD_CLK. The DPSM has six states, as shown in Figure 66.
Reset
Disabled or
FIFO underrun or
end of data or
CRC fail
IDLE
Disabled or
CRC fail or
timeout
Disabled or
Rx FIFO empty
or timeout or
start bit error
Disabled or
end of data
Enable
and send
BUSY
Enable and
not send
Disabled or
CRC fail
WAIT_R
Not busy
WAIT_S
End of packet
Start bit
End of packet
or end of data
or FIFO overrun
Data ready
SEND
RECEIVE
Fig 66. Data path state machine
• IDLE: The data path is inactive, and the SD_DAT[3:0] outputs are in HI-Z. When the
data control register is written and the enable bit is set, the DPSM loads the data
counter with a new value and, depending on the data direction bit, moves to either the
WAIT_S or WAIT_R state.
WAIT_R: If the data counter equals zero, the DPSM moves to the IDLE state when
the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start
bit on SD_DAT.
The DPSM moves to the RECEIVE state if it receives a start bit before a timeout, and
loads the data block counter. If it reaches a timeout before it detects a start bit, or a start
bit error occurs, it moves to the IDLE state and sets the timeout status flag.
• RECEIVE: Serial data received from a card is packed in bytes and written to the data
FIFO. Depending on the transfer mode bit in the data control register, the data transfer
mode can be either block or stream:
– In block mode, when the data block counter reaches zero, the DPSM waits until it
receives the CRC code. If the received code matches the internally generated
CRC code, the DPSM moves to the WAIT_R state. If not, the CRC fail status flag is
set and the DPSM moves to the IDLE state.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
441 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
– In stream mode, the DPSM receives data while the data counter is not zero. When
the counter is zero, the remaining data in the shift register is written to the data
FIFO, and the DPSM moves to the WAIT_R state.
If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the
WAIT_R state.
• WAIT_S: The DPSM moves to the IDLE state if the data counter is zero. If not, it waits
until the data FIFO empty flag is deasserted, and moves to the SEND state.
Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr
timing constraints.
• SEND: The DPSM starts sending data to a card. Depending on the transfer mode bit
in the data control register, the data transfer mode can be either block or stream:
– In block mode, when the data block counter reaches zero, the DPSM sends an
internally generated CRC code and end bit, and moves to the BUSY state.
– In stream mode, the DPSM sends data to a card while the enable bit is HIGH and
the data counter is not zero. It then moves to the IDLE state.
If a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the
IDLE state.
• BUSY: The DPSM waits for the CRC status flag:
– If it does not receive a positive CRC status, it moves to the IDLE state and sets the
CRC fail status flag.
– If it receives a positive CRC status, it moves to the WAIT_S state if SD_DAT[0] is
not LOW (the card is not busy).
If a timeout occurs while the DPSM is in the BUSY state, it sets the data timeout flag and
moves to the IDLE state.
The data timer is enabled when the DPSM is in the WAIT_R or BUSY state, and
generates the data timeout error:
• When transmitting data, the timeout occurs if the DPSM stays in the BUSY state for
longer than the programmed timeout period
• When receiving data, the timeout occurs if the end of the data is not true, and if the
DPSM stays in the WAIT_R state for longer than the programmed timeout period.
16.6.3.8 Data counter
The data counter has two functions:
• To stop a data transfer when it reaches zero. This is the end of the data condition.
• To start transferring a pending command (see Figure 67). This is used to send the
stop command for a stream data transfer.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
442 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
SD_CLK
SD_CMD
3
2
1
cmd state
SD_DAT0
0
7
6
5
4
PEND
Z
Z
data
counter
3
2
1
CMD
CMD
CMD
SEND
Z
Z
Z
S
CMD
CMD
6
7
CmdPend
Fig 67. Pending command start
The data block counter determines the end of a data block. If the counter is zero, the
end-of-data condition is TRUE (see Section 16.7.9 “Data Control Register” for more
information).
16.6.3.9 Bus mode
In wide bus mode, all four data signals (SD_DAT[3:0]) are used to transfer data, and the
CRC code is calculated separately for each data signal. While transmitting data blocks to
a card, only SD_DAT[0] is used for the CRC token and busy signalling. The start bit must
be transmitted on all four data signals at the same time (during the same clock period). If
the start bit is not detected on all data signals on the same clock edge while receiving
data, the DPSM sets the start bit error flag and moves to the IDLE state.
The data path also operates in half-duplex mode, where data is either sent to a card or
received from a card. While not being transferred, SD_DAT[3:0] are in the HI-Z state.
Data on these signals is synchronous to the rising edge of the clock period.
If standard bus mode is selected the SD_DAT[3:1] outputs are always in HI-Z state and
only the SD_DAT[0] output is driven LOW when data is transmitted.
Design note: If wide mode is selected, all data outputs enabled at the same time. If not,
the SD_DAT[3:1] outputs are always off, and only the SD_DAT[0] output is driven LOW
when data is transmitted.
16.6.3.10 CRC Token status
The CRC token status follows each write data block, and determines whether a card has
received the data block correctly. When the token has been received, the card asserts a
busy signal by driving SD_DAT[0] LOW. Table 340 shows the CRC token status values.
Table 340. CRC token status
UM10562
User manual
Token
Description
010
Card has received error-free data block.
101
Card has detected a CRC error.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
443 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.6.3.11 Status flags
Table 341 lists the data path status flags (see Section 16.7.11 “Status Register” on page
452 for more information).
Table 341. Data path status flags
Flag
Description
TxFifoFull
Transmit FIFO is full.
TxFifoEmpty
Transmit FIFO is empty.
TxFifoHalfEmpty
Transmit FIFO is half full.
TxDataAvlbl
Transmit FIFO data available.
TxUnderrun
Transmit FIFO underrun error.
RxFifoFull
Receive FIFO is full.
RxFifoEmpty
Receive FIFO is empty.
RxFifoHalfFull
Receive FIFO is half full.
RxDataAvlbl
Receive FIFO data available.
RxOverrun
Receive FIFO overrun error.
DataBlockEnd
Data block sent/received.
StartBitErr
Start bit not detected on all data signals in wide bus mode.
DataCrcFail
Data packet CRC failed.
DataEnd
Data end (data counter is zero).
DataTimeOut
Data timeout.
TxActive
Data transmission in progress.
RxActive
Data reception in progress.
16.6.3.12 CRC generator
The CRC generator calculates the CRC checksum only for the data bits in a single block,
and is bypassed in data stream mode. The checksum is a 16 bit value:
CRC[15:0] = Remainder [(M(x)  x15) / G(x)]
G(x) = x16 + x12 + x5 + 1
M(x) - (first data bit)  xn + … + (last data bit)  x0
16.6.3.13 Data FIFO
The data FIFO (first-in-first-out) subunit is a data buffer with transmit and receive logic.
The FIFO contains a 32 bit wide, 16-word deep data buffer, and transmit and receive
logic. Because the data FIFO operates in the APB clock domain (PCLK), all signals from
the subunits in the SD card interface clock domain (MCLK) are re-synchronized.
Depending on TxActive and RxActive, the FIFO can be disabled, transmit enabled, or
receive enabled. TxActive and RxActive are driven by the data path subunit and are
mutually exclusive:
• The transmit FIFO refers to the transmit logic and data buffer when TxActive is
asserted (see Section 16.6.3.14 “Transmit FIFO”)
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
444 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
• The receive FIFO refers to the receive logic and data buffer when RxActive is
asserted (see Section 16.6.3.15 “Receive FIFO”).
16.6.3.14 Transmit FIFO
Data can be written to the transmit FIFO through the APB interface once the SD card
interface is enabled for transmission.
The transmit FIFO is accessible via 16 sequential addresses (see Section 16.7.15 “Data
FIFO Register”). The transmit FIFO contains a data output register that holds the data
word pointed to by the read pointer. When the data path subunit has loaded its shift
register, it increments the read pointer and drives new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit
asserts TxActive when it transmits data. Table 342 lists the transmit FIFO status flags.
Table 342. Transmit FIFO status flags
Flag
Description
TxFifoFull
Set to HIGH when all 16 transmit FIFO words contain valid data.
TxFifoEmpty
Set to HIGH when the transmit FIFO does not contain valid data.
TxHalfEmpty
Set to HIGH when 8 or more transmit FIFO words are empty. This flag can be used as a DMA request.
TxDataAvlbl
Set to HIGH when the transmit FIFO contains valid data. This flag is the inverse of the TxFifoEmpty flag.
TxUnderrun
Set to HIGH when an underrun error occurs. This flag is cleared by writing to the MCIClear register.
16.6.3.15 Receive FIFO
When the data path subunit receives a word of data, it drives data on the write data bus
and asserts the write enable signal. This signal is synchronized to the PCLK domain. The
write pointer is incremented after the write is completed, and the receive FIFO control
logic asserts RxWrDone, that then deasserts the write enable signal.
On the read side, the content of the FIFO word pointed to by the current value of the read
pointer is driven on the read data bus. The read pointer is incremented when the APB bus
interface asserts RxRdPrtInc.
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data. Table
353 lists the receive FIFO status flags.
The receive FIFO is accessible via 16 sequential addresses (see Section 16.7.15 “Data
FIFO Register”).
If the receive FIFO is disabled, all status flags are deasserted, and the read and write
pointers are reset. The data path subunit asserts RxActive when it receives data.
Table 343 lists the receive FIFO status flags.
Table 343. Receive FIFO status flags
Symbol
Description
RxFifoFull
Set to HIGH when all 16 receive FIFO words contain valid data.
RxFifoEmpty
Set to HIGH when the receive FIFO does not contain valid data.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
445 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
Table 343. Receive FIFO status flags
Symbol
Description
RxHalfFull
Set to HIGH when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA
request.
RxDataAvlbl
Set to HIGH when the receive FIFO is not empty. This flag is the inverse of the RxFifoEmpty flag.
RxOverrun
Set to HIGH when an overrun error occurs. This flag is cleared by writing to the MCIClear register.
16.6.3.16 APB interfaces
The APB interface generates the interrupt and DMA requests, and accesses the SD card
interface registers and the data FIFO. It consists of a data path, register decoder, and
interrupt/DMA logic. DMA is controlled by the General Purpose DMA controller, see that
chapter for details.
16.6.3.17 Interrupt logic
The interrupt logic generates an interrupt request signal that is asserted when at least one
of the selected status flags is HIGH. A mask register is provided to allow selection of the
conditions that will generate an interrupt. A status flag generates the interrupt request if a
corresponding mask flag is set.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
446 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7 Register description
Table 344. Register overview: SD card interface (base address 0x400C 0000)
Name
Access Address offset Description
Reset Table
value[1]
PWR
R/W
0x000
Power control register.
0
345
CLOCK
R/W
0x004
Clock control register.
0
346
ARGUMENT
R/W
0x008
Argument register.
0
347
COMMAND
R/W
0x00C
Command register.
0
348
RESPCMD
RO
0x010
Response command register.
0
350
RESPONSE0
RO
0x014
Response register.
0
351
RESPONSE1
RO
0x018
Response register.
0
351
RESPONSE2
RO
0x01C
Response register.
0
351
RESPONSE3
RO
0x020
Response register.
0
351
DATATIMER
R/W
0x024
Data Timer.
0
353
DATALENGTH
R/W
0x028
Data length register.
0
354
DATACTRL
R/W
0x02C
Data control register.
0
355
DATACNT
RO
0x030
Data counter.
0
357
STATUS
RO
0x034
Status register.
0
358
CLEAR
WO
0x038
Clear register.
-
359
MASK0
R/W
003C
Interrupt 0 mask register.
0
360
FIFOCNT
RO
0x4048
FIFO Counter.
0
361
FIFO
R/W
0x080 to
0x0BC
Data FIFO Register.
0
362
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
16.7.1 Power Control Register
The PWR register controls an external power supply. Power can be switched on and off,
and adjust the output voltage. Table 345 shows the bit assignment of the Power register.
The active level of the SD_PWR pin can be selected by bit 3 of the SCS register (see
Section 3.3.7.1 “System Controls and Status register” on page 44 for details).
Table 345: Power Control register (PWR - address 0x400C 0000) bit description
Bit
Symbol
1:0
CTRL
Value Description
Reset Value
Power control
0x0
Power-off
0x1
Reserved
0x2
Power-up
0x3
Power-on
0
5:2
-
Reserved. Read value is undefined, only zero should be written.
6
OPENDRAIN
SD_CMD output control.
7
ROD
Rod control.
31:8
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
NA
0
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
447 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
When the external power supply is switched on, the software first enters the power-up
phase, and waits until the supply output is stable before moving to the power-on phase.
During the power-up phase, SD_PWR is set HIGH. The card bus outlets are disabled
during both phases.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
16.7.2 Clock Control Register
The Clock register controls the SD_CLK output. Table 346 shows the bit assignment of
the clock control register.
Table 346: MCI Clock Control register (CLOCK - address 0x400C 0004) bit description
Bit
Symbol
7:0
CLKDIV
8
ENABLE
Value Description
Reset Value
0
Bus clock period:
SD_CLK frequency = MCLK / [2(ClkDiv+1)].
9
10
11
Enable SD card bus clock:
0
Clock disabled.
1
Clock enabled.
0
Always enabled.
1
Clock enabled when bus is active.
PWRSAVE
Disable SD_CLK output when bus is idle:
BYPASS
Enable bypass of clock divide logic:
0
Disable bypass.
1
Enable bypass. MCLK driven to card bus output (SD_CLK).
WIDEBUS
Enable wide bus mode.
0
1
31:12
-
0
0
0
0
Standard bus mode (only SD_DAT[0] used).
Wide bus mode (SD_DAT[3:0] used)
Reserved. Read value is undefined, only zero should be written.
NA
While the SD card interface is in identification mode, the SD_CLK frequency must be less
than 400 kHz. The clock frequency can be changed to the maximum card bus frequency
when relative card addresses are assigned to all cards.
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
16.7.3 Argument Register
The Argument register contains a 32 bit command argument, which is sent to a card as
part of a command message. Table 347 shows the bit assignment of the Argument
register.
Table 347: MCI Argument register (ARGUMENT - address 0x400C 0008) bit description
Bit
Symbol
Description
Reset Value
31:0
CmdArg
Command argument
0x0000 0000
If a command contains an argument, it must be loaded into the argument register before
writing a command to the command register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
448 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7.4 Command Register
The Command register contains the command index and command type bits:
• The command index is sent to a card as part of a command message.
• The command type bits control the Command Path State Machine (CPSM). Writing 1
to the enable bit starts the command send operation, while clearing the bit disables
the CPSM.
Table 348 shows the bit assignment of the Command register.
Table 348: MCI Command register (COMMAND - address 0x400C 000C) bit description
Bit
Symbol
5:0
CmdIndex Command index.
Description
Reset Value
0
6
Response If set, CPSM waits for a response.
0
7
LongRsp
If set, CPSM receives a 136 bit long response.
0
8
Interrupt
If set, CPSM disables command timer and waits for interrupt request.
0
9
Pending
If set, CPSM waits for CmdPend before it starts sending a command.
0
10
Enable
If set, CPSM is enabled.
0
31:11
-
Reserved. Read value is undefined, only zero should be written.
NA
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Table 349 shows the response types.
Table 349: Command Response Types
Response Long Response Description
0
0
No response, expect CmdSent flag.
0
1
No response, expect CmdSent flag.
1
0
Short response, expect CmdRespEnd or CmdCrcFail flag.
1
1
Long response, expect CmdRespEnd or CmdCrcFail flag.
16.7.5 Command Response Register
The RespCommand register contains the command index field of the last command
response received. Table 348 shows the bit assignment of the RespCommand register.
Table 350: MCI Command Response register (RESPCMD - address 0x400C 0010) bit description
Bit
Symbol
Description
Reset Value
5:0
RESPCMD
Response command index
31:6
-
Reserved. Read value is undefined, only zero should be written.
0
NA
If the command response transmission does not contain the command index field (long
response), the RespCmd field is unknown, although it must contain 111111 (the value of
the reserved field from the response).
16.7.6 Response Registers
The Response0-3 registers contain the status of a card, which is part of the received
response. Table 351 shows the bit assignment of the Response0-3 registers.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
449 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
Table 351: MCI Response registers (RESPONSE[0:3] - addresses 0x400C 0014, 0x400C 0018,
0x400C 001C and 0x400C 0020) bit description
Bit
Symbol
Description
Reset Value
31:0 STATUS Card status
0
The card status size can be 32 or 127 bits, depending on the response type (see
Table 352).
Table 352: Response Register Type
Description
Short Response
Long Response
Response0
Card status [31:0]
Card status [127:96]
Response1
Unused
Card status [95:64]
Response2
Unused
Card status [63:32]
Response3
Unused
Card status [31:1]
The most significant bit of the card status is received first. The Response3 register LSBit
is always 0.
16.7.7 Data Timer Register
The DataTimer register contains the data timeout period, in card bus clock periods.
Table 353 shows the bit assignment of the DataTimer register.
Table 353: MCI Data Timer register (DATATIMER - address 0x400C 0024) bit description
Bit
Symbol
Description
31:0
DATATIME
Data timeout period.
Reset Value
0
A counter loads the value from the data timer register, and starts decrementing when the
Data Path State Machine (DPSM) enters the WAIT_R or BUSY state. If the timer reaches
0 while the DPSM is in either of these states, the timeout status flag is set.
A data transfer must be written to the data timer register and the data length register
before being written to the data control register.
16.7.8 Data Length Register
The DataLength register contains the number of data bytes to be transferred. The value is
loaded into the data counter when data transfer starts. Table 354 shows the bit
assignment of the DataLength register.
Table 354: MCI Data Length register (DATALENGTH - address 0x400C 0028) bit description
Bit
Symbol
Description
Reset Value
15:0
DATALENGTH Data length value
31:16
-
0
Reserved. Read value is undefined, only zero should be written.
NA
For a block data transfer, the value in the data length register must be a multiple of the
block size (see Section 16.7.9 “Data Control Register”).
To initiate a data transfer, write to the data timer register and the data length register
before writing to the data control register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
450 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7.9 Data Control Register
The DataCtrl register controls the DPSM. Table 355 shows the bit assignment of the
DataCtrl register.
Table 355: Data Control register (DATACTRL - address 0x400C 002C) bit description
Bit
Symbol
0
ENABLE
Data transfer enable.
0
1
DIRECTION
Data transfer direction
0
2
3
7:4
Value Description
0
From controller to card.
1
From card to controller.
MODE
Data transfer mode
0
Block data transfer.
1
Stream data transfer.
DMAENABLE
BLOCKSIZE
31:8 -
Reset Value
Enable DMA
0
DMA disabled.
1
DMA enabled.
0
0
Data block length
Reserved. Read value is undefined, only zero should be written.
0
NA
Note: After a data write, data cannot be written to this register for three MCLK clock
periods plus two PCLK clock periods.
Data transfer starts if 1 is written to the enable bit. Depending on the direction bit, the
DPSM moves to the WAIT_S or WAIT_R state. It is not necessary to clear the enable bit
after the data transfer. BlockSize controls the data block length if Mode is 0, as shown in
Table 356.
Table 356: Data Block Length
Block Size
Block Length
0
20= 1 byte.
1
21 = 2 bytes.
:
:
11
12:15
211 = 2048 bytes.
Reserved.
16.7.10 Data Counter Register
The DataCnt register loads the value from the data length register (see Section 16.7.8
“Data Length Register”) when the DPSM moves from the IDLE state to the WAIT_R or
WAIT_S state. As data is transferred, the counter decrements the value until it reaches 0.
The DPSM then moves to the IDLE state and the data status end flag is set. Table 357
shows the bit assignment of the DataCnt register.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
451 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
Table 357: MCI Data Counter register (DATACNT - address 0x400C 0030) bit description
Bit
Symbol
Description
15:0
DATACOUNT Remaining data
31:16
-
Reset Value
0
Reserved. Read value is undefined, only zero should be written.
NA
Note: This register should be read only when the data transfer is complete.
16.7.11 Status Register
The Status register is a read-only register. It contains two types of flag:
• Static [10:0]: These remain asserted until they are cleared by writing to the Clear
register (see Section 16.7.12 “Clear Register”).
• Dynamic [21:11]: These change state depending on the state of the underlying logic
(for example, FIFO full and empty flags are asserted and deasserted as data while
written to the FIFO).
Table 358 shows the bit assignment of the Status register.
Table 358: MCI Status register (STATUS - address 0x400C 0034) bit description
Bit
Symbol
Description
Reset Value
0
CMDCRCFAIL
Command response received (CRC check failed).
0
1
DATACRCFAIL
Data block sent/received (CRC check failed).
0
2
CMDTIMEOUT
Command response timeout.
0
3
DATATIMEOUT
Data timeout.
0
4
TXUNDERRUN
Transmit FIFO underrun error.
0
5
RXOVERRUN
Receive FIFO overrun error.
0
6
CMDRESPEND
Command response received (CRC check passed).
0
7
CMDSENT
Command sent (no response required).
0
8
DATAEND
Data end (data counter is zero).
0
9
STARTBITERR
Start bit not detected on all data signals in wide bus mode.
0
10
DATABLOCKEND
Data block sent/received (CRC check passed).
0
11
CMDACTIVE
Command transfer in progress.
0
12
TXACTIVE
Data transmit in progress.
0
13
RXACTIVE
Data receive in progress.
0
14
TXFIFOHALFEMPTY
Transmit FIFO half empty.
0
15
RXFIFOHALFFULL
Receive FIFO half full.
0
16
TXFIFOFULL
Transmit FIFO full.
0
17
RXFIFOFULL
Receive FIFO full.
0
18
TXFIFOEMPTY
Transmit FIFO empty.
0
19
RXFIFOEMPTY
Receive FIFO empty.
0
20
TXDATAAVLBL
Data available in transmit FIFO.
0
21
RXDATAAVLBL
Data available in receive FIFO.
31:22
-
Reserved. The value read from a reserved bit is not defined.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
452 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7.12 Clear Register
The Clear register is a write-only register. The corresponding static status flags can be
cleared by writing a 1 to the corresponding bit in the register. Table 359 shows the bit
assignment of the Clear register.
Table 359: MCI Clear register (CLEAR - address 0x400C 0038) bit description
UM10562
User manual
Bit
Symbol
Description
0
CMDCRCFAILCLR
Clears CmdCrcFail flag.
1
DATACRCFAILCLR
Clears DataCrcFail flag.
2
CMDTIMEOUTCLR
Clears CmdTimeOut flag.
3
DATATIMEOUTCLR
Clears DataTimeOut flag.
4
TXUNDERRUNCLR
Clears TxUnderrun flag.
5
RXOVERRUNCLR
Clears RxOverrun flag.
6
CMDRESPENDCLR
Clears CmdRespEnd flag.
7
CMDSENTCLR
Clears CmdSent flag.
8
DATAENDCLR
Clears DataEnd flag.
9
STARTBITERRCLR
Clears StartBitErr flag.
10
DATABLOCKENDCLR
Clears DataBlockEnd flag.
31:11
-
Reserved. Read value is undefined, only zero should be written.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
453 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7.13 Interrupt Mask Registers
The interrupt mask registers determine which status flags generate an interrupt request by
setting the corresponding bit to 1. Table 360 shows the bit assignment of the Maskx
registers.
Table 360: MCI Interrupt Mask registers (MASK0 - address 0x400C 003C) bit description
Bit
Symbol
Description
Reset Value
0
MASK0
Mask CmdCrcFail flag.
0
1
MASK1
Mask DataCrcFail flag.
0
2
MASK2
Mask CmdTimeOut flag.
0
3
MASK3
Mask DataTimeOut flag.
0
4
MASK4
Mask TxUnderrun flag.
0
5
MASK5
Mask RxOverrun flag.
0
6
MASK6
Mask CmdRespEnd flag.
0
7
MASK7
Mask CmdSent flag.
0
8
MASK8
Mask DataEnd flag.
0
9
MASK9
Mask StartBitErr flag.
0
10
MASK10 Mask DataBlockEnd flag.
0
11
MASK11 Mask CmdActive flag.
0
12
MASK12 Mask TxActive flag.
0
13
MASK13 Mask RxActive flag.
0
14
MASK14 Mask TxFifoHalfEmpty flag.
0
15
MASK15 Mask RxFifoHalfFull flag.
0
16
MASK16 Mask TxFifoFull flag.
0
17
MASK17 Mask RxFifoFull flag.
0
18
MASK18 Mask TxFifoEmpty flag.
0
19
MASK19 Mask RxFifoEmpty flag.
0
20
MASK20 Mask TxDataAvlbl flag.
0
21
MASK21 Mask RxDataAvlbl flag.
0
31:22
-
Reserved. Read value is undefined, only zero should be written.
NA
16.7.14 FIFO Counter Register
The FifoCnt register contains the remaining number of words to be written to or read from
the FIFO. The FIFO counter loads the value from the data length register (see
Section 16.7.8 “Data Length Register”) when the Enable bit is set in the data control
register. If the data length is not word aligned (multiple of 4), the remaining 1 to 3 bytes are
regarded as a word. Table 361 shows the bit assignment of the FifoCnt register.
Table 361: MCI FIFO Counter register (FIFOCNT - address 0x400C 0048) bit description
Bit
Symbol
Description
14:0
DATACOUNT
Remaining data
31:15
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
Reset Value
0
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
454 of 942
UM10562
NXP Semiconductors
Chapter 16: LPC408x/407x SD card interface
16.7.15 Data FIFO Register
The receive and transmit FIFOs can be read or written as 32 bit wide registers. The FIFOs
contain 16 entries on 16 sequential addresses. This allows the microprocessor to use its
load and store multiple operands to read/write to the FIFO. Table 362 shows the bit
assignment of the FIFO register.
Table 362: MCI Data FIFO register (FIFO - address 0x400C 0080 to 0x400C 00BC) bit
description
UM10562
User manual
Bit
Symbol
Description
31:0
DATA
FIFO data.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
Reset Value
0
© NXP B.V. 2012. All rights reserved.
455 of 942
UM10562
Chapter 17: LPC408x/407x UART1
Rev. 1 — 13 September 2012
User manual
17.1 Basic configuration
The UART1 peripheral is configured using the following registers:
1. Power: In the PCONP register (Section 3.3.2.2), set bits PCUART1.
Remark: On reset, UART1 is enabled (PCUART1 = 1).
2. Peripheral clock: UART1 operates from the common PCLK that clocks both the bus
interface and functional portion of most APB peripherals. See Section 3.3.3.5.
3. Baud rate: In register U1LCR (Table 373), set bit DLAB =1. This enables access to
registers DLL (Table 367) and DLM (Table 368) for setting the baud rate. Also, if
needed, set the fractional baud rate in the fractional divider register (Table 380).
4. UART FIFO: Use bit FIFO enable (bit 0) in register U1FCR (Table 372) to enable the
FIFOs.
5. Pins: Select UART pins and pin modes through the in the relevant IOCON registers
(Section 7.4.1).
Remark: UART receive pins should not have pull-down resistors enabled.
6. Interrupts: To enable UART interrupts set bit DLAB =0 in register U1LCR (Table 373).
This enables access to U1IER (Table 369). Interrupts are enabled in the NVIC using
the appropriate Interrupt Set Enable register.
7. DMA: UART1 transmit and receive functions can operated with the GPDMA controller
(see Table 692).
17.2 Features
•
•
•
•
•
•
•
•
•
•
•
UM10562
User manual
Full modem control handshaking available
Data sizes of 5, 6, 7, and 8 bits.
Parity generation and checking: odd, even mark, space or none.
One or two stop bits.
16 byte Receive and Transmit FIFOs.
Built-in baud rate generator, including a fractional rate divider for great versatility.
Supports DMA for both transmit and receive.
Auto-baud capability
Break generation and detection.
Multiprocessor addressing mode.
RS-485/EIA-485 support.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
456 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.3 Architecture
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART1.
The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid
character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers
the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register
(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the
serial output pin, TXD1.
The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by
the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This
divided down clock is the 16x oversample clock.
The modem interface contains registers U1MCR and U1MSR. This interface is
responsible for handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface
receives several one clock wide enables from the U1TX and U1RX blocks.
Status information from the U1TX and U1RX is stored in the U1LSR. Control information
for the U1TX and U1RX is stored in the U1LCR.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
457 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
Transmitter
Transmitter
Holding
Register
Transmitter
FIFO
Transmitter
Shift
Register
U1_TXD
Transmitter
DMA
Interface
TX_DMA_REQ
TX_DMA_CLR
Baud Rate Generator
Fractional
Main
Rate
Divider
Divider
(DLM, DLL)
PCLK
UART1 interrupt
FIFO Control
& Status
U1_CTS
U1_RTS
U1_DSR
U1_DTR
U1_DCD
U1_RI
Modem
Control
&
Status
Interrupt
Control &
Status
U1_OE
Line Control
& Status
RS485 &
Auto-baud
Receiver
Receiver
Buffer
Register
Receiver
FIFO
Receiver
Shift
Register
U1_RXD
Receiver
DMA
Interface
RX_DMA_REQ
RX_DMA_CLR
120601
Fig 68. UART1 block diagram
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
458 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.4 Pin description
Table 363: UART1 Pin Description
Pin
Type
Description
U1_RXD
Input
Serial Input. Serial receive data.
U1_TXD
Output Serial Output. Serial transmit data.
U1_CTS
Input
Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via
TXD1 from the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the complement
value of this signal is stored in U1MSR[4]. State change information is stored in U1MSR[0] and is a
source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
Clear to send. CTS1 is an asynchronous, active low modem status signal. Its condition can be checked
by reading bit 4 (CTS) of the modem status register. Bit 0 (DCTS) of the Modem Status Register (MSR)
indicates that CTS1 has changed states since the last read from the MSR. If the modem status interrupt
is enabled when CTS1 changes levels and the auto-cts mode is not enabled, an interrupt is generated.
CTS1 is also used in the auto-cts mode to control the transmitter.
U1_DCD
Input
Data Carrier Detect. Active low signal indicates if the external modem has established a
communication link with the UART1 and data may be exchanged. In normal operation of the modem
interface (U1MCR[4]=0), the complement value of this signal is stored in U1MSR[7]. State change
information is stored in U1MSR3 and is a source for a priority level 4 interrupt, if enabled
(U1IER[3] = 1).
U1_DSR
Input
Data Set Ready. Active low signal indicates if the external modem is ready to establish a
communications link with the UART1. In normal operation of the modem interface (U1MCR[4] = 0), the
complement value of this signal is stored in U1MSR[5]. State change information is stored in U1MSR[1]
and is a source for a priority level 4 interrupt, if enabled (U1IER[3] = 1).
U1_DTR
Output Data Terminal Ready. Active low signal indicates that the UART1 is ready to establish connection with
external modem. The complement value of this signal is stored in U1MCR[0].
The DTR pin can also be used as an RS-485/EIA-485 output enable signal.
U1_RI
Input
U1_RTS
Output Request To Send. Active low signal indicates that the UART1 would like to transmit data to the external
modem. The complement value of this signal is stored in U1MCR[1].
Ring Indicator. Active low signal indicates that a telephone ringing signal has been detected by the
modem. In normal operation of the modem interface (U1MCR[4] = 0), the complement value of this
signal is stored in U1MSR[6]. State change information is stored in U1MSR[2] and is a source for a
priority level 4 interrupt, if enabled (U1IER[3] = 1).
In auto-rts mode, RTS1 is used to control the transmitter FIFO threshold logic.
Request to send. RTS1 is an active low signal informing the modem or data set that the UART is ready
to receive data. RTS1 is set to the active (low) level by setting the RTS modem control register bit and is
set to the inactive (high) level either as a result of a system reset or during loop-back mode operations
or by clearing bit 1 (RTS) of the MCR. In the auto-rts mode, RTS1 is controlled by the transmitter FIFO
threshold logic.
The RTS pin can also be used as an RS-485/EIA-485 output enable signal.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
459 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5 Register description
The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the
Divisor Latches.
Table 364: Register overview: UART1 (base address 0x4001 0000)
Name
Access
Address
offset
Description
Reset Table
Value[1]
RBR
RO
0x000
DLAB =0. Receiver Buffer Register. Contains the next received
character to be read.
NA
365
THR
WO
0x000
DLAB =0. Transmit Holding Register. The next character to be
transmitted is written here.
NA
366
DLL
R/W
0x000
DLAB =1. Divisor Latch LSB. Least significant byte of the baud
rate divisor value. The full divisor is used to generate a baud
rate from the fractional rate divider.
0x01
367
DLM
R/W
0x004
DLAB =1. Divisor Latch MSB. Most significant byte of the baud
rate divisor value. The full divisor is used to generate a baud
rate from the fractional rate divider.
0
368
IER
R/W
0x004
DLAB =0. Interrupt Enable Register. Contains individual
interrupt enable bits for the 7 potential UART1 interrupts.
0
369
IIR
RO
0x008
Interrupt ID Register. Identifies which interrupt(s) are pending.
0x01
370
FCR
WO
0x008
FIFO Control Register. Controls UART1 FIFO usage and
modes.
0
372
LCR
R/W
0x00C
Line Control Register. Contains controls for frame formatting
and break generation.
0
373
MCR
R/W
0x010
Modem Control Register. Contains controls for flow control
handshaking and loopback mode.
0
374
LSR
RO
0x014
Line Status Register. Contains flags for transmit and receive
status, including line errors.
0x60
376
MSR
RO
0x018
Modem Status Register. Contains handshake signal status
flags.
0
377
SCR
R/W
0x01C
Scratch Pad Register. 8-bit temporary storage for software.
0
378
ACR
R/W
0x020
Auto-baud Control Register. Contains controls for the auto-baud
feature.
0
379
FDR
R/W
0x028
Fractional Divider Register. Generates a clock input for the baud
rate divider.
0x10
380
TER
R/W
0x030
Transmit Enable Register. Turns off UART transmitter for use
with software flow control.
0x80
382
RS485CTRL
R/W
0x04C
RS-485/EIA-485 Control. Contains controls to configure various
aspects of RS-485/EIA-485 modes.
0
383
RSADRMATCH
R/W
0x050
RS-485/EIA-485 address match. Contains the address match
value for RS-485/EIA-485 mode.
0
384
RS485DLY
R/W
0x054
RS-485/EIA-485 direction control delay.
0
385
[1]
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
460 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.1 UART1 Receiver Buffer Register
The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1RBR. The U1RBR is always read-only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U1LSR
register, and then to read a byte from the U1RBR.
Table 365: UART1 Receiver Buffer Register when DLAB = 0 (RBR - address 0x4001 0000 ) bit description
Bit
Symbol Description
Reset
Value
7:0
RBR
The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO. undefined
31:8
-
Reserved, the value read from a reserved bit is not defined.
NA
17.5.2 UART1 Transmitter Holding Register
The write-only U1THR is the top byte of the UART1 TX FIFO. The top byte is the newest
character in the TX FIFO and can be written via the bus interface. The LSB represents the
first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U1LCR must be zero in order to access the
U1THR. The U1THR is write-only.
Table 366: UART1 Transmitter Holding Register when DLAB = 0 (THR - address 0x4001 0000 ) bit description
Bit
Symbol Description
7:0
THR
Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO.
The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.
31:8
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
461 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.3 UART1 Divisor Latch LSB and MSB Registers
The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the APB clock (PCLK) in order to produce
the baud rate clock, which must be 16x the desired baud rate. The U1DLL and U1DLM
registers together form a 16-bit divisor where U1DLL contains the lower 8 bits of the
divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like
a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in
U1LCR must be one in order to access the UART1 Divisor Latches. Details on how to
select the right value for U1DLL and U1DLM can be found later in this chapter, see
Section 17.5.16.
Table 367: UART1 Divisor Latch LSB Register when DLAB = 1 (DLL - address 0x4001 0000 ) bit description
Bit
Symbol Description
7:0
DLLSB
The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the
baud rate of the UART1.
Reset Value
31:8
-
Reserved. Read value is undefined, only zero should be written.
0x01
NA
Table 368: UART1 Divisor Latch MSB Register when DLAB = 1 (DLM - address 0x4001 0004 ) bit description
Bit
Symbol Description
7:0
DLMSB
The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the
baud rate of the UART1.
31:8
-
Reserved. Read value is undefined, only zero should be written.
UM10562
User manual
Reset Value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
NA
© NXP B.V. 2012. All rights reserved.
462 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.4 UART1 Interrupt Enable Register
The U1IER is used to enable the four UART1 interrupt sources.
Table 369: UART1 Interrupt Enable Register when DLAB = 0 (IER - address 0x4001 0004 ) bit description
Bit
Symbol
0
RBRIE
1
2
3
Value Description
Reset
Value
RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also
controls the Character Receive Time-out interrupt.
0
Disable the RDA interrupts.
1
Enable the RDA interrupts.
THREIE
THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this
interrupt can be read from LSR[5].
0
Disable the THRE interrupts.
1
Enable the THRE interrupts.
RXIE
0
RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of
this interrupt can be read from LSR[4:1].
0
Disable the RX line status interrupts.
1
Enable the RX line status interrupts.
MSIE
0
Modem Status Interrupt Enable. Enables the modem interrupt. The status of this
interrupt can be read from MSR[3:0].
0
Disable the modem interrupt.
1
Enable the modem interrupt.
0
0
6:4
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
7
CTSIE
CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem
status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a
CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is
set.
0
In normal operation a CTS1 signal transition will generate a Modem Status Interrupt
unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In
auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3]
and IER[7] bits are set.
8
9
0
Disable the CTS interrupt.
1
Enable the CTS interrupt.
0
Disable end of auto-baud Interrupt.
1
Enable end of auto-baud Interrupt.
ABEOIE
Enables the end of auto-baud interrupt.
ABTOIE
31:10 -
UM10562
User manual
0
Enables the auto-baud time-out interrupt.
0
Disable auto-baud time-out Interrupt.
1
Enable auto-baud time-out Interrupt.
0
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
463 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.5 UART1 Interrupt Identification Register
The U1IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during
an U1IIR access, the interrupt is recorded for the next U1IIR access.
Table 370: UART1 Interrupt Identification Register (IIR - address 0x4001 0008) bit description
Bit
Symbol
0
INTSTATUS
Value Description
Interrupt status. Note that IIR[0] is active low. The pending interrupt can be
determined by evaluating IIR[3:1].
0
1
3:1
Reset Value
INTID
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. IER[3:1] identifies an interrupt corresponding to the
UART1 RX or TX FIFO. All other combinations of IER[3:1] not listed below
are reserved (100,101,111).
0x3
1
0
1 - Receive Line Status (RLS).
0x2
2a - Receive Data Available (RDA).
0x6
2b - Character Time-out Indicator (CTI).
0x1
3 - THRE Interrupt.
0x0
4 - Modem Interrupt.
5:4
-
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
7:6
FIFOENABLE
Copies of FCR[0].
0
8
ABEOINT
End of auto-baud interrupt. True if auto-baud has finished successfully
and interrupt is enabled.
0
9
ABTOINT
Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt
is enabled.
0
31:10 -
Reserved, the value read from a reserved bit is not defined.
NA
NA
Bit U1IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in Table 371. Given the status of U1IIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
464 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 371: UART1 Interrupt Handling
U1IIR[3:0] Priority Interrupt
value[1]
Type
Interrupt Source
Interrupt Reset
0001
-
None
-
0110
Highest RX Line
Status /
Error
OE[2] or PE[2] or FE[2] or BI[2]
U1LSR Read[2]
0100
Second RX Data
Available
Rx data available or trigger level reached in FIFO
(U1FCR0=1)
U1RBR Read[3] or UART1
FIFO drops below trigger level
1100
Second Character Minimum of one character in the RX FIFO and no
U1RBR Read[3]
Time-out character input or removed during a time period depending
indication on how many characters are in FIFO and what the trigger
level is set at (3.5 to 4.5 character times).
None
The exact time will be:
[(word length)  7 - 2]  8 + [(trigger level - number of
characters)  8 + 1] RCLKs
0010
Third
THRE
THRE[2]
U1IIR Read[4] (if source of
interrupt) or THR write
0000
Fourth
Modem
Status
CTS or DSR or RI or DCD
MSR Read
[1]
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2]
For details see Section 17.5.10 “UART1 Line Status Register”
[3]
For details see Section 17.5.1 “UART1 Receiver Buffer Register”
[4]
For details see Section 17.5.5 “UART1 Interrupt Identification Register” and Section 17.5.2 “UART1
Transmitter Holding Register”
The UART1 THRE interrupt (U1IIR[3:1] = 001) is a third level interrupt and is activated
when the UART1 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART1 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U1THR at one time
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
465 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U1THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART1 THR FIFO has held two or more characters at one time and
currently, the U1THR is empty. The THRE interrupt is reset when a U1THR write occurs or
a read of the U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001).
It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
466 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.6 UART1 FIFO Control Register
The write-only U1FCR controls the operation of the UART1 RX and TX FIFOs.
Table 372: UART1 FIFO Control Register (FCR - address 0x4001 0008) bit description
Bit
Symbol
0
FIFOEN
1
2
Value Description
Reset
Value
FIFO enable.
0
0
Must not be used in the application.
1
Active high enable for both UART1 RX and TX FIFOs and FCR[7:1] access. This bit
must be set for proper UART1 operation. Any transition on this bit will automatically
clear the UART1 FIFOs.
0
No impact on either of UART1 FIFOs.
1
Writing a logic 1 to FCR[1] will clear all bytes in UART1 RX FIFO, reset the pointer
logic. This bit is self-clearing.
0
No impact on either of UART1 FIFOs.
1
Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer
logic. This bit is self-clearing.
RXFIFORES
RX FIFO Reset.
TXFIFORES
0
TX FIFO Reset.
0
3
DMAMODE
DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit
selects the DMA mode. See Section 17.5.6.1.
5:4
-
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
7:6
RXTRIGLVL
RX Trigger Level. These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.
31:8
-
0x0
Trigger level 0 (1 character or 0x01).
0x1
Trigger level 1 (4 characters or 0x04).
0x2
Trigger level 2 (8 characters or 0x08).
0x3
Trigger level 3 (14 characters or 0x0E).
Reserved, user software should not write ones to reserved bits.
0
NA
0
NA
17.5.6.1 DMA Operation
The user can optionally operate the UART transmit and/or receive using DMA. The DMA
mode is determined by the DMA Mode Select bit in the FCR register. This bit only has an
affect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character timeout occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
467 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
468 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.7 UART1 Line Control Register
The U1LCR determines the format of the data character that is to be transmitted or
received.
Table 373: UART1 Line Control Register (LCR - address 0x4001 000C) bit description
Bit
Symbol
1:0
WLS
2
3
5:4
6
7
31:8
Value Description
0x0
5-bit character length.
0x1
6-bit character length.
0x2
7-bit character length.
0x3
8-bit character length.
SBS
0
1 stop bit.
1
2 stop bits (1.5 if LCR[1:0]=00).
0
Disable parity generation and checking.
1
Enable parity generation and checking.
0
Parity Select.
0
0x0
Odd parity. Number of 1s in the transmitted character and the attached
parity bit will be odd.
0x1
Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
0x2
Forced "1" stick parity.
0x3
Forced "0" stick parity.
BC
Break Control.
0
0
Disable break transmission.
1
Enable break transmission. Output pin UART1 TXD is forced to logic 0
when LCR[6] is active high.
DLAB
User manual
0
Parity Enable.
PS
UM10562
0
Stop Bit Select.
PE
-
Reset Value
Word Length Select.
Divisor Latch Access Bit (DLAB)
0
Disable access to Divisor Latches.
1
Enable access to Divisor Latches.
0
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
469 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.8 UART1 Modem Control Register
The U1MCR enables the modem loopback mode and controls the modem output signals.
Table 374: UART1 Modem Control Register (MCR - address 0x4001 0010) bit description
Bit
Symbol
Value Description
Reset
value
0
DTRCTRL
-
DTR Control.
Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is
active.
0
1
RTSCTRL
-
RTS Control.
Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is
active.
0
3:2
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0
4
LMS
Loopback Mode Select.
The modem loopback mode provides a mechanism to perform diagnostic loopback
testing. Serial data from the transmitter is connected internally to serial input of the
receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in
marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected
externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4
modem outputs are connected to the 4 modem inputs. As a result of these
connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR
rather than the 4 modem inputs in normal mode. This permits modem status interrupts
to be generated in loopback mode by writing the lower 4 bits of MCR.
0
0
Disable modem loopback mode.
1
Enable modem loopback mode.
5
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0
6
RTSEN
RTS enable.
0
7
31:8
0
Disable auto-rts flow control.
1
Enable auto-rts flow control.
CTSEN
-
CTS enable.
0
0
Disable auto-cts flow control.
1
Enable auto-cts flow control.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
17.5.9 Auto-flow control
If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1
output of the UART1. If the auto-CTS mode is enabled the UART1‘s U1TSR hardware will
only start transmitting if the CTS1 input signal is asserted.
17.5.9.1 Auto-RTS
The auto-RTS function is enabled by setting the RTSen bit. Auto-RTS data flow control
originates in the U1RBR module and is linked to the programmed receiver FIFO trigger
level. If auto-RTS is enabled, the data-flow is controlled as follows:
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
470 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
When the receiver FIFO level reaches the programmed trigger level, RTS1 is de-asserted
(to a high value). It is possible that the sending UART sends an additional byte after the
trigger level is reached (assuming the sending UART has another byte to send) because it
might not recognize the de-assertion of RTS1 until after it has begun sending the
additional byte. RTS1 is automatically reasserted (to a low value) once the receiver FIFO
has reached the previous trigger level. The re-assertion of RTS1 signals to the sending
UART to continue transmitting data.
If Auto-RTS mode is disabled, the RTSen bit controls the RTS1 output of the UART1. If
Auto-RTS mode is enabled, hardware controls the RTS1 output, and the actual value of
RTS1 will be copied in the RTS Control bit of the UART1. As long as Auto-RTS is enabled,
the value of the RTS Control bit is read-only for software.
Example: Suppose the UART1 operating in ‘550 mode has trigger level in U1FCR set to
0x2 then if Auto-RTS is enabled the UART1 will de-assert the RTS1 output as soon as the
receive FIFO contains 8 bytes (Table 372 on page 467). The RTS1 output will be
reasserted as soon as the receive FIFO hits the previous trigger level: 4 bytes.
~
~
UART1 Rx
byte N
stop
start
bits0..7
stop
N-1
N-2
start
bits0..7
stop
~
~
start
RTS1 pin
~
~~
~
UART1 Rx
FIFO read
UART1 Rx
FIFO level
N
N-1
N-2
M+2
M+1
M
M-1
~
~
N-1
Fig 69. Auto-RTS Functional Timing
17.5.9.2 Auto-CTS
The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the
transmitter circuitry in the U1TSR module checks CTS1 input before sending the next
data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the
transmitter from sending the following byte, CTS1 must be released before the middle of
the last stop bit that is currently being sent. In Auto-CTS mode a change of the CTS1
signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set,
Delta CTS bit in the U1MSR will be set though. Table 375 lists the conditions for
generating a Modem Status interrupt.
Table 375: Modem status interrupt generation
Enable Modem Status
CTSen
CTS Interrupt
Delta CTS Delta DCD or Trailing Edge RI Modem Status
Interrupt (U1ER[3])
(U1MCR[7]) Enable (U1IER[7]) (U1MSR[0]) or Delta DSR (U1MSR[3] or
Interrupt
U1MSR[2] or U1MSR[1])
0
x
x
x
x
1
0
x
0
0
No
1
0
x
1
x
Yes
1
0
x
x
1
Yes
1
1
0
x
0
No
1
1
0
x
1
Yes
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
No
© NXP B.V. 2012. All rights reserved.
471 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
Table 375: Modem status interrupt generation
Enable Modem Status
CTSen
CTS Interrupt
Delta CTS Delta DCD or Trailing Edge RI Modem Status
Interrupt (U1ER[3])
(U1MCR[7]) Enable (U1IER[7]) (U1MSR[0]) or Delta DSR (U1MSR[3] or
Interrupt
U1MSR[2] or U1MSR[1])
1
1
1
0
0
No
1
1
1
1
x
Yes
1
1
1
x
1
Yes
~
~
UART1 TX
bits0..7
stop
start
bits0..7
stop
start
bits0..7
stop
~
~
start
~
~
The auto-CTS function reduces interrupts to the host system. When flow control is
enabled, a CTS1 state change does not trigger host interrupts because the device
automatically controls its own transmitter. Without Auto-CTS, the transmitter sends any
data present in the transmit FIFO and a receiver overrun error can result. Figure 70
illustrates the Auto-CTS functional timing.
~
~
CTS1 pin
Fig 70. Auto-CTS Functional Timing
While starting transmission of the initial character the CTS1 signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS1 is de-asserted (high). As soon as CTS1 gets
de-asserted transmission resumes and a start bit is sent followed by the data bits of the
next character.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
472 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.10 UART1 Line Status Register
The U1LSR is a read-only register that provides status information on the UART1 TX and
RX blocks.
Table 376: UART1 Line Status Register (LSR - address 0x4001 0014) bit description
Bit
Symbol Value Description
0
RDR
1
2
Reset
Value
Receiver Data Ready.
LSR[0] is set when the RBR holds an unread character and is cleared when the UART1
RBR FIFO is empty.
0
The UART1 receiver FIFO is empty.
1
The UART1 receiver FIFO is not empty.
OE
0
Overrun Error.
The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1]
is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full.
In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1
RSR will be lost.
0
Overrun error status is inactive.
1
Overrun error status is active.
PE
0
0
Parity Error.
When the parity bit of a received character is in the wrong state, a parity error occurs. An
LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0].
Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.
3
0
Parity error status is inactive.
1
Parity error status is active.
FE
Framing Error.
When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read
clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon
detection of a framing error, the RX will attempt to resynchronize to the data and assume
that the bad stop bit is actually an early start bit. However, it cannot be assumed that the
next received byte will be correct even if there is no Framing Error.
0
Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.
4
0
Framing error status is inactive.
1
Framing error status is active.
BI
Break Interrupt.
When RXD1 is held in the spacing state (all zeroes) for one full character transmission
(start, data, parity, stop), a break interrupt occurs. Once the break condition has been
detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read
clears this status bit. The time of break detection is dependent on FCR[0].
0
Note: The break interrupt is associated with the character at the top of the UART1 RBR
FIFO.
5
0
Break interrupt status is inactive.
1
Break interrupt status is active.
THRE
UM10562
User manual
Transmitter Holding Register Empty.
THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR
write.
0
THR contains valid data.
1
THR is empty.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
1
© NXP B.V. 2012. All rights reserved.
473 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
Table 376: UART1 Line Status Register (LSR - address 0x4001 0014) bit description
Bit
Symbol Value Description
6
TEMT
7
31:8
Transmitter Empty.
TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or
the THR contain valid data.
0
THR and/or the TSR contains valid data.
1
THR and the TSR are empty.
RXFE
-
Reset
Value
1
Error in RX FIFO.
LSR[7] is set when a character with a RX error such as framing error, parity error or break
interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there
are no subsequent errors in the UART1 FIFO.
0
RBR contains no UART1 RX errors or FCR[0]=0.
1
UART1 RBR contains at least one UART1 RX error.
0
Reserved, the value read from a reserved bit is not defined.
NA
17.5.11 UART1 Modem Status Register
The U1MSR is a read-only register that provides status information on the modem input
signals. U1MSR[3:0] is cleared on U1MSR read. Note that modem signals have no direct
effect on UART1 operation, they facilitate software implementation of modem signal
operations.
Table 377: UART1 Modem Status Register (MSR - address 0x4001 0018) bit description
Bit
Symbol
0
DCTS
1
2
3
Value Description
Reset Value
Delta CTS.
Set upon state change of input CTS. Cleared on an MSR read.
0
No change detected on modem input, CTS.
1
State change detected on modem input, CTS.
DDSR
0
Delta DSR.
Set upon state change of input DSR. Cleared on an MSR read.
0
No change detected on modem input, DSR.
1
State change detected on modem input, DSR.
TERI
0
Trailing Edge RI.
Set upon low to high transition of input RI. Cleared on an MSR read.
0
No change detected on modem input, RI.
1
Low-to-high transition detected on RI.
0
No change detected on modem input, DCD.
1
State change detected on modem input, DCD.
DDCD
0
Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.
0
4
CTS
-
Clear To Send State. Complement of input signal CTS. This bit is connected
to MCR[1] in modem loopback mode.
0
5
DSR
-
Data Set Ready State. Complement of input signal DSR. This bit is
connected to MCR[0] in modem loopback mode.
0
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
474 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
Table 377: UART1 Modem Status Register (MSR - address 0x4001 0018) bit description
Bit
Symbol
6
RI
-
Ring Indicator State. Complement of input RI. This bit is connected to
MCR[2] in modem loopback mode.
0
7
DCD
-
Data Carrier Detect State. Complement of input DCD. This bit is connected
to MCR[3] in modem loopback mode.
0
31:8
-
UM10562
User manual
Value Description
-
Reset Value
Reserved, the value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
NA
© NXP B.V. 2012. All rights reserved.
475 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.12 UART1 Scratch Pad Register
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
Table 378: UART1 Scratch Pad Register (SCR - address 0x4001 0014) bit description
Bit
Symbol Description
Reset
Value
7:0
Pad
A readable, writable byte.
31:8
-
Reserved. Read value is undefined, only zero should be written.
0
NA
17.5.13 UART1 Auto-baud Control Register
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
Table 379: Auto-baud Control Register (ACR - address 0x4001 0020) bit description
Bit
Symbol
0
START
1
2
0
Auto-baud stop (auto-baud is not running).
1
Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
8
ABEOINTCLR
0
Mode 0.
1
Mode 1.
UM10562
User manual
0
Auto-baud restart bit.
0
0
No restart
1
Restart in case of time-out (counter restarts at next UART1 Rx falling edge)
-
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
0
End of auto-baud interrupt clear bit (write-only).
0
0
Writing a 0 has no impact.
1
Writing a 1 will clear the corresponding interrupt in the IIR.
ABTOINTCLR
31:10 -
0
Auto-baud mode select bit.
AUTORESTART
-
Reset
value
Auto-baud start bit.
This bit is automatically cleared after auto-baud completion.
MODE
7:3
9
Value Description
Auto-baud time-out interrupt clear bit (write-only).
0
0
Writing a 0 has no impact.
1
Writing a 1 will clear the corresponding interrupt in the IIR.
-
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
0
© NXP B.V. 2012. All rights reserved.
476 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.14 Auto-baud
The UART1 auto-baud function can be used to measure the incoming baud rate based on
the “AT” protocol (Hayes command). If enabled the auto-baud feature will measure the bit
time of the receive data stream and set the divisor latch registers U1DLM and U1DLL
accordingly.
Remark: the fractional rate divider is not connected during auto-baud operations, and
therefore should not be used when the auto-baud feature is needed.
Auto-baud is started by setting the U1ACR Start bit. Auto-baud can be stopped by clearing
the U1ACR Start bit. The Start bit will clear once auto-baud has finished and reading the
bit will return the status of auto-baud (pending/finished).
Two auto-baud measuring modes are available which can be selected by the U1ACR
Mode bit. In mode 0 the baud rate is measured on two subsequent falling edges of the
UART1 RX pin (the falling edge of the start bit and the falling edge of the least significant
bit). In mode 1 the baud rate is measured between the falling edge and the subsequent
rising edge of the UART1 RX pin (the length of the start bit).
The U1ACR AutoRestart bit can be used to automatically restart baud rate measurement
if a time-out occurs (the rate measurement counter overflows). If this bit is set the rate
measurement will restart at the next falling edge of the UART1 RX pin.
The auto-baud function can generate two interrupts.
• The U1IIR ABTOInt interrupt will get set if the interrupt is enabled (U1IER ABToIntEn
is set and the auto-baud rate measurement counter overflows).
• The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn
is set and the auto-baud has completed successfully).
The auto-baud interrupts have to be cleared by setting the corresponding U1ACR
ABTOIntClr and ABEOIntEn bits.
Typically the fractional baud rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UART1 RX pin baud rate, but the value of the U1FDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U1DLM and U1DLL registers should be done before U1ACR register write.
The minimum and the maximum baud rates supported by UART1 are function of pclk,
number of data bits, stop bits and parity bits.
(1)
2  P CLK
PCLK
ratemin = -------------------------  UART 1 baudrate  ------------------------------------------------------------------------------------------------------------ = ratemax
16  2 15
UM10562
User manual
16   2 + databits + paritybits + stopbits 
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
477 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.15 Auto-baud modes
When the software is expecting an “AT” command, it configures the UART1 with the
expected character format and sets the U1ACR Start bit. The initial values in the divisor
latches U1DLM and U1DLM don‘t care. Because of the “A” or “a” ASCII coding
(”A" = 0x41, “a” = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U1ACR Start bit is set, the
auto-baud protocol will execute the following phases:
1. On U1ACR Start bit setting, the baud rate measurement counter is reset and the
UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
2. A falling edge on UART1 RX pin triggers the beginning of the start bit. The rate
measuring counter will start counting pclk cycles optionally pre-scaled by the
fractional baud rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the (fractional baud rate pre-scaled) UART1 input clock,
guaranteeing the start bit is stored in the U1RSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UART1 input clock (pclk).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
6. The rate counter is loaded into U1DLM/U1DLL and the baud rate will be switched to
normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the
remaining bits of the “A/a” character.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
478 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
'A' (0x41) or 'a' (0x61)
start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity stop
UART1 RX
start bit
LSB of 'A' or 'a'
U1ACR start
rate counter
16xbaud_rate
16 cycles
16 cycles
a. Mode 0 (start bit and LSB are used for auto-baud)
'A' (0x41) or 'a' (0x61)
start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
parity stop
UART1 RX
start bit
LSB of 'A' or 'a'
U1ACR start
rate counter
16xbaud_rate
16 cycles
b. Mode 1 (only start bit is used for auto-baud)
Fig 71. Auto-baud a) mode 0 and b) mode 1 waveform
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
479 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.16 UART1 Fractional Divider Register
The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the
baud rate generation and can be read and written at the user’s discretion. This pre-scaler
takes the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be greater than 2.
Table 380: UART1 Fractional Divider Register (FDR - address 0x4001 0028) bit description
Bit
Function
Value Description
Reset value
3:0
DIVADDVAL
0
Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud
rate generator will not impact the UART1 baud rate.
0
7:4
MULVAL
1
Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for
UART1 to operate properly, regardless of whether the fractional baud rate
generator is used or not.
1
31:8
-
Reserved. Read value is undefined, only zero should be written.
0
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART1 disabled making sure that UART1
is fully software and hardware compatible with UARTs not equipped with this feature.
UART1 baud rate can be calculated as (n = 1):
(2)
PCLK
UART1 baudrate = ---------------------------------------------------------------------------------------------------------------------------------DivAddVal
16   256  U1DLM + U1DLL    1 + ---------------------------
MulVal 
Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud
rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1  MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL < MULVAL
The value of the U1FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U1FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
480 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
17.5.16.1 Baud rate calculation
UART1 can operate with or without using the Fractional Divider. In real-life applications it
is likely that the desired baud rate can be achieved using several different Fractional
Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
Calculating UART
baudrate (BR)
PCLK,
BR
DL est = PCLK/(16 x BR)
DL est is an
integer?
True
False
DIVADDVAL = 0
MULVAL = 1
FR est = 1.5
Pick another FR est from
the range [1.1, 1.9]
DL est = Int(PCLK/(16 x BR x FR est))
FR est = PCLK/(16 x BR x DL est)
False
1.1 < FR est < 1.9?
True
DIVADDVAL = table(FR est )
MULVAL = table(FR est )
DLM = DL est [15:8]
DLL = DLest [7:0]
End
Fig 72. Algorithm for setting UART dividers
UM10562
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 13 September 2012
© NXP B.V. 2012. All rights reserved.
481 of 942
UM10562
NXP Semiconductors
Chapter 17: LPC408x/407x UART1
Table 381. Fractional Divider setting look-up table
17.5.16.1.1
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
1.000
0/1
1.250
1/4
1.500
1/2
1.750
3/4
1.067
1/15
1.267
4/15
1.533
8/15
1.769
10/13
1.071
1/14
1.273
3/11
1.538
7/13
1.778
7/9
1.077
1/13
1.286
2/7
1.545
6/11
1.786
11/14
1.083
1/12
1.300
3/10
1.556
5/9
1.800
4/5
1.091
1/11
1.308
4/13
1.571
4/7
1.818
9/11
1.100
1/10
1.333
1/3
1.583
7/12
1.833
5/6
1.111
1/9
1.357
5/14
1.600
3/5
1.846
11/13
1.125
1/8
1.364
4/11
1.615
8/13
1.857
6/7
1.133
2/15
1.375
3/8
1.625
5/8
1.867
13/15
1.143
1/7
1.385
5/13
1.636
7/11
1.875
7/8
1.154
2/13
1.400
2/5
1.643
9/14
1.889
8/9
1.167
1/6
1.417
5/12
1.667
2/3
1.900
9/10
1.182
2/11
1.429
3/7
1.692
9/13
1.909
10/11
1.200
1/5
1.444
4/9
1.700
7/10
1.917
11/12
1.214
3/14
1.455
5/11
1.714
5/7
1.923
12/13
1.222
2/9
1.462
6/13
1.727
8/11
1.929
13/14
1.231
3/13
1.467
7/15
1.733
11/15
1.933
14/15
Example 1: PCLK = 14.7456 MHz, BR = 9600
According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)
= 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and
DLL = 96.
17.5.16.1.2
Example 2: PCLK = 12 MHz, BR = 115200
According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) =
6.51. This DLest is not an integer number and the next step is to estimate the FR
parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest
is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1
and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up
table.
The closest value for FRest = 1.628 in the look-up Table 381 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equat