Order Now Product Folder Technical Documents Support & Community Tools & Software LMG1205 SNOSD37 – MARCH 2017 LMG1205 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs 1 Features 3 Description • The LMG1205 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or halfbridge configuration. The device has an integrated 100-V bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LMG1205 are TTL logic compatible and can withstand input voltages up to 14 V regardless of the VDD voltage. The LMG1205 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently. 1 • • • • • • • • • Independent High-Side and Low-Side TTL Logic Inputs 1.2-A Peak Source, 5-A Sink Current High-Side Floating Bias Voltage Rail Operates up to 100 VDC Internal Bootstrap Supply Voltage Clamping Split Outputs for Adjustable Turnon, Turnoff Strength 0.6-Ω Pulldown, 2.1-Ω Pullup Resistance Fast Propagation Times (35 ns Typical) Excellent Propagation Delay Matching (1.5 ns Typical) Supply Rail Undervoltage Lockout Low Power Consumption In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching. The LMG1205 can operate up to several MHz. The LMG1205 is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance. 2 Applications • • • • • Current-Fed Push-Pull Converters Half and Full-Bridge Converters Synchronous Buck Converters Two-Switch Forward Converters Forward with Active Clamp Converters Device Information(1) PART NUMBER LMG1205 PACKAGE DSBGA (12) BODY SIZE (NOM) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Diagram 0.1 F VIN HB HOH VDD 1 F HI LI HS LMG1205 Load LOH LOL VSS Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMG1205 SNOSD37 – MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics .......................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Examples................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 10 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History 2 DATE REVISION NOTES March 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 5 Pin Configuration and Functions YFX Package 12-Pin DSBGA Top View A LOL B LOH HI C HS VDD D HOL HOH HB HS 1 2 3 4 VSS VDD LI Pin Functions PIN NUMBER NAME TYPE (1) DESCRIPTION A1 LOL O Low-side gate driver sink-current output: connect to the gate of the low-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnoff speed. A2 VSS G Ground return: all signals are referenced to this ground. A3, C4 (2) VDD P 5-V positive gate drive supply: locally decouple to VSS using low ESR/ESL capacitor located as close as possible to the IC. A4 LI I Low-side driver control input. The LMG1205 inputs have TTL type thresholds. Unused inputs must be tied to ground and not left open. B1 LOH O Low-side gate driver source-current output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnon speed. B4 HI I High-side driver control input. The LMG1205 inputs have TTL type thresholds. Unused inputs must be tied to ground and not left open. C1, D4 (2) HS P High-side GaN FET source connection: connect to the bootstrap capacitor negative terminal and the source of the high-side GaN FET. D1 HOL O High-side gate driver turnoff output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnoff speed. D2 HOH O High-side gate driver turnon output: connect to the gate of high-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turnon speed. D3 HB P High-side gate driver bootstrap rail: connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor must be placed as close as possible to the IC. (1) (2) I = Input, O = Output, G = Ground, P = Power A3 and C4, C1 and D4 are internally connected Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 3 LMG1205 SNOSD37 – MARCH 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VDD to VSS –0.3 7 V HB to HS –0.3 7 V LI or HI input –0.3 15 V LOH, LOL output –0.3 VDD +0.3 V HOH, HOL output VHS – 0.3 VHB +0.3 V HS to VSS –5 93 V HB to VSS 0 100 V 150 °C 150 °C Operating junction temperature Storage temperature, Tstg (1) –55 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD NOM MAX UNIT 4.5 5.5 V 0 14 V HS –5 90 V HB VHS + 4 VHS + 5.5 V 50 V/ns –40 125 °C LI or HI input HS slew rate Operating junction temperature 6.4 Thermal Information LMG1205 THERMAL METRIC (1) YFX (DSBGA) UNIT 12 PINS RθJA Junction-to-ambient thermal resistance 76.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.6 °C/W RθJB Junction-to-board thermal resistance 12.0 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 12.0 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 6.5 Electrical Characteristics Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V. No load on LOL and HOL or HOH and HOL (1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTS IDD VDD quiescent current LI = HI = 0 V, VDD = VHB = TJ = 25°C 4V TJ = –40°C to 125°C IDDO VDD operating current f = 500 kHz IHB Total HB quiescent current LI = HI = 0 V, VDD = VHB = TJ = 25°C 4V TJ = –40°C to 125°C IHBO Total HB operating current f = 500 kHz IHBS HB to VSS quiescent current HS = HB = 80 V IHBSO HB to VSS operating current f = 500 kHz 0.09 0.12 TJ = 25°C 2 TJ = –40°C to 125°C 3 0.10 0.12 TJ = 25°C 1.5 TJ = –40°C to 125°C 2.5 TJ = 25°C 0.1 TJ = –40°C to 125°C 8 TJ = 25°C 0.4 TJ = –40°C to 125°C 1 mA mA mA mA µA mA INPUT PINS VIR Input voltage threshold Rising edge VIF Input voltage threshold Falling edge VIHYS Input voltage hysteresis RI Input pulldown resistance TJ = 25°C TJ = –40°C to 125°C 2.06 1.89 TJ = 25°C TJ = –40°C to 125°C 2.18 1.66 1.48 1.76 400 TJ = 25°C 100 V mV 200 TJ = –40°C to 125°C V 300 kΩ UNDERVOLTAGE PROTECTION VDDR VDD rising threshold VDDH VDD threshold hysteresis VHBR HB rising threshold VHBH HB threshold hysteresis TJ = 25°C 3.8 TJ = –40°C to 125°C 3.2 4.5 0.2 TJ = 25°C V 3.2 TJ = –40°C to 125°C 2.5 V 3.9 0.2 V V BOOTSTRAP DIODE AND CLAMP VDL Low-current forward voltage IVDD-HB = 100 µA VDH High-current forward voltage IVDD-HB = 100 mA RD Dynamic resistance IVDD-HB = 100 mA HB-HS clamp regulation voltage (1) TJ = 25°C 0.45 TJ = –40°C to 125°C 0.65 TJ = 25°C 0.9 TJ = –40°C to 125°C 1 TJ = 25°C 1.85 TJ = –40°C to 125°C 3.6 TJ = 25°C TJ = –40°C to 125°C 5 4.5 5.25 V V Ω V Parameters that show only a typical value are ensured by design and may not be tested in production. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 5 LMG1205 SNOSD37 – MARCH 2017 www.ti.com Electrical Characteristics (continued) Specifications are TJ = 25°C. Unless otherwise specified: VDD = VHB = 5 V, VSS = VHS = 0 V. No load on LOL and HOL or HOH and HOL(1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW- and HIGH-SIDE GATE DRIVER VOL Low-level output voltage IHOL = ILOL = 100 mA VOH High-level output voltage VOH = VDD – LOH or VOH = HB – HOH IHOH = ILOH = 100 mA IOHL Peak source current HOH, LOH = 0 V IOLL Peak sink current HOL, LOL = 5 V TJ = 25°C 0.06 TJ = –40°C to 125°C V 0.1 TJ = 25°C 0.21 TJ = –40°C to 125°C V 0.31 1.2 A 5 A 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TJ = 25°C TYP MAX 33.5 UNIT tLPHL LO turnoff propagation delay LI falling to LOL falling tLPLH LO turnon propagation delay LI rising to LOH rising tHPHL HO turnoff propagation delay HI falling to HOL falling tHPLH HO turnon propagation delay HI rising to HOH rising tMON Delay matching LO on and HO off TJ = 25°C tMOFF Delay matching LO off and HO on TJ = 25°C tHRC HO rise time (0.5 V – 4.5 V) CL = 1000 pF 7 ns tLRC LO rise time (0.5 V – 4.5 V) CL = 1000 pF 7 ns tHFC HO fall time (0.5 V – 4.5 V) CL = 1000 pF 3.5 ns tLFC LO fall time (0.5 V – 4.5 V) CL = 1000 pF 3.5 ns tPW Minimum input pulse width that changes the output 10 ns tBS Bootstrap diode reverse recovery time 40 ns TJ = –40°C to 125°C TJ = 25°C 50 35 TJ = –40°C to 125°C TJ = 25°C 50 33.5 TJ = –40°C to 125°C TJ = 25°C 50 35 TJ = –40°C to 125°C 50 1.5 TJ = –40°C to 125°C 8 1.5 TJ = –40°C to 125°C 8 IF = 100 mA, IR = 100 mA ns ns ns ns ns ns LI LI HI HI tHPLH tLPLH tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 6.7 Typical Characteristics Figure 2. Peak Source Current vs Output Voltage Figure 3. Peak Sink Current vs Output Voltage Figure 5. IHBO vs Frequency 80 100 75 95 70 90 CURRENT (µA) CURRENT (µA) Figure 4. IDDO vs Frequency 65 60 55 85 80 75 50 70 45 65 40 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (ºC) D005 60 -50 Figure 6. IDD vs Temperature -25 0 25 50 75 100 125 150 TEMPERATURE (ºC) D006 Figure 7. IHB vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 7 LMG1205 SNOSD37 – MARCH 2017 www.ti.com Typical Characteristics (continued) Figure 8. UVLO Rising Thresholds vs Temperature Figure 9. UVLO Falling Thresholds vs Temperature Figure 10. Input Thresholds vs Temperature Figure 11. Input Threshold Hysteresis vs Temperature 45 40 DELAY (ns) T_PLH 35 T_PHL 30 25 20 -50 Figure 12. Bootstrap Diode Forward Voltage 8 -25 0 25 50 75 100 125 150 TEMPERATURE (ºC) D012 Figure 13. Propagation Delay vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 Typical Characteristics (continued) 5.2 REGULATION (V) 5.1 5 4.9 4.8 4.7 -50 Figure 14. LO & HO Gate Drive – High/Low Level Output Voltage vs Temperature -25 0 25 50 75 100 125 150 TEMPERATURE (ºC) D014 Figure 15. HB Regulation Voltage vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 9 LMG1205 SNOSD37 – MARCH 2017 www.ti.com 7 Detailed Description 7.1 Overview The LMG1205 is a high frequency high- and low- side gate driver for enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently. The LMG1205 can operate up to several MHz, and is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance. 7.2 Functional Block Diagram HB UVLO & CLAMP HOH LEVEL SHIFT HOL HS HI VDD UVLO LOH LOL LI VSS Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Input and Output The input pins of the LMG1205 are independently controlled with TTL input thresholds and can withstand voltages up to 12 V regardless of the VDD voltage. This allows the inputs to be directly connected to the outputs of an analog PWM controller with up to 12-V power supply, eliminating the need for a buffer stage. The output pulldown and pullup resistance of LMG1205 is optimized for enhancement mode GaN FETs to achieve high frequency and efficient operation. The 0.6-Ω pulldown resistance provides a robust low impedance turnoff path necessary to eliminate undesired turnon induced by high dv/dt or high di/dt. The 2.1-Ω pullup resistance helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LMG1205 offers flexibility to adjust the turnon and turnoff speed by independently adding additional impedance in either the turnon path and/or the turnoff path. If the input signal for either of the the two channels, HI or LI, is not used, the control pin must be tied to either VDD or VSS. These inputs must not be left floating. 7.3.2 Start-up and UVLO The LMG1205 has an undervoltage lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VDD voltage, the UVLO actively pulls the LOL and HOL low. When the VDD voltage is above its UVLO threshold, but the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only HOL is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering. 10 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 Feature Description (continued) Table 1. VDD UVLO Feature Logic Operation CONDITION (VHB-HS > VHBR for all cases below) HI LI HO LO VDD - VSS < VDDR during device start-up H L L L VDD - VSS < VDDR during device start-up L H L L VDD - VSS < VDDR during device start-up H H L L VDD - VSS < VDDR during device start-up L L L L VDD - VSS < VDDR - VDDH after device start-up H L L L VDD - VSS < VDDR - VDDH after device start-up L H L L VDD - VSS < VDDR - VDDH after device start-up H H L L VDD - VSS < VDDR - VDDH after device start-up L L L L LI HO LO Table 2. VHB-HS UVLO Feature Logic Operation CONDITION (VDD > VDDR for all cases below) HI VHB-HS < VHBR during device start-up H L L L VHB-HS < VHBR during device start-up L H L H VHB-HS < VHBR during device start-up H H L H L VHB-HS < VHBR during device start-up L L L VHB-HS < VHBR - VHBH after device start-up H L L L VHB-HS < VHBR - VHBH after device start-up L H L H VHB-HS < VHBR - VHBH after device start-up H H L H VHB-HS < VHBR - VHBH after device start-up L L L L 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping Due to the intrinsic nature of enhancement mode GaN FETs, the source-to-drain voltage of the bottom switch is usually higher than a diode forward voltage drop when the gate is pulled low. This causes negative voltage on HS pin. Moreover, this negative voltage transient may become even more pronounced due to the effects of board layout and device drain/source parasitic inductances. With high-side driver using the floating bootstrap configuration, negative HS voltage can lead to an excessive bootstrap voltage, which can damage the high-side GaN FET. The LMG1205 solves this problem with an internal clamping circuit that prevents the bootstrap voltage from exceeding 5 V typical. 7.3.4 Level Shift The level-shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output, which is referenced to the HS pin and provides excellent delay matching with the low-side driver. Typical delay matching between LO and HO is around 1.5 ns. 7.4 Device Functional Modes Table 3 shows the device truth table. Table 3. Truth Table HI LI HOH HOL LOH LOL L L Open L Open L Open L H Open L H H L H Open Open L H H H Open H Open Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 11 LMG1205 SNOSD37 – MARCH 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality. 8.1 Application Information To operate GaN transistors at very high switching frequencies and to reduce associated switching losses, a powerful gate driver is employed between the PWM output of controller and the gates of the GaN transistor. Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3 V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also address other needs such as minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to the power switch), driving gate-drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. The LMG1205 is a MHz high- and low-side gate driver for enhancement mode GaN FETs in a synchronous buck, boost, or half-bridge configuration. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The LMG1205 has split-gate outputs with strong sink capability, providing flexibility to adjust the turnon and turnoff strength independently. 12 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 8.2 Typical Application The circuit in Figure 16 shows a synchronous buck converter to evaluate LMG1205. Detailed synchronous buck converter specifications are listed in Design Requirements. Optimization of he power loop (loop impedance from VIN capacitor to PGND) is critical to the performance of the design. Having a high power loop inductance causes significant ringing in the SW node and also causes an associated power loss. For more information, please refer to Related Documentation. 0.1 F VIN Rgh HB HOH VDD HOL VOUT 1 F HI HS LMG1205 COUT Rgl LI LOH LOL VSS Copyright © 2017, Texas Instruments Incorporated Figure 16. Application Circuit 8.2.1 Design Requirements When designing a synchronous buck converter application that incorporates the LMG1205 gate driver and GaN power FETs, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are the input voltages, passive components, operating frequency, and controller selection. Table 4 shows some sample values for a typical application. See Power Supply Recommendations, Layout, and Power Dissipation for other key design considerations for the LMG1205. Table 4. Design Parameters PARAMETER SAMPLE VALUE Half-bridge input supply voltage, VIN 48 V Output voltage, VOUT 12 V Output current 8A Dead time 8 ns Inductor 4.7 µH Switching frequency 1 MHz 8.2.2 Detailed Design Procedure This procedure outlines the design considerations of LMG1205 in a synchronous buck converter with enhancement mode GaN FET. For additional design help, see Related Documentation. 8.2.2.1 VDD Bypass Capacitor The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with Equation 1. QgH QgL Qrr CVDD ! 'V where • QgH and QgL are gate charge of the high-side and low-side transistors, respectively Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 13 LMG1205 SNOSD37 – MARCH 2017 • • www.ti.com Qrr is the reverse recovery charge of the bootstrap diode, which is typically around 4nC ΔV is the maximum allowable voltage drop across the bypass capacitor (1) TI recommends a 0.1–µF or larger value, good-quality ceramic capacitor. The bypass capacitor must be placed as close as possible to the device pins to minimize the parasitic inductance. 8.2.2.2 Bootstrap Capacitor The bootstrap capacitor provides the gate charge for the high-side switch, DC bias power for HB undervoltage lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with Equation 2. QgH IHB u tON Qrr CBST ! 'V where • • IHB is the quiescent current of the high-side driver ton is the maximum on-time period of the high-side transistor (2) A good-quality ceramic capacitor must be used for the bootstrap capacitor. TI recommends placing the bootstrap capacitor as close as possible to the HB and HS pins. 8.2.2.3 Power Dissipation The power consumption of the driver is an important measure that determines the maximum achievable operating frequency of the driver. It must be kept below the maximum power dissipation limit of the package at the operating temperature. The total power dissipation of the LMG1205 is the sum of the gate driver losses and the bootstrap diode power loss. The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as P CLoadH 2 CLoadL u VDD u fSW where • CLoadH and CLoadL are the high-side and the low-side capacitive loads, respectively (3) It can also be calculated with the total input gate charge of the high-side and the low-side transistors as P QgH QgL u VDD u fSW (4) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. Figure 17 shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equations. Figure 17 can be used to approximate the power losses due to the gate drivers. Gate driver power dissipation (LO+HO), VDD = 5 V Figure 17. Neglecting Bootstrap Diode Losses 14 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Because each of these events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge also result in higher reverse recovery losses. Figure 18 and Figure 19the forward bias power loss and the reverse bias power loss of the bootstrap diode respectively. The plots are generated based on calculations and lab measurements of the diode reverse time and current under several operating conditions. Figure 18 and Figure 19 can be used to predict the bootstrap diode power loss under different operating conditions. The load of high-side driver is a GaN FET with total gate charge of 10 nC. Figure 18. Forward Bias Power Loss of Bootstrap Diode VIN = 50 V The load of high-side driver is a GaN FET with total gate charge of 10 nC. Figure 19. Reverse Recovery Power Loss of Bootstrap Diode VIN = 50 V The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient temperature, the maximum allowable power loss of the IC can be defined as Equation 5. (TJ - TA) P= TJA (5) Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 15 LMG1205 SNOSD37 – MARCH 2017 www.ti.com 8.2.3 Application Curves Conditions: Input Voltage = 48 V DC, Load Current = 5 A Traces: Top Trace: Gate of Low-Side eGaN FET, Volt/div = 2 V Bottom Trace: LI of LMG1205, Volt/div = 5 V Bandwidth Limit = 600 MHz Horizontal Resolution = 0.2 µs/div Figure 20. Low-Side Driver Input and Output Conditions: Input Voltage = 48 V DC, Load Current = 10 A Traces: Trace: Switch-Node Voltage, Volts/div = 20 V Bandwidth Limit = 600 MHz Horizontal Resolution = 50 ns/div Figure 21. Switch-Node Voltage 9 Power Supply Recommendations The recommended bias supply voltage range for LMG1205 is from 4.5 V to 5.5 V. The lower end of this range is governed by the internal UVLO protection feature of the VDD supply circuit. TI recommends keeping proper margin to allow for transient voltage spikes while not violating the LMG1205 absolute maximum VDD voltage rating and the GaN transistor gate breakdown voltage limit. The UVLO protection feature also involves a hysteresis function. This means that once the device is operating in normal mode, if the VDD voltage drops, the device continues to operate in normal mode as far as the voltage drop does not exceeds the hysteresis specification, VDDH. If the voltage drop is more than hysteresis specification, the device shuts down. Therefore, while operating at or near the 4.5-V range, the voltage ripple on the VDD power supply output must be smaller than the hysteresis specification of LMG1205 UVLO to avoid triggering device shutdown. A local bypass capacitor must be placed between the VDD and VSS pins. This capacitor must be located as close as possible to the device. TI recommends a low-ESR, ceramic, surface-mount capacitor. TI also recommends using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high frequency filtering placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to 10 μF, for IC bias requirements. 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 LMG1205 www.ti.com SNOSD37 – MARCH 2017 10 Layout 10.1 Layout Guidelines Small gate capacitance and Miller capacitance enable enhancement mode GaN FETs to operate with fast switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum performance. Following are some recommendations: 1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and discharge the GaN FETs gate into a minimal physical area. This decreases the loop inductance and minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs must be placed close to the driver. 2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose excessive negative voltage transients on the driver. TI recommends connecting the HS pin and VSS pin to the respective source of the high-side and low-side transistors with a short and low-inductance path. 4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form an LCR resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp the ringing. 5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the HB and HS pins to support the high peak current being drawn from VDD during turnon of the FETs. Keeping bullet #1 (minimized GaN FETs gate driver loop) as the first priority, it is also desirable to place the VDD decoupling capacitor and the HB to HS bootstrap capacitor on the same side of the PC board as the driver. The inductance of vias can impose excessive ringing on the IC pins. 6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing lowESR ceramic capacitors adjacent to the GaN FETs. Figure 22 and Figure 23 show recommended layout patterns for the LMG1205. Two cases are considered: (1) without any gate resistors, and (2) with an optional turnon gate resistor. Note that 0402 surface mount package is assumed for the passive components in the drawings. For information on DSBGA package assembly, refer to Related Documentation. spacer 10.2 Layout Examples Bootstrap Capacitor HO HS Bootstrap Capacitor HO To Hi-Side FET D HS HOL D HS C VDD HS C VDD HS B HI LOH B HI LOH A LI VDD VSS LOL A LI VDD VSS 4 3 2 4 3 2 HB HOH 1 LO Bypass Capacitor To Hi-Side FET HS To Low-Side FET Bypass Capacitor GND HB HOH HOL LOL 1 LO GND Figure 22. Layout Example Without Gate Resistors To Low-Side FET Figure 23. Layout Example with HOH and LOH Gate Resistors Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 17 LMG1205 SNOSD37 – MARCH 2017 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • AN-1112 DSBGA Wafer Level Chip Scale Package • Using the LMG1205HBEVM GaN Half-Bridge EVM 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: LMG1205 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMG1205YFXR ACTIVE DSBGA YFX 12 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1205 LMG1205YFXT ACTIVE DSBGA YFX 12 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 1205 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LMG1205YFXR DSBGA YFX 12 3000 178.0 8.4 LMG1205YFXT DSBGA YFX 12 250 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.85 2.01 0.76 4.0 8.0 Q1 1.85 2.01 0.76 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMG1205YFXR DSBGA YFX 12 3000 210.0 185.0 35.0 LMG1205YFXT DSBGA YFX 12 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFX0012xxx D 0.600 ±0.075 E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE TMP12XXX (Rev A) D: Max = 1.905 mm, Min =1.845 mm E: Max = 1.756 mm, Min =1.695 mm 4215094/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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