TI1 LM5115 Secondary side post regulator / synchronous buck controller Datasheet

LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
LM5115 Secondary Side Post Regulator / Synchronous Buck Controller
Check for Samples: LM5115
FEATURES
1
•
•
•
•
2
•
•
Self-synchronization to main channel output
Standalone DC/DC Synchronous buck mode
Leading edge pulse width modulation
Voltage-mode control with current injection
and input line feed-forward
Operates from AC or DC input up to 75V
Wide 4.5V to 30V bias supply range
•
•
•
•
•
•
•
Wide 0.75V to 13.5V output range.
Top and bottom gate drivers sink 2.5A peak
Adaptive gate driver dead-time control
Wide bandwidth error amplifier (4MHz)
Programmable soft-start
Thermal shutdown protection
TSSOP-16 or thermally enhanced LLP-16
packages
DESCRIPTION
The LM5115 is a versatile switching regulator controller. It has two main application configurations. The first is
utilizing the Secondary Side Post Regulation (SSPR) technique to implement multiple output power converters. In
the second configuration, it can be used as a standalone synchronous buck controller (Please see page 14 for
more details). The SSPR technique develops a highly efficient and well regulated auxiliary output from the
secondary side switching waveform of an isolated power converter. Regulation of the auxiliary output voltage is
achieved by leading edge pulse width modulation (PWM) of the main channel duty cycle. Leading edge
modulation is compatible with either current mode or voltage mode control of the main output. The LM5115
drives external high side and low side NMOS power switches configured as a synchronous buck regulator. A
current sense amplifier provides overload protection and operates over a wide common mode input range.
Additional features include a low dropout (LDO) bias regulator, error amplifier, precision reference, adaptive dead
time control of the gate signals and thermal shutdown.
Typical Application Circuit
Phase Signal
Main
Output
3.3V
FEEDBACK
INPUT
Main Converter
PWM Controller
+12V
VCC Sync
HB
LM5115
VBIAS
RAMP
SS
HO
HS
RS
Auxiliary
Output
2.0V
LO
CO
COMP
CS
VOUT
FB
PGND AGND
Figure 1. Simplified Multiple Output Power Converter Utilizing SSPR Technique
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Connection Diagram
1
2
3
4
5
6
7
8
VBIAS
CS
VOUT
HB
AGND
HO
CO
HS
VCC
COMP
FB
LO
SS
PGND
RAMP
SYNC
16
15
14
13
12
11
10
9
Figure 2. 16-Lead TSSOP
See NS Package Numbers MTC16
16 VBIAS
CS 1
VOUT 2
15 HB
AGND 3
14 HO
CO 4
COMP 5
13 HS
12 VCC
EP
FB 6
11 LO
SS 7
10 PGND
RAMP 8
9 SYNC
Figure 3. 16-Lead LLP
See NS Package Numbers SDA16A
Pin Functions
Pin Descriptions
2
Pin
Name
Description
1
CS
Current Sense amplifier positive input
A low inductance current sense resistor is connected between CS
and VOUT. Current limiting occurs when the differential voltage
between CS and VOUT exceeds 45mV (typical).
Application Information
2
VOUT
Current sense amplifier negative input
Connected directly to the output voltage. The current sense
amplifier operates over a voltage range from 0V to 13.5V at the
VOUT pin.
3
AGND
Analog ground
Connect directly to the power ground pin (PGND).
4
CO
Current limit output
For normal current limit operation, connect the CO pin to the
COMP pin. Leave this pin open to disable the current limit function.
5
COMP
Compensation. Error amplifier output
COMP pin pull-up is provided by an internal 300uA current source.
6
FB
Feedback. Error amplifier inverting input
Connected to the regulated output through the feedback resistor
divider and compensation components. The non-inverting input of
the error amplifier is internally connected to the SS pin.
7
SS
Soft-start control
An external capacitor and the equivalent impedance of an internal
resistor divider connected to the bandgap voltage reference set the
soft-start time. The steady state operating voltage of the SS pin
equal to 0.75V (typical).
8
RAMP
PWM Ramp signal
An external capacitor connected to this pin sets the ramp slope for
the voltage mode PWM. The RAMP capacitor is charged with a
current that is proportional to current into the SYNC pin. The
capacitor is discharged at the end of every cycle by an internal
MOSFET.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Pin Descriptions (continued)
Pin
Name
9
SYNC
Synchronization input
A low impedance current input pin. The current into this pin sets the
RAMP capacitor charge current and the frequency of an internal
oscillator that provides a clock for the free-run (DC input) mode .
10
PGND
Power Ground
Connect directly to the analog ground pin (AGND).
11
LO
Low side gate driver output
Connect to the gate of the low side synchronous MOSFET through
a short low inductance path.
12
VCC
Output of bias regulator
Nominal 7V output from the internal LDO bias regulator. Locally
decouple to PGND using a low ESR/ESL capacitor located as
close to controller as possible.
13
HS
High side MOSFET source connection
Connect to negative terminal of the bootstrap capacitor and the
source terminal of the high side MOSFET.
14
HO
High side gate driver output
Connect to the gate of high side MOSFET through a short low
inductance path.
15
HB
High side gate driver bootstrap rail
Connect to the cathode of the bootstrap diode and the positive
terminal of the bootstrap capacitor. The bootstrap capacitor
supplies current to charge the high side MOSFET gate and should
be placed as close to controller as possible.
16
VBIAS
Supply Bias Input
Input to the LDO bias regulator and current sense amplifier that
powers internal blocks. Input range of VBIAS is 4.5V to 30V.
-
Description
Application Information
Exposed Pad Exposed Pad, underside of LLP package
(LLP
Package
Only)
Internally bonded to the die substrate. Connect to system ground
for low thermal impedance.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
3
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Block Diagram
VCC
VBIAS
7V LDO
REGULATOR
VCC
LOGIC
UVLO
7V
THERMAL
LIMIT
SYNC
HB
I SYNC
VCC
15 PA
2.5k
CLK
2.5k
VCC
I SYNC x 3
RAMP
R
Q
S
Q
LEVEL
SHIFT
HO
DRIVER
HS
0.7V
BUFFER
ADAPTIVE
DEAD TIME
DELAY
75k
CLK
CRMIX
100k
PWM
COMPARATOR
40k
VCC
LO
DRIVER
ERROR AMP
(Sink Only)
300 PA
FB
1V
0.75V
SS
VCC
NEGATIVE
CURRENT
DETECTOR
PGND
120k
1.27V
AGND
175k
ENABLE
COMP
CS
CURRENT SENSE AMP
Gain = 16
Vbias
VOUT
CV
ILIMIT AMP
Gm = 16 mA/V
(Sink Only)
1.27V
2V
CO
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1)
VBIAS to GND
–0.3V to 32V
VCC to GND
–0.3V to 9V
HS to GND
–1V to 76V
VOUT, CS to GND
– 0.3V to 15V
All other inputs to GND
−0.3V to 7.0V
Storage Temperature Range
–55°C to +150°C
Junction Temperature
+150°C
ESD Rating
HBM (2)
(1)
(2)
4
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed
performance limits and associated test conditions, see the Electrical Characteristics tables.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Operating Ratings
VBIAS supply voltage
5V to 30V
VCC supply voltage
5V to 7.5V
HS voltage
0V to 75V
HB voltage
VCC + HS
Operating Junction Temperature
–40°C to +125°C
Table 1. Typical Operating Conditions
PARAMETER
MIN
TYP
Supply Voltage, VBIAS
4.5
Supply Voltage, VCC
4.5
Supply voltage bypass, CVBIAS
0.1
1
Reference bypass capacitor, CVCC
0.1
1
HB-HS bootstrap capacitor
SYNC Current Range (VCC = 4.5V)
RAMP Saw Tooth Amplitude
VOUT regulation voltage (VBIAS min = 3V + VOUT)
MAX
UNITS
30
V
7
V
µF
10
µF
50
150
µA
1
1.75
V
0.75
13.5
V
0.047
µF
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
5
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Electrical Characteristics
Unless otherwise specified, TJ = –40°C to +125°C, VBIAS = 12V, No Load on LO or HO.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4
mA
7.15
V
VBIAS SUPPLY
Ibias
VBIAS Supply Current
FSYNC = 200kHz
VCC LOW DROPOUT BIAS REGULATOR
VccReg
VCC Regulation
VCC open circuit. Outputs not switching
VCC Current Limit
(Note 4)
VCC Under-voltage Lockout Voltage
Positive going VCC
6.65
7
40
4
VCC Under-voltage Hysteresis
0.2
SS Source Impedance
43
mA
4.5
V
0.25
0.3
V
60
77
kΩ
SOFT-START
SS Discharge Impedance
Ω
100
ERROR AMPLIFIER and FEEDBACK REFERENCE
VREF
GBW
Vio
FB Reference Voltage
Measured at FB pin
FB Input Bias Current
FB = 2V
0.737
0.75
0.763
V
0.2
0.5
µA
COMP Source Current
300
Open Loop Voltage Gain
60
dB
Gain Bandwidth Product
4
MHz
Input Offset Voltage
-7
0
µA
7
mV
COMP Offset
Threshold for VHO = high RAMP = CS =
VOUT = 0V
2
V
RAMP Offset
Threshold for VHO = high COMP = 1.5V,
CS = VOUT = 0V
1.1
V
CURRENT SENSE AMPLIFIER
Current Sense Amplifier Gain
16
V/V
Output DC Offset
1.27
V
Amplifier Bandwidth
500
kHz
16
mA / V
CURRENT LIMIT
ILIMIT Amp Transconductance
Overall Transconductance
VCLneg
237
mA / V
Positive Current Limit
VCL = VCS - VVOUT
VOUT = 6V and CO/COMP = 1.5V
37
45
53
mV
Positive Current Limit Foldback
VCL = VCS - VVOUT
VOUT = 0V and CO/COMP = 1.5V
31
38
45
mV
Negative Current Limit
VOUT = 6V
VCL = VCS - VVOUT to cause LO to
shutoff
-17
mV
2.5
kΩ
15
µA
RAMP GENERATOR
SYNC Input Impedance
SYNC Threshold
End of cycle detection threshold
Free Run Mode Peak Threshold
RAMP peak voltage with dc current
applied to SYNC.
Current Mirror Gain
Ratio of RAMP charge current to SYNC
input current.
Discharge Impedance
2.7
2.3
V
3.3
A/A
Ω
100
LOW SIDE GATE DRIVER
VOLL
LO Low-state Output Voltage
ILO = 100mA
0.2
0.5
VOHL
LO High-state Output Voltage
ILO = -100mA, VOHL = VCC -VLO
0.4
0.8
LO Rise Time
CLOAD = 1000pF
15
ns
LO Fall Time
CLOAD = 1000pF
12
ns
Peak LO Source Current
VLO = 0V
2
A
IOHL
6
Submit Documentation Feedback
V
V
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Electrical Characteristics (continued)
Unless otherwise specified, TJ = –40°C to +125°C, VBIAS = 12V, No Load on LO or HO.
SYMBOL
IOLL
PARAMETER
Peak LO Sink Current
CONDITIONS
MIN
TYP
VLO = 12V
2.5
MAX
UNITS
A
HIGH SIDE GATE DRIVER
VOLH
HO Low-state Output Voltage
IHO = 100mA
0.2
0.5
V
VOHH
HO High-state Output Voltage
IHO = -100mA, VOHH = VHB –VHO
0.4
0.8
V
HO Rise Time
CLOAD = 1000pF
15
ns
HO High Side Fall Time
CLOAD = 1000pF
12
ns
IOHH
Peak HO Source Current
VHO = 0V
2
A
IOLH
Peak HO Sink Current
VHO = 12V
2.5
A
LO Fall to HO Rise Delay
CLOAD = 0
70
ns
HO Fall to LO Rise Delay
CLOAD = 0
50
ns
SYNC Fall to HO Fall Delay
CLOAD = 0
120
ns
SYNC Rise to LO Fall Delay
CLOAD = 0
50
ns
165
°C
25
°C
SWITCHING CHARACTERISITCS
THERMAL SHUTDOWN
TSD
Thermal Shutdown Temp.
150
Thermal Shutdown Hysteresis
THERMAL RESISTANCE
θJA
Junction to Ambient
MTC Package
125
°C/W
θJA
Junction to Ambient
SDA Package
32
°C/W
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
7
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Typical Performance Characteristics
Efficiency
vs.
Load Current and Vphase
VCC Regulator Start-up Characteristics, VCC
vs.
VBIAS
100
16
Vphase = 6V
98
12
94 Vphase = 8V
10
VCC (V)
EFFICIENCY (%)
VBIAS
14
96
92
90
Vphase = 12V
88
6
86
4
84
2
82
0
1
2
3
4
5
6
VCC
8
0
7
0
2
4
6
8
10
12
14
16
LOAD (A)
VBIAS (V)
Current Value (CV)
vs.
Current Limit (VCL)
Current Sense Amplifier Gain and Phase
vs.
Frequency
2.5
25
VOUT = 6V
2
5
Gain
-10
20
Offset 1.27V
0.5
0
15
-25
10
-40
5
-55
-70
0
-20 -10
0
10
20
30
40
50
60
PHASE (o)
1
GAIN (dB)
CV (V)
Phase
16 V/V
1.5
100
1K
VCL (mV)
10K
100K
1M
FREQUENCY (Hz)
Current Error Amplifier Transconductance
Overall Current Amplifier Transconductance
400
400
VOUT = 6V
350
350
300
300
250
250
ICO (PA)
ICO (PA)
VOUT = 6V
200
16 mA/V
150
150
100
100
50
50
0
1.99
237 mA/V
0
1.995
2
2.005
2.01
2.015 2.02
30
35
40
45
50
VCL (mV)
CV (V)
8
200
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Typical Performance Characteristics (continued)
Common Mode Output Voltage
vs.
Positive Current Limit
14
Common Mode Output Voltage
vs.
Negative Current Limit (Room Temp)
12
27oC
12
10
-40oC
8
125oC
8
VOUT (V)
VOUT (V)
10
6
6
4
4
2
2
0
0
10
20
30
40
0
-20
50
VCL (mV)
-19
-18
-17
-16
-15
VCL (mV)
VCC Load Regulation to Current Limit
8
7
VCC (V)
6
5
4
3
2
1
0
0
5
10
15
20
25
30
35
40
45
ICC (mA)
Detailed Operating Description
The LM5115 controller contains all of the features necessary to implement multiple output power converters
utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient
and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter.
Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main
channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of
the main output. The LM5115 drives external high side and low side NMOS power switches configured as a
synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide
common mode input range from 0V to 13.5V. Additional features include a low dropout (LDO) bias regulator,
error amplifier, precision reference, adaptive dead time control of the gate driver signals and thermal shutdown. A
programmable oscillator provides a PWM clock signal when the LM5115 is powered by a dc input (free-run
mode) instead of the phase signal of the main channel converter (SSPR mode).
Low Drop-Out Bias Regulator (VCC)
The LM5115 contains an internal LDO regulator that operates over an input supply range from 4.5V to 30V. The
output of the regulator at the VCC pin is nominally regulated at 7V and is internally current limited to 40mA. VCC
is the main supply to the internal logic, PWM controller, and gate driver circuits. When power is applied to the
VBIAS pin, the regulator is enabled and sources current into an external capacitor connected to the VCC pin.
The recommended output capacitor range for the VCC regulator is 0.1uF to 100uF. When the voltage at the VCC
pin reaches the VCC under-voltage lockout threshold of 4.25V, the controller is enabled. The controller is
disabled if VCC falls below 4.0V (250mV hysteresis). In applications where an appropriate regulated dc bias
supply is available, the LM5115 controller can be powered directly through the VCC pin instead of the VBIAS pin.
In this configuration, it is recommended that the VCC and the VBIAS pins be connected together such that the
external bias voltage is applied to both pins. The allowable VCC range when biased from an external supply is
4.5V to 7V.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
9
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Synchronization (SYNC) and Feed-Forward (RAMP)
The pulsing “phase signal” from the main converter synchronizes the PWM ramp and gate drive outputs of the
LM5115. The phase signal is the square wave output from the transformer secondary winding before rectification
(Figure 1). A resistor connected from the phase signal to the low impedance SYNC pin produces a square wave
current (ISYNC) as shown in Figure 4. A current comparator at the SYNC input monitors ISYNC relative to an
internal 15µA reference. When ISYNC exceeds 15µA, the internal clock signal (CLK) is reset and the capacitor
connected to the RAMP begins to charge. The current source that charges the RAMP capacitor is equal to 3
times the ISYNC current. The falling edge of the phase signal sets the CLK signal and discharges the RAMP
capacitor until the next rising edge of the phase signal. The RAMP capacitor is discharged to ground by a low
impedance (100Ω) n-channel MOSFET. The input impedance at SYNC pin is 2.5kΩ which is normally much less
than the external SYNC pin resistance.
Phase
Signal
R SYNC
SYNC
CLK
15 PA
Isync
2.5K
2.5k
Isync x 3
RAMP
BUFFER
C RAMP
CLK
Figure 4. Line Feed-Forward Diagram
The RAMP and SYNC functions illustrated in Figure 4 provide line voltage feed-forward to improve the regulation
of the auxiliary output when the input voltage of the main converter changes. Varying the input voltage to the
main converter produces proportional variations in amplitude of the phase signal. The main channel PWM
controller adjusts the pulse width of the phase signal to maintain constant volt*seconds and a regulated main
output as shown in Figure 5. The variation of the phase signal amplitude and duration are reflected in the slope
and duty cycle of the RAMP signal of the LM5115 (ISYNC α phase signal amplitude). As a result, the duty cycle of
the LM5115 is automatically adjusted to regulate the auxiliary output voltage with virtually no change in the PWM
threshold voltage. Transient line regulation is improved because the PWM duty cycle of the auxiliary converter is
immediately corrected, independent of the delays of the voltage regulation loop.
12V
Phase signal
6V
Main Output = 3.3V
RAMP pin
PWM Threshold
12V
HS pin
6V
Secondary Output = 2.5V
Figure 5. Line Feed-forward Waveforms
The recommended SYNC input current range is 50µA to 150µA. The SYNC pin resistor (RSYNC) should be
selected to set the SYNC current (ISYNC) to 150µA with the maximum phase signal amplitude, VPHASE(max). This
will guarantee that ISYNC stays within the recommended range over a 3:1 change in phase signal amplitude. The
SYNC pin resistor is therefore:
10
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
RSYNC = (VPHASE(max) / 150µA) - 2.5kΩ
(1)
Once ISYNC has been established by selecting RSYNC, the RAMP signal amplitude may be programmed by
selecting the proper RAMP pin capacitor value. The recommended peak amplitude of the RAMP waveform is 1V
to 1.75V. The CRAMP capacitor is chosen to provide the desired RAMP amplitude with the nominal phase signal
voltage and pulse width.
CRAMP = (3 x ISYNC x TON ) / VRAMP
(2)
Where
CRAMP = RAMP pin capacitance
ISYNC = SYNC pin current current
TON = corresponding phase signal pulse width
VRAMP = desired RAMP amplitude (1V to 1.75V)
For example,
Main channel output = 3.3V. Phase signal maximum amplitude = 12V. Phase signal frequency = 250kHz
• Set ISYNC = 150µA with phase signal at maximum amplitude (12V):
– ISYNC = 150µA = VPHASE(max) / (RSYNC + 2.5 kΩ) = 12V / (RSYNC + 2.5 kΩ)
– RSYNC = 12V/150µA - 2.5kΩ = 77.5kΩ
• TON = Main channel duty cycle / Phase frequency = (3.3V/12V) / 250kHz = 1.1µs
• Assume desired VRAMP = 1.5V
• CRAMP = (3 x ISYNC x TON ) / VRAMP = (3 x 150µA x 1.1µs) / 1.5V
• CRAMP = 330pF
Error Amplifier and Soft-Start (FB, CO, & COMP, SS)
An internal wide bandwidth error amplifier is provided within the LM5115 for voltage feedback to the PWM
controller. The amplifier’s inverting input is connected to the FB pin. The output of the auxiliary converter is
regulated by connecting a voltage setting resistor divider between the output and the FB pin. Loop compensation
networks are connected between the FB pin and the error amplifier output (COMP). The amplifier’s non-inverting
input is internally connected to the SS pin. The SS pin is biased at 0.75V by a resistor divider connected to the
internal 1.27V bandgap reference. When the VCC voltage is below the UVLO threshold, the SS pin is discharged
to ground. When VCC rises and exceeds the positive going UVLO threshold (4.25V), the SS pin is released and
allowed to rise. If an external capacitor is connected to the SS pin, it will be charged by the internal resistor
divider to gradually increase the non-inverting input of the error amplifier to 0.75V. The equivalent impedance of
the SS resistor divider is nominally 60kΩ which determines the charging time constant of the SS capacitor.
During start-up, the output of the LM5115 converter will follow the exponential equation:
VOUT(t) = VOUT(final) x (1 - exp(-t/RSS x CSS))
(3)
Where
Rss = internal resistance of SS pin (60kΩ)
Css = external Soft-Start capacitor
VOUT(final) = regulator output set point
The initial Δv / Δt of the output voltage is VOUT(final) / Rss x Css and VOUT will be within 1% of the final
regulation level after 4.6 time constants or when t = 4.6 x Rss x Css.
Pull-up current for the error amplifier output is provided by an internal 300µA current source. The PWM threshold
signal at the COMP pin can be controlled by either the open drain error amplifier or the open drain current
amplifier connected through the CO pin to COMP. Since the internal error amplifier is configured as an open
drain output it can be disabled by connecting FB to ground. The current sense amplifier and current limiting
function will be described in a later section.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
11
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
Leading Edge Pulse Width Modulation
Unlike conventional voltage mode controllers, the LM5115 implements leading edge pulse width modulation. A
current source equal to 3 times the ISYNC current is used to charge the capacitor connected to the RAMP pin as
shown in Figure 6. The ramp signal and the output of the error amplifier (COMP) are combined through a resistor
network to produce a voltage ramp with variable dc offset (CRMIX in Figure 6). The high side MOSFET which
drives the HS pin is held in the off state at the beginning of the phase signal. When the voltage of CRMIX
exceeds the internal threshold voltage CV, the PWM comparator turns on the high side MOSFET. The HS pin
rises and the MOSFET delivers current from the main converter phase signal to the output of the auxiliary
regulator. The PWM cycle ends when the phase signal falls and power is no longer supplied to the drain of the
high side MOSFET.
Isync x 3
0.7V
RAMP
CLK
C RAMP
Phase or CLK
BUFFER
75K
RAMP
CRMIX
PWM
CV
40k
COMP
CV
CRMIX
100k
FB
HS
ERROR
AMP
SS
Leading Edge
Modulation
0.75V
Figure 6. Synchronization and Leading Edge Modulation
Leading edge modulation of the auxiliary PWM controller is required if the main converter is implemented with
peak current mode control. If trailing edge modulation were used, the additional load on the transformer
secondary from the auxiliary channel would be drawn only during the first portion of the phase signal pulse.
Referring to Figure 7, the turn off the high side MOSFET of the auxiliary regulator would create a non-monotonic
negative step in the transformer current. This negative current step would produce instability in a peak current
mode controller. With leading edge modulation, the additional load presented by the auxiliary regulator on the
transformer secondary will be present during the latter portion of the phase signal. This positive step in the phase
signal current can be accommodated by a peak current mode controller without instability.
Main
PWM
Main
PWM
Auxilary
PWM
Trailing Edge
Modulation
Auxilary
PWM
Leading Edge
Modulation
Peak Current
Threshold
Peak Current
Threshold
Transformer
Current
Transformer
Current
Figure 7. Leading versus Trailing Edge Modulation
12
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Voltage Mode Control with Current Injection
The LM5115 controller uniquely combines elements and benefits of current mode control in a voltage mode
PWM controller. The current sense amplifier shown in Figure 8 monitors the inductor current as it flows through a
sense resistor connected between CS and VOUT. The voltage gain of the sense amplifier is nominally equal to
16. The current sense output signal is shifted by 1.27V to produce the internal CV reference signal. The CV
signal is applied to the negative input of the PWM comparator and compared to CRMIX as illustrated in Figure 6.
Thus the PWM threshold of the voltage mode controller (CV) varies with the instantaneous inductor current.
Insure that the Vbias voltage is at least 3V above the regulated output voltage (VOUT).
PWM
Comparator
to PWM
Latch
CRMIX
CV
Negative Current
Comparator
Current
Sense Amp
CS
Low Side
Enable
1V
Vbias
Current
Limit Amp
1.27V
CO
VCL
AV = 16
2V
VOUT
Gm = 15 mA/V
Figure 8. Current Sensing and Limiting
Injecting a signal proportional to the instantaneous inductor current into a voltage mode controller improves the
control loop stability and bandwidth. This current injection eliminates the lead R-C lead network in the feedback
path that is normally required with voltage mode control (see Figure 9). Eliminating the lead network not only
simplifies the compensation, but also reduces sensitivity to output noise that could pass through the lead network
to the error amplifier.
The design of the voltage feedback path through the error amp begins with the selection of R1 and R2 in
Figure 9 to set the regulated output voltage. The steady state output voltage after soft-start is determined by the
following equation:
VOUT(final) = 0.75V x (1+R1/R2)
(4)
The parallel impedance of the R1, R2 resistor divider should be approximately 2kΩ (between 0.5kΩ and 5kΩ).
Lower resistance values may not be properly driven by the error amplifier output and higher feedback resistances
can introduce noise sensitivity. The next step in the design process is selection of R3, which sets the ac gain of
the error amplifier. The ac gain is given by the following equation and should be set to a value less than 30.
GAIN(ac) = R3/(R1|| R2) < 30
(5)
The capacitor C1 is connected in series with R3 to increase the dc gain of the voltage regulation loop and
improve output voltage accuracy. The corner frequency set by R3 x C1 should be less than 1/10th of the crossover frequency of the overall converter such that capacitor C1 does not add phase lag at the crossover
frequency. Capacitor C2 is added to reduce the noise in the voltage control loop. The value of C2 should be less
than 500pF and C2 may not be necessary with very careful PC board layout.
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
13
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
VOUT
No Lead
Network
Required
R1
ERROR
AMP
FB
PWM
CV
40k
SS
100k
CSS
0.75V
60k
COMP
R3
C1
C2
R2
Figure 9. Voltage Sensing and Feedback
Current Limiting (CS, CO and VOUT)
Current limiting is implemented through the current sense amplifier as illustrated in Figure 8. The current sense
amplifier monitors the inductor current that flows through a sense resistor connected between CS and VOUT.
The voltage gain of the current sense amplifier is nominally equal to 16. The output of current sense signal is
shifted by 1.27V to produce the internal CV reference signal. The CV signal drives a current limit amplifier with
nominal transconductance of 16mA/V. The current limit amplifier has an open drain (sink only) output stage and
its output pin CO is typically connected to the COMP pin. During normal operation, the voltage error amplifier
controls the COMP pin voltage which adjusts the PWM duty cycle by varying the internal CRMIX level (Figure 6).
However, when the current sense input voltage VCL exceeds 45mV, the current limit amplifier pulls down on
COMP through the CO pin. Pulling COMP low reduces the CRMIX signal below the CV signal level. When
CRMIX does not exceed the CV signal, the PWM comparator inhibits output pulses until the CRMIX signal
increases to a normal operating level.
A current limit fold-back feature is provided by the LM5115 to reduce the peak output current delivered to a
shorted load. When the common mode input voltage to the current sense amplifier (CS and VOUT pins) falls
below 2V, the current limit threshold is reduced from the normal level. At common mode voltages > 2V, the
current limit threshold is nominally 45mV. When VOUT is reduced to 0V the current limit threshold drops to 36mV
to reduce stress on the inductor and power MOSFETs.
Negative Current Limit
When inductor current flows from the regulator output through the low side MOSFET, the input to the current
sense comparator becomes negative. The intent of the negative current comparator is to protect the low side
MOSFET from excessive currents. Negative current can lead to large negative voltage spikes on the output at
turn off which can damage circuitry powered by the output. The negative current comparator threshold is
sufficiently negative to allow inductor current to reverse at no load or light load conditions. It is not intended to
support discontinuous conduction mode with diode emulation by the low side MOSFET. The negative current
comparator shown illustrated in Figure 8 monitors the CV signal and compares this signal to a fixed 1V threshold.
This corresponds to a negative VCL voltage between CS and VOUT of -17mV. The negative current limit
comparator turns off the low side MOSFET for the remainder of the cycle when the VCL input falls below this
threshold.
14
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
LM5115
www.ti.com
SNVS343D – MARCH 2005 – REVISED JULY 2006
Gate Drivers Outputs (HO & LO)
The LM5115 provides two gate driver outputs, the floating high side gate driver HO and the synchronous rectifier
low side driver LO. The low side driver is powered directly by the VCC regulator. The high side gate driver is
powered from a bootstrap capacitor connected between HB and HS. An external diode connected between VCC
and HB charges the bootstrap capacitor when the HS is low. When the high side MOSFET is turned on, HB rises
with HS to a peak voltage equal to VCC + VHS - VD where VD is the forward drop of the external bootstrap diode.
Both output drivers have adaptive dead-time control to avoid shoot through currents. The adaptive dead-time
control circuit monitors the state of each driver to ensure that the opposing MOSFET is turned off before the
other is turned on. The HB and VCC capacitors should be placed close to the pins of the LM5115 to minimize
voltage transients due to parasitic inductances and the high peak output currents of the drivers. The
recommended range of the HB capacitor is 0.047µF to 0.22µF.
Both drivers are controlled by the PWM logic signal from the PWM latch. When the phase signal is low, the
outputs are held in the reset state with the low side MOSFET on and the high side MOSFET off. When the phase
signal switches to the high state, the PWM latch reset signal is de-asserted. The high side MOSFET remains off
until the PWM latch is set by the PWM comparator (CRMIX > CV as shown in Figure 6). When the PWM latch is
set, the LO driver turns off the low side MOSFET and the HO driver turns on the high side MOSFET. The high
side pulse is terminated when the phase signal falls and SYNC input comparator resets the PWM latch.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature limit is exceeded. When activated, typically at 165 degrees Celsius, the controller is forced into a low
power standby state with the output drivers and the bias regulator disabled. The device will restart when the
junction temperature falls below the thermal shutdown hysteresis, which is typically 25 degrees. The thermal
protection feature is provided to prevent catastrophic failures from accidental device overheating.
Standalone DC/DC Synchronous Buck Mode
The LM5115 can be configured as a standalone DC/DC synchronous buck controller. In this mode the LM5115
uses leading edge modulation in conjunction with valley current mode control to control the synchronous buck
power stage. The internal oscillator within the LM5115 sets the clock frequency for the high and low side drivers
of the external synchronous buck power MOSFETs . The clock frequency in the synchronous buck mode is
programmed by the SYNC pin resistor and RAMP pin capacitor. Connecting a resistor between a dc bias supply
and the SYNC pin produces a current, ISYNC, which sets the charging current of the RAMP pin capacitor . The
RAMP capacitor is charged until its voltage reaches the peak ramp threshold of 2.25V. The RAMP capacitor is
then discharged for 300ns before beginning a new PWM cycle. The 300ns reset time of the RAMP pin sets the
minimum off time of the PWM controller in this mode. The internal clock frequency in the synchronous buck
mode is set by ISYNC, the ramp capacitor, the peak ramp threshold, and the 300ns deadtime.
FCLK ≊ 1 / ((CRAMP x 2.25V) / (ISYNC x 3) + 300ns)
(6)
See the LM5115 dc evaluation board application note (AN-1367) for more details on the synchronous buck
mode.
Input
7-70 VDC
+12V
Vcc Sync
HB
LM5115
Vbias
HO
RAMP
HS
SS
LO
Rs
Output
5V@6A
CO
CS
VOUT
FB
PGND AGND
COMP
Figure 10. Simplified Typical Application Circuit (Synchronous Buck Mode)
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
15
LM5115
SNVS343D – MARCH 2005 – REVISED JULY 2006
www.ti.com
100
VIN = 7V
EFFICIENCY (%)
95
90
85
VIN = 48V
VIN = 24V
80
VIN = 70V
75
70
1
2
3
4
5
6
LOAD (A)
Figure 11. Efficiency vs. Load Current and VIN (Synchronous Buck Mode)
Application Circuit
Figure 12. LM5115 Secondary Side Post Regulator
(Inputs from LM5025 Forward Active Clamp Converter, 36V to 78V)
16
Submit Documentation Feedback
Copyright © 2005–2006, Texas Instruments Incorporated
Product Folder Links: LM5115
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Samples
(3)
(Requires Login)
LM5115MTC
ACTIVE
TSSOP
PW
16
92
TBD
CU SNPB
Level-1-260C-UNLIM
LM5115MTC/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5115MTCX
ACTIVE
TSSOP
PW
16
2500
TBD
CU SNPB
Level-1-260C-UNLIM
LM5115MTCX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5115SD
ACTIVE
WSON
NHQ
16
1000
TBD
CU SNPB
Level-1-260C-UNLIM
LM5115SD/NOPB
ACTIVE
WSON
NHQ
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5115SDX
ACTIVE
WSON
NHQ
16
4500
TBD
CU SNPB
Level-1-260C-UNLIM
LM5115SDX/NOPB
ACTIVE
WSON
NHQ
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2012
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM5115MTCX
TSSOP
LM5115MTCX/NOPB
LM5115SD
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
PW
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
TSSOP
PW
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5115SD/NOPB
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5115SDX
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
LM5115SDX/NOPB
WSON
NHQ
16
4500
330.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5115MTCX
TSSOP
PW
16
2500
349.0
337.0
45.0
LM5115MTCX/NOPB
TSSOP
PW
16
2500
349.0
337.0
45.0
LM5115SD
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5115SD/NOPB
WSON
NHQ
16
1000
203.0
190.0
41.0
LM5115SDX
WSON
NHQ
16
4500
349.0
337.0
45.0
LM5115SDX/NOPB
WSON
NHQ
16
4500
349.0
337.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
LM5115DCEVAL