ALSC AS7C331MFT18A-85TQCN 3.3v 1m x 18 flow-through synchronous sram Datasheet

January 2005
AS7C331MFT18A
®
3.3V 1M x 18 Flow-through synchronous SRAM
Features
•
•
•
•
•
•
•
Organization: 1,048,576 words x18 bits
Fast clock to data access: 6.8/7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow-through operation
Asynchronous output enable control
Available 100-pin TQFP packages
Individual byte write and global write
•
•
•
•
•
•
Multiple chip enables for easy expansion
3.3 V core power supply
2.5 V or 3.3V I/O operation with separate VDDQ
Linear or interleaved burst control
Common data inputs and data outputs
Snooze mode for reduced power-standby
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
CLR
20
A[19:0]
Burst logic
Q
D
CS Address
register
20
1M x 18
Memory
array
18 20
CLK
18
18
GWE
BWb
D DQb
BWE
CLK
D DQa Q
Q
Byte Write
registers
BWa
2
Byte Write
registers
CLK
CE0
CE1
CE2
D
Enable
register
OE
Q
CE
CLK
ZZ
Power
down
Input
registers
Output
buffers
CLK
D Enable Q
delay
register
CLK
18
OE
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
1/21/05, v 1.4
-68
7.5
6.8
285
90
60
-75
8.5
7.5
275
90
60
Alliance Semiconductor
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
AS7C331MFT18A
®
16 Mb Synchronous SRAM products list1,2
Org
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
1MX18
512KX32
512KX36
Part Number
AS7C331MPFS18A
AS7C33512PFS32A
AS7C33512PFS36A
AS7C331MPFD18A
AS7C33512PFD32A
AS7C33512PFD36A
AS7C331MFT18A
AS7C33512FT32A
AS7C33512FT36A
AS7C331MNTD18A
AS7C33512NTD32A
AS7C33512NTD36A
AS7C331MNTF18A
AS7C33512NTF32A
AS7C33512NTF36A
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
Speed
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
6.8/7.5/8.5/10 ns
6.8/7.5/8.5/10 ns
6.8/7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
NTD1-PL
NTD-FT
:
:
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
Pipelined Burst Synchronous SRAM with NTDTM
Flow-through Burst Synchronous SRAM with NTDTM
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
1/21/05, v 1.4
Alliance Semiconductor
2 of 19
AS7C331MFT18A
®
Pin assignments
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 × 20 mm
1M x 18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
NC
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
NC
NC
VSSQ
VDDQ
NC
NC
NC
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
NC
VDD
NC
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
NC
VSSQ
VDDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
Pin configuration for 100-pin TQFP
1/21/05, v 1.4
Alliance Semiconductor
3 of 19
AS7C331MFT18A
®
Functional description
The AS7C331MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device
organized as 1,048,576 words x18 bits.
Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.8/7.5/8.5/10 ns. Three chip enable (CE) inputs permit
easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the
processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.
In a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK is
carried to the data-out buffers. ADV is ignored on the clock edge that samples ADSP asserted, but it is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and
both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst
operations use an interleaved count sequence. With LBO driven LOW, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 18 bits regardless of the state of individual BW[a,b] inputs. Alternately, when GWE is HIGH, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP LOW, but it is sampled on all subsequent clock edges. Output buffers
are disabled when BWn is sampled LOW, regardless of OE. Data is clocked into the data input register when BWn is sampled
LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C331MFT18A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at
2.5V or 3.3V. These devices are available in 100-pin TQFP package.
TQFP capacitance
Parameter
Symbol
Test conditions
Min
Max
Unit
Input capacitance
CIN*
VIN = 0V
-
5
pF
I/O capacitance
CI/O*
VOUT = 0V
-
7
pF
*Guaranteed not tested
TQFP thermal resistance
Description
Thermal resistance
(junction to ambient)1
Thermal resistance
(junction to top of case)1
Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
Symbol
Typical
Units
1–layer
θJA
40
°C/W
4–layer
θJA
22
°C/W
θJC
8
°C/W
1 This parameter is sampled
1/21/05, v 1.4
Alliance Semiconductor
4 of 19
AS7C331MFT18A
®
Signal descriptions
Signal
I/O Properties
Description
CLK
I
CLOCK
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
A,A0,A1
I
SYNC
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
DQ[a,b]
I/O
SYNC
Data. Driven as output when the chip is enabled and when OE is active.
CE0
I
SYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
CE1, CE2
I
SYNC
Synchronous chip enables. Active high and active LOW, respectively. Sampled on clock edges
when ADSC is active or when CE0 and ADSP are active.
ADSP
I
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode.
ADSC
I
SYNC
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.
ADV
I
SYNC
Advance. Asserted LOW to continue burst read/write.
GWE
I
SYNC
Global write enable. Asserted LOW to write all 32/36 and 18 bits. When HIGH, BWE and
BW[a,b] control write enable.
BWE
I
SYNC
Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs.
BW[a,b]
I
SYNC
Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is
LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write cycle.
If all BW[a,b] are inactive, the cycle is a read cycle.
OE
I
ASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO
I
STATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When
driven LOW, device follows linear Burst order. This signal is internally pulled HIGH.
ZZ
I
ASYNC
Sleep. Places device in low power mode; data is retained. Connect to GND if unused.
NC
-
-
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.
1/21/05, v 1.4
Alliance Semiconductor
5 of 19
AS7C331MFT18A
®
Write enable truth table (per byte)
Function
GWE
BWE
BWa
BWb
L
X
X
X
Write all bytes (a, b)
H
L
L
L
Write byte a
H
L
L
H
Write byte b
H
L
H
L
H
H
X
X
H
L
H
H
Read
Key: X = don’t care; L = low; H = high; BWE, BWn = internal write signal
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
L
L
L
Read
Write
Deselected
OE
X
L
H
X
X
I/O Status
High-Z
Dout
High-Z
Din, High-Z
High-Z
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Interleaved burst address (LBO = 1)
A1 A0
A1 A0
A1 A0
1st Address
00
01
10
2nd Address
01
00
11
Linear burst address (LBO = 0)
A1 A0
A1 A0
A1 A0
A1 A0
A1 A0
11
1st Address
00
01
10
11
10
2nd Address
01
10
11
00
10
11
00
01
11
10
01
10
3rd Address
10
11
00
01
3rd Address
4th Address
11
10
01
00
4th Address
1/21/05, v 1.4
Alliance Semiconductor
6 of 19
AS7C331MFT18A
®
Synchronous truth table[4]
CE01
CE1
CE2
ADSP
ADSC
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV WRITE[2]
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
OE
Address accessed
CLK
Operation
DQ
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
Q
Hi−Z
D3
D
D
D
D
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time
4 ZZ pin is always Low.
1/21/05, v 1.4
Alliance Semiconductor
7 of 19
AS7C331MFT18A
®
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
VDD, VDDQ
–0.5
+4.6
V
Input voltage relative to GND (input pins)
VIN
–0.5
VDD + 0.5
V
Input voltage relative to GND (I/O pins)
VIN
–0.5
VDDQ + 0.5
V
Power dissipation
PD
–
1.8
W
DC output current
IOUT
–
20 mA
mA
Storage temperature
Tstg
–65
+150
oC
Temperature under bias
Tbias
–65
+135
oC
Power supply voltage relative to GND
Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
Recommended operating conditions at 3.3V I/O
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage for inputs
VDD
3.135
3.3
3.465
V
Supply voltage for I/O
VDDQ
3.135
3.3
3.465
V
Vss
0
0
0
V
Symbol
Min
Nominal
Max
Unit
Supply voltage for inputs
VDD
3.135
3.3
3.465
V
Supply voltage for I/O
VDDQ
2.375
2.5
2.625
V
Vss
0
0
0
V
Ground supply
Recommended operating conditions at 2.5V I/O
Parameter
Ground supply
1/21/05, v 1.4
Alliance Semiconductor
8 of 19
AS7C331MFT18A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Sym
Conditions
Min
Max
Unit
current†
|ILI|
VDD = Max, 0V < VIN < VDD
-2
2
µA
Output leakage current
|ILO|
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
-2
2
µA
Input high (logic 1) voltage
VIH
Address and control pins
2*
VDD+0.3
I/O pins
2*
VDDQ+0.3
Input low (logic 0) voltage
VIL
Address and control pins
-0.3**
0.8
I/O pins
-0.5**
0.8
Output high voltage
VOH
IOH = –4 mA, VDDQ = 3.135V
2.4
–
V
Output low voltage
VOL
IOL = 8 mA, VDDQ = 3.465V
–
0.4
V
Input leakage
V
V
DC electrical characteristics for 2.5V I/O operation
Parameter
Sym
Conditions
Min
Max
Unit
Input leakage current†
|ILI|
VDD = Max, 0V < VIN < VDD
-2
2
µA
Output leakage current
|ILO|
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
-2
2
µA
Input high (logic 1) voltage
VIH
Address and control pins
1.7*
VDD+0.3
V
I/O pins
1.7*
VDDQ+0.3
V
Input low (logic 0) voltage
VIL
Address and control pins
-0.3**
0.7
V
I/O pins
-0.3**
0.7
V
Output high voltage
VOH
IOH = –4 mA, VDDQ = 2.375V
1.7
–
V
Output low voltage
VOL
IOL = 8 mA, VDDQ = 2.625V
–
0.7
V
† LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
*
VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**
VIL min = -1.5 for pulse width less than 0.2 X tCYC
IDD operating conditions and maximum limits
Parameter
Sym
Operating power supply current1
ICC
ISB
Standby power supply current
Conditions
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax,
IOUT = 0 mA, ZZ < VIL
All VIN ≤ 0.2V or > VDD – 0.2V, Deselected,
f = fMax, ZZ < VIL
-68
-75
-85
-10
Max
Typ
Max
Max
Max
285
225
275
250
230
90
70
90
80
80
ISB1
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
60
40
60
60
60
ISB2
Deselected, f = fMax, ZZ ≥ VDD – 0.2V,
all VIN ≤ VIL or ≥ VIH
50
30
50
50
50
Unit
mA
mA
1 ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
1/21/05, v 1.4
Alliance Semiconductor
9 of 19
AS7C331MFT18A
®
Timing characteristics over operating range
–68
Parameter
–75
–85
Sym
Min Max Min Max
Cycle time
tCYC
7.5
–
8.5
Clock access time
tCD
–
6.8
Output enable low to data valid
tOE
–
Clock high to output low Z
tLZC
Data output invalid from clock high
–10
Notes1
Min
Max
Min
Max
Unit
–
10
–
12
–
ns
–
7.5
–
8.5
–
10
ns
3.5
–
3.5
–
4.0
–
4.0
ns
2.5
–
2.5
–
2.5
–
2.5
–
ns
2,3,4
tOH
3.0
–
3.0
–
3.0
–
3.0
–
ns
2
Output enable low to output low Z
tLZOE
0
–
0
–
0
–
0
–
ns
2,3,4
Output enable high to output high Z
tHZOE
-
3.5
-
3.5
–
4.0
-
4.0
ns
2,3,4
Clock high to output high Z
tHZC
-
4.0
-
4.0
–
3.5
-
3.8
ns
2,3,4
tOHOE
0
–
0
–
0
–
0
–
ns
Clock high pulse width
tCH
2.5
–
2.5
–
3.0
–
4.0
–
ns
5
Clock low pulse width
tCL
2.5
–
2.5
–
3.0
–
4.0
–
ns
5
Address setup to clock high
tAS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
Data setup to clock high
tDS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
Write setup to clock high
tWS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6,7
Chip select setup to clock high
tCSS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6,8
Address hold from clock high
tAH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Data hold from clock high
tDH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Write hold from clock high
tWH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,7
Chip select hold from clock high
tCSH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6,8
ADV setup to clock high
tADVS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADSP setup to clock high
tADSPS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADSC setup to clock high
tADSCS
1.5
–
2.0
–
2.0
–
2.0
–
ns
6
ADV hold from clock high
tADVH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSP hold from clock high
tADSPH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
ADSC hold from clock high
tADSCH
0.5
–
0.5
–
0.5
–
0.5
–
ns
6
Output enable high to invalid output
1 See “Notes” on page 16.
Snooze Mode Electrical Characteristics
Description
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
1/21/05, v 1.4
Conditions
Symbol
ZZ > VIH
ISB2
tPDS
tPUS
tZZI
tRZZI
Alliance Semiconductor
Min
Max
Units
50
mA
cycle
cycle
cycle
cycle
2
2
2
0
10 of 19
AS7C331MFT18A
®
Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
tAS
LOAD NEW ADDRESS
tAH
A1
Address
A2
tWS
A3
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
ADV inserts wait states
OE
tOE
tHZOE
tLZOE
Dout
tOH
Q(A2Ý01)
Q(A1)
Q(A2Ý10)
Q(A2Ý11)
tCD
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
tHZC
Burst
Burst
Read
Suspend
Burst
Burst
Burst
Burst
Read
Read
Q(A3)
Read
Read
Read
Read
Read
Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11)
Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11)
DSEL
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
1/21/05, v 1.4
Alliance Semiconductor
11 of 19
AS7C331MFT18A
®
Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
tAS
tAH
Address
A1
A3
A2
tWS
tWH
BWE
BW[a:b]
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV SUSPENDS BURST
ADV
OE
tDS
Din
D(A1)
Read
Q(A1)
Suspend
Write
D(A1)
D(A2)
Read
Q(A2)
D(A2Ý01)
Suspend
Write
D(A 2)
D(A2Ý01)
D(A2Ý10)
D(A2Ý11)
D(A3)
ADV
Suspend
ADV
ADV
Burst
Write
Burst
Burst
Write
D(A 2Ý01)
Write
Write
D(A 2Ý01)
D(A 2Ý10) D(A 2Ý11)
D(A3Ý01)
Write
D(A 3)
tDH
D(A3Ý10)
Burst
Write
D(A 3Ý01)
ADV
Burst
Write
D(A 3Ý10)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
1/21/05, v 1.4
Alliance Semiconductor
12 of 19
AS7C331MFT18A
®
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tAS
tAH
Address
A2
A1
A3
tWS
tWH
BWE
BW[a:b]
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
tDS tDH
Din
D(A2)
tOE
tCD
Dout
tLZC
Q(A1)
Read
Q(A1)
tOH
tLZOE
tHZOE
Q(A3)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
D(A 2)
Read
Q(A3)
Q(A3Ý01)
ADV
Burst
Read
Q(A 3Ý01)
Q(A3Ý10)
ADV
Burst
Read
Q(A 3Ý10)
Q(A3Ý11)
ADV
Burst
Read
Q(A 3Ý11)
Suspend
Read
Q(A 3Ý11)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
1/21/05, v 1.4
Alliance Semiconductor
13 of 19
AS7C331MFT18A
®
Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCH
tCYC
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
ADDRESS
A1
A3
A2
A5
A4
A7
A6
tWS
BWE
BW[a:b]
tCSS
tAH
A8
A9
A10
tWH
tCSH
CE0,CE2
CE1
OE
tOE
tLZOE
Q(A1)
Dout
tCD
tHZOE
Q(A2)
Q(A3)
Q(A9)
Q(A4)
D(A5)
READ
Q(A1)
READ
Q(A2)
READ
Q(A3)
READ
Q(A4)
Q(A10)
tDH
tDS
Din
tOH
D(A6)
D(A7)
D(A8)
WRITE WRITE WRITE WRITE
D(A6) D(A7) D(A8)
D(A5)
READ
Q(A9)
READ
Q(A10)
Note: ADV is don’t care here.
1/21/05, v 1.4
Alliance Semiconductor
14 of 19
AS7C331MFT18A
®
Timing waveform of power down cycle
tCH
tCYC
tCL
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
tWH
tWS
BWE
BW[a:b]
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
Din
tLZOE
tHZOE
tHZC
Dout
Q(A2)
Q(A1)
tPUS
tPDS
ZZ
ZZ Recovery Cycle
Q(A2(Ý01))
Normal Operation Mode
ZZ Setup Cycle
tZZI
tRZZI
Isupply
ISB2
Sleep
State
READ
Q(A1)
1/21/05, v 1.4
READ
Q(A2)
READ
Q(A1Ý01)
Alliance Semiconductor
READ
Q(A2Ý01)
15 of 19
AS7C331MFT18A
®
AC test conditions
• Output load: For tLZC, tLZOE, tHZOE, tHZC, see Figure C. For all others, see Figure B.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
• Input and output timing reference levels: 1.5V.
+3.0V
90%
10%
GND
90%
10%
Figure A: Input waveform
DOUT
Z0 = 50Ω
50Ω
VL = 1.5V
for 3.3V I/O;
30 pF* VL = VDDQ/2
for 2.5V I/O
Figure B: Output load (A)
319Ω/1667Ω
DOUT
353Ω/1538Ω
5 pF*
GND *including scope
and jig capacitance
Figure C: Output load(B)
Notes
1
2
3
4
5
6
7
8
For test conditions, see “AC Test Conditions”, Figures A, B, and C.
This parameter is measured with output load condition in Figure C.
This parameter is sampled but not 100% tested.
tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
tCH is measured as high above VIH, and tCL is measured as low below VIL.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
Write refers to GWE, BWE, and BW[a,b].
Chip select refers to CE0, CE1, and CE2.
1/21/05, v 1.4
Alliance Semiconductor
16 of 19
AS7C331MFT18A
®
Package dimensions
100-pin TQFP (quad flat pack)
TQFP
Hd
Min
Max
A1
0.05
0.15
A2
1.35
1.45
b
0.22
0.38
c
0.09
0.20
D
13.90
14.10
E
19.90
20.10
e
0.65 nominal
Hd
15.85
16.15
He
21.80
22.20
L
0.45
0.75
L1
α
D
c
L1
L
b
A1 A2
e
α
He E
1.00 nominal
0°
7°
Dimensions in millimeters
1/21/05, v 1.4
Alliance Semiconductor
17 of 19
AS7C331MFT18A
®
Ordering information
Package
&Width
TQFP x18
–68
–75
–85
–10
AS7C331MFT18A-68TQC
AS7C331MFT18A-75TQC
AS7C331MFT18A-85TQC
AS7C331MFT18A-10TQC
AS7C331MFT18A-68TQI
AS7C331MFT18A-75TQI
AS7C331MFT18A-85TQI
AS7C331MFT18A-10TQI
Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C331MFT18A-85TQCN)
Part numbering guide
AS7C
33
1M
FT
18
A
–XX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 1M
4. Flow-through mode
5. Organization: 18 = x18
6. Production version: A = first production version
7. Clock access time: [-68 = 6.8 ns; -75 = 7.5 ns; -85 = 8.5 ns; -10 = 10.0 ns]
8. Package type: TQ = TQFP
9. Operating temperature: C = commercial (0° C to 70° C); I = industrial (-40° C to 85° C)
10. N = Lead free part
1/21/05, v 1.4
Alliance Semiconductor
18 of 19
AS7C331MFT18A
®
®
Alliance Semiconductor Corporation
Copyright © Alliance Semiconductor
2575, Augustine Drive,
All Rights Reserved
Santa Clara, CA 95054
Part Number:AS7C331MFT18A
Tel: 408 - 855 - 4900
Document Version: v 1.4
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or
registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right
to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this
document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or
correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are
possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not
intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising
out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance
products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights,
except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent
rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its
products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and
agrees to indemnify Alliance against all claims arising from such use.