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LMX2485Q 500 MHz - 3.1 GHz High Performance Delta-Sigma Low Power Dual
PLLatinum™ Frequency Synthesizers with 800 MHz Integer PLL
Check for Samples:
FEATURES
APPLICATIONS
•
•
1
23
•
•
•
•
Quadruple Modulus Prescalers for Lower
Divide Ratios
– RF PLL: 8/9/12/13 or 16/17/20/21
– IF PLL: 8/9 or 16/17
Advanced Delta Sigma Fractional
Compensation
– 12 bit or 22 bit Selectable Fractional
Modulus
– Up to 4th Order Programmable Delta-sigma
Modulator
Features for Improved Lock Times and
Programming
– Fastlock / Cycle Slip Reduction
– Integrated Time-out Counter
– Single Word Write to Change Frequencies
with Fastlock
Wide Operating Range
– LMX2485Q RF PLL: 500 MHz to 3.1 GHz
Useful Features
– Digital Lock Detect Output
– Hardware and Software Power-down
Control
– On-chip Crystal Reference Frequency
Doubler.
– RF Phase Comparison Frequency up to 50
MHz
– 2.5 to 3.6 Volt Operation with ICC = 5.0 mA
at 3.0 V
– LMX2485Q is AEC-Q100 Grade 2 Qualified
and is Manufactured on an Automotive
Grade Flow
•
•
•
Cellular Phones and Base Stations
– CDMA, WCDMA, GSM/GPRS, TDMA, EDGE,
PDC
Direct Digital Modulation Applications
Satellite and Cable TV Tuners
WLAN Standards
DESCRIPTION
The LMX2485Q is a low power, high performance
delta-sigma fractional-N PLL with an auxiliary integerN PLL. The device is fabricated using TI’s advanced
process.
With delta-sigma architecture, fractional spurs at
lower offset frequencies are pushed to higher
frequencies outside the loop bandwidth. The ability to
push close in spur and phase noise energy to higher
frequencies is a direct function of the modulator
order. Unlike analog compensation, the digital
feedback technique used in the LMX2485Q is highly
resistant to changes in temperature and variations in
wafer processing. The LMX2485Q delta-sigma
modulator is programmable up to fourth order, which
allows the designer to select the optimum modulator
order to fit the phase noise, spur, and lock time
requirements of the system.
Serial data for programming the LMX2485Q is
transferred via a three line high speed (20 MHz)
MICROWIRE interface. The LMX2485Q offers fine
frequency resolution, low spurs, fast programming
speed, and a single word write to change the
frequency. This makes it ideal for direct digital
modulation applications, where the N counter is
directly modulated with information. The LMX2485Q
is available in a 24 lead 4.0 X 4.0 X 0.8 mm WQFN
package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PLLatinum is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
SNOSCP7 – MARCH 2013
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Functional Block Diagram
VddIF1
IF N Divider
B Counter
8/9
or
16/17
Prescaler
A Counter
FinIF
ENOSC
OSCin
VddIF2
Phase
Comp
Charge
Pump
CPoutIF
Ftest/LD
MUX
Ftest/LD
Charge
Pump
CPoutRF
IF
LD
IF R
Divider
OSCout
VddRF1
VddRF2
RF R
Divider
1X / 2X
VddRF3
RF LD
VddRF4
VddRF5
RF N Divider
C Counter
8/9/12/13
or
B
Counter
RF
N
Divider
16/17/20/21
Prescaler
A Counter
FinRF
FinRF*
Phase
Comp
CE
CLK
DATA
LE
RF Fastlock
MICROWIRE
Interface
6'
Compensation
FLoutRF
GND
GND
GND
Connection Diagram
2
VddRF4
FLoutRF
VddRF3
NC
OSCin
ENOSC
Figure 1. Top View
24-Pin WQFN (RTW)
24
23
22
21
20
19
CPoutRF
1
18 OSCout
GND
2
17 VddIF2
VddRF1
3
16 CPoutIF
Pin 0
(Ground Substrate)
FinRF
4
FinRF*
5
14 VddIF1
LE
6
13 FinIF
7
8
9
10
11
12
DATA
CLK
VddRF2
CE
VddRF5
Ftest/LD
15 GND
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Pin Descriptions
Pin #
Pin Name
I/O
Pin Description
0
GND
-
Ground Substrate. This is on the bottom of the package and must be grounded.
1
CPoutRF
O
RF PLL charge pump output.
2
GND
-
RF PLL analog ground.
3
VddRF1
-
RF PLL analog power supply.
4
FinRF
I
RF PLL high frequency input pin.
5
FinRF*
I
RF PLL complementary high frequency input pin. Shunt to ground with a 100 pF capacitor.
6
LE
I
MICROWIRE Load Enable. High impedance CMOS input. Data stored in the shift registers is loaded
into the internal latches when LE goes HIGH
7
DATA
I
MICROWIRE Data. High impedance binary serial data input.
8
CLK
I
MICROWIRE Clock. High impedance CMOS Clock input. Data for the various counters is clocked
into the 24 bit shift register on the rising edge
9
VddRF2
-
Power supply for RF PLL digital circuitry.
10
CE
I
Chip Enable control pin. Must be pulled high for normal operation.
11
VddRF5
I
Power supply for RF PLL circuitry.
12
Ftest/LD
O
Test frequency output / Lock Detect.
13
FinIF
I
IF PLL high frequency input pin.
14
VddIF1
-
IF PLL analog power supply.
15
GND
-
IF PLL digital ground.
16
CPoutIF
O
IF PLL charge pump output
17
VddIF2
-
IF PLL power supply.
18
OSCout
O
Buffered output of the OSCin signal.
19
ENOSC
I
Oscillator enable. When this is set to high, the OSCout pin is enabled regardless of the state of other
pins or register bits.
20
OSCin
I
Input for TCXO signal.
21
NC
I
This pin must be left open.
22
VddRF3
-
Power supply for RF PLL digital circuitry.
23
FLoutRF
O
RF PLL Fastlock Output. Also functions as Programmable TRI-STATE CMOS output.
24
VddRF4
-
RF PLL analog power supply.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Parameter
Power Supply Voltage
Symbol
Value
Min
Typ
Max
Units
VCC
-0.3
4.25
Voltage on any pin with GND = 0V
Vi
-0.3
VCC+0.3
V
Storage Temperature Range
Ts
-65
+150
°C
Lead Temperature (Solder 4 sec.)
TL
+260
°C
(1)
(2)
V
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions"
indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC
will be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
This Device is a high performance RF integrated circuit and is ESD sensitive. Handling and assembly of this device should only be done
at ESD-free workstations.
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Recommended Operating Conditions
Parameter
Symbol
Power Supply Voltage
(1)
Operating Temperature
(1)
Value
Units
Min
Typ
Max
VCC
2.5
3.0
3.6
V
TA
-40
25
+105
°C
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. "Recommended Operating Conditions"
indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured
specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
The voltage at all the power supply pins of VddRF1, VddRF2, VddRF3, VddRF4, VddRF5, VddIF1 and VddIF2 must be the same. VCC
will be used to refer to the voltage at these pins and ICC will be used to refer to the sum of all currents through all these power pins.
Electrical Characteristics
(VCC = 3.0V; -40°C ≤ TA ≤ +105°C unless otherwise specified)
Symbol
Parameter
Conditions
Value
Min
Typ
Units
Max
Icc PARAMETERS
ICCRF
Power Supply Current, RF
Synthesizer
IF PLL OFF
RF PLL ON
Charge Pump TRI-STATE
3.3
mA
ICCIF
Power Supply Current, IF
Synthesizer
IF PLL ON
RF PLL OFF
Charge Pump TRI-STATE
1.7
mA
ICCTOTAL
Power Supply Current, Entire
Synthesizer
IF PLL ON
RF PLL ON
Charge Pump TRI-STATE
5.0
mA
ICCPD
Power Down Current
CE = ENOSC = 0V
CLK, DATA, LE = 0V
1
10
µA
RF SYNTHESIZER PARAMETERS
fFinRF
Operating Frequency (1)
pFinRF
Input Sensitivity
fPD
Phase Detector Frequency (2)
ICPoutRFSR RF Charge Pump Source
CE
Current (3)
ICPoutRFSI
NK
RF Charge Pump Sink Current (3)
RF_P = 8
500
2000
RF_P = 16
500
3100
-15
MHz
µA
RF_CPG = 1
VCPoutRF = VCC/2
190
µA
...
...
µA
RF_CPG = 15
VCPoutRF = VCC/2
1520
µA
RF_CPG = 0
VCPoutRF = VCC/2
-95
µA
RF_CPG = 1
VCPoutRF = VCC/2
-190
µA
...
µA
-1520
µA
ICPoutRFTR RF Charge Pump TRI-STATE
I
Current Magnitude
0.5 ≤ VCPoutRF ≤ VCC -0.5
|
ICPoutRF%
MIS |
VCPoutRF = VCC/2
TA = 25°C
4
dBm
95
RF_CPG = 15
VCPoutRF = VCC/2
(1)
(2)
(3)
0
50
RF_CPG = 0
VCPoutRF = VCC/2
...
Magnitude of RF CP Sink vs. CP
Source Mismatch
MHz
2
10
nA
RF_CPG > 2
3
10
%
RF_CPG ≤ 2
3
13
%
A slew rate of at least 100 V/uS is recommended for frequencies below 500 MHz for optimal performance.
For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Refer to table in RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
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Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +105°C unless otherwise specified)
Symbol
Parameter
Conditions
Value
Min
|
Magnitude of RF CP Current vs.
ICPoutRF%V
CP Voltage
|
|
Magnitude of RF CP Current vs.
ICPoutRF%T
Temperature
|
Units
Typ
Max
0.5 ≤ VCPoutRF ≤ VCC -0.5
TA = 25°C
2
8
VCPoutRF = VCC/2
4
%
%
IF SYNTHESIZER PARAMETERS
fFinIF
Operating Frequency
75
800
MHz
pFinIF
IF Input Sensitivity
-10
5
dBm
fCOMP
Phase Detector Frequency
10
MHz
ICPoutIFSR
CE
IF Charge Pump Source Current
ICPoutIFSIN
IF Charge Pump Sink Current
K
IF Charge Pump TRI-STATE
Current Magnitude
VCPoutIF = VCC/2
3.5
mA
VCPoutIF = VCC/2
-3.5
mA
0.5 ≤ VCPoutIF ≤ VCC RF -0.5
2
10
nA
|
Magnitude of IF CP Sink vs. CP
ICPoutIF%M
Source Mismatch
IS |
VCPoutIF = VCC/2
TA = 25°C
1
8
%
|
ICPoutIF%V
|
Magnitude of IF CP Current vs.
CP Voltage
0.5 ≤ VCPoutIF ≤ VCC -0.5
TA = 25°C
4
10
%
|
ICPoutIF%T
EMP
Magnitude of IF CP Current vs.
Temperature
VCPoutIF = VCC/2
4
ICPoutIFTRI
%
OSCILLATOR PARAMETERS
fOSCin
Oscillator Operating Frequency
vOSCin
Oscillator Input Sensitivity
IOSCin
Oscillator Input Current
OSC2X = 0
5
110
MHz
OSC2X = 1
5
20
MHz
0.5
VCC
VP-P
-100
100
µA
SPURS
Spurs in band
See
(4)
-55
dBc
PHASE NOISE
LF1HzRF
LF1HzIF
RF Synthesizer Normalized
Phase Noise Contribution (5)
RF_CPG = 0
-202
RF_CPG = 1
-202
RF_CPG = 3
-206
RF_CPG = 7
-208
RF_CPG = 15
-210
IF Synthesizer Normalized Phase
Noise Contribution
dBc/H
z
dBc/H
z
-209
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
(4)
(5)
1.6
VCC
V
0.4
V
In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is
one. The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop
bandwidth must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10
kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order
Modulator (FM = 0). These are relatively consistent over tuning range.
Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band
phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than
the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement
conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency =
20 MHz, FM = 0, DITH = 0.
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Electrical Characteristics (continued)
(VCC = 3.0V; -40°C ≤ TA ≤ +105°C unless otherwise specified)
Symbol
Parameter
Conditions
Value
Min
Typ
Units
Max
IIH
High-Level Input Current
VIH = VCC
-5.0
5.0
µA
IIL
Low-Level Input Current
VIL = 0 V
-5.0
5.0
µA
VOH
High-Level Output Voltage
IOH = -500 µA
VOL
Low-Level Output Voltage
IOL = 500 µA
VCC-0.4
V
0.4
V
MICROWIRE INTERFACE TIMING
tCS
Data to Clock Set Up Time
See Figure 2
25
ns
tCH
Data to Clock Hold Time
tCWH
Clock Pulse Width High
See Figure 2
8
ns
See Figure 2
25
tCWL
ns
Clock Pulse Width Low
See Figure 2
25
ns
tES
Clock to Load Enable Set Up
Time
See Figure 2
25
ns
tEW
Load Enable Pulse Width
See Figure 2
25
ns
Figure 2. MICROWIRE INPUT TIMING DIAGRAM
MSB
DATA
D19
LSB
D18
D17
D16
D15
D0
C3
C2
C1
C0
CLK
tCS
tCH
tCWH
tCWL
tES
LE
tEW
6
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Typical Performance Characteristics : Sensitivity
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
RF PLL Fin Sensitivity
TA = 25°C, RF_P = 16
20
10
VCC = 2.5V, 3.0V and 3.6V
pFinRF (dBm)
0
-10
-20
VCC = 3.6V
-30
VCC = 2.5V
VCC = 3.0V
-40
-50
0
1000
2000
3000
4000
fFinRF (MHz)
Figure 3.
RF PLL Fin Sensitivity
VCC = 3.0 V, RF_P = 16
20
10
TA = 25oC, and 85oC
0
pFinRF (dBm)
TA = -40oC
-10
-20
TA = 85oC
-30
TA = -40oC
-40
TA = 25oC
-50
0
1000
2000
3000
4000
fFinRF (MHz)
Figure 4.
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Typical Performance Characteristics : Sensitivity (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
IF PLL Fin Sensitivity
TA = 25°C, IF_P = 16
20
10
VCC = 3.0V
VCC = 3.6V
0
pFinIF (dBm)
VCC = 2.5V
-10
-20
VCC = 3.6V
VCC = 3.0V
-30
-40
VCC = 2.5V
-50
0
200
400
600
800
1000
fFinIF (MHz)
Figure 5.
IF PLL Fin Sensitivity
VCC = 3.0 V, IF_P = 16
20
10
TA = -40oC, 25oC, and 85oC
pFinIF (dBm)
0
-10
-20
TA = -40oC
-30
TA = 85oC
TA = 25oC
-40
-50
0
200
400
600
800
1000
fFinIF (MHz)
Figure 6.
8
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Typical Performance Characteristics : Sensitivity (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
OSCin Sensitivity
TA = 25°C, OSC_2X = 0
20
10
VCC = 2.5V, 3.0V, and 3.6V
INPUT POWER (dBm)
0
-10
VCC = 3.6V
-20
VCC = 3.0V
VCC = 2.5V
-30
-40
-50
0
10
30
60
90
120
150
fOSCin (MHz)
Figure 7.
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 0
20
10
TA = -40oC, 25oC, and 85oC
INPUT POWER (dBm)
0
-10
-20
TA = -40oC
o
TA = 85 C
-30
-40
TA = 25oC
-50
0
10
30
60
90
120
150
fOSCin (MHz)
Figure 8.
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Typical Performance Characteristics : Sensitivity (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
OSCin Sensitivity
TA = 25°C, OSC_2X = 1
20
10
VCC = 2.5V, 3.0V, and 3.6V
INPUT POWER (dBm)
0
VCC = 3.6V
-10
VCC = 3.0V
-20
VCC =2.5V
-30
-40
-50
0
10
5
15
20
25
fOSCin (MHz)
Figure 9.
OSCin Sensitivity
VCC = 3.0 V, OSC_2X = 1
20
10
TA = -40oC, 25oC, and 85oC
INPUT POWER (dBm)
0
-10
TA = 85oC
-20
TA = -40oC
-30
-40
TA = 25oC
-50
0
5
10
15
20
25
fOSCin (MHz)
Figure 10.
10
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Typical Performance Characteristic: FinRF Input Impedance
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
Marker 1:
50 MHz
Marker 2:
1.0 GHz
Marker 3:
2.0 GHz
2
Marker 4:
3.0 GHz
1
3
Start 1.0 GHz
Stop 3.5 GHz
4
Figure 11.
FinRF Input Impedance
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
50
670
-276
100
531
-247
200
452
-209
300
408
-212
400
373
-222
500
337
-231
600
302
-237
700
270
-239
800
241
-236
900
215
-231
1000
192
-221
1100
172
-218
1200
154
-209
1300
139
-200
1400
127
-192
1500
114
-184
1600
104
-175
1700
96
-168
1800
88
-160
1900
80
-153
2000
74
-147
2200
64
-134
2400
56
-123
2600
50
-113
2800
45
-103
3000
39
-94
3200
37
-86
3400
33
-78
3600
30
-72
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Typical Performance Characteristic: FinRF Input Impedance (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
FinRF Input Impedance
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
3800
28
-69
4000
26
-66
Typical Performance Characteristic: FinIF Input Impedance
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
Marker 1:
75 MHz
Marker 2:
800 MHz
2
1
Start 50 MHz
Stop 1000 MHz
Figure 12.
FinIF Input Impedance
12
Frequency (MHz)
Real (Ohms)
Imaginary (Ohms)
50
583
-286
75
530
-256
100
499
-241
200
426
-209
300
384
-209
400
347
-219
500
310
-224
600
276
-228
700
244
-228
800
216
-223
900
192
-218
1000
173
-208
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Typical Performance Characteristic: OSCin Input Impedance
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
MAGNITUDE OF INPUT IMPEDANCE (:)
6000
5000
4000
3000
Powered
Down
2000
1000
Powered
Up
0
0
25
50
75
100
125
150
FREQUENCY (MHz)
Figure 13.
Frequency (MHz)
Powered Up
Powered Down
Real
Imaginary
Magnitude
Real
Imaginary
Magnitude
5
1730
-3779
4157
392
-8137
8146
10
846
-2236
2391
155
-4487
4490
20
466
-1196
1284
107
-2215
2217
30
351
-863
932
166
-1495
-1504
40
316
-672
742
182
-1144
1158
50
278
-566
631
155
-912
925
60
261
-481
547
153
-758
774
70
252
-425
494
154
-652
669
80
239
-388
456
147
-576
595
90
234
-358
428
145
-518
538
100
230
-337
407
140
-471
492
110
225
-321
392
138
-436
458
120
219
-309
379
133
-402
123
130
214
-295
364
133
-374
397
140
208
-285
353
132
-349
373
150
207
-279
348
133
-329
355
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Typical Performance Characteristic: Currents
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
Power Supply Current
CE = High
6.0
TA = 85oC
5.0
TA = 25oC
TA = -40oC
ICC TOTAL (mA)
4.0
3.0
2.0
1.0
0
2.5
2.75
3.3
3.0
3.6
VCC (V)
Figure 14.
Power Supply Current
CE = LOW
0.5
ICC PD (PA)
0.4
0.3
0.2
TA = 85oC
TA = -40oC
TA = 25oC
0.1
0
2.5
2.75
3.0
3.3
3.6
VCC (V)
Figure 15.
14
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Typical Performance Characteristic: Currents (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
RF PLL Charge Pump Current
VCC = 3.0 Volts
2000
1500
RF_CPG = 15
1000
ICPoutRF (PA)
500
RF_CPG = 8
0
-500
RF_CPG = 0
-1000
RF_CPG = 1
-1500
-2000
0
0.5
1.0
1.5
2.0
2.5
3.0
VCPoutRF (V)
Figure 16.
IF PLL Charge Pump Current
VCC = 3.0 Volts
5.0
4.0
3.0
ICPoutIF (mA)
2.0
1.0
0
-1.0
-2.0
-3.0
-4.0
-5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
VCPoutIF (V)
Figure 17.
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Typical Performance Characteristic: Currents (continued)
Typical performance characteristics do not imply any sort of specification. Ensured specifications are in the Electrical
Characteristics section.
Charge Pump Leakage
RF PLL
VCC = 3.0 Volts
10
8
6
ICPoutRF TRI (nA)
4
TA = 85o C
2
0
TA = -40o C
-2
TA = 25o C
-4
-6
-8
-10
0
0.5
1.0
1.5
2.0
2.5
3.0
VCPoutRF (V)
Figure 18.
Charge Pump Leakage
IF PLL
VCC = 3.0 Volts
10
8
6
TA = 85o C
ICPoutIF TRI (nA)
4
2
0
-2
TA = -40o C
-4
TA = 25o C
-6
-8
-10
0
0.5
1.0
1.5
2.0
2.5
3.0
VCPoutIF (V)
Figure 19.
16
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Bench Test Setups
DC
Blocking
Capacitor
10 MHz
SMA Cable
Frequency
Input Pin
SMA Cable
CPout
Pin
Signal Generator
Semiconductor
Parameter
Analyzer
Device
Under
Test
OSCin
Pin
Evaluation Board
Power Supply
Charge Pump Current Measurement Procedure
The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include
absolute current level, mismatch, and leakage measurement. In order to measure the charge pump currents, a
signal is applied to the high frequency input pins. The reason for this is to specify that the phase detector gets
enough transitions in order to be able to change states. If no signal is applied, it is possible that the charge pump
current reading will be low due to the fact that the duty cycle is not 100%. The OSCin Pin is tied to the supply.
The charge pump currents can be measured by simply programming the phase detector to the necessary
polarity. For instance, in order to measure the RF charge pump, a 10 MHz signal is applied to the FinRF pin. The
source current can be measured by setting the RF PLL phase detector to a positive polarity, and the sink current
can be measured by setting the phase detector to a negative polarity. The IF PLL currents can be measured in a
similar way. Note that the magnitude of the RF PLL charge pump current is controlled by the RF_CPG bit. Once
the charge pump currents are known, the mismatch can be calculated as well. In order to measure leakage, the
charge pump is set to a TRI-STATE mode by enabling the RF_CPT and IF_CPT bits. The table below shows a
summary of the various charge pump tests.
Current Test
RF_CPG
RF_CPP
RF_CPT
IF_CPP
IF_CPT
RF Source
0 to 15
0
0
X
X
RF Sink
0 to 15
1
0
X
X
RF TRI-STATE
X
X
1
X
X
IF Source
X
X
X
0
0
IF Sink
X
X
X
1
0
IF TRI-STATE
X
X
X
X
1
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Charge Pump Current Specification Definitions
I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV
I2 = Charge Pump Sink Current at VCPout = Vcc/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = Vcc - ΔV
I5 = Charge Pump Source Current at VCPout = Vcc/2
I6 = Charge Pump Source Current at VCPout = ΔV
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 volts for this part.
vCPout refers to either VCPoutRF or VCPoutIF
ICPout refers to either ICPoutRF or ICPoutIF
Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage
Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch
Charge Pump Output Current Magnitude Variation vs. Temperature
18
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SMA Cable
Signal Generator
Frequency
Input Pin
Matching
Network
DC
Blocking
Capacitor
SMA Cable
Device
Under
Test
Ftest/LD
Pin
Frequency Counter
Evaluation Board
Power Supply
Frequency Input Pin
DC Blocking Capacitor
Corresponding Counter
Default Counter Value
MUX Value
OSCin
1000 pF
RF_R / 2
50
14
FinRF
100 pF// 1000 pF
RF_N / 2
502 + 2097150 / 4194301
15
FinIF
100 pF
IF_N / 2
534
13
OSCin
1000 pF
IF_R / 2
50
12
Sensitivity Measurement Procedure
Sensitivity is defined as the power level limits beyond which the output of the counter being tested is off by 1 Hz
or more of its expected value. It is typically measured over frequency, voltage, and temperature. In order to test
sensitivity, the MUX[3:0] word is programmed to the appropriate value. The counter value is then programmed to
a fixed value and a frequency counter is set to monitor the frequency of this pin. The expected frequency at the
Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The
factor of two comes in because the LMX2485Q has a flip-flop which divides this frequency by two to make the
duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input
impedance should be set to high impedance. In order to perform the measurement, the temperature, frequency,
and voltage is set to a fixed value and the power level of the signal is varied. Note that the power level at the part
is assumed to be 4 dB less than the signal generator power level. This accounts for 1 dB for cable losses and 3
dB for the pad. The power level range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy
is recorded for the sensitivity limits. The temperature, frequency, and voltage can be varied in order to produce a
family of sensitivity curves. Since this is an open-loop test, the charge pump is set to TRI-STATE and the unused
side of the PLL (RF or IF) is powered down when not being tested. For this part, there are actually four frequency
input pins, although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown
in above table.
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Note that for the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a fraction of
2097150 / 4194301 is used. The reason for this long fraction is to test the RF N counter and supporting fractional
circuitry as completely as possible.
Frequency
Input Pin
Network Analyzer
Device
Under
Test
Evaluation Board
Power Supply
Input Impedance Measurement Procedure
The above block diagram shows the test setup used for measuring the input impedance for the LMX2485. The
DC blocking capacitor used between the input SMA connector and the pin being measured must be changed to
a zero Ohm resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to
calibrate the network analyzer, ensure that the part is powered up, and then measure the input impedance. The
network analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the
evaluation board. An open can be implemented by putting no resistor, a short can be implemented by soldering a
zero ohm resistor as close as possible to the pin being measured, and a short can be implemented by soldering
two 100 ohm resistors in parallel as close as possible to the pin being measured. Calibration is done with the
PLL removed from the PCB. This requires the use of a clamp down fixture that may not always be generally
available. If no clamp down fixture is available, then this procedure can be done by calibrating up to the point
where the DC blocking capacitor usually is, and then implementing port extensions with the network analyzer.
Zero ohm resistor is added back for the actual measurement. Once the setup is calibrated, it is necessary to
ensure that the PLL is powered up. This can be done by toggling the power down bits (RF_PD and IF_PD) and
observing that the current consumption indeed increases when the bit is disabled. Sometimes it may be
necessary to apply a signal to the OSCin pin in order to program the part. If this is necessary, disconnect the
signal once it is established that the part is powered up. It is useful to know the input impedance of the PLL for
the purposes of debugging RF problems and designing matching networks. Another use of knowing this
parameter is make the trace width on the PCB such that the input impedance of this trace matches the real part
of the input impedance of the PLL frequency of operation. In general, it is good practice to keep trace lengths
short and make designs that are relatively resistant to variations in the input impedance of the PLL.
20
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FUNCTIONAL DESCRIPTION
NOTE
For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction,
Fastlock, and many other topics, visit ti.com/wireless. Here there is the EasyPLL
simulation tool and an online reference called "PLL Performance, Simulation, and Design",
by Dean Banerjee.
GENERAL
The LMX2485Q consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop
filter are supplied external to the chip. The various blocks are described below.
TCXO, OSCILLATOR BUFFER, AND R COUNTER
The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is
included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The
ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the
registers in the LMX2485.
The R counter divides this TXCO frequency down to the comparison frequency.
PHASE DETECTOR
The maximum phase detector operating frequency for the IF PLL is straightforward, but it is a little more involved
for the RF PLL since it is fractional. The maximum phase detector frequency for the LMX2485Q RF PLL is 50
MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal
reference frequency also limits the phase detector frequency, although the doubler helps with this limitation.
There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise
will be lower, but lock time may be increased due to cycle slipping and the capacitors in the loop filter may
become rather large.
CHARGE PUMP
For the majority of the time, the charge pump output is high impedance, and the only current through this pin is
the Tri-State leakage. However, it does put out fast correction pulses that have a width that is proportional to the
phase error presented at the phase detector.
The charge pump converts the phase error presented at the phase detector into a correction current. The
magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF
PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL
allows for a higher charge pump current to be used when the PLL is locking in order to reduce the lock time.
LOOP FILTER
The loop filter design can be rather involved. In addition to the regular constraints and design parameters, deltasigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of
the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the
delta sigma noise at 20 dB/decade faster than it rises. However, since the noise can not have infinite power, it
must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes
of discussion in this datasheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has 3
components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although a
5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is used
in this case. The loop filter design, especially for higher orders can be rather involved, but there are many
simulation tools and references available, such as the one given at the end of the functional description block.
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N COUNTERS AND HIGH FREQUENCY INPUT PINS
The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used,
there are limitations on how small the N value can be. The N counters are discussed in greater depth in the
programming section. Since the input pins to these counters ( FinRF and FinIF ) are high frequency, layout
considerations are important.
High Frequency Input Pins, FinRF and FinIF
It is generally recommended that the VCO output go through a resistive pad and then through a DC blocking
capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short ( < 1/10th of a
wavelength ), then the pad may not be necessary, but a series resistor of about 39 ohms is still recommended to
isolate the PLL from the VCO. The DC blocking capacitor should be chosen at least to be 27 pF, depending on
frequency. It may turn out that the frequency is above the self-resonant frequency of the capacitor, but since the
input impedance of the PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad
and the DC blocking capacitor should be placed as close to the PLL as possible
Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended
fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such
that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating
frequency of the PLL. 100 pF is a typical value, depending on frequency.
POWER PINS, POWER DOWN, AND POWER UP MODES
It is recommended that all of the power pins be filtered with a series 18 ohm resistor and then placing two
capacitors shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values
in theory, the ESR ( Equivalent Series Resistance ) is greater for larger capacitors. For optimal filtering minimize
the sum of the ESR and theoretical impedance of the capacitor. It is therefore recommended to provide two
capacitors of very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor
should be placed as close as possible to the pin.
The power down state of the LMX2485Q is controlled by many factors. The one factor that overrides all other
factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is
necessary to power up the chip, however, there are other bits in the programming registers that can override this
and put the PLL back in a power down state. Provided that the voltage on the CE pin is high, programming the
RF_PD and IF_PD bits to zero specifies that the part will be powered up. Programming either one of these bits to
one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this.
CE Pin
RF_PD
ATPU
Bit Enabled +
Write to RF
N Counter
PLL State
Low
X
X
Powered Down
(Asynchronous)
High
X
Yes
Powered Up
High
0
No
Powered Up
High
1
No
Powered Down
( Asynchronous )
DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase
detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less
than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to
approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The
values of ε and δ are dependent on which PLL is used and are shown in the table below:
22
PLL
ε
δ
RF
10 ns
20 ns
IF
15 ns
30 ns
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When the PLL is in the power down mode and the Ftest/LD pin is programmed for the lock detect function, it is
forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the
DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to
divide the comparison frequency presented to the lock detect circuit by 4. Note that if the MUX[3:0] word is set
such as to view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the
PLLs is determined to be out of lock.
START
LD = LOW
(Not Locked)
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
NO
Phase Error < H
YES
LD = HIGH
(Locked)
NO
YES
Phase Error > G
CYCLE SLIP REDUCTION AND FASTLOCK
The LMX2485Q offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means
that it requires no additional programming overhead to use them. It is generally recommended that the charge
pump current in the steady state be 8X or less in order to use cycle slip reduction, and 4X or less in steady state
in order to use Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be
made based on the ratio of the comparison frequency ( fCOMP ) to loop bandwidth ( BW ).
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Comparison Frequency
( fCOMP )
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fCOMP ≤ 1.25 MHz
Noticeable better than CSR
1.25 MHz < fCOMP ≤ 2 MHz
Marginally better than CSR
fCOMP > 2 MHz
Cycle Slip Reduction
( CSR )
Fastlock
Likely to provide a benefit, provided that
fCOMP > 100 X BW
Same or worse than CSR
Cycle Slip Reduction (CSR)
Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the
same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases
where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can
occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically
the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR
provides no benefit. There is a glitch when CSR is disengaged, but since CSR should be disengaged long before
the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at
the peak time of the transient response. Because this time is typically much sooner than Fastlock should be
disengaged, it does not make sense to use CSR and Fastlock in combination.
Fastlock
Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the
comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can
offer. Since Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a
significant benefit in cases where the comparison frequency is above 2 MHz. However, CSR can usually provide
an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The
reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of
engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits
the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option
of reducing the comparison frequency at the expense of phase noise in order to satisfy this constraint on
comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these
circumstances. When using Fastlock, it is also recommended that the steady state charge pump state be 4X or
less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher
order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well
optimized when the higher charge pump current and Fastlock resistor are engaged.
Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping
Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available
factors are 1/2, 1/4, and 1/16. In order to preserve the same loop characteristics, it is recommended that the
following constraint be satisfied:
(Fastlock Charge Pump Current) / (Steady State Charge Pump Current) = CSR
In order to satisfy this constraint, the maximum charge pump current in steady state is 8X for a CSR of 1/2, 4X
for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump
currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger
than this will not improve lock time, and will result in worse phase noise.
Consider an example where the desired loop bandwidth in steady state is 100 kHz and the comparison
frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it
was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is
probably sufficient. A charge pump current of 8X could be used in steady state, and a factor of 16X could be
used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies
the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the
time, since it would probably have better phase noise, and the degradation in lock time would not be too severe.
24
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Using Fastlock to Improve Lock Times
Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed in order to determine
the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel
during Fastlock. This ratio is calculated as follows:
K = ( Fastlock Charge Pump Current ) / ( Steady State Charge Pump Current )
K
Loop Bandwidth
R2p Value
Lock Time
1
1.00 X
Open
100 %
2
1.41 X
R2/0.41
71 %
3
1.73 X
R2/0.73
58%
4
2.00 X
R2
50%
8
2.83 X
R2/1.83
35%
9
3.00 X
R2/2
33%
16
4.00 X
R2/3
25%
The above table shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the
ratio , K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, it is generally
recommended that the loop filter order be one greater than the order of the delta sigma modulator, which means
that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it
would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep
the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but
not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation
tools, or trial and error.
Capacitor Dielectric Considerations for Lock Time
The LMX2485Q has a high fractional modulus and high charge pump gain for the lowest possible phase noise.
One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop
filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor
dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock
times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general
tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor
dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances,
allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the
fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase
noise and spurs.
FRACTIONAL SPUR AND PHASE NOISE CONTROLS
Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be
made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at
increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than
the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional
spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The
bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.
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The first step to do is choose FM, for the delta sigma modulator order. It is recommended to start with FM = 3 for
a third order modulator and use strong dithering. In general, there is a trade-off between primary and subfractional spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary
fractional spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order),
typically gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd
order modulator is a compromise.
The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs,
but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or
even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but
the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best).
Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them
completely, but adds the most phase noise. Weak dithering (DITH = 1) is a compromise.
The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same,
expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the
fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional
denominator as large as possible, but not to exceed 4095, so it is not necessary to use the extended fractional
numerator or denominator.
This steps can be done in different orders and it might take a few iterations to find the optimum performance.
Special considerations should be taken for lower frequencies that are below about 100 MHz. In addition squaring
up the wave, it is often helpful to use lowest terms fractions instead of highest terms fractions. Also, dithering
may turn out to not be so useful. All the things are to introduce a methodical way of thinking about optimizing
spurs, not an exact method. There will be exceptions to all these rules.
Programming Description
GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program
the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data
register is shown below. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data
stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted
in MSB first. Note that it is best to program the N counter last, since doing so initializes the digital lock detector
and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT program values into
these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the
R7 register.
MSB
LSB
DATA [21:0]
CTL [3:0]
23
4 3
2 1
0
Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are
mapped to the target control register.
26
C3
C2
C1
C0
DATA Location
x
x
x
0
R0
0
0
1
1
R1
0
1
0
1
R2
0
1
1
1
R3
1
0
0
1
R4
1
0
1
1
R5
1
1
0
1
R6
1
1
1
1
R7
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Control Register Content Map
Because the LMX2485Q registers are complicated, they are organized into two groups, basic and advanced. The
first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The
last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page
shows these registers.
Quick Start Register Map
Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2485, the quick start register map is
shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following default
conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with no dithering and no Fastlock.
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
R0
RF_N[10:0]
R1
RF_
PD
R2
IF_P
D
RF_
P
1
0
C3
C2
C1
C0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
RF_FN[11:0]
RF_R[5:0]
0001
0
2
0
RF_FD[11:0]
IF_N[18:0]
R3
R4
3
0
RF_CPG[3:0]
1
0
0
0
IF_R[11:0]
0
0
1
1
0
0
0
1
1
1
0
0
0
0
Complete Register Map
The complete register map shows all the functionality of all registers, including the last five.
REG
ISTE
R
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
R0
RF_N[10:0]
R1
RF_
PD
R2
IF_P
D
R3
R4
RF_
P
2
1
0
C3
C2
C1
C0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
RF_FN[11:0]
RF_R[5:0]
0
RF_FD[11:0]
IF_N[18:0]
ACCESS[3:0]
ATP
U
3
0
1
RF_CPG[3:0]
0
R5
0
0
IF_R[11:0]
DITH
[1:0]
FM
[1:0]
0
OSC
_2X
OSC
_OU
T
IF_
CPP
RF_FD[21:12]
R6
CSR[1:0]
R7
0
0
0
0
IF_P
MUX
[3:0]
RF_FN[21:12]
RF_CPF[3:0]
0
RF_
CPP
RF_TOC[13:0]
0
0
0
0
0
DIV4
0
1
0
0
1
IF_R
ST
RF_
RST
IF_C
PT
RF_
CPT
R0 REGISTER
Note that this register has only one control bit, so the N counter value to be changed with a single write
statement to the PLL.
REGI 23 22
STER
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DATA[22:0]
R0
RF_N[10:0]
RF_FN[11:0]
0
C0
0
RF_FN[11:0] -- Fractional Numerator for RF PLL
Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] } for a more detailed
description of this control word.
RF_N[10:0] -- RF N Counter Value
The RF N counter contains an 8/9/12/13 and a 16/17/20/21 prescaler. The N counter value can be calculated as
follows:
N = RF_P·RF_C + 4·RF_B + RF_A
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RF_C ≥Max{RF_A, RF_B} , for N-2FM-1 ... N+2FM is a necessary condition. This rule is slightly modified in the
case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for
the purposes of modulation. Consult the tables below for valid operating ranges for each prescaler.
Table 1. Operation with the 8/9/12/13 Prescaler (RF_P=0)
RF_N
RF_N [10:0]
RF_C [6:0]
RF_B [1:0]
<25
N values less than 25 are prohibited.
25-26
Possible only with a second order delta-sigma engine.
27-30
Possible only with a second or third order delta-sigma engine.
RF_A [1:0]
31
0
0
0
0
0
1
1
0
1
1
...
.
.
.
.
.
.
.
0
.
.
.
1023
1
1
1
1
1
1
1
0
1
1
1
>1023
1
N values above 1023 are prohibited.
Table 2. Operation with the 16/17/20/21 Prescaler (RF_P=1)
RF_N [10:0]
RF_N
RF_C [6:0]
<49
RF_B [1:0]
RF_A [1:0]
N values less than 49 are prohibited.
49-50
Possible only with a second order delta-sigma engine.
51-54
Possible with a second or third order delta-sigma engine.
55
0
0
0
0
0
1
1
0
1
1
1
...
.
.
.
.
.
.
.
.
.
.
.
2039
1
1
1
1
1
1
1
0
1
1
1
20402043
Possible with a second or third order delta-sigma engine.
20442045
Possible only with a second order delta-sigma engine.
>2045
N values greater than 2045 are prohibited.
R1 REGISTER
REGI
STER
23
22
R1
RF
_P
D
RF
_P
21
20
19 18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
RF_R[5:0]
RF_FD[11:0]
3
2
1
0
C3
0
C2
0
C1
1
C0
1
RF_FD[11:0] -- RF PLL Fractional Denominator
The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0],
ACCESS[1]}.
RF_R [5:0] -- RF R Divider Value
The RF R Counter value is determined by this control word. Note that this counter does allow values down to
one.
R Value
28
RF_R[5:0]
1
0
0
0
0
0
...
.
.
.
.
.
.
63
1
1
1
1
1
1
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RF_P -- RF Prescaler bit
The prescaler used is determined by this bit.
RF_P
Prescaler
Maximum Frequency
0
8/9/12/13
2000 MHz
1
16/17/20/21
3000 MHz
RF_PD -- RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and
the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions,
and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL
will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so,
regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit
then takes control of the power down function for the RF PLL.
R2 REGISTER
REGI
STER
23
R2
IF_
PD
22 21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
IF_N[18:0]
3
2
1
0
C3
0
C2
1
C1
0
C0
1
IF_N[18:0] -- IF N Divider Value
Table 3. IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
N
Value
IF_B
IF_A
≤23
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
24-55
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
56
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
57
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
...
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
26214
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Table 4. Operation with the 16/17 Prescaler (IF_P=1)
N
Value
IF_B
IF_A
≤47
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48239
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
241
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
...
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
52428
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
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R3 REGISTER
REGI
STER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
3
2
1
0
C3
0
C2
1
C1
1
C0
1
IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for
IF_R is 3.
R Value
IF_R[11:0]
3
0
0
0
0
0
0
0
0
0
0
1
1
...
.
.
.
.
.
.
.
.
.
.
.
.
4095
1
1
1
1
1
1
1
1
1
1
1
1
RF_CPG -- RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady state operation.
RF_CPG
Charge Pump State
Typical RF Charge Pump Current at 3
Volts (µA)
0
1X
95
1
2X
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
950
10
11X
1045
11
12X
1140
12
13X
1235
13
14X
1330
14
15X
1425
15
16X
1520
ACCESS -- Register Access word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional.
The ACCESS[3:0] bits determine which additional registers need to be programmed. Any one of these registers
can be individually programmed. According to the table below, when the state of a register is in default mode, all
the bits in that register are forced to a default state and it is not necessary to program this register. When the
register is programmable, it needs to be programmed through the MICROWIRE. Using this register access
technique, the programming required is reduced up to 37%.
30
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ACCESS Bit
Register Location
Register Controlled
ACCESS[0]
R3[20]
Must be set to 1
ACCESS[1]
R3[21]
R5
ACCESS[2]
R3[22]
R6
ACCESS[3]
R3[23]
R7
The default conditions the registers is shown below:
Regis
23
ter
22
21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
Data[19:0]
R4
3
2
1
0
C3
C2
C1
C0
R4 Must be programmed manually.
R5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
R6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
R7
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
This corresponds to the following bit settings.
Register
Bit Location
Bit Name
Bit Description
Bit Value
Bit State
R4[23]
ATPU
Autopowerup
0
Disabled
R4[17:16]
DITH
Dithering
2
Strong
R4[15:14]
FM
Modulation Order
3
3rd Order
R4[12]
OSC_2X
Oscillator Doubler
0
Disabled
R4[11]
OSC_OUT
OSCout Pin Enable
0
Disabled
R4[10]
IF_CPP
IF Charge Pump
Polarity
1
Positive
R4[9]
RF_CPP
RF Charge Pump
Polarity
1
Positive
R4[8]
IF_P
IF PLL Prescaler
1
16/17
R4[7:4]
MUX
Ftest/LD Output
0
Disabled
R5[23:14]
RF_FD[21:12]
Extended Fractional
Denominator
0
Disabled
R5[13:4]
RF_FN[21:12]
Extended Fractional
Numerator
0
Disabled
R6[23:22]
CSR
Cycle Slip Reduction
0
Disabled
R6[21:18]
RF_CPF
Fastlock Charge
Pump Current
0
Disabled
R6[17:4]
RF_TOC
RF Timeout Counter
0
Disabled
R7[13]
DIV4
Lock Detect
Adjustment
0
Disabled (Fcomp ≤
20 MHz)
R7[7]
IF_RST
IF PLL Counter Reset
0
Disabled
RF_RST
RF PLL Counter
Reset
0
Disabled
R4
R5
R6
R7
R7[6]
R7[5]
IF_CPT
IF PLL Tri-State
0
Disabled
R7[4]
RF_CPT
RF PLL Tri-State
0
Disabled
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R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGI
STER
23
22
21
20 19
18
17
16
15
14
13
12
11
10
9
IF_
CP
P
RF
_
CP
P
8
7
6
5
4
DATA[19:0]
R4
AT
PU
0
1
0
0
0
DITH
[1:0]
FM
[1:0]
0
OS
C_
2X
OS
C_
OU
T
IF_
P
MUX
[3:0]
3
2
1
0
C3
C2
C1
C0
1
0
0
1
MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
Output Description
0
0
0
0
High Impedance
Disabled
0
0
0
1
Push-Pull
General purpose
output, Logical “High”
State
0
0
1
0
Push-Pull
General purpose
output, Logical “Low”
State
0
0
1
1
Push-Pull
RF & IF Digital Lock
Detect
0
1
0
0
Push-Pull
RF Digital Lock
Detect
0
1
0
1
Push-Pull
IF Digital Lock Detect
0
1
1
0
Open Drain
RF & IF Analog Lock
Detect
0
1
1
1
Open Drain
RF Analog Lock
Detect
1
0
0
0
Open Drain
IF Analog Lock
Detect
1
0
0
1
Push-Pull
RF & IF Analog Lock
Detect
1
0
1
0
Push-Pull
RF Analog Lock
Detect
1
0
1
1
Push-Pull
IF Analog Lock
Detect
1
1
0
0
Push-Pull
IF R Divider divided
by 2
1
1
0
1
Push-Pull
IF N Divider divided
by 2
1
1
1
0
Push-Pull
RF R Divider divided
by 2
1
1
1
1
Push-Pull
RF N Divider divided
by 2
IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
32
IF_P
IF Prescaler
Maximum Frequency
0
8/9
800 MHz
1
16/17
800 MHz
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RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP
RF Charge Pump Polarity
0
Negative
1
Positive (Default)
IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a
negative phase detector polarity.
IF_CPP
IF Charge Pump Polarity
0
Negative
1
Positive
OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
OSCout Pin
0
Disabled (High Impedance)
1
Buffered output of OSCin pin
OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF
R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency
presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.
OSC2X
Frequency Presented to RF R Counter
Frequency Presented to IF R Counter
0
fOSCin
fOSCin
1
2 x fOSCin
FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels
closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the
loop filter should be at least one greater than the order of the delta-sigma modulator in order to allow for
sufficient roll-off.
FM
Function
0
Fractional PLL mode with a 4th order delta-sigma
modulator
1
Disable the delta-sigma modulator. Recommended
for test use only.
2
Fractional PLL mode with a 2nd order delta-sigma
modulator
3
Fractional PLL mode with a 3rd order delta-sigma
modulator
DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional
spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific.
Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero,
dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often
occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends
not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is
decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.
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DITH
Dithering Mode Used
0
Disabled
1
Weak Dithering
2
Strong Dithering
3
Reserved
ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0
register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case
is when the CE pin is low. In this case, the ATPU function is disabled.
R5 REGISTER
REGI
STER
23
22
21
20
R5
19
18
17
16
15
14 13 12
DATA[19:0]
11
10
RF_FD[21:12]
9
8
7
6
5
4
3
C3
1
RF_FN[21:12]
2
C2
0
1
C1
1
0
C0
1
Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12]
bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the
fractional numerator is expanded from 12 to 22-bits.
Fractio
nal
RF_FN[21:12]
Numer
ator
( These bits only apply in 22- bit mode)
RF_FN[11:0]
0
In 12- bit mode, these are do not care.
In 22- bit mode, for N <4096,
these bits should be all set to 0.
1
...
4095
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
4096
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
...
.
.
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.
419430
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], ACCESS[1]}
In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the
RF_FD[21:12] bits become do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode
and the fractional denominator is expanded from 12 to 22-bits.
Fractio
nal
RF_FD[21:12]
Denom
inator
( These bits only apply in 22- bit mode)
0
In 12- bit mode, these are do not care.
In 22- bit mode, for N <4096,
these bits should be all set to 0.
1
RF_FD[11:0]
...
4095
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
4096
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
...
.
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.
.
419430
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
34
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Product Folder Links:
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SNOSCP7 – MARCH 2013
R6 REGISTER
REGI
STER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
DATA[19:0]
R6
CSR[1:0]
RF_CPF[3:0]
RF_TOC[13:0]
3
2
1
0
C3
C2
C1
C0
1
1
0
1
RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin
The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the
FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and
the FLoutRF pin operates as a general purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value
between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is utilized as the RF Fastlock
output pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase
detector comparison cycles the RF synthesizer will spend in the Fastlock state.
RF_TOC
Fastlock Mode
Fastlock Period [CP events]
FLoutRF Pin Functionality
0
Disabled
N/A
High Impedance
1
Manual
N/A
Logic “0” State.
Forces all Fastlock conditions
2
Disabled
N/A
Logic “0” State
3
Disabled
N/A
Logic “1” State
4
Enabled
4X2 = 8
Fastlock
5
Enabled
5X2 = 10
Fastlock
…
Enabled
…
Fastlock
16383
Enabled
16383X2 = 32766
Fastlock
RF_CPF -- RF PLL Fastlock Charge Pump Current
Specify the charge pump current for the Fastlock operation mode for the RF PLL. Note that the Fastlock charge
pump current, steady state current, and CSR control are all interrelated.
RF_CPF
RF Charge Pump State
Typical RF Charge Pump
Current at 3 Volts (µA)
0
1X
95
1
2X
190
2
3X
285
3
4X
380
4
5X
475
5
6X
570
6
7X
665
7
8X
760
8
9X
855
9
10X
950
10
11X
1045
11
12X
1140
12
13X
1235
13
14X
1330
14
15X
1425
15
16X
1520
CSR[1:0] -- RF Cycle Slip Reduction
CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence
of phase detector cycle slips. Note that the Fastlock charge pump current, steady state current, and CSR control
are all interrelated. Refer to CYCLE SLIP REDUCTION AND FASTLOCK for information on how to use this.
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SNOSCP7 – MARCH 2013
www.ti.com
CSR
CSR State
Sample Rate Reduction Factor
0
Disabled
1
1
Enabled
1/2
2
Enabled
1/4
3
Enabled
1/16
R7 REGISTER
REGI
STER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
R7
0
0
0
0
0
0
0
0
0
Data[19:0]
0 DIV 0
4
1
0
0
1
IF_
RS
T
RF
_R
ST
IF_
CP
T
RF
_C
PT
3
2
1
0
C3
1
C2
1
C1
1
C0
1
DIV4 -- RF Digital Lock Detect Divide By 4
Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked
condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison
frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4.
This enables this circuitry to work at higher comparison frequencies. It is recommended that this bit be enabled
whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.
IF_RST -- IF PLL Counter Reset
When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a Tri-State
condition. This feature should be disabled for normal operation. Note that a counter reset is applied whenever the
chip is powered up via software or CE pin.
IF_RST
IF PLL N and R
Counters
IF PLL Charge Pump
0 (Default)
Normal Operation
Normal Operation
1
Counter Reset
Tri-State
RF_RST -- RF PLL Counter Reset
When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a Tri-State
condition. This feature should be disabled for normal operation. This feature should be disabled for normal
operation. Note that a counter reset is applied whenever the chip is powered up via software or CE pin.
RF_RST
RF PLL N and R
Counters
RF PLL Charge
Pump
0 (Default)
Normal Operation
Normal Operation
1
Counter Reset
Tri-State
RF_TRI -- RF Charge Pump Tri-State
When this bit is enabled, the RF PLL charge pump is put in a Tri-State condition, but the counters are not reset.
This feature is typically disabled for normal operation.
RF_TRI
RF PLL N and R
Counters
RF PLL Charge
Pump
0 (Default)
Normal Operation
Normal Operation
1
Normal Operation
Tri-State
IF_TRI -- IF Charge Pump Tri-State
When this bit is enabled, the IF PLL charge pump is put in a Tri-State condition, but the counters are not reset.
This feature is typically disabled for normal operation.
36
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Product Folder Links:
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SNOSCP7 – MARCH 2013
IF_TRI
IF PLL N and R
Counters
IF PLL Charge Pump
0 (Default)
Normal Operation
Normal Operation
1
Normal Operation
Tri-State
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Product Folder Links:
37
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMX2485QSQ/NOPB
ACTIVE
WQFN
RTW
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
X2485Q
LMX2485QSQX/NOPB
ACTIVE
WQFN
RTW
24
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
X2485Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
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