ESMT (Preliminary) Flash 2.5V Only 4 Mbit Serial Flash Memory with Dual Output FEATURES y y Single supply voltage 2.3~3.3V Standard, Dual SPI y Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 86MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 86MHz/ 100MHz (100MHz / 172MHz/ 200MHz equivalent Dual SPI) y Low power consumption - Active current: 25 mA - Standby current: 5 μ A - Deep Power Down current: 3 μ A y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Byte programming time: 7 μ s (typical) - Page programming time: 0.8 ms (typical) F25S04PA y Erase - Chip erase time 3 sec (typical) - Block erase time 0.4 sec (typical) - Sector erase time 40 ms (typical) y Page Programming - 256 byte per programmable page y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y End of program or erase detection y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant ORDERING INFORMATION Product ID Speed Package COMMENTS F25S04PA –50PG 50MHz 8-lead SOIC 150 mil Pb-free F25S04PA –86PG 86MHz 8-lead SOIC 150 mil Pb-free F25S04PA –100PG 100MHz 8-lead SOIC 150 mil Pb-free F25S04PA –50PAG 50MHz 8-lead SOIC 200 mil Pb-free F25S04PA –86PAG 86MHz 8-lead SOIC 200 mil Pb-free F25S04PA –100PAG 100MHz 8-lead SOIC 200 mil Pb-free F25S04PA –50DG 50MHz 8-lead PDIP 300 mil Pb-free F25S04PA –86DG 86MHz 8-lead PDIP 300 mil Pb-free F25S04PA –100DG 100MHz 8-lead PDIP 300 mil Pb-free F25S04PA –50HG 50MHz 8-lead DFN 5x6 mm Pb-free F25S04PA –86HG 86MHz 8-lead DFN 5x6 mm Pb-free F25S04PA –100HG 100MHz 8-lead DFN 5x6 mm Pb-free Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 1/34 ESMT (Preliminary) GENERAL DESCRIPTION The F25S04PA is a 4Megabit, 2.5V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. is divided into 128 uniform sectors with 4K byte each; 8 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The memory array can be organized into 2,048 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. The device features sector erase architecture. The memory array F25S04PA PIN CONFIGURATIONS 8- LEAD SOIC CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 2/34 ESMT (Preliminary) F25S04PA 8- LEAD PDIP CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI 8- LEAD DFN CE 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 3/34 ESMT (Preliminary) F25S04PA PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing for serial input and output operations SI Serial Data Input To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. CE Chip Enable To activate the device when CE is low. WP Write Protect The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. HOLD Hold VDD Power Supply VSS Ground To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. FUNCTIONAL BLOCK DIAGRAM Address Buffers and Latches Flash X-Decoder Y-Decoder I/O Butters and Data Latches Control Logic Serial Interface CE SCK Elite Semiconductor Memory Technology Inc. SI SO WP HOLD Publication Date: May 2009 Revision: 0.2 4/34 ESMT (Preliminary) F25S04PA SECTOR STRUCTURE Table 1: F25S04PA Sector Address Table Block 7 6 5 4 3 2 1 0 Sector Sector Size (Kbytes) 127 4KB Address range A17 A16 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 0 0 0 07F000H – 07FFFFH : : 112 4KB 070000H – 070FFFH 111 4KB 06F000H – 06FFFFH : : : : 96 4KB 060000H – 060FFFH 95 4KB 05F000H – 05FFFFH : : : 80 4KB 050000H – 050FFFH 79 4KB 04F000H – 04FFFFH : : : 64 4KB 040000H – 040FFFH 63 4KB 03F000H – 03FFFFH : : 48 4KB 030000H – 030FFFH 47 4KB 02F000H – 02FFFFH : : 32 4KB 020000H – 020FFFH 31 4KB 01F000H – 01FFFFH : : : : : 16 4KB 010000H – 010FFFH 15 4KB 00F000H – 00FFFFH : : : 0 4KB 000000H – 000FFFH Elite Semiconductor Memory Technology Inc. Block Address A18 Publication Date: May 2009 Revision: 0.2 5/34 ESMT (Preliminary) F25S04PA STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit Name 0 BUSY 1 WEL 2 3 4 5 6 BP0 BP1 BP2 TB RESERVED 7 BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Top / Bottom write protect Reserved for future use 1 = BP2,BP1,BP0 and TB are read-only bits 0 = BP2,BP1,BP0 and TB are read/writable Default at Power-up Read/Write 0 R 0 R 0 0 0 0 0 R/W R/W R/W R/W N/A 0 R/W Note: 1. Only BP0, BP1, BP2, TB and BPL are writable. 2. BP0, BP1, BP2, TB and BPL are non-volatile; others volatile. 3. All area are protected at power-on (BP2=BP1=BP0=1) WRITE ENABLE LATCH (WEL) BUSY The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. • • • • • • • Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions Elite Semiconductor Memory Technology Inc. Top/Bottom Block Protect (TB) The Top/Bottom bit (TB) controls if the Block-Protection (BP2, BP1, BP0) bits protect from the Top (TB=0) or the Bottom (TB=1) of the array as show in Table 3, The TB bit can be set with Write Status Register (WRSR) instruction. The TB bit can not be written to if the Block- Protection-Look (BPL) bit is 1 or WP is low. Publication Date: May 2009 Revision: 0.2 6/34 ESMT (Preliminary) F25S04PA Table 3: F25S04PA Block Protection Table Protection Level Status Register Bit TB BP2 BP1 Protected Memory Area BP0 Block Range Address Range 0 X 0 0 0 None None Upper 1/8 0 0 0 1 Block 7 070000H – 07FFFFH Upper 1/4 0 0 1 0 Block 6~7 060000H – 07FFFFH Upper 1/2 0 0 1 1 Block 4~7 040000H – 07FFFFH Lower 1/8 1 0 0 1 Block 0 000000H – 00FFFFH Lower 1/4 1 0 1 0 Block 0~1 000000H – 01FFFFH Lower 1/2 1 0 1 1 Block 0~3 000000H – 03FFFFH All Blocks X 1 X X Block 0~7 000000H – 07FFFFH Block Protection (BP2, BP1, BP0) Block Protection Lock-Down (BPL) The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the TB, BPL, BP2, BP1, and BP0 bits. When BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to 0. Elite Semiconductor Memory Technology Inc. the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Publication Date: May 2009 Revision: 0.2 7/34 ESMT (Preliminary) F25S04PA HOLD OPERATION HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform. activate the HOLD mode, CE must be in active low state. The Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 22 for Hold timing. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in SCK HO LD A c t iv e H o ld H old A c ti v e A c t iv e Figure 1: HOLD Condition Waveform WRITE PROTECTION The device provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for Block-Protection description. Write Protect Pin ( WP ) Table 4: Conditions to Execute Write-Status-Register (WRSR) Instruction WP BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 8/34 ESMT (Preliminary) F25S04PA INSTRUCTIONS Instructions are used to Read, Write (Erase and Program), and configure the F25S04PA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. significant bit. CE must be driven low before an instruction is Table 5: Device Operation Instructions Operation Read Fast Read Fast Read Dual 11,12 Output Sector Erase4 (4K Byte) Block Erase4, (64K Byte) Max. Freq SIN 33 MHz 03H 0BH Read Status Register (RDSR) 6 Write Status Register (WRSR) Write Enable (WREN) 9 Write Disable (WRDI) Deep Power Down (DP) Release from Deep Power Down (RDP) Read Electronic 7 Signature (RES) Jedec Read ID (JEDEC-ID) 8 Read ID (RDID) 10 2 SOUT SIN Hi-Z A23-A16 Hi-Z A23-A16 3BH 20H D8H 60H / C7H Chip Erase Page Program (PP) 1 Bus Cycle 1~3 4 SOUT SIN SOUT SIN SOUT SIN Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X 3 A23-A16 A15-A8 A7-A0 5 6 SOUT DOUT0 X SIN X X X N SOUT DOUT1 DOUT0 SIN SOUT X X cont. cont. cont. DOUT0~1 Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z - - - - - - Hi-Z - - - - - - DIN0 Hi-Z DIN1 Hi-Z - - - - - - Up to 256 Hi-Z bytes 02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z 05H Hi-Z X DOUT - - - - - - - - - - 01H Hi-Z DIN Hi-Z - - -. - - - - - - - 100MHz 06H 04H B9h Hi-Z Hi-Z Hi-Z - - - - - - - - - - - - ABH Hi-Z - - - - - - - - - - - - ABH Hi-Z X X X X X X X 12H - - - - 9FH Hi-Z X 8CH X 20H X 13H - - - - - - 90H Hi-Z 00H Hi-Z 00H Hi-Z 00H 01H Hi-Z Hi-Z X X 8CH 12H X X 12H 8CH - - 50MHz ~ Note: 1. 2. 3. 4. 5. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One bus cycle is eight clock periods. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. 6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . 7. 8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as memory capacity. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both 9. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 9/34 ESMT (Preliminary) F25S04PA instructions effective. WREN can enable WRSR, user just need to execute it. A successful WRSR can reset WREN. 10. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 11. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 12. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1) DOUT0 DOUT1 Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 10/34 ESMT (Preliminary) F25S04PA Read (33MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a the data from address location 7FFFFH had been read, the next output will be from address location 00000H. low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence. Figure 2: Read Sequence Fast Read (50 MHz ~ 100 MHz) The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4Mbit density, once the data from address location 7FFFFH has been read, the next output will be from address location 000000H. [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 ADD. 0B SI MSB SO 15 16 23 24 ADD. 31 32 ADD. 39 40 47 48 55 56 63 64 71 72 80 X MSB HIGH IMPENANCE N N+1 N+2 N+3 N+4 DOUT DOUT DOUT DOUT DOUT MSB Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 3: Fast Read Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 11/34 ESMT (Preliminary) F25S04PA Fast Read Dual Output (50 MHz ~ 100 MHz) The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on SI and SO pins. This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache code- segments to RAM for execution. The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence. Figure 4: Fast Read Dual Output Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 12/34 ESMT (Preliminary) F25S04PA Page Program (PP) The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Prior to any Write operation, the Write Enable (WREN) instruction CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the Busy bit. It is recommended to wait for a duration of TBP before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 7 for the Page Program sequence. must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously Figure 7: Page Program Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 13/34 ESMT (Preliminary) F25S04PA 64K Byte Block Erase The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be -A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 8 for the Block Erase sequence. executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23 Figure 8: 64K-byte Block Erase Sequence 4K Byte Sector Erase [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 9 for the Sector Erase sequence. Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits CE MODE3 15 16 0 1 2 3 4 5 6 7 8 31 23 24 SCK MODE0 20 SI MSB SO ADD. ADD. ADD. MSB HIGH IMPENANCE Figure 9: 4K-byte Sector Erase Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 14/34 ESMT (Preliminary) F25S04PA Chip Erase The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 10 for the Chip Erase sequence. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 60 or C7 SI MSB SO HIGH IMPENANCE Figure 10: Chip Erase Sequence Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 11 for the RDSR instruction sequence. Figure 11: Read Status Register (RDSR) Sequence Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 15/34 ESMT (Preliminary) F25S04PA Write Enable (WREN) The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. CE 0 1 2 3 4 5 6 7 MODE3 SCK MODE0 06 SI MSB HIGH IMPENANCE SO Figure 12: Write Enable (WREN) Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 04 SI MSB SO Figure 13: Write Disable (WRDI) Sequence Elite Semiconductor Memory Technology Inc. HIGH IMPENANCE CE Publication Date: May 2009 Revision: 0.2 16/34 ESMT (Preliminary) F25S04PA Write-Status-Register (WRSR) The Write Status Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 14 for WREN and WRSR instruction sequences. Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lock down the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, TB, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the TB, BP0; BP1 and BP2 bits at the same time. See Table 4 for a summary description of WP and BPL functions. CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Stauts Register Da ta In 06 SI 01 MSB SO 7 6 5 4 3 2 1 0 MSB HIGH IMPENANCE Figure 14: Write-Enable (WREN) and Write-Status-Register (WRSR) Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 17/34 ESMT (Preliminary) F25S04PA Deep Power Down (DP) Once the device is in deep power down status, all instructions will be ignored except the Release from Deep Power Down instruction (RDP) and Read Electronic Signature instruction (RES). The device always power-up in the normal operation with the standby current (ISB1). See Figure 15 for the Deep Power Down instruction. The Deep Power Down instruction is for minimizing power consumption (the standby current is reduced from ISB1 to ISB2.). This instruction is initiated by executing an 8-bit command, B9H, and then CE must be driven high. After CE is driven high, the device will enter to deep power down within the duration of TDP. CE MODE3 0 1 2 3 4 5 6 SCK MODE0 7 T DP B9 SI MSB Standard Current Deep Power Down Current (ISB2) Figure 15: Deep Power Down Instruction Release from Deep Power Down (RDP) and Read-Electronic-Signature (RES) The Release form Deep Power Down and Read-ElectronicSignature instruction is a multi-purpose instruction. The instruction can be used to release the device from the deep power down status. This instruction is initiated by driving CE low and executing an 8-bit command, ABH, and then drive CE high. See Figure 16 for RDP instruction. Release from the deep power down will take the duration of TRES1 before the device will resume normal operation and other instructions are accepted. CE must remain high during TRES1. CE low and executing an 8-bit command, ABH, followed by 3 dummy bytes. The Electronic-Signature byte is then output from the device. The Electronic-Signature can be read continuously until CE go high. See Figure 17 for RES sequence. After driving CE high, it must remain high during for the duration of TRES2, and then the device will resume normal operation and other instructions are accepted. The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. The instruction also can be used to read the 8-bit ElectronicSignature of the device on the SO pin. It is initiated by driving Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 18/34 ESMT (Preliminary) F25S04PA CE MODE3 0 1 2 3 4 5 6 7 T RES1 SCK MODE0 AB SI MSB HIGH IMPEDANCE SO Standby Current Deep Power Down Current (ISB2) Figure 16: Release from Deep Power Down (RDP) Instruction CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 30 9 31 32 33 34 35 36 37 38 TRES2 SS 3 Dummy Bytes SS AB SI MSB SO HIGH IMPEDANCE SS Electronic-Signature Data Out MSB Deep Power Down Current (ISB2) Standby Current Figure 17: Read Electronic -Signature (RES) Sequence Table 6: Electronic Signature Data Command Electronic Signature Data RES 12H Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 19/34 ESMT (Preliminary) F25S04PA JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as F25S04PA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 13H, identifies the device as F25S04PA. The instruction sequence is shown in Figure 18. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH). CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031 9F SI MSB SO HIGH IMPENANCE 20 8C MSB 13 MSB MSB Figure 18: JEDEC Read-ID Sequence Table 7: JEDEC READ-ID Data Manufacturer’s ID (Byte 1) 8CH Elite Semiconductor Memory Technology Inc. Device ID Memory Type (Byte 2) Memory Capacity (Byte 3) 20H 13H Publication Date: May 2009 Revision: 0.2 20/34 ESMT (Preliminary) F25S04PA Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25 S04PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE . CE MODE3 SCK MODE0 15 16 0 1 2 3 4 5 6 7 8 90 SI 00 31 32 23 24 39 40 47 4 8 55 56 63 1 00 ADD MSB MSB HIGH IMPENANCE SO 8C 12 8C 12 HIGH IMPENA NCE MSB Note: The Manufacture’s an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE. 1. 00H will output the Manufacture’s ID first a nd 01H will output Device ID first b efore toggling between the two. . Figure 19: Read-ID Sequence Table 8: Product ID Data Address 00000H 00001H Elite Semiconductor Memory Technology Inc. Byte1 Byte2 8CH 12H Manufacturer’s ID Device ID ESMT F25S04PA 12H 8CH Device ID ESMT F25S04PA Manufacturer’s ID Publication Date: May 2009 Revision: 0.2 21/34 ESMT (Preliminary) F25S04PA ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA ( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. ) AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz See Figures 28 and 29 OPERATING RANGE Parameter Symbol Value Unit Operating Supply Voltage VDD 2.3 ~ 3.3 V Ambient Operating Temperature TA 0 ~ 70 ℃ Table 9: DC OPERATING CHARACTERISTICS Symbol Parameter IDDW Standard Dual Standard Dual Standard Dual Standard Dual Program and Erase Current ISB1 Standby Current ISB2 Deep Power Down Current ILI ILO VIL VIH VOL VOH Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IDDR1 IDDR2 IDDR3 IDDR4 Min Read Current @33 MHz Read Current @ 50MHz Read Current @ 86MHz Read Current @ 100MHz Limits Max 3 4 6 8 10 12 20 25 15 5 -0.5 0.7 x VDD Elite Semiconductor Memory Technology Inc. VDD-0.2 5 ±2 ±2 0.3 x VDD VDD +0.4 0.4 Test Condition Unit mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =0.1 VDD/0.9 VDD, SO=open mA CE =VDD µA CE =VDD, VIN =VDD or VSS µA CE =VDD, VIN =VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL= 1.6mA, VDD=VDD Min IOH=-100 µA, VDD=VDD Min µA µA V V V V Publication Date: May 2009 Revision: 0.2 22/34 ESMT (Preliminary) F25S04PA Table 10: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ1 TPU-WRITE 1 Parameter Minimum Unit VDD Min to Read Operation 10 µs VDD Min to Write Operation 10 µs Test Condition Maximum VOUT = 0V 8 pF VIN = 0V 6 pF Table 11: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open) Parameter COUT 1 CIN1 Description Output Pin Capacitance Input Capacitance Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 12: AC OPERATING CHARACTERISTICS Normal 33MHz Symbol Fast 50 MHz Fast 86 MHz Min Min Fast 100 MHz Parameter Unit Min Max Min TSCKH2 Serial Clock High Time 13 9 5 4 ns TSCKL2 Serial Clock Low Time 13 9 5 4 ns TCLCH Clock Rise Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns TCHCL Clock Fall Time (Slew Rate) 0.1 0.1 0.1 0.1 V/ns CE Active Setup Time 5 5 5 5 ns TCEH1 CE Active Hold Time 5 5 5 5 ns TCHS1 CE Not Active Setup Time 5 5 5 5 ns 1 TCHH CE Not Active Hold Time 5 5 5 5 ns TCPH CE High Time 100 100 100 100 ns TCHZ CE High to High-Z Output TCLZ SCK Low to Low-Z Output 0 0 0 0 ns TDS Data In Setup Time 2 2 2 2 ns TDH Data In Hold Time 5 5 5 5 ns THLS HOLD Low Setup Time 5 5 5 5 ns THHS HOLD High Setup Time 5 5 5 5 ns Elite Semiconductor Memory Technology Inc. 6 86 Max Serial Clock Frequency TCES 50 Max FCLK 1 33 Max 6 100 6 MHz 6 Publication Date: May 2009 Revision: 0.2 23/34 ns ESMT (Preliminary) F25S04PA Table 12: AC OPERATING CHARACTERISTICS - Continued Symbol Normal 33MHz Parameter Min Max Fast 50 MHz Fast 86 MHz Min Min Max Max Fast 100 MHz Min Unit Max THLH HOLD Low Hold Time 5 5 5 5 ns THHH HOLD High Hold Time 5 5 5 5 ns THZ3 TLZ3 TOH TV TWHSL4 TSHWL4 TW TDP3 HOLD Low to High-Z Output 6 6 6 6 ns HOLD High to Low-Z Output Output Hold from SCK Change Output Valid from SCK 6 6 6 6 ns ns ns ns 0 0 (typ.) 3 CE High to Deep Power Down Mode TRES13 TRES23 0 8 20 8 20 8 20 100 15 3 100 15 3 100 15 3 100 15 3 ms us Write Protect Setup Time before CE Low Write Protect Hold Time after CE High Write Status Register Time 0 12 20 (typ.) 3 (typ.) 3 (typ.) 3 ns CE High to Standby Mode ( for DP) 3 3 3 3 us CE High to Standby Mode (for RES) 1.8 1.8 1.8 1.8 us Note: 1. Relative to SCK. 2. TSCKH + TSCKL must be less than or equal to 1/ FCLK. 3. Value guaranteed by characterization, not 100% tested in production. 4. Only applicable as a constraint for a Write status Register instruction when Block- Protection-Look (BPL) bit is set at 1. ERASE AND PROGRAMMING PERFORMANCE Parameter Limit Symbol Typ 2 Max3 Unit Sector Erase Time TSE 40 100 ms Block Erase Time TBE 0.4 2 s Chip Erase Time TCE 3 7 s Byte Programming Time TBP 7 10 us Page Programming Time TPP 0.8 3 ms Chip Programming Time 3 5 s Erase/Program Cycles1 100,000 - Cycles 20 - Years Data Retention Notes: 1. Not 100% Tested, Excludes external system level over head. 2. Typical values measured at 25°C, 2.5V. 3. Maximum values measured at 85°C, 2.3V. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 24/34 ESMT (Preliminary) F25S04PA Figure 20: Serial Input Timing Diagram Figure 21: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 25/34 ESMT (Preliminary) F25S04PA Figure 22: HOLD Timing Diagram WP T WHSL TSHWL CE SCK SI HIGH IMPENANCE SO Figure 23: Write Protect setup and hold timing during WRSR when SRWD = 1 Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 26/34 ESMT (Preliminary) F25S04PA VCC VCC (max) Program, Erase and Write command is ignored CE must track VCC VCC (min) TVSL Reset State Read command is allowed Device is fully accessible VWI TPUW Time Figure 24: Power-Up Timing Diagram Table 13: Power-Up Timing and VWI Threshold Parameter Max. Unit Symbol Min. VCC(min) to CE low TVSL 10 Time Delay before Write instruction TPUW 1 10 ms VWI 1 2 V Write Inhibit Threshold Voltage us Note: These parameters are characterized only. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 27/34 ESMT (Preliminary) Input timing reference level F25S04PA Output timing reference level 0.8VCC 0.7VCC 0.3VCC 0.2VCC AC Measurement Level 0.5VCC Note : Input pulse rise and fall time are <5ns Figure 25: AC Input/Output Reference Waveforms Figure 26: A Teat Load Example Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 28/34 ESMT (Preliminary) F25S04PA PACKAGING DIAGRAMS 8-LEAD SOIC ( 150 mil ) 5 GAUGE PLANE 0 0.25 H E 8 L DETAIL "X" 1 4 e b L1 "X" A1 A2 A C D SEATING PLANE Dimension in mm Dimension in inch Dimension in mm Symbol Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A 1.35 1.60 1.75 0.053 0.063 0.069 D 4.80 4.90 5.00 0.189 0.193 0.197 A1 0.10 0.15 0.25 0.004 0.006 0.010 E 3.80 3.90 4.00 0.150 0.154 0.157 A2 1.25 1.45 1.55 0.049 0.057 0.061 L 0.40 0.66 1.27 0.016 0.026 0.050 b 0.33 0.406 0.51 0.013 0.016 0.020 e c 0.19 0.203 0.25 0.0075 0.008 0.010 L1 1.00 1.05 1.10 0.039 0.041 0.043 H 5.80 6.00 6.20 0.228 0.236 0.244 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 29/34 ESMT (Preliminary) F25S04PA PACKING DIMENSIONS 8-LEAD SOIC 200 mil ( official name – 209 mil ) 5 1 4 E1 8 E θ b e A A2 D L A1 L1 SEATING PLANE Dimension in mm Dimension in inch DETAIL "X" Dimension in mm Symbol Dimension in inch Symbol Min Norm Max Min Norm Max Min Norm Max Min Norm Max A --- --- 2.16 --- --- 0.085 E 7.70 7.90 8.10 0.303 0.311 0.319 A1 0.05 0.15 0.25 0.002 0.006 0.010 E1 5.18 5.28 5.38 0.204 0.208 0.212 A2 1.70 1.80 1.91 0.067 0.071 0.075 L 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e c 0.19 0.20 0.25 0.007 0.008 0.010 L1 1.27 1.37 1.47 0.050 0.054 0.058 D 5.13 5.23 5.33 0.202 0.206 0.210 θ 0° --- 8° 0° --- 8° 1.27 BSC 0.050 BSC Controlling dimension : millimenter Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 30/34 ESMT (Preliminary) F25S04PA PACKING DIMENSIONS 8-LEAD P-DIP ( 300 mil ) D 8 5 E A eB E1 1 A2 0 4 b L A1 S e a t in g P la n e b 1 e Dimension in mm Symbol Min Norm A Dimension in inch Max Min Norm Max 5.00 0.21 A1 0.38 A2 3.18 3.30 3.43 0.125 0.130 0.135 D 9.02 9.27 10.16 0.355 0.365 0.400 E 0.015 7.62 BSC. 0.300 BSC. E1 6.22 6.35 6.48 0.245 0.250 0.255 L 9.02 9.27 10.16 0.115 0.130 0.150 e eB 2.54 TYP. 8.51 b θ 9.53 0.335 0.46 TYP. b1 O 9.02 0.100 TYP. 0 7 O 0.375 0.018 TYP. 1.52 TYP. O 0.355 0.060 TYP. 15 O 0 O 7O 15O Controlling dimension : Inch. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 31/34 ESMT PACKING 8-LEAD (Preliminary) F25S04PA DIMENSIONS DFN ( 5x6 mm ) D E A PIN# 1 A1 L DETAIL : "B" "A" E2 b e D2 DETAIL : "A" "B" PIN# 1 Symbol A A1 b D D2 E E2 e L Dimension in inch Min Norm Max 0.028 0.030 0.031 0.000 0.001 0.002 0.014 0.016 0.018 0.232 0.236 0.240 --0.161 0.193 0.197 0.201 --0.161 0.050 BSC 0.022 0.024 0.026 Dimension in mm Min Norm Max 0.70 0.75 0.80 0.00 0.02 0.05 0.35 0.40 0.45 5.90 6.00 6.10 --4.10 4.90 5.00 5.10 --4.10 1.27 BSC 0.55 0.60 0.65 Controlling dimension : millimeter Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 32/34 ESMT (Preliminary) F25S04PA Revision History Revision Date 0.1 2009.02.20 Original 0.2 2009.05.14 1. Add DFN package 2. Modify the test condition of VOL Elite Semiconductor Memory Technology Inc. Description Publication Date: May 2009 Revision: 0.2 33/34 ESMT (Preliminary) F25S04PA Important Notice All rights reserved. No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Publication Date: May 2009 Revision: 0.2 34/34