EUP7996 1.5A DDR Termination Regulator DESCRIPTION FEATURES The EUP7996 is a high performance linear regulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The EUP7996 contains a high-speed operational amplifier to provide excellent response to load transients. The EUP7996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for chipset and DIMMs. An additional feature found on the EUP7996 is an active low shutdown (SD) pin. When SD is pulled low the VTT output will Tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. z Extremely low quiescent current (305uA) z Fast transient response time z Capable of sourcing and sinking 1.5A for DDR-I termination z Reference out for other memory and control components z Low-current shutdown mode z Over-temperature protection z High accuracy output voltage at full-load z Low external component count z Available in SOP-8, SOP(FD) package z RoHS compliant and 100% lead (Pb)-free APPLICATIONS z The EUP7996, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses. A typical DDR memory system is seen in Figure 1. SIMPLIFIED SYSTEM DIRGRAM Figure 1. DS7996 Ver2.5 June.2005 1 DDR-I and DDR-II termination voltage EUP7996 Pin Configurations Package Type Pin Plastic SOP-8(FD) ＊Thermal Pad Configurations (TOP VIEW) ＊ Pin Description PIN SYMBOL DESCRIPTION 1 GND Ground 2 SD Shutdown 3 VSENSE Feedback pin for regulating VTT 4 VREF Buffered internal reference voltage of VDDQ/2 5 VDDQ Input for internal reference equal to VDDQ/2 6 AVIN Analog input pin 7 PVIN Power Input pin 8 VTT Output voltage for connection to termination resistors Typical Application Circuit Figure 2. Recommended DDR-I Termination DS7996 Ver2.5 June.2005 2 EUP7996 Figure 3. Recommended DDR-II Termination Ordering Information Order Number Package Type EUP7996ADIR1 SOP-8 Xxxx EUP7996 A -40 °C to 125°C EUP7996ADIR0 SOP-8 Xxxx EUP7996 A -40 °C to 125°C EUP7996A □ Marking □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type D: SOP DS7996 Ver2.5 June.2005 3 Operating Temperature range EUP7996 Operating Range Absolute Maximum Ratings ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Input voltage - - - - - - - - - - - - - - - - - - 6V Power dissipation - - - - - - - - - - - - - - - Internal limiting ESD rating - - - - - - - - - - - - - - - - - - 3KV Maximum junction temperature - - - - - 150 °C Storage temperature range - - - - - - - - - -65°C to150°C Lead temperature (soldering , 5 sec) - 260 °C SOP-8 thermal resistance, θjA - - - - - - 67.9 °C/W SOP-8(FD) thermal resistance, θjA - - -42.3 °C/W ▓ ▓ ▓ ▓ Junction Temp. Range - - - - -40°C to 125°C AVIN to GND - - - - - - - - - - -1.8V to 5.5V PVIN,VDDQ to GND - - - - - 1.8V to AVIN SD Input Voltage - - - - - - - - - - 0 to AVIN Electrical Characteristics Specifications with standard typeface are for TA=25 °C, unless otherwise specified, AVIN=2.5V Symbol Parameter VREF VREF Voltage VTT VOS VTT Output Voltage Output Offset Voltage Conditions IREF=0mA PVIN=VDDQ=2.5V PVIN=VDDQ=1.8V PVIN=VDDQ=2.5V IOUT = 0A IOUT =±1.5A PVIN=VDDQ=1.8V IOUT =0A IOUT =±0.9 A PVIN=VDDQ=2.5V IOUT=0A IOUT=-1.5A IOUT=+1.5A PVIN=VDDQ=1.8V IOUT=0A IOUT=-1A IOUT=+0.9A Min Typ Max Units 1.235 0.886 1.242 0.899 1.285 0.914 V 1.225 1.225 1.251 1.251 1.290 1.290 V 0.885 0.885 0.892 0.892 0.915 0.915 V -20 -25 -25 0 0 0 20 25 25 mV -15 -20 -20 0 0 0 15 20 20 mV IQ Quiescent Current (Note 2) IOUT = 0A 200 305 500 µA ISHDN Quiescent Current in Shutdown SD = 0V 50 75 200 µA ILKG_SD Shutdown leakage current SD = 0V -- 0.16 -- µA IV VTT Leakage Current in Shutdown SD = 0V, VTT = 1.25V -- 0.13 -- µA Guaranteed by design -- 155 -- °C Guaranteed by design -- 30 -- °C Output = High 1.8 -- -- Output = Low -- -- 0.6 Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis TSD TSD _HYS Shutdown function VIH Shutdown Threshold Trigger VIL V Note 1: VOS offset is the voltage measurement defined as VTT subtracted from VREF. Note 2: Quiescent current defined as the current flow into AVIN. DS7996 Ver2.5 June.2005 4 EUP7996 Typical Performance Characteristics Vtt Vs. Itt Vref vs. Iref 1.26 1.3 1.255 1.28 VTT(V) Vref(V) 1.25 1.26 1.24 1.245 1.24 1.22 1.235 1.2 1.23 -30 -20 -10 0 Iref(uA) 10 20 30 -1.6 -1.2 -0.4 0 0.4 Load Current(A) 0.8 1.2 1.6 VTT vs VDDQ Vref vs VDDQ 3 3 2.5 2.5 2 2 VTT(V) Vref(V) -0.8 1.5 1 1.5 1 0.5 0.5 0 0 1 2 3 4 5 0 6 0 VDDQ(V) DS7996 Ver2.5 June.2005 1 2 3 VDDQ(V) 5 4 5 EUP7996 Maximum Sourcing Current vs. Avin (VDDQ=2.5V , Pvin=2.5V) 1.4 2 1.2 1.9 1.0 1.8 Output(A) Output(A) Maximum Source Current vs Avin (VDDQ=2.5V,PVIN=1.8V) 0.8 0.6 1.7 1.6 0.4 1.5 0.2 1.4 0.0 1.3 2.5 3.0 3.5 4.0 4.5 AVIN(V) 5.0 5.5 2.5 Maximum Sourcing Current vs AVIN VDDQ=2.5V, PVIN=3.3V 3.4 3.0 Output(A) Output(A) 3.2 2.8 2.6 2.4 2.2 2.0 3.5 4.0 4.5 AVIN(V) 5.0 4.0 4.5 AVIN(V) 5.0 5.5 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 5.5 2.2 Maximum Sourcing Current vs Avin 2.5 3.0 3.5 4.0 AVIN(V) 4.5 5.0 5.5 Maximum Sourcing Current vs. Avin (VDDQ=1.8V , Pvin=3.3V) VDDQ=1.8V, PVIN=1.8V 1.4 3.5 Maximum Sinking Current vs AVIN (VDDQ=2.5V,PVIN=2.5V) 3.6 3.0 3.0 1.2 3.1 Output(A) Output(A) 1.0 0.8 0.6 2.9 2.7 0.4 2.5 0.2 2.3 0.0 2.2 DS7996 Ver2.5 2.5 3.0 June.2005 3.5 4.0 AVIN(V) 4.5 5.0 5.5 3.0 6 3.5 4.0 4.5 AVIN(V) 5.0 5.5 EUP7996 1.25Vtt Transient Response AVIN==PVIN=VDDQ=2.5V Cour=330uF/16V Maximum Sinking Current vs. Avin (VDDQ=1.8V , Pvin=2.5V) 2.6 Output(A) 2.4 2.2 2 1.8 1.6 2.5 3.0 3.5 4.0 4.5 AVIN(V) 5.0 5.5 0.9Vtt Transient Response AVIN=2.5V, PVIN=VDDQ=1.8V Cour=330uF/16V DS7996 Ver2.5 June.2005 7 EUP7996 Block Diagram Pin Functions VREF VREF provides the buffered output of the internal reference voltage VDDQ/2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.01uF to 0.1uF is recommended. This output remains active during the shutdown state and thermal shutdown events. AVIN and PVIN AVIN and PVIN are the input supply pins for the EUP7996. AVIN is used to supply the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. For SSTL-2 application, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. For SSTL-18 applications, it is recommended to connect PVIN to 1.8V rail used for the memory core and AVIN to a rail typically 2.5V supply. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. VTT VTT is a regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ/2. The EUP7996 is capable of sinking and sourcing 1.5A continues current. If a transient above the maximum continues current is expected for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. If large current are required for longer duration, then care should be taken to ensure that the maximum junction temperature is not exceeded. If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until the part returns below the hysteretic trip-point. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50KΩ resistors. This guarantees that VTT will track VDDQ/2 precisely. For SSTL-2 applications, VDDQ should be a 2.5V. The optimal implementation of VDDQ is as remote sense. This can be achieved by connecting VDDQ directly to the 2.5V rail at DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-18 applications, VDDQ will be a 1.8V signal. VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard application the termination resistors will connect to VTT in a long plane. The VSENSE pin can be used by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. When remote sense is used, it may necessary to put a 0.1uf ceramic capacitor beside the VSENSE pin to eliminate the noise that coupled to VSENSE due to the long trace. VSENSE pin must be connected to VTT if remote load regulation is not used. DS7996 Ver2.5 June.2005 SD SD can be used to put the regulator into low-power mode. When SD is pulled low, the VTT power amplifier is turned off and the VTT output is tri-state, but, VREF will remain active, allowing those circuits requiring a reference during the standby state to remain active. 8 EUP7996 Component Selection INPUT CAPACITOR The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 47uF. If the two supply rails (AVIN and PVIN) are separated then the 47uF capacitor should be placed as close to possible to PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device. When size and performance are critical, several hybrid capacitors such OS-CON and SP that offer a large capacitance while maintaining a low ESR are the better solution. PCB Layout Considerations The EUP7996 regulator is packaged in plastic SOP-8 package. This small footprint package is unable to convectively dissipate at high current levels. The junction temperature should be kept well away from the thermal shutdown temperature in normal operation. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on several variables: the thickness of copper on PCB; the area of top side copper used; and the airflow. Using large traces and more copper on the top side of board with careful layout are possible to reduce thermal resistance on the part. OUTPUT CAPACITOR As general recommendation, the output capacitor should be sized above 220uF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by maximum current spikes expected from the DDR memory system to ensure VTT staying within +/-40mV of VREF. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. With motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple bulk capacitors. Large aluminum electrolytic capacitors can be used for their low ESR and low cost. Additional 0.1uF ceramic capacitor is needed for high frequency decoupling. If the large ground trace around the IC is unavailable on top, numerous vias to connect the part and dissipate heat to the internal ground plane will help. The vias should be small enough to retain solder when the board is wave- soldered. Additional improvements can be achieved with a constant airflow across the package. Test Circuit Figure 2. Load transient (+1.5A ~ –1.5A) test circuit DS7996 Ver2.5 June.2005 9 EUP7996 Mechanical Information X Y Z Standard Solder Map Bottom Ues as much copper area as possible Symbols A B C D E H F L1 L2 M N A1 B1 EXPOSED PAD Dimension in Millimeters Min. Max. 4.80 5.00 5.80 6.20 3.80 4.00 1.194 1.346 1.45 1.55 0.00 0.10 0.33 0.51 0.19 0.25 0.40 1.27 0° 8° 40° 50° 2.6 2.8 2.4 2.6 Dimension in Inches Min. Max. 0.189 0.197 0.228 0.244 0.150 0.157 0.047 0.053 0.057 0.061 0.000 0.004 0.013 0.020 0.007 0.010 0.016 0.050 0° 8° 40° 50° 0.102 0.110 0.095 0.102 8 – Lead SOP(FD) Plastic Package DS7996 Ver2.5 June.2005 10