ON MTD15N06VL Power mosfet Datasheet

MTD15N06VL
Power MOSFET
15 Amps, 60 Volts
N−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
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15 AMPERES
60 VOLTS
RDS(on) = 75 mW (Typ)
N−Channel
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Value
Unit
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 25
Vdc
Vpk
ID
ID
15
12
53
Adc
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C (Note 2)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak
IL = 15 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1)
− Junction to Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
IDM
Apk
PD
60
0.4
2.1
Watts
W/°C
Watts
TJ, Tstg
−55 to
175
°C
EAS
113
mJ
RqJC
RqJA
RqJA
2.5
100
71.4
TL
260
°C/W
°C
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. pad size.
G
S
4
1 2
4
Drain
3
DPAK
CASE 369C
Style 2
August, 2006 − Rev. 5
1
2
1
3
Drain
Gate
Source
4
4
Drain
1
2
3
DPAK
CASE 369D
Style 2
1 2 3
Gate Drain Source
15N06VL Device Code
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2006
MARKING DIAGRAMS
YWW
15N
06VL
Symbol
YWW
15N
06VL
Rating
Drain−to−Source Voltage
Package
Shipping
MTD15N06VL
DPAK
75 Units/Rail
MTD15N06VL−1
DPAK
75 Units/Rail
MTD15N06VLT4
DPAK
2500 Tape & Reel
Publication Order Number:
MTD15N06VL/D
MTD15N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
−
68
−
−
−
−
−
−
10
100
−
−
100
1.0
−
1.5
4.0
2.0
−
−
0.075
0.085
−
−
−
−
1.5
1.3
gFS
8.0
10
−
mhos
Ciss
−
570
880
pF
Coss
−
180
380
Crss
−
45
110
td(on)
−
11
50
tr
−
150
210
td(off)
−
27
160
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 5)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 5)
Static Drain−to−Source On−Resistance
(VGS = 5.0 Vdc, ID = 7.5 Adc)
(Cpk ≥ 2.0) (Note 5)
Drain−to−Source On−Voltage
(VGS = 5.0 Vdc, ID = 15 Adc)
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C)
VGS(th)
RDS(on)
VDS(on)
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)
Vdc
mV/°C
W
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
(VDD = 30 Vdc, ID = 15 Adc,
VGS = 5.0 Vdc,
RG = 9.1 W)
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 5.0 Vdc)
tf
−
70
140
QT
−
12
20
Q1
−
3.0
−
Q2
−
7.0
−
Q3
−
11
−
−
−
0.96
0.85
1.6
−
trr
−
63
−
ta
−
42
−
tb
−
21
−
QRR
−
0.140
−
−
−
3.5
4.5
−
−
−
7.5
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
(IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored
Charge
VSD
Vdc
ns
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
5. Reflects typical values.
Cpk =
3 x SIGMA
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2
nH
nH
MTD15N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
I D , DRAIN CURRENT (AMPS)
9V
VGS = 10V
TJ = 25°C
45
8V
50
7V
40
35
5V
30
25
20
15
10
2
3
4
5
6
7
9
8
40
100°C
35
30
25
20
15
10
0
10
3
5
4
6
7
Figure 2. Transfer Characteristics
0.12
0.1
25°C
0.08
− 55°C
0.06
0.04
0.02
5
15
25
10
20
ID, DRAIN CURRENT (AMPS)
30
35
8
9
45
50
0.16
TJ = 25°C
0.14
0.12
VGS = 5 V
0.1
0.08
10 V
0.06
0.04
0.02
0
0
Figure 3. On−Resistance versus Drain Current
and Temperature
10
5
15
25
20
30
35
ID, DRAIN CURRENT (AMPS)
40
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100
2.0
VGS = 5 V
ID = 7.5 A
VGS = 0 V
TJ = 125°C
1.6
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2
Figure 1. On−Region Characteristics
TJ = 100°C
1.8
1
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 5 V
0
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
1
0
0.14
0
25°C
TJ = −55°C
5
5
0
VDS ≥ 5 V
45
6V
I D , DRAIN CURRENT (AMPS)
50
1.4
1.2
1
0.8
10
100°C
0.6
0.4
0.2
−50
−25
0
25
50
75
100 125
TJ, JUNCTION TEMPERATURE (°C)
150
0
175
0
5
10
15
20
25
30
35
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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40
45
MTD15N06VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2200
2000
Ciss VDS = 0 V
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
1800
1600
1400
1200
Crss
1000
800
Ciss
600
400
Coss
200
0
10
Crss
0
5
5
VGS
VDS
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
30
QT
9
27
24
8
VGS
7
21
6
18
Q1
5
Q2
15
4
12
3
9
2
1
0
Q3
0
5
TJ = 25°C
ID = 15 A
VDS
10
15
20
25
30
6
3
0
35
1000
t, TIME (ns)
10
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTD15N06VL
TJ = 25°C
ID = 15 A
VDD = 30 V
VGS = 5 V
100
tr
tf
td(off)
10
td(on)
1
1
10
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
I S , SOURCE CURRENT (AMPS)
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
15
14 TJ = 25°C
13 VGS = 0 V
12
11
10
9
8
7
6
5
4
3
2
1
0
0.5 0.55 0.6
0.65
0.7
0.75
0.8
0.85
0.9
0.95
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
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MTD15N06VL
I D , DRAIN CURRENT (AMPS)
100
VGS = 15 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
10 ms
10
100 ms
1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
120
110
ID = 15 A
100
100
90
80
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.00
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
D = 0.5
0.2
0.1
P(pk)
0.10
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
MTD15N06VL
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
6.20
0.244
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm Ǔ
ǒinches
SCALE 3:1
DPAK
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
PD = 175°C − 25°C = 2.1 Watts
71.4°C/W
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RqJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
PD =
The 71.4°C/W for the DPAK package assumes the use of
0.5 sq. in. source pad on a glass epoxy printed circuit board
to achieve a power dissipation of 2.1 W. There are other
alternatives to achieving higher power dissipation from the
surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which
can defeat the purpose of using surface mount technology.
For example, a graph of RqJA versus drain pad area is
shown in Figure 15.
TJ(max) − TA
RqJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
DPAK device, PD is calculated as follows.
RθJA , THERMAL RESISTANCE, JUNCTION
TO AMBIENT (°C/W)
100
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
2.1 Watts
80
TA = 25°C
60
3.6 Watts
40
6.0 Watts
20
0
2
4
6
A, AREA (SQUARE INCHES)
8
10
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
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MTD15N06VL
SOLDER STENCIL GUIDELINES
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D2PAK packages. The
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
D2PAK is not recommended for wave soldering.
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MTD15N06VL
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177−189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 17 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 17. Typical Solder Heating Profile
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MTD15N06VL
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
C
B
V
SEATING
PLANE
E
R
4
Z
A
S
1
2
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
3
U
K
F
J
L
H
D
2 PL
G
0.13 (0.005)
M
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
DPAK
CASE 369D−01
ISSUE O
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
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