Renesas HD64F2147AVFA10 Renesas 16-bit single-chip microcomputer h8s family/h8s/2100 sery Datasheet

REJ09B0327-0400
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2148 Group, H8S/2144 Group,
H8S/2148F-ZTAT™, H8S/2147N F-ZTAT™,
H8S/2144F-ZTAT™, H8S/2142F-ZTAT™
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2100 Series
H8S/2148
H8S/2147
HD6432148S
HD6432148SW
HD64F2148
HD64F2148V
HD64F2148A
HD64F2148AV
HD6432147S
HD6432147SW
HD64F2147A
HD64F2147AV
Rev. 4.00
Revision Date: Sep 27, 2006
H8S/2147N HD64F2147N
HD64F2147NV
H8S/2144
HD6432144S
HD64F2144
HD64F2144V
HD64F2144A
HD64F2144AV
H8S/2143
HD6432143S
H8S/2142
HD6432142
HD64F2142R
HD64F2142RV
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 4.00 Sep 27, 2006 page ii of xliv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 4.00 Sep 27, 2006 page iii of xliv
Rev. 4.00 Sep 27, 2006 page iv of xliv
Preface
The H8S/2148 Group, H8S/2144 Group, and H8S/2147N comprise high-performance
microcomputers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions
required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
(SCI, IrDA), PS/2-compatible keyboard buffer controller, host interface (HIF), D/A converter
2
(DAC), A/D converter (ADC), and I/O ports. An I C bus interface (IIC) can also be incorporated
as an option.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
The H8S/2148 Group has all the above on-chip supporting functions, and can also be provided
with an IIC module as an option. The H8S/2144 Group comprises reduced-function versions, with
fewer TMR channels, and no PWM, keyboard buffer controller, HIF, IIC, or DTC modules, and
the H8S/2147N with fewer TMR channels, no DTC and some other functions.
Use of the H8S/2148 Group, H8S/2144 Group, H8S/2147N enables compact, high-performance
systems to be implemented easily. The comprehensive PC-related interface functions and 16 × 8
matrix key-scan functions are ideal for applications such as notebook PC keyboard control and
intelligent battery and power supply control, while the various timer functions and their
2
interconnectability (timer connection), plus the interlinked operation of the I C bus interface and
data transfer controller (DTC), in particular, make these devices ideal for use in PC monitors. In
addition, the combination of F-ZTAT™* and reduced-function versions is ideal for applications
such as CD-ROM drive units in which on-chip program memory is essential to meet performance
requirements, product start-up times are short, and program modifications may be necessary after
end-product assembly.
Rev. 4.00 Sep 27, 2006 page v of xliv
This manual describes the hardware of the H8S/2148 Group, H8S/2144 Group, and H8S/2147N.
Refer to the H8S/2600 Series and H8S/2000 Series Software Manual for a detailed description of
the instruction set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
On-Chip Supporting Modules
Group
H8S/2148 Group
H8S/2147N
H8S/2144 Group
Product names
H8S/2148,
H8S/2147
H8S/2147N
H8S/2144,
H8S/2143,
H8S/2142
Bus controller (BSC)
Available (16 bits) Available (16 bits) Available (16 bits)
Data transfer controller (DTC)
Available
—
—
8-bit PWM timer (PWM)
×16
×16
—
14-bit PWM timer (PWMX)
×2
×2
×2
16-bit free-running timer (FRT)
×1
×1
×1
8-bit timer (TMR)
×4
×3
×3
Timer connection
Available
—
—
Watchdog timer (WDT)
×2
×2
×2
Serial communication interface (SCI)
×3
×3
×3
I C bus interface (IIC)
×2 (option)
×2 (option)
—
Keyboard buffer controller
(PS/2 compatible)
×3
×3
—
Host interface (HIF)
×4
×4
—
D/A converter
×2
×2
×2
×8
×8
×8
×16
×16
2
A/D converter
Analog inputs
Expansion A/D inputs ×16
Rev. 4.00 Sep 27, 2006 page vi of xliv
Main Revisions for This Edition
Item
Page
Revision (See Manual for Details)
All
—
• Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8S/2148 Series → (After) H8S/2148 Group
(Before) H8S/2144 Series → (After) H8S/2144 Group
1.1 Overview
4
Host interface specification in table 1.1 amended
• 8-bit host interface (ISA) port
Table 1.1 Overview
6
Product lineup specification in table 1.1 amended
Product Code*2
Group
Mask ROM
Versions
F-ZTAT
Versions
ROM/RAM
(Bytes)
H8S/2148
HD6432148S
HD64F2148
HD64F2148V*2
128 k/4 k
HD6432148SW*1
HD64F2148A
HD64F2148AV*2
HD6432147S
HD64F2147A
HD6432147SW*1
HD64F2147AV*2
H8S/2147N
—
HD64F2147N
HD64F2147NV*2
64 k/2 k
H8S/2144
HD6432144S
HD64F2144
HD64F2144V*2
128 k/4 k
Packages
FP-100B,
TFP-100B
64 k/2 k
HD64F2144A
HD64F2144AV*2
HD6432143S
—
96 k/4 k
HD6432142
HD64F2142R
HD64F2142RV*2
64 k/2 k
2
Notes: 1. W indicates the I C bus option.
2. V indicates the 3-V version. Please refer to appendix F, Product
Code Lineup.
1.2 Internal Block
Diagram
7
Figure 1.1 (a) amended
(Before) STBY → (After) STBY
Figure 1.1 (a) Internal
Block Diagram of
H8S/2148 Group
Figure 1.1 (b) Internal
Block Diagram of
H8S/2147N
8
Figure 1.1 (b) amended
(Before) IIC × 2ch → (After) IIC × 2ch (option)
Rev. 4.00 Sep 27, 2006 page vii of xliv
Item
Page
Revision (See Manual for Details)
1.3.2 Pin Functions in
Each Operating Mode
14
Mode 1 description of pin 35 amended
Table 1.2 (a) Pin
Functions in Each
Operating Mode
Table 1.2 (b)
H8S/2147N Pin
Functions in Each
Operating Mode
(Before) P67/TMOX/CIN/KIN7/IRQ7 →
(After) P67/TMOX/CIN7/KIN7/IRQ7
17
Modes 2 and 3 in single chip modes of pin 95 amended
(Before) P82 → (After) P82/HIFSD
19
Mode 1 description of pin 35 amended
(Before) P67/CIN/KIN7/IRQ7 → (After) P67/CIN7/KIN7/IRQ7
21
Modes 2 and 3 in single chip modes of pin 95 amended
(Before) P82 → (After) P82/HIFSD
1.3.3 Pin Functions
30
Table 1.3 amended
Pin No.
Table 1.3 Pin Functions
Type
Symbol
FP-100B
TFP-100B
Host
interface
(HIF)
HIRQ11
HIRQ1
HIRQ12
HIRQ3
HIRQ4
52
53
54
91
90
52
Type
Symbol
I/O ports
PA7 to
PA0
FP-100B
TFP-100B
10, 11, 20,
21, 30, 31,
47, 48
I/O
Name and Function
Input/
output
Port A: Eight input/output pins. The data direction
of each pin can be selected in the port A data
direction register (PADDR). These pins have built-in
MOS input pull-ups. These are the VCCB drive
pins. [H8S/2148 Group and H8S/2147N only]
Instruction in arithmetic operations amended
Table 2.1 Instruction
Classification
(Before) EG → (After) NEG
3.2.4 Serial Timer
89
Control Register (STCR)
Bit 3 bit table amended
4.5 Stack Status after
Exception Handling
111
Name and Function
Output Host interrupt 11, 1, 12, 3, and 4: Output pins for
interrupt requests to the host.
Pin No.
33
2.6.1 Overview
I/O
Bit 3
FLSHE
Description
0
Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register
and supporting module control register access
(Initial value)
1
Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register
access (F-ZTAT version only)
Note * deleted from figure 4.5 (2)
Figure 4.5 (2) Stack
Status after Exception
Handling (Advanced
Mode)
Rev. 4.00 Sep 27, 2006 page viii of xliv
Item
Page
Revision (See Manual for Details)
5.2.8 Address Break
Control Register
(ABRKCR)
124
Read/Write description amended
5.5.3 Interrupt control
Mode 1
140
Bit 7 (Before) R/W → (After) R
(Before) Only NMI interrupts enabled and address break →
(After) Only NMI interrupts and address break enabled
Figure 5.9 Example of
State Transitions in
Interrupt control Mode 1
8.1 Overview
Figure 5.9 amended
213
Table 8.1 H8S/2148
Group Port Functions
Table 8.1 amended
Expanded Modes
Port
Port A
Description
Pins
• 8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
Table 8.2 H8S/2147N
Port Functions
216
Mode 1
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 1)
Mode 2, Mode 3
(EXPE = 0)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8),
expansion A/D converter
input (CIN15 to CIN8), and
keyboard buffer controller
input/output (PS2CD,
PS2CC, PS2BD, PS2BC,
PS2AD, PS2AC)
Table 8.2 amended
Expanded Modes
Port
Port A
Description
Pins
• 8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
Mode 1
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 1)
Mode 2, Mode 3
(EXPE = 0)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8), expansion
A/D converter input (CIN15
to CIN8), and keyboard
buffer controller
input/output (PS2CD,
PS2CC, PS2BD, PS2BC,
PS2AD, PS2AC)
Rev. 4.00 Sep 27, 2006 page ix of xliv
Item
Page
Revision (See Manual for Details)
8.1 Overview
220
Table 8.3 amended
Table 8.3 H8S/2144 Port
Functions
Expanded Modes
Port
Port A
8.7.2 Register
Configuration
247
Table 8.19 Port 8 Pin
Functions
Pins
Mode 1
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8), and
expansion A/D
converter input
(CIN15 to
CIN8)
• 8-bit I/O port PA7 to PA0/
A23 to A16/
KIN15 to KIN8/
CIN15 to CIN8
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 1)
Mode 2, Mode 3
(EXPE = 0)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
and expansion A/D
converter input
(CIN15 to CIN8)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8) and
expansion A/D converter
input (CIN15 to CIN8)
Table 8.14 amended
(Before) System control register → (After) System control
register 2
Table 8.14 Port 6
Registers
8.9.3 Pin Functions
Description
258
P81/GA20/CS2 selection method and pin function description
amended
Pin
Selection Method and Pin Functions
P81/GA20/CS2
The pin function is switched as shown below according to the combination of
operating mode, bit CS2E in SYSCR, bit FGA20E in HICR of the HIF, and bit
P81DDR.
Operating
mode
Not slave mode
FGA20E
—
CS2E
—
P81DDR
Pin function
Slave mode
0
0
1
1
—
0
1
0
1
—
0
1
P81
input
pin
P81
output
pin
P81
input
pin
P81
output
pin
CS2
input
pin
P81
input
pin
GA20
output
pin
This pin should be used as the GA20 output pin or CS2 input pin only in mode
2 or 3 (EXPE = 0).
Rev. 4.00 Sep 27, 2006 page x of xliv
Item
Page
Revision (See Manual for Details)
8.11.3 Pin Functions
270
Table 8.23 amended
Table 8.23 Port A Pin
Functions
Pin
Selection Method and Pin Functions
PA1/A17/KIN9/
CIN9
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Operating
mode
Modes 1,
2 (EXPE = 0), 3
Mode 2 (EXPE = 1)
PA1DDR
0
1
0
IOSE
—
—
—
0
1
PA1
input pin
PA1
output pin
PA1
input pin
A17
output pin
PA1
output pin
Pin function
1
KIN9 input pin, CIN9 input pin
This pin can always be used as the KIN9 or CIN9 input pin.
PA0/A16/KIN8/
CIN8
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA0DDR.
Operating
mode
Modes 1,
2 (EXPE = 0), 3
Mode 2 (EXPE = 1)
PA0DDR
0
1
0
IOSE
—
—
—
0
1
PA0
input pin
PA0
output pin
PA0
input pin
A16
output pin
PA0
output pin
Pin function
1
KIN8 input pin, CIN8 input pin
This pin can always be used as the KIN8 or CIN8 input pin.
9.3.1 Correspondence
between PWM Data
Register Contents and
Output Waveform
289
Description of upper 6 bits changed to of upper 4 bits
Table 9.4 Duty Cycle of
Basic Pulse
10.3 Bus Master
Interface
299
Description amended
... Example 2: Read DADRA
MOV.W @DADRA, R0 ; Transfer contents of DADRA to R0
10.4 Operation
Table 10.4 Settings and
Operation (Examples
when φ = 10 MHz)
303
Table 10.4 amended
Resolution
T
CKS
(µs)
0
1
0.1
0.2
CFS
Base Conversion
Cycle
Cycle
(µs)
(µs)
Fixed DADR Bits
TL (if OS = 0)
TH (if OS = 1)
Precision Bit Data
(Bits)
3 2 1 0
Conversion
Cycle*
(µs)
0
6.4
1638.4
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14
1638.4
1
25.6
1638.4
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14
1638.4
0
12.8
3276.8
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14
3276.8
1
51.2
3276.8
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14
3276.8
Rev. 4.00 Sep 27, 2006 page xi of xliv
Item
Page
Revision (See Manual for Details)
16.1.1 Features
492
• Automatic switching from formatless mode to I C bus format
(channel 0 only)
2
Description added
16.4 Usage Notes
548
Figure 16.19 Flowchart
and Timing of Start
Condition Instruction
Issuance for
Retransmission
Figure 16.19 amended
9
SCL
SDA
ACK
IRIC
[3] Start condition
instruction issuance
[1] IRIC determination
550 to
557
[2] Determination
of SCL = low
Description added
• Notes on WAIT Function
• Notes on ICDR Reads and ICCR Access in Slave Transmit
Mode
• Notes on TRS Bit Setting in Slave Mode
• Notes on Arbitration Lost in Master Mode
• Notes on Interrupt Occurrence after ACKB Reception
• Notes on TRS Bit Setting and ICDR Register Access
20.4.3 Input Sampling 628
and A/D Conversion Time
Figure 20.5 A/D
Conversion Time
Figure 20.5 amended
(1)
φ
Address
Write signal
Rev. 4.00 Sep 27, 2006 page xii of xliv
(2)
Item
Page
Revision (See Manual for Details)
22.4.2 Block Diagram
643
Figure 22.2 amended
Figure 22.2 Block
Diagram of Flash
Memory
Internal address bus
Internal data bus (16 bits)
Module bus
FLMCR1 *
FLMCR2 *
EBR1
EBR2
Operating
mode
Bus interface/controller
Mode pins
*
*
Flash memory
(128 kbytes/64 kbytes)
22.5.3 Erase Block
Registers 1 and 2
(EBR1, EBR2)
653
22.10.1 Programmer
Mode Setting
671
Bit figure amended
Read/Write description of bits 7 to 2 (Before) * → (After) 
2
Note amended
In programmer mode, ... Renesas Technology microcomputer
1 3
2 3
device types with 128-kbyte* * or 64-kbyte* * on-chip flash
memory. ...
Note: 3. Use products other than the A-mask version of the
H8S/2148, H8S/2147N, H8S/2144, and H8S/2142 ...
22.10.4 Memory Read
Mode
Figure 22.17 Timing
Waveforms when
Entering Another Mode
from Memory Read
Mode
675
Figure 22.17 amended
Memory read mode
FA17 to FA0
Other mode command write
Address stable
CE
twep
tnxtc
OE
tces
WE
FO7 to FO0
tceh
tf
Data
tr
H'XX
tdh
tds
Rev. 4.00 Sep 27, 2006 page xiii of xliv
Item
Page
Revision (See Manual for Details)
22.10.4 Memory Read
Mode
676
Figure 22.19 amended
FA17 to FA0
Figure 22.19 Timing
Waveforms for CE/OE
Clocked Read
Address stable
Address stable
tacc
CE
tce
tce
OE
toe
toe
WE
tdf
tdf
tacc
FO7 to FO0
Data
Data
toh
22.10.7 Status Read
Mode
681
toh
Figure 22.22 amended
CE
Figure 22.22 Status
Read Mode Timing
Waveforms
tnxtc
tce
OE
WE
699
tnxtc
twep
tceh
tces
tf
23.5.3 Erase Block
Registers 1 and 2
(EBR1, EBR2)
tr
tnxtc
twep
tces
tf
tceh
toe
tdf
tr
Bit figure amended
Read/Write description of bits 7 to 2 (Before) * → (After) 
2
Bit
1
0
2
2
EB9/—* EB8/—*
EBR1
Initial value
0
0
1 2
1 2
R/W* * R/W* *
Read/Write
Note 2 amended
Note: 2. Bits EB8 and EB9 are not present in the 64-kbyte
versions; they must not be set to1.
Table 23.5 Flash
Memory Erase Blocks
VIH
700
64-kbyte description added to table 23.5
Block (Size)
128-kbyte Version
64-kbyte Version
Address
EB0 (1 kbyte)
EB0 (1 kbyte)
H'(00)0000 to H'(00)03FF
EB1 (1 kbyte)
EB1 (1 kbyte)
H'(00)0400 to H'(00)07FF
EB2 (1 kbyte)
EB2 (1 kbyte)
H'(00)0800 to H'(00)0BFF
EB3 (1 kbytes)
EB3 (1 kbytes)
H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes)
EB4 (28 kbytes)
H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes)
EB5 (16 kbytes)
H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes)
EB6 (8 kbytes)
H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes)
EB7 (8 kbytes)
H'00E000 to H'00FFFF
EB8 (32 kbytes)
—
H'010000 to H'017FFF
EB9 (32 kbytes)
—
H'018000 to H'01FFFF
Rev. 4.00 Sep 27, 2006 page xiv of xliv
Item
Page
Revision (See Manual for Details)
23.6.1 Boot Mode
705
Description amended
H'(FF)E088 and above
23.7.2 Program-Verify
Mode
710
Figure 23.12
Program/Program-Verify
Flowcharts
Note *6 added to figure 23.12
Write pulse application subroutine
Sub-routine write pulse
Start of programming
Start
Enable WDT
Set SWE bit in FLMCR1
Set PSU bit in FLMCR1
Wait (x) µs
Wait (y) µs
*6
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Store 128-byte program data in program
data area and reprogram data area
m=0
*6
Write 128-byte data in RAM reprogram data
*1
area consecutively to flash memory
Sub-routine-call
Write pulse
See Note 7 for pulse width
(z1) µs or (z2) µs
*6
Clear PSU bit in FLMCR2
Wait (β) µs
*4
n=1
*5
Clear P bit in FLMCR1
Wait (α) µs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
*6
Disable WDT
Set PV bit in FLMCR1
End sub
Wait (γ) µs
*6
H'FF dummy write to verify address
Wait (ε) µs
Increment address
*6
Read verify data
Note 7: Write Pulse Width
Number of Writes n Write Time (z*6) µsec
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
13
z2
..
..
.
.
998
z2
999
z2
1000
z2
Note: Use a (z3) µs write pulse for additional
programming.
Program data =
verify data?
*2
m=1
OK
NG
6 ≥ n?
OK
Additional program data computation
Transfer additional program data
to additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
NG
End of 128-byte
data verification?
OK
Clear PV bit in FLMCR1
Wait (η) µs
*6
NG
6 ≥ n?
RAM
Program data storage
area (128 bytes)
n←n+1
NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
*1
Additional write pulse (z3) µs
*6
Reprogram data storage
area (128 bytes)
NG
m = 0?
Additional program data
storage area (128 kbytes)
Wait (θ) µs
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
End of programming
23.10.4 Memory Read
Mode
Figure 23.17 Timing
Waveforms when
Entering Another Mode
from Memory Read
Mode
721
NG
n ≥ 1000?
OK
Clear SWE bit in FLMCR1
*6
Programming failure
Figure 23.17 amended
Memory read mode
FA17 to FA0
Other mode command write
Address stable
CE
twep
tnxtc
OE
tces
WE
FO7 to FO0
tceh
tf
Data
tr
H'XX
tdh
tds
Rev. 4.00 Sep 27, 2006 page xv of xliv
Item
Page
Revision (See Manual for Details)
23.10.4 Memory Read
Mode
722
Figure 23.19 amended
FA17 to FA0
Figure 23.19 Timing
Waveforms for CE/OE
Clocked Read
Address stable
Address stable
tacc
CE
tce
tce
OE
toe
toe
WE
FO7 to FO0
Data
Data
toh
23.10.5 Auto-Program
Mode
724
toh
Figure 23.20 amended
Address
stable
FA17 to FA0
Figure 23.20 AutoProgram Mode Timing
Waveforms
tceh
CE
tas
tah
tnxtc
OE
tnxtc
twep
WE
FO7
Data transfer
1 byte to 128 bytes
tces
twsts
twrite (1 to 3000 ms)
Programming operation
end identification signal
tr
tf
tspa
tds
tdh
Programming normal
end identification signal
FO6
Programming wait
FO7 to FO0
23.10.6 Auto-Erase
Mode
VIH
tdf
tdf
tacc
725
H'40
Data
Data
FO0 to FO5 = 0
Figure 23.21 amended
FA17 to FA0
tceh
tces
Figure 23.21 AutoErase Mode Timing
Waveforms
CE
tspa
OE
WE
tnxtc
twep
tf
tests
tr
terase (100 to 40000 ms)
tds
FO7
Erase end identification
signal
tdh
Erase normal end
confirmation signal
FO6
FO7 to FO0
Rev. 4.00 Sep 27, 2006 page xvi of xliv
CLin
DLin
H'20
H'20
FO0 to FO5 = 0
tnxtc
Item
Page
Revision (See Manual for Details)
23.10.7 Status Read
Mode
727
Figure 23.22 amended
CE
Figure 23.22 Status
Read Mode Timing
Waveforms
WE
tnxtc
twep
tceh
tces
tf
tnxtc
twep
tceh
tces
tf
tr
toe
tdf
tr
tds
tds
tdh
tdh
24.7 Subclock Input
Circuit
740
25.12 Usage Notes
764
Section 25.12 added
26.2.6 Flash Memory
Characteristics
799
Table 26.15 amended
Table 26.15 Flash
Memory Characteristics
(Programming/erasing
operating range)
tnxtc
tce
OE
Note on Subclock Usage
Description added
800
Item
Symbol
Reprogramming count
Data retention time*10
NWEC
Min
100*8
Typ
Max
10000*9 —
Unit
tDRP
10
—
—
Years
Programming Wait time after SWE-bit setting*1
x
10
—
—
µs
Test
Condition
Times
Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.3.3 AC
Characteristics
819
Table 26.20 Clock
Timing
2
Table 26.25 I C Bus
Timing
829
Table 26.20 amended
Condition A
Condition B
20 MHz
16 MHz
Condition C
10 MHz
Item
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test
Conditions
Oscillation settling
time at reset
(crystal)
tOSC1
10
—
10
—
20
—
ms
Figure 26.6
Oscillation settling
time in software
standby (crystal)
tOSC2
8
—
8
—
8
—
ms
Figure 26.7
Table 26.25 amended
Ratings
Item
Symbol
Min
Typ
Max
Unit
SCL, SDA input
fall time
tSf
—
—
300
ns
SCL, SDA output tof
fall time
20 + 0.1 Cb —
250
ns
SCL, SDA input
spike pulse
elimination time
—
1
tcyc
tSP
—
Test Conditions Notes
Figure 26.28
Rev. 4.00 Sep 27, 2006 page xvii of xliv
Item
Page
Revision (See Manual for Details)
26.3.4 A/D Conversion
Characteristics
831
Note *4 added to table condition
4
4
Condition C: VCC = 3.0 V to 3.6V* , AVCC = 3.0 V to 3.6 V* ,
4
4
*
*
AVref = 3.0 V to AVCC , VCCB = 3.0 V to 5.5 V , ...
Table 26.27 A/D
Conversion
Characteristics (CIN15 to
CIN0 Input: 134/266State Conversion)
26.3.6 Flash Memory
Characteristics
Note 4 amended
Note: 4. When using CIN, the applicable range is VCC = 3.0 V to
3.6 V, ...
833
Table 26.29 amended
Item amended (Before) Wait time after dummy write → (After)
Wait time after H'FF dummy write
Table 26.29 Flash
Memory Characteristics
(Programming/erasing
operating range)
Symbol of wait time after SWE-bit clear (Before) Θ → (After) θ
Item
834
Symbol
Reprogramming count
Data retention time*10
NWEC
Min
100*8
Typ
tDRP
10
—
—
Years
Programming Wait time after SWE-bit setting*1
x
1
—
—
µs
10000*
9
Max
Unit
—
Times
Test
Condition
Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.4.3 AC
Characteristics
849
Unit of tNMIH amended
(Before)  → (After) ns
Table 26.35 Control
Signal Timing
Table 26.37 Timing of
On-Chip Supporting
Modules (1)
854,
855
Units of tPRS, tPRH, tFTIS, tFTCS, tTMRS, tTMCS amended
(Before)  → (After) ns
Units of tFTCWL, tTMCWL, synchronous tScyc amended
(Before)  → (After) tcyc
Unit of tSCKf amended
(Before) 1.5 → (After) tcyc
26.4.4 A/D Conversion
Characteristics
Table 26.41 A/D
Conversion
Characteristics (CIN15 to
CIN0 Input: 134/266State Conversion)
860
Table condition amended
Table condition A (Before) ..., Ta = −20 to +75°C (regular
specifications), Ta = −40 to +85°C (wide-range specifications)
→ (After) ... Ta = −20 to +75°C
Rev. 4.00 Sep 27, 2006 page xviii of xliv
Item
Page
Revision (See Manual for Details)
26.4.6 Flash Memory
Characteristics
862
Table 26.43 amended
Item
Table 26.43 Flash
Memory Characteristics
(Programming/erasing
operating range)
Symbol
Reprogramming count
Data retention time*10
Programming Wait time after SWE-bit setting*
863
1
Typ
NWEC
Min
100*8
Max
10000*9 —
Unit
tDRP
10
—
—
Years
x
10
—
—
µs
Test
Condition
Times
Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.5.3 AC
Characteristics
877
Unit of tNMIH amended
(Before) (blank) → (After) ns
Table 26.49 Control
Signal Timing
26.5.6 Flash Memory
Characteristics
Table 26.55 Flash
Memory Characteristics
(Programming/erasing
operating range)
885
886
Table 26.55 amended
Item
Symbol
Reprogramming count
NWEC
Min
100*8
Typ
Max
10000*9 —
Unit
Data retention time*10
tDRP
10
—
—
Years
Programming Wait time after SWE-bit setting*1
x
10
—
—
µs
Condition
Times
Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.6.3 AC
Characteristics
900
Unit of tNMIH amended
(Before) (blank) → (After) ns
Table 26.61 Control
Signal Timing
Rev. 4.00 Sep 27, 2006 page xix of xliv
Item
Page
Revision (See Manual for Details)
26.6.6 Flash Memory
Characteristics
908
Table 26.67 amended
Symbol of wait time after SWE-bit clear (Before) Θ → (After) θ
Table 26.67 Flash
Memory Characteristics
(Programming/erasing
operating range)
909
Min
100*8
Typ
Max
10000*9 —
Test
Condition
Item
Symbol
Reprogramming count
NWEC
Unit
Data retention time*10
tDRP
10
—
—
Years
Programming Wait time after SWE-bit setting*1
x
1
—
—
µs
Times
Notes 8 to 10 added
Notes: 8. Minimum number of times for which all
characteristics are guaranteed after rewriting (Guarantee range
is 1 to minimum value).
9. Reference value for 25°C (as a guideline, rewriting should
normally function up to this value).
10. Data retention characteristic when rewriting is performed
within the specification range, including the minimum value.
26.7.2 Clock Timing
912
Figure 26.6 Oscillation
Settling Timing
Figure 26.6 amended
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
26.7.5 Timing of On924
Chip Supporting Modules
Figure 26.28 amended
2
Figure 26.28 I C Bus
Interface Input/Output
Timing (Option)
VIH
SDA0,
SDA1
VIL
tBUF
tSTAH
SCL0,
SCL1
P*
tSCLH
S*
tSf
tof
tSCLL
tSr
tSCL
Rev. 4.00 Sep 27, 2006 page xx of xliv
tSDAH
Item
Page
Revision (See Manual for Details)
A.1 Instruction
930
Table A.1 amended
Table A.1 Instruction
Set
2. Arithmetic Instructions
EXTU
TAS
933
Condition Code
No. of
States*1
V C
Advanced
H N Z
Normal
I
—
@@aa
@(d,PC)
Operation
@aa
@(d,ERn)
@ERn
Rn
#xx
Size
Mnemonic
@-ERn/@ERn+
Addressing Mode and
Instruction Length (Bytes)
EXTU.W Rd
W
2
0 → (<bits 15 to 8> of Rd16)
— — 0
0 —
1
EXTU.L ERd
L
2
0 → (<bits 31 to 16> of ERd32)
— — 0
0 —
1
TAS @ERd*3
B
@ERd-0 → CCR set, (1) →
(<bit 7> of @ERd)
— —
0 —
4
4
Table A.1 amended
4. Shift Instructions
SHLR
939
Condition Code
No. of
States*1
V C
Advanced
H N Z
Normal
I
—
@@aa
@(d,PC)
Operation
@aa
@(d,ERn)
@ERn
Rn
#xx
Size
Mnemonic
@-ERn/@ERn+
Addressing Mode and
Instruction Length (Bytes)
B
2
— — 0
0
1
SHLR.B #2,Rd
B
2
— — 0
0
1
SHLR.W Rd
W
2
— — 0
0
1
SHLR.W #2,Rd
W
2
— — 0
0
1
SHLR.L ERd
L
2
— — 0
0
1
SHLR.L #2,ERd
L
2
— — 0
0
1
SHLR.B Rd
0
MSB
LSB
C
Table A.1 amended
6. Branch Instructions
JMP
BSR
JSR
RTS
A.2 Instruction Codes
Table A.2 Instruction
Codes
949
JMP @ERn
—
JMP @aa:24
—
JMP @@aa:8
—
BSR d:8
—
BSR d:16
—
JSR @ERn
—
JSR @aa:24
—
JSR @@aa:8
—
RTS
—
Condition Code
No. of
States*1
V C
Advanced
H N Z
Normal
I
—
@@aa
@(d,PC)
Operation
@aa
@(d,ERn)
@ERn
Rn
#xx
Size
Mnemonic
@-ERn/@ERn+
Addressing Mode and
Instruction Length (Bytes)
2
PC←ERn
— — — — — —
PC←aa:24
— — — — — —
PC←@aa:8
— — — — — —
4
5
2
PC→@-SP,PC←PC+d:8
— — — — — —
3
4
4
PC→@-SP,PC←PC+d:16
— — — — — —
4
5
PC→@-SP,PC←ERn
— — — — — —
3
4
PC→@-SP,PC←aa:24
— — — — — —
4
5
PC→@-SP,PC←@aa:8
— — — — — —
4
6
— — — — — —
4
5
2
4
2
2
4
2
2 PC←@SP+
3
Table A.2 amended
Instruction
LDC
Mnemonic
Instruction Format
Size
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte
LDC @aa:16,CCR
W
0
1
4
0
6
B
0
0
abs
LDC @aa:16,EXR
W
0
1
4
1
6
B
0
0
abs
Rev. 4.00 Sep 27, 2006 page xxi of xliv
Item
Page
Revision (See Manual for Details)
B.3 Functions
1013
Subheading amended
KBCOMPH'FEE4 IrDA/Expansion A/D
1016
ISRH'FEEB Interrupt Controller
Figure amended
IRQ7 to IRQ0 flags
0
[Clearing conditions]
• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high*
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
Note: * When a product, in which a DTC is incorporated, is
used in the following settings, the corresponding flag bit is not
automatically cleared even when exception handling, which is a
clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source),
IRQ4F flag is not automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt
source), IRQ5F flag is not automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt
source), IRQ6F flag is not automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt
source), IRQ7F flag is not automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts
are used with the above combinations, clear the interrupt flag
by software in the interrupt handling routine of the
corresponding IRQ.
1019
ABRKCRH'FEF4 Interrupt Controller
Read/Write description amended
Bit 7 (Before) R/W → (After) R
1021
FLMCR1H'FF80 Flash Memory
Initial value description amended
Bit 7 (Before)  → (After) 1
Rev. 4.00 Sep 27, 2006 page xxii of xliv
Item
Page
Revision (See Manual for Details)
B.3 Functions
1025
EBR1H'FF82 Flash Memory
EBR2H'FF83 Flash Memory
Figure amended
Read/Write description of bits 7 to 2 (Before) * → (After) 
2
Bit
7
6
5
4
3
2
EBR1
—
—
—
—
—
—
EB9/—*2 EB8/—*2
0
0
R/W*1*2 R/W*1*2
Initial value
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
7
6
5
4
3
2
1
0
EB6
EB5
EB4
EB3
EB2
EB1
EB0
0
R/W*1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2
Read/Write
1030
0
EB7
Bit
Initial value
1
ICCR1H'FF88 IIC1
ICCR0H'FFD8 IIC0
Figure amended
I2C bus interface enable
1059
0
I2C bus interface module disabled, with
SCL and SDA signal pins set to port
function
SAR and SARX can be accessed
1
I2C bus interface module enabled for
transfer operations (pins SCL and SDA
are driving the bus)
ICMR and ICDR can be accessed
SYSCRH'FFC4 System
Figure amended
IOS enable
0
The AS/IOS pin functions as the address strobe pin
(Low output when accessing an external area)
1
The AS/IOS pin functions as the I/O strobe pin
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*
Note: * In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version,
the address range is from H'(FF)F000 to H'(FF)F7FF.
Rev. 4.00 Sep 27, 2006 page xxiii of xliv
Item
Page
Revision (See Manual for Details)
B.3 Functions
1077
TICRRH'FFF2 TMRX
TICRFH'FFF3 TMRX
Figure amended
(Before) Stores TCNT value at fall of external trigger input →
(After) Stores TCNT value at fall of external reset input
1080
STR1H'FFF6 HIF
STR2H'FFFE HIF
Slave R/W description amended
Bit 0 (Before) R → (After) R/(W)
C.2 Port 2 Block
Diagrams
1089
Figure C.4 amended
Figure C.4 Port 2 Block
Diagram (Pin P27)
Hardware
standby
Mode 1
P27
Appendix F Product
Code Lineup
1128
HD64F2144ATE20 (Before) FP-100B → (After) TFP-100B
Table F.1 H8S/2148
Group and H8S/2144
Group Product Code
Lineup
Appendix G Package
Dimensions
Package code in table F.1 amended
HD64F2144AVFA10 (Before) TFP-100B → (After) FP-100B
1129
Figure G.1 replaced
1130
Figure G.2 replaced
Figure G.1 Package
Dimensions (FP-100B)
Figure G.2 Package
Dimensions (TFP-100B)
Rev. 4.00 Sep 27, 2006 page xxiv of xliv
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
Overview...........................................................................................................................
Internal Block Diagram.....................................................................................................
Pin Arrangement and Functions........................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions in Each Operating Mode ...............................................................
1.3.3 Pin Functions .......................................................................................................
1
1
7
10
10
13
26
Section 2 CPU ...................................................................................................................... 35
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................
2.1.3 Differences from H8/300 CPU ............................................................................
2.1.4 Differences from H8/300H CPU..........................................................................
CPU Operating Modes ......................................................................................................
Address Space...................................................................................................................
Register Configuration......................................................................................................
2.4.1 Overview..............................................................................................................
2.4.2 General Registers .................................................................................................
2.4.3 Control Registers .................................................................................................
2.4.4 Initial Register Values..........................................................................................
Data Formats.....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Overview..............................................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Table of Instructions Classified by Function .......................................................
2.6.4 Basic Instruction Formats ....................................................................................
2.6.5 Notes on Use of Bit-Manipulation Instructions ...................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Mode.................................................................................................
2.7.2 Effective Address Calculation .............................................................................
Processing States...............................................................................................................
2.8.1 Overview..............................................................................................................
2.8.2 Reset State............................................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Program Execution State......................................................................................
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2.8.5 Bus-Released State...............................................................................................
2.8.6 Power-Down State ...............................................................................................
2.9 Basic Timing .....................................................................................................................
2.9.1 Overview..............................................................................................................
2.9.2 On-Chip Memory (ROM, RAM) .........................................................................
2.9.3 On-Chip Supporting Module Access Timing ......................................................
2.9.4 External Address Space Access Timing ..............................................................
2.10 Usage Note........................................................................................................................
2.10.1 TAS Instruction....................................................................................................
2.10.2 STM/LDM Instruction .........................................................................................
76
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78
80
81
82
82
82
Section 3 MCU Operating Modes .................................................................................. 83
3.1
3.2
3.3
3.4
3.5
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR) ......................................................................
3.2.3 Bus Control Register (BCR) ................................................................................
3.2.4 Serial Timer Control Register (STCR) ................................................................
Operating Mode Descriptions ...........................................................................................
3.3.1 Mode 1 .................................................................................................................
3.3.2 Mode 2 .................................................................................................................
3.3.3 Mode 3 .................................................................................................................
Pin Functions in Each Operating Mode ............................................................................
Memory Map in Each Operating Mode ............................................................................
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84
84
85
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88
89
89
89
90
90
91
Section 4 Exception Handling ......................................................................................... 103
4.1
4.2
4.3
4.4
4.5
4.6
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation.............................................................................
4.1.3 Exception Sources and Vector Table ...................................................................
Reset..................................................................................................................................
4.2.1 Overview..............................................................................................................
4.2.2 Reset Sequence ....................................................................................................
4.2.3 Interrupts after Reset............................................................................................
Interrupts ...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Notes on Use of the Stack .................................................................................................
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103
104
104
106
106
106
108
109
110
111
112
Section 5 Interrupt Controller .......................................................................................... 113
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Overview...........................................................................................................................
5.1.1 Features................................................................................................................
5.1.2 Block Diagram .....................................................................................................
5.1.3 Pin Configuration.................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
5.2.1 System Control Register (SYSCR) ......................................................................
5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)............................................
5.2.3 IRQ Enable Register (IER) ..................................................................................
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................
5.2.5 IRQ Status Register (ISR)....................................................................................
5.2.6 Keyboard Matrix Interrupt Mask Register (KMIMR) .........................................
5.2.7 Keyboard Matrix Interrupt Mask Register (KMIMRA).......................................
5.2.8 Address Break Control Register (ABRKCR).......................................................
5.2.9 Break Address Registers A, B, C (BARA, BARB, BARC).................................
Interrupt Sources...............................................................................................................
5.3.1 External Interrupts ...............................................................................................
5.3.2 Internal Interrupts.................................................................................................
5.3.3 Interrupt Exception Vector Table ........................................................................
Address Breaks .................................................................................................................
5.4.1 Features................................................................................................................
5.4.2 Block Diagram .....................................................................................................
5.4.3 Operation .............................................................................................................
5.4.4 Usage Notes .........................................................................................................
Interrupt Operation............................................................................................................
5.5.1 Interrupt Control Modes and Interrupt Operation ................................................
5.5.2 Interrupt Control Mode 0 .....................................................................................
5.5.3 Interrupt Control Mode 1 .....................................................................................
5.5.4 Interrupt Exception Handling Sequence ..............................................................
5.5.5 Interrupt Response Times ....................................................................................
Usage Notes ......................................................................................................................
5.6.1 Contention between Interrupt Generation and Disabling.....................................
5.6.2 Instructions That Disable Interrupts.....................................................................
5.6.3 Interrupts during Execution of EEPMOV Instruction..........................................
DTC Activation by Interrupt.............................................................................................
5.7.1 Overview..............................................................................................................
5.7.2 Block Diagram .....................................................................................................
5.7.3 Operation .............................................................................................................
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120
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126
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Section 6 Bus Controller ................................................................................................... 151
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Overview...........................................................................................................................
6.1.1 Features................................................................................................................
6.1.2 Block Diagram .....................................................................................................
6.1.3 Pin Configuration.................................................................................................
6.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
6.2.1 Bus Control Register (BCR) ................................................................................
6.2.2 Wait State Control Register (WSCR) ..................................................................
Overview of Bus Control ..................................................................................................
6.3.1 Bus Specifications................................................................................................
6.3.2 Advanced Mode...................................................................................................
6.3.3 Normal Mode.......................................................................................................
6.3.4 I/O Select Signal ..................................................................................................
Basic Bus Interface ...........................................................................................................
6.4.1 Overview..............................................................................................................
6.4.2 Data Size and Data Alignment.............................................................................
6.4.3 Valid Strobes........................................................................................................
6.4.4 Basic Timing........................................................................................................
6.4.5 Wait Control ........................................................................................................
Burst ROM Interface.........................................................................................................
6.5.1 Overview..............................................................................................................
6.5.2 Basic Timing........................................................................................................
6.5.3 Wait Control ........................................................................................................
Idle Cycle ..........................................................................................................................
6.6.1 Operation .............................................................................................................
6.6.2 Pin States in Idle Cycle ........................................................................................
Bus Arbitration..................................................................................................................
6.7.1 Overview..............................................................................................................
6.7.2 Operation .............................................................................................................
6.7.3 Bus Transfer Timing ............................................................................................
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158
158
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160
160
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163
171
173
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175
176
177
177
177
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Section 7 Data Transfer Controller (DTC) ................................................................... 179
7.1
7.2
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram .....................................................................................................
7.1.3 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
7.2.1 DTC Mode Register A (MRA) ............................................................................
7.2.2 DTC Mode Register B (MRB).............................................................................
7.2.3 DTC Source Address Register (SAR)..................................................................
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180
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7.3
7.4
7.5
7.2.4 DTC Destination Address Register (DAR)..........................................................
7.2.5 DTC Transfer Count Register A (CRA) ..............................................................
7.2.6 DTC Transfer Count Register B (CRB)...............................................................
7.2.7 DTC Enable Registers (DTCER) .........................................................................
7.2.8 DTC Vector Register (DTVECR)........................................................................
7.2.9 Module Stop Control Register (MSTPCR) ..........................................................
Operation ..........................................................................................................................
7.3.1 Overview..............................................................................................................
7.3.2 Activation Sources ...............................................................................................
7.3.3 DTC Vector Table................................................................................................
7.3.4 Location of Register Information in Address Space ............................................
7.3.5 Normal Mode.......................................................................................................
7.3.6 Repeat Mode ........................................................................................................
7.3.7 Block Transfer Mode ...........................................................................................
7.3.8 Chain Transfer .....................................................................................................
7.3.9 Operation Timing.................................................................................................
7.3.10 Number of DTC Execution States........................................................................
7.3.11 Procedures for Using the DTC.............................................................................
7.3.12 Examples of Use of the DTC ...............................................................................
Interrupts ...........................................................................................................................
Usage Notes ......................................................................................................................
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189
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191
193
195
196
197
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200
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202
204
205
207
207
Section 8 I/O Ports .............................................................................................................. 209
8.1
8.2
8.3
8.4
8.5
Overview...........................................................................................................................
Port 1.................................................................................................................................
8.2.1 Overview..............................................................................................................
8.2.2 Register Configuration.........................................................................................
8.2.3 Pin Functions in Each Mode ................................................................................
8.2.4 MOS Input Pull-Up Function...............................................................................
Port 2.................................................................................................................................
8.3.1 Overview..............................................................................................................
8.3.2 Register Configuration.........................................................................................
8.3.3 Pin Functions in Each Mode ................................................................................
8.3.4 MOS Input Pull-Up Function...............................................................................
Port 3.................................................................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 Register Configuration.........................................................................................
8.4.3 Pin Functions in Each Mode ................................................................................
8.4.4 MOS Input Pull-Up Function...............................................................................
Port 4.................................................................................................................................
8.5.1 Overview..............................................................................................................
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8.5.2 Register Configuration.........................................................................................
8.5.3 Pin Functions .......................................................................................................
8.6 Port 5.................................................................................................................................
8.6.1 Overview..............................................................................................................
8.6.2 Register Configuration.........................................................................................
8.6.3 Pin Functions .......................................................................................................
8.7 Port 6.................................................................................................................................
8.7.1 Overview..............................................................................................................
8.7.2 Register Configuration.........................................................................................
8.7.3 Pin Functions .......................................................................................................
8.7.4 MOS Input Pull-Up Function...............................................................................
8.8 Port 7.................................................................................................................................
8.8.1 Overview..............................................................................................................
8.8.2 Register Configuration.........................................................................................
8.8.3 Pin Functions .......................................................................................................
8.9 Port 8.................................................................................................................................
8.9.1 Overview..............................................................................................................
8.9.2 Register Configuration.........................................................................................
8.9.3 Pin Functions .......................................................................................................
8.10 Port 9.................................................................................................................................
8.10.1 Overview..............................................................................................................
8.10.2 Register Configuration.........................................................................................
8.10.3 Pin Functions .......................................................................................................
8.11 Port A................................................................................................................................
8.11.1 Overview..............................................................................................................
8.11.2 Register Configuration.........................................................................................
8.11.3 Pin Functions .......................................................................................................
8.11.4 MOS Input Pull-Up Function...............................................................................
8.12 Port B ................................................................................................................................
8.12.1 Overview..............................................................................................................
8.12.2 Register Configuration.........................................................................................
8.12.3 Pin Functions .......................................................................................................
8.12.4 MOS Input Pull-Up Function...............................................................................
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261
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278
Section 9 8-Bit PWM Timers........................................................................................... 279
9.1
9.2
Overview...........................................................................................................................
9.1.1 Features................................................................................................................
9.1.2 Block Diagram .....................................................................................................
9.1.3 Pin Configuration.................................................................................................
9.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
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280
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9.3
9.2.1 PWM Register Select (PWSL).............................................................................
9.2.2 PWM Data Registers (PWDR0 to PWDR15) ......................................................
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)....................
9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) .................
9.2.5 Peripheral Clock Select Register (PCSR) ............................................................
9.2.6 Port 1 Data Direction Register (P1DDR).............................................................
9.2.7 Port 2 Data Direction Register (P2DDR).............................................................
9.2.8 Port 1 Data Register (P1DR)................................................................................
9.2.9 Port 2 Data Register (P2DR)................................................................................
9.2.10 Module Stop Control Register (MSTPCR) ..........................................................
Operation ..........................................................................................................................
9.3.1 Correspondence between PWM Data Register Contents
and Output Waveform..........................................................................................
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287
288
289
289
Section 10 14-Bit PWM Timer (PWMX)..................................................................... 291
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.1.2 Block Diagram .....................................................................................................
10.1.3 Pin Configuration.................................................................................................
10.1.4 Register Configuration.........................................................................................
10.2 Register Descriptions ........................................................................................................
10.2.1 PWM (D/A) Counter (DACNT) ..........................................................................
10.2.2 D/A Data Registers A and B (DADRA and DADRB).........................................
10.2.3 PWM D/A Control Register (DACR) ..................................................................
10.2.4 Module Stop Control Register (MSTPCR) ..........................................................
10.3 Bus Master Interface .........................................................................................................
10.4 Operation ..........................................................................................................................
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293
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294
295
296
298
299
302
Section 11 16-Bit Free-Running Timer.........................................................................
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram .....................................................................................................
11.1.3 Input and Output Pins ..........................................................................................
11.1.4 Register Configuration.........................................................................................
11.2 Register Descriptions ........................................................................................................
11.2.1 Free-Running Counter (FRC) ..............................................................................
11.2.2 Output Compare Registers A and B (OCRA, OCRB) .........................................
11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ...............................
11.2.5 Output Compare Register DM (OCRDM) ...........................................................
11.2.6 Timer Interrupt Enable Register (TIER) ..............................................................
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11.2.7 Timer Control/Status Register (TCSR) ................................................................
11.2.8 Timer Control Register (TCR) .............................................................................
11.2.9 Timer Output Compare Control Register (TOCR) ..............................................
11.2.10 Module Stop Control Register (MSTPCR) ..........................................................
Operation ..........................................................................................................................
11.3.1 FRC Increment Timing ........................................................................................
11.3.2 Output Compare Output Timing ..........................................................................
11.3.3 FRC Clear Timing................................................................................................
11.3.4 Input Capture Input Timing .................................................................................
11.3.5 Timing of Input Capture Flag (ICF) Setting ........................................................
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................
11.3.7 Setting of FRC Overflow Flag (OVF) .................................................................
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF .........................................
11.3.9 ICRD and OCRDM Mask Signal Generation ......................................................
Interrupts ...........................................................................................................................
Sample Application...........................................................................................................
Usage Notes ......................................................................................................................
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331
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335
Section 12 8-Bit Timers .....................................................................................................
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 Timer Counter (TCNT)........................................................................................
12.2.2 Time Constant Register A (TCORA)...................................................................
12.2.3 Time Constant Register B (TCORB) ...................................................................
12.2.4 Timer Control Register (TCR) .............................................................................
12.2.5 Timer Control/Status Register (TCSR) ................................................................
12.2.6 Serial/Timer Control Register (STCR) ................................................................
12.2.7 System Control Register (SYSCR) ......................................................................
12.2.8 Timer Connection Register S (TCONRS)............................................................
12.2.9 Input Capture Register (TICR) [TMRX Additional Function] ............................
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]...................
12.2.11 Input Capture Registers R and F (TICRR, TICRF)
[TMRX Additional Functions].............................................................................
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function].....................
12.2.13 Module Stop Control Register (MSTPCR) ..........................................................
12.3 Operation ..........................................................................................................................
12.3.1 TCNT Incrementation Timing .............................................................................
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11.3
11.4
11.5
11.6
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12.3.2 Compare-Match Timing.......................................................................................
12.3.3 TCNT External Reset Timing ..............................................................................
12.3.4 Timing of Overflow Flag (OVF) Setting .............................................................
12.3.5 Operation with Cascaded Connection..................................................................
12.3.6 Input Capture Operation ......................................................................................
12.4 Interrupt Sources...............................................................................................................
12.5 8-Bit Timer Application Example.....................................................................................
12.6 Usage Notes ......................................................................................................................
12.6.1 Contention between TCNT Write and Clear........................................................
12.6.2 Contention between TCNT Write and Increment ................................................
12.6.3 Contention between TCOR Write and Compare-Match ......................................
12.6.4 Contention between Compare-Matches A and B.................................................
12.6.5 Switching of Internal Clocks and TCNT Operation.............................................
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374
Section 13 Timer Connection...........................................................................................
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram .....................................................................................................
13.1.3 Input and Output Pins ..........................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 Timer Connection Register I (TCONRI) .............................................................
13.2.2 Timer Connection Register O (TCONRO) ..........................................................
13.2.3 Timer Connection Register S (TCONRS)............................................................
13.2.4 Edge Sense Register (SEDGR) ............................................................................
13.2.5 Module Stop Control Register (MSTPCR) ..........................................................
13.3 Operation ..........................................................................................................................
13.3.1 PWM Decoding (PDC Signal Generation) ..........................................................
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) .....................
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period ....................................
13.3.4 IHI Signal and 2fH Modification .........................................................................
13.3.5 IVI Signal Fall Modification and IHI Synchronization .......................................
13.3.6 Internal Synchronization Signal Generation
(IHG/IVG/CL4 Signal Generation) .....................................................................
13.3.7 HSYNCO Output .................................................................................................
13.3.8 VSYNCO Output .................................................................................................
13.3.9 CBLANK Output .................................................................................................
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403
404
405
Section 14 Watchdog Timer (WDT) .............................................................................. 407
14.1 Overview........................................................................................................................... 407
14.1.1 Features................................................................................................................ 407
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14.1.2 Block Diagram .....................................................................................................
14.1.3 Pin Configuration.................................................................................................
14.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
14.2.1 Timer Counter (TCNT)........................................................................................
14.2.2 Timer Control/Status Register (TCSR) ................................................................
14.2.3 System Control Register (SYSCR) ......................................................................
14.2.4 Notes on Register Access.....................................................................................
Operation ..........................................................................................................................
14.3.1 Watchdog Timer Operation .................................................................................
14.3.2 Interval Timer Operation .....................................................................................
14.3.3 Timing of Setting of Overflow Flag (OVF) .........................................................
14.3.4 RESO Signal Output Timing ...............................................................................
Interrupts ...........................................................................................................................
Usage Notes ......................................................................................................................
14.5.1 Contention between Timer Counter (TCNT) Write and Increment .....................
14.5.2 Changing Value of CKS2 to CKS0......................................................................
14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................
14.5.4 System Reset by RESO Signal.............................................................................
14.5.5 Counter Value in Transitions between High-Speed Mode, Subactive Mode,
and Watch Mode..................................................................................................
14.5.6 OVF Flag Clear Condition...................................................................................
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414
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418
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419
420
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421
Section 15 Serial Communication Interface (SCI, IrDA) ........................................
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram .....................................................................................................
15.1.3 Pin Configuration.................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions ........................................................................................................
15.2.1 Receive Shift Register (RSR) ..............................................................................
15.2.2 Receive Data Register (RDR) ..............................................................................
15.2.3 Transmit Shift Register (TSR) .............................................................................
15.2.4 Transmit Data Register (TDR).............................................................................
15.2.5 Serial Mode Register (SMR)................................................................................
15.2.6 Serial Control Register (SCR)..............................................................................
15.2.7 Serial Status Register (SSR) ................................................................................
15.2.8 Bit Rate Register (BRR) ......................................................................................
15.2.9 Serial Interface Mode Register (SCMR)..............................................................
15.2.10 Module Stop Control Register (MSTPCR) ..........................................................
15.2.11 Keyboard Comparator Control Register (KBCOMP) ..........................................
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452
14.2
14.3
14.4
14.5
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422
15.3 Operation ..........................................................................................................................
15.3.1 Overview..............................................................................................................
15.3.2 Operation in Asynchronous Mode .......................................................................
15.3.3 Multiprocessor Communication Function............................................................
15.3.4 Operation in Synchronous Mode .........................................................................
15.3.5 IrDA Operation ....................................................................................................
15.4 SCI Interrupts....................................................................................................................
15.5 Usage Notes ......................................................................................................................
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453
455
466
474
483
486
487
Section 16 I2C Bus Interface [Option] ........................................................................... 491
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram .....................................................................................................
16.1.3 Input/Output Pins .................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions ........................................................................................................
2
16.2.1 I C Bus Data Register (ICDR) .............................................................................
16.2.2 Slave Address Register (SAR) .............................................................................
16.2.3 Second Slave Address Register (SARX) .............................................................
2
16.2.4 I C Bus Mode Register (ICMR) ...........................................................................
2
16.2.5 I C Bus Control Register (ICCR) .........................................................................
2
16.2.6 I C Bus Status Register (ICSR)............................................................................
16.2.7 Serial/Timer Control Register (STCR) ................................................................
16.2.8 DDC Switch Register (DDCSWR) ......................................................................
16.2.9 Module Stop Control Register (MSTPCR) ..........................................................
16.3 Operation ..........................................................................................................................
2
16.3.1 I C Bus Data Format ............................................................................................
16.3.2 Master Transmit Operation ..................................................................................
16.3.3 Master Receive Operation....................................................................................
16.3.4 Slave Receive Operation......................................................................................
16.3.5 Slave Transmit Operation ....................................................................................
16.3.6 IRIC Setting Timing and SCL Control ................................................................
2
16.3.7 Automatic Switching from Formatless Mode to I C Bus Format ........................
16.3.8 Operation Using the DTC ....................................................................................
16.3.9 Noise Canceler .....................................................................................................
16.3.10 Sample Flowcharts...............................................................................................
16.3.11 Initialization of Internal State ..............................................................................
16.4 Usage Notes ......................................................................................................................
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521
521
523
525
528
531
533
534
535
536
536
541
542
Section 17 Keyboard Buffer Controller ........................................................................ 559
17.1 Overview........................................................................................................................... 559
Rev. 4.00 Sep 27, 2006 page xxxv of xliv
17.1.1 Features................................................................................................................
17.1.2 Block Diagram .....................................................................................................
17.1.3 Input/Output Pins .................................................................................................
17.1.4 Register Configuration.........................................................................................
17.2 Register Descriptions ........................................................................................................
17.2.1 Keyboard Control Register H (KBCRH) .............................................................
17.2.2 Keyboard Control Register L (KBCRL) ..............................................................
17.2.3 Keyboard Data Buffer Register (KBBR) .............................................................
17.2.4 Module Stop Control Register (MSTPCR) ..........................................................
17.3 Operation ..........................................................................................................................
17.3.1 Receive Operation................................................................................................
17.3.2 Transmit Operation ..............................................................................................
17.3.3 Receive Abort ......................................................................................................
17.3.4 KCLKI and KDI Read Timing.............................................................................
17.3.5 KCLKO and KDO Write Timing.........................................................................
17.3.6 KBF Setting Timing and KCLK Control .............................................................
17.3.7 Receive Timing....................................................................................................
17.3.8 KCLK Fall Interrupt Operation............................................................................
17.3.9 Usage Note...........................................................................................................
559
561
562
562
563
563
565
567
567
568
568
570
573
576
577
578
579
580
581
Section 18 Host Interface ..................................................................................................
18.1 Overview...........................................................................................................................
18.1.1 Features................................................................................................................
18.1.2 Block Diagram .....................................................................................................
18.1.3 Input and Output Pins ..........................................................................................
18.1.4 Register Configuration.........................................................................................
18.2 Register Descriptions ........................................................................................................
18.2.1 System Control Register (SYSCR) ......................................................................
18.2.2 System Control Register 2 (SYSCR2) .................................................................
18.2.3 Host Interface Control Register (HICR) ..............................................................
18.2.4 Input Data Register 1 (IDR1)...............................................................................
18.2.5 Output Data Register 1 (ODR).............................................................................
18.2.6 Status Register (STR) ..........................................................................................
18.2.7 Module Stop Control Register (MSTPCR) ..........................................................
18.3 Operation ..........................................................................................................................
18.3.1 Host Interface Activation .....................................................................................
18.3.2 Control States.......................................................................................................
18.3.3 A20 Gate ..............................................................................................................
18.3.4 Host Interface Pin Shutdown Function ................................................................
18.4 Interrupts ...........................................................................................................................
18.4.1 IBF1, IBF2, IBF3, IBF4.......................................................................................
583
583
583
584
585
586
587
587
588
590
592
592
593
595
595
595
597
597
599
601
601
Rev. 4.00 Sep 27, 2006 page xxxvi of xliv
18.4.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................ 601
18.5 Usage Note........................................................................................................................ 603
Section 19 D/A Converter ................................................................................................. 605
19.1 Overview...........................................................................................................................
19.1.1 Features................................................................................................................
19.1.2 Block Diagram .....................................................................................................
19.1.3 Input and Output Pins ..........................................................................................
19.1.4 Register Configuration.........................................................................................
19.2 Register Descriptions ........................................................................................................
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................
19.2.2 D/A Control Register (DACR) ............................................................................
19.2.3 Module Stop Control Register (MSTPCR) ..........................................................
19.3 Operation ..........................................................................................................................
605
605
606
607
607
608
608
608
610
611
Section 20 A/D Converter ................................................................................................. 613
20.1 Overview...........................................................................................................................
20.1.1 Features................................................................................................................
20.1.2 Block Diagram .....................................................................................................
20.1.3 Pin Configuration.................................................................................................
20.1.4 Register Configuration.........................................................................................
20.2 Register Descriptions ........................................................................................................
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................
20.2.2 A/D Control/Status Register (ADCSR) ...............................................................
20.2.3 A/D Control Register (ADCR) ............................................................................
20.2.4 Keyboard Comparator Control Register (KBCOMP) ..........................................
20.2.5 Module Stop Control Register (MSTPCR) ..........................................................
20.3 Interface to Bus Master .....................................................................................................
20.4 Operation ..........................................................................................................................
20.4.1 Single Mode (SCAN = 0) ....................................................................................
20.4.2 Scan Mode (SCAN = 1).......................................................................................
20.4.3 Input Sampling and A/D Conversion Time .........................................................
20.4.4 External Trigger Input Timing.............................................................................
20.5 Interrupts ...........................................................................................................................
20.6 Usage Notes ......................................................................................................................
613
613
614
615
616
616
616
617
620
621
622
623
624
624
626
628
629
629
630
Section 21 RAM ..................................................................................................................
21.1 Overview...........................................................................................................................
21.1.1 Block Diagram .....................................................................................................
21.1.2 Register Configuration.........................................................................................
21.2 System Control Register (SYSCR) ...................................................................................
635
635
635
636
636
Rev. 4.00 Sep 27, 2006 page xxxvii of xliv
21.3 Operation .......................................................................................................................... 637
21.3.1 Expanded Mode (Modes 1, 2, 3 (EXPE = 1)) ...................................................... 637
21.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0)) ................................................. 637
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT,
H8S/2147N F-ZTAT, H8S/2144 F-ZTAT,
and H8S/2142 F-ZTAT) ............................................................................... 639
22.1 Overview...........................................................................................................................
22.1.1 Block Diagram .....................................................................................................
22.1.2 Register Configuration.........................................................................................
22.2 Register Descriptions ........................................................................................................
22.2.1 Mode Control Register (MDCR) .........................................................................
22.3 Operation ..........................................................................................................................
22.4 Overview of Flash Memory ..............................................................................................
22.4.1 Features................................................................................................................
22.4.2 Block Diagram .....................................................................................................
22.4.3 Flash Memory Operating Modes .........................................................................
22.4.4 Pin Configuration.................................................................................................
22.4.5 Register Configuration.........................................................................................
22.5 Register Descriptions ........................................................................................................
22.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................
22.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................
22.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2).....................................................
22.5.4 Serial/Timer Control Register (STCR) ................................................................
22.6 On-Board Programming Modes........................................................................................
22.6.1 Boot Mode ...........................................................................................................
22.6.2 User Program Mode.............................................................................................
22.7 Programming/Erasing Flash Memory ...............................................................................
22.7.1 Program Mode .....................................................................................................
22.7.2 Program-Verify Mode..........................................................................................
22.7.3 Erase Mode ..........................................................................................................
22.7.4 Erase-Verify Mode ..............................................................................................
22.8 Flash Memory Protection..................................................................................................
22.8.1 Hardware Protection ............................................................................................
22.8.2 Software Protection..............................................................................................
22.8.3 Error Protection....................................................................................................
22.9 Interrupt Handling when Programming/Erasing Flash Memory.......................................
22.10 Flash Memory Programmer Mode ....................................................................................
22.10.1 Programmer Mode Setting ...................................................................................
22.10.2 Socket Adapters and Memory Map .....................................................................
22.10.3 Programmer Mode Operation ..............................................................................
Rev. 4.00 Sep 27, 2006 page xxxviii of xliv
639
639
640
640
640
641
642
642
643
644
648
648
649
649
651
653
654
655
656
661
662
662
663
665
665
667
667
667
668
670
671
671
672
672
22.10.4 Memory Read Mode ............................................................................................
22.10.5 Auto-Program Mode ............................................................................................
22.10.6 Auto-Erase Mode.................................................................................................
22.10.7 Status Read Mode ................................................................................................
22.10.8 Status Polling .......................................................................................................
22.10.9 Programmer Mode Transition Time ....................................................................
22.10.10 Notes on Memory Programming......................................................................
22.11 Flash Memory Programming and Erasing Precautions.....................................................
22.12 Note on Switching from F-ZTAT Version to Mask ROM Version ..................................
673
677
679
680
681
682
683
683
684
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version,
H8S/2147 F-ZTAT A-Mask Version,
H8S/2144 F-ZTAT A-Mask Version) ...................................................... 685
23.1 Overview...........................................................................................................................
23.1.1 Block Diagram .....................................................................................................
23.1.2 Register Configuration.........................................................................................
23.2 Register Descriptions ........................................................................................................
23.2.1 Mode Control Register (MDCR) .........................................................................
23.3 Operation ..........................................................................................................................
23.4 Overview of Flash Memory ..............................................................................................
23.4.1 Features................................................................................................................
23.4.2 Block Diagram .....................................................................................................
23.4.3 Flash Memory Operating Modes .........................................................................
23.4.4 Pin Configuration.................................................................................................
23.4.5 Register Configuration.........................................................................................
23.5 Register Descriptions ........................................................................................................
23.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................
23.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................
23.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2).....................................................
23.5.4 Serial/Timer Control Register (STCR) ................................................................
23.6 On-Board Programming Modes........................................................................................
23.6.1 Boot Mode ...........................................................................................................
23.6.2 User Program Mode.............................................................................................
23.7 Programming/Erasing Flash Memory ...............................................................................
23.7.1 Program Mode .....................................................................................................
23.7.2 Program-Verify Mode..........................................................................................
23.7.3 Erase Mode ..........................................................................................................
23.7.4 Erase-Verify Mode ..............................................................................................
23.8 Flash Memory Protection..................................................................................................
23.8.1 Hardware Protection ............................................................................................
23.8.2 Software Protection..............................................................................................
685
685
686
686
686
687
688
688
689
690
694
694
695
695
697
699
700
701
702
707
708
708
709
711
711
713
713
713
Rev. 4.00 Sep 27, 2006 page xxxix of xliv
23.8.3 Error Protection....................................................................................................
23.9 Interrupt Handling when Programming/Erasing Flash Memory.......................................
23.10 Flash Memory Programmer Mode ....................................................................................
23.10.1 Programmer Mode Setting ...................................................................................
23.10.2 Socket Adapters and Memory Map .....................................................................
23.10.3 Programmer Mode Operation ..............................................................................
23.10.4 Memory Read Mode ............................................................................................
23.10.5 Auto-Program Mode ............................................................................................
23.10.6 Auto-Erase Mode.................................................................................................
23.10.7 Status Read Mode ................................................................................................
23.10.8 Status Polling .......................................................................................................
23.10.9 Programmer Mode Transition Time ....................................................................
23.10.10 Notes on Memory Programming......................................................................
23.11 Flash Memory Programming and Erasing Precautions.....................................................
23.12 Note on Switching from F-ZTAT Version to Mask ROM Version ..................................
714
716
717
717
718
718
719
723
725
726
727
728
729
729
730
Section 24 Clock Pulse Generator ..................................................................................
24.1 Overview...........................................................................................................................
24.1.1 Block Diagram .....................................................................................................
24.1.2 Register Configuration.........................................................................................
24.2 Register Descriptions ........................................................................................................
24.2.1 Standby Control Register (SBYCR) ....................................................................
24.2.2 Low-Power Control Register (LPWRCR) ...........................................................
24.3 Oscillator...........................................................................................................................
24.3.1 Connecting a Crystal Resonator...........................................................................
24.3.2 External Clock Input ............................................................................................
24.4 Duty Adjustment Circuit...................................................................................................
24.5 Medium-Speed Clock Divider ..........................................................................................
24.6 Bus Master Clock Selection Circuit ..................................................................................
24.7 Subclock Input Circuit ......................................................................................................
24.8 Subclock Waveform Shaping Circuit................................................................................
24.9 Clock Selection Circuit .....................................................................................................
731
731
731
732
732
732
733
734
734
736
739
739
739
739
740
741
Section 25 Power-Down State ......................................................................................... 743
25.1 Overview...........................................................................................................................
25.1.1 Register Configuration.........................................................................................
25.2 Register Descriptions ........................................................................................................
25.2.1 Standby Control Register (SBYCR) ....................................................................
25.2.2 Low-Power Control Register (LPWRCR) ...........................................................
25.2.3 Timer Control/Status Register (TCSR) ................................................................
25.2.4 Module Stop Control Register (MSTPCR) ..........................................................
Rev. 4.00 Sep 27, 2006 page xl of xliv
743
747
747
747
749
751
752
25.3 Medium-Speed Mode........................................................................................................
25.4 Sleep Mode .......................................................................................................................
25.4.1 Sleep Mode ..........................................................................................................
25.4.2 Clearing Sleep Mode............................................................................................
25.5 Module Stop Mode ...........................................................................................................
25.5.1 Module Stop Mode ..............................................................................................
25.5.2 Usage Note...........................................................................................................
25.6 Software Standby Mode....................................................................................................
25.6.1 Software Standby Mode.......................................................................................
25.6.2 Clearing Software Standby Mode ........................................................................
25.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ..........
25.6.4 Software Standby Mode Application Example....................................................
25.6.5 Usage Note...........................................................................................................
25.7 Hardware Standby Mode ..................................................................................................
25.7.1 Hardware Standby Mode .....................................................................................
25.7.2 Hardware Standby Mode Timing.........................................................................
25.8 Watch Mode......................................................................................................................
25.8.1 Watch Mode.........................................................................................................
25.8.2 Clearing Watch Mode ..........................................................................................
25.9 Subsleep Mode..................................................................................................................
25.9.1 Subsleep Mode.....................................................................................................
25.9.2 Clearing Subsleep Mode ......................................................................................
25.10 Subactive Mode ................................................................................................................
25.10.1 Subactive Mode ...................................................................................................
25.10.2 Clearing Subactive Mode.....................................................................................
25.11 Direct Transition ...............................................................................................................
25.11.1 Overview of Direct Transition .............................................................................
25.12 Usage Notes ......................................................................................................................
753
754
754
754
755
755
756
757
757
757
757
758
759
759
759
760
761
761
761
762
762
762
763
763
763
764
764
764
Section 26 Electrical Characteristics.............................................................................. 765
26.1 Voltage of Power Supply and Operating Range ...............................................................
26.2 Electrical Characteristics of H8S/2148 F-ZTAT...............................................................
26.2.1 Absolute Maximum Ratings ................................................................................
26.2.2 DC Characteristics ...............................................................................................
26.2.3 AC Characteristics ...............................................................................................
26.2.4 A/D Conversion Characteristics...........................................................................
26.2.5 D/A Conversion Characteristics...........................................................................
26.2.6 Flash Memory Characteristics .............................................................................
26.2.7 Usage Note...........................................................................................................
765
768
768
769
784
796
798
799
800
Rev. 4.00 Sep 27, 2006 page xli of xliv
26.3 Electrical Characteristics of H8S/2148 F-ZTAT (A-mask version),
H8S/2147 F-ZTAT (A-mask version), and Mask ROM Versions of H8S/2148
and H8S/2147....................................................................................................................
26.3.1 Absolute Maximum Ratings ................................................................................
26.3.2 DC Characteristics ...............................................................................................
26.3.3 AC Characteristics ...............................................................................................
26.3.4 A/D Conversion Characteristics...........................................................................
26.3.5 D/A Conversion Characteristics...........................................................................
26.3.6 Flash Memory Characteristics .............................................................................
26.3.7 Usage Note...........................................................................................................
26.4 Electrical Characteristics of H8S/2147N F-ZTAT............................................................
26.4.1 Absolute Maximum Ratings ................................................................................
26.4.2 DC Characteristics ...............................................................................................
26.4.3 AC Characteristics ...............................................................................................
26.4.4 A/D Conversion Characteristics...........................................................................
26.4.5 D/A Conversion Characteristics...........................................................................
26.4.6 Flash Memory Characteristics .............................................................................
26.4.7 Usage Note...........................................................................................................
26.5 Electrical Characteristics of H8S/2144 F-ZTAT, H8S/2142 F-ZTAT,
and Mask ROM Version of H8S/2142..............................................................................
26.5.1 Absolute Maximum Ratings ................................................................................
26.5.2 DC Characteristics ...............................................................................................
26.5.3 AC Characteristics ...............................................................................................
26.5.4 A/D Conversion Characteristics...........................................................................
26.5.5 D/A Conversion Characteristics...........................................................................
26.5.6 Flash Memory Characteristics .............................................................................
26.5.7 Usage Note...........................................................................................................
26.6 Electrical Characteristics of H8S/2144 F-ZTAT (A-mask version)
and Mask ROM Versions of H8S/2144 and H8S/2143 ....................................................
26.6.1 Absolute Maximum Ratings ................................................................................
26.6.2 DC Characteristics ...............................................................................................
26.6.3 AC Characteristics ...............................................................................................
26.6.4 A/D Conversion Characteristics...........................................................................
26.6.5 D/A Conversion Characteristics...........................................................................
26.6.6 Flash Memory Characteristics .............................................................................
26.6.7 Usage Note...........................................................................................................
26.7 Operational Timing ...........................................................................................................
26.7.1 Test Conditions for the AC Characteristics..........................................................
26.7.2 Clock Timing .......................................................................................................
26.7.3 Control Signal Timing .........................................................................................
26.7.4 Bus Timing ..........................................................................................................
Rev. 4.00 Sep 27, 2006 page xlii of xliv
802
802
804
818
830
832
832
835
836
836
837
847
859
861
862
863
864
864
865
875
882
884
885
886
887
887
888
898
905
907
907
910
911
911
911
912
914
26.7.5 Timing of On-Chip Supporting Modules............................................................. 919
Appendix A Instruction Set .............................................................................................. 925
A.1
A.2
A.3
A.4
A.5
Instruction .........................................................................................................................
Instruction Codes ..............................................................................................................
Operation Code Map.........................................................................................................
Number of States Required for Execution ........................................................................
Bus States during Instruction Execution ...........................................................................
925
943
957
961
974
Appendix B Internal I/O Registers ................................................................................. 990
B.1
B.2
B.3
Addresses .......................................................................................................................... 990
Register Selection Conditions ........................................................................................... 997
Functions......................................................................................................................... 1004
Appendix C I/O Port Block Diagrams......................................................................... 1086
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
Port 1 Block Diagram .....................................................................................................
Port 2 Block Diagrams....................................................................................................
Port 3 Block Diagram .....................................................................................................
Port 4 Block Diagrams....................................................................................................
Port 5 Block Diagrams....................................................................................................
Port 6 Block Diagrams....................................................................................................
Port 7 Block Diagrams....................................................................................................
Port 8 Block Diagrams....................................................................................................
Port 9 Block Diagrams....................................................................................................
Port A Block Diagrams ...................................................................................................
Port B Block Diagram.....................................................................................................
1086
1087
1090
1091
1098
1101
1106
1107
1113
1118
1121
Appendix D Pin States ..................................................................................................... 1124
D.1
Port States in Each Processing State ............................................................................... 1124
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode ............................................................................................ 1126
E.1
E.2
Timing of Transition to Hardware Standby Mode .......................................................... 1126
Timing of Recovery from Hardware Standby Mode....................................................... 1126
Appendix F Product Code Lineup ................................................................................ 1127
Appendix G Package Dimensions ................................................................................ 1129
Rev. 4.00 Sep 27, 2006 page xliii of xliv
Rev. 4.00 Sep 27, 2006 page xliv of xliv
Section 1 Overview
Section 1 Overview
1.1
Overview
This LSI comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Renesas
Technology proprietary architecture, and equipped with supporting modules on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting modules required for system configuration include a data transfer controller
(DTC) bus master, ROM and RAM, a 16-bit free-running timer module (FRT), 8-bit timer module
(TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), serial
communication interface (SCI), PS/2-compatible keyboard buffer controller, host interface (HIF),
2
D/A converter (DAC), A/D converter (ADC), and I/O ports. An I C bus interface (IIC) can also be
incorporated as an option.
The on-chip ROM is either flash memory (F-ZTAT™*) or mask ROM, with a capacity of 128, 96,
or 64 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word
data to be accessed in one state. Instruction fetching has been speeded up, and processing speed
increased.
Three operating modes, modes 1 to 3, are provided, and there is a choice of address space and
single-chip mode or externally expanded modes.
The features of this LSI are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 4.00 Sep 27, 2006 page 1 of 1130
REJ09B0327-0400
Section 1 Overview
Table 1.1
Overview
Item
Specifications
CPU
•
General-register architecture
 Sixteen 16-bit general registers (also usable as sixteen 8-bit
registers or eight 32-bit registers)
•
High-speed operation suitable for real-time control
 Maximum operating frequency: 20 MHz/5 V, 10 MHz/3 V
 High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns (20-MHz operation)
16 × 16-bit register-register multiply: 1000 ns (20-MHz operation)
32 ÷ 16-bit register-register divide: 1000 ns (20-MHz operation)
•
Instruction set suitable for high-speed operation
 Sixty-five basic instructions
 8/16/32-bit transfer/arithmetic and logic instructions
 Unsigned/signed multiply and divide instructions
 Powerful bit-manipulation instructions
•
Two CPU operating modes
 Normal mode: 64-kbyte address space
 Advanced mode: 16-Mbyte address space
Operating modes
• Three MCU operating modes
External Data Bus
Mode
CPU Operating
Mode
1
Normal
Expanded mode
with on-chip ROM
disabled
Disabled
8 bits
16 bits
2
Advanced
Single-chip mode
Enabled
None
None
Expanded mode
with on-chip ROM
enabled
Enabled
8 bits
16 bits
Single-chip mode
Enabled
None
None
Expanded mode
with on-chip ROM
enabled
Enabled
8 bits
16 bits
3
Normal
Rev. 4.00 Sep 27, 2006 page 2 of 1130
REJ09B0327-0400
Description
On-Chip
ROM
Initial
Value
Maximum
Value
Section 1 Overview
Item
Specifications
Bus controller
•
2-state or 3-state access space can be designated for external
expansion areas
•
Number of program wait states can be set for external expansion areas
•
Can be activated by internal interrupt or software
•
Multiple transfers or multiple types of transfer possible for one
activation source
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Request can be sent to CPU for interrupt that activated DTC
•
One 16-bit free-running counter (also usable for external event
counting)
•
Two output compare outputs
•
Four input capture inputs (with buffer operation capability)
Data transfer
controller (DTC)
(H8S/2148 Group)
16-bit free-running
timer module
(FRT: 1 channel)
8-bit timer module
(2 channels: TMR0,
TMR1)
Each channel has:
•
One 8-bit up-counter (also usable for external event counting)
•
Two timer constant registers
•
The two channels can be connected
Timer connection and Input/output and FRT, TMR1, TMRX, TMRY can be interconnected
8-bit timer module
• Measurement of input signal or frequency-divided waveform pulse
(TMR) (2 channels:
width and cycle (FRT, TMR1)
TMRX, TMRY)
(Timer connection and • Output of waveform obtained by modification of input signal edge (FRT,
TMRX provided in
TMR1)
H8S/2148 Group)
• Determination of input signal duty cycle (TMRX)
Watchdog timer
module
(WDT: 2 channels)
•
Output of waveform synchronized with input signal (FRT, TMRX,
TMRY)
•
Automatic generation of cyclical waveform (FRT, TMRY)
•
Watchdog timer or interval timer function selectable
•
Subclock operation capability (channel 1 only)
8-bit PWM timer
•
(PWM)
•
(H8S/2148 Group and
•
H8S/2147N)
•
Up to 16 outputs
Pulse duty cycle settable from 0 to 100%
Resolution: 1/256
1.25 MHz maximum carrier frequency (20-MHz operation)
Rev. 4.00 Sep 27, 2006 page 3 of 1130
REJ09B0327-0400
Section 1 Overview
Item
Specifications
14-bit PWM timer
(PWMX)
•
Up to 2 outputs
•
Resolution: 1/16384
•
312.5 kHz maximum carrier frequency (20-MHz operation)
Serial communication •
interface
•
(SCI: 2 channels,
SCI0 and SCI1)
Asynchronous mode or synchronous mode selectable
•
Asynchronous mode or synchronous mode selectable
•
Multiprocessor communication function
•
Compatible with IrDA specification version 1.0
SCI with IrDA:
1 channel (SCI2)
Multiprocessor communication function
•
TxD and RxD encoding/decoding in IrDA format
Keyboard buffer
controller (PS2:
3 channels)
(H8S/2148 Group,
H8S/2147N)
•
Compatible with PS/2 interface
•
Direct manipulation of transmission output by software
•
Receive data input to 8-bit shift register
•
Data receive completed interrupt, parity error detection, stop bit
monitoring
Host interface (HIF)
(H8S/2148 Group,
H8S/2147N)
•
8-bit host interface (ISA) port
•
Five host interrupt requests (HIRQ11, HIRQ1, HIRQ12, HIRQ3,
HIRQ4)
•
Normal and fast A20 gate output
•
Four register sets (each comprising two data registers and two status
registers)
Keyboard controller
•
Matrix keyboard control using keyboard scan with wakeup interrupt and
sense port configuration
A/D converter
•
Resolution: 10 bits
•
Input:
 8 channels (dedicated analog pins)
 16 channels (same pins as keyboard sense port)
•
High-speed conversion: 6.7 µs minimum conversion time (20-MHz
operation)
•
Single or scan mode selectable
•
Sample-and-hold function
•
A/D conversion can be activated by external trigger or timer trigger
Rev. 4.00 Sep 27, 2006 page 4 of 1130
REJ09B0327-0400
Section 1 Overview
Item
Specifications
D/A converter
•
Resolution: 8 bits
•
Output: 2 channels
•
74 input/output pins (including 24 with LED drive capability)
•
8 input-only pins
•
VCCB (separate power supply) drive pins among I/O pins (H8S/2148
Group and H8S/2147N)
•
Flash memory or mask ROM
•
High-speed static RAM
I/O ports
Memory
Interrupt controller
Power-down state
Product Name
ROM
RAM
H8S/2144, H8S/2148
128 kbytes
4 kbytes
H8S/2143
96 kbytes
4 kbytes
H8S/2142, H8S/2147,
H8S/2147N
64 kbytes
2 kbytes
•
Nine external interrupt pins (NMI, IRQ0 to IRQ7)
•
44 internal interrupt sources
•
Three priority levels settable
•
Medium-speed mode
•
Sleep mode
•
Module stop mode
•
Software standby mode
•
Hardware standby mode
•
Subclock operation
Clock pulse generator •
Packages
2
I C bus interface
(IIC: 2 channels)
(option in H8S/2148
Group and
H8S/2147N)
Built-in duty correction circuit
•
100-pin plastic QFP (FP-100B)
•
100-pin plastic TQFP (TFP-100B)
•
Conforms to Philips I C bus interface standard
•
Single master mode/slave mode
•
Arbitration lost condition can be identified
•
Supports two slave addresses
2
Rev. 4.00 Sep 27, 2006 page 5 of 1130
REJ09B0327-0400
Section 1 Overview
Item
Specifications
Product Code*2
Product lineup
(preliminary)
Group
Mask ROM
Versions
F-ZTAT
Versions
ROM/RAM
(Bytes)
H8S/2148
HD6432148S
HD64F2148
HD64F2148V*2
128 k/4 k
HD6432148SW*1
HD64F2148A
HD64F2148AV*2
HD6432147S
HD64F2147A
HD6432147SW*1
HD64F2147AV*2
H8S/2147N
—
HD64F2147N
HD64F2147NV*2
64 k/2 k
H8S/2144
HD6432144S
HD64F2144
HD64F2144V*2
128 k/4 k
Packages
FP-100B,
TFP-100B
64 k/2 k
HD64F2144A
HD64F2144AV*2
HD6432143S
—
96 k/4 k
HD6432142
HD64F2142R
HD64F2142RV*2
64 k/2 k
2
Notes: 1. W indicates the I C bus option.
2. V indicates the 3-V version. Please refer to appendix F, Product
Code Lineup.
Rev. 4.00 Sep 27, 2006 page 6 of 1130
REJ09B0327-0400
Section 1 Overview
1.2
Internal Block Diagram
VCC1
VCC2 (VCL)
VSS
VSS
VSS
VSS
VSS
An internal block diagram of the H8S/2148 Group is shown in figure 1.1 (a), an internal block
diagram of the H8S/2147N is shown in figure 1.1 (b), and an internal block diagram of the
H8S/2144 Group in figure 1.1 (c).
Interrupt
controller
Port A
PA1/A17/KIN9/CIN9
Port 9
DTC
ROM
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
Port 4
Host interface
10-bit A/D
8-bit D/A
IIC × 2ch
(option)
P37/D15/HDB7
P36/D14/HDB6
P35/D13/HDB5
P34/D12/HDB4
P33/D11/HDB3
P32/D10/HDB2
P31/D9/HDB1
P30/D8/HDB0
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
P70/AN0
P71/AN1
P75/AN5
P74/AN4
P73/AN3
P72/AN2
AVSS
P77/AN7/DA1
P76/AN6/DA0
AVref
AVCC
Port 7
P81/CS2/GA20
P80/HA0
P84/IRQ3/TxD1
P83
P82/HIFSD
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
Port 8
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
PB7/D7
PB6/D6
Port B
SCI × 3ch
(IrDA × 1ch)
Port 5
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
Port 3
14-bit PWM
8-bit timer × 4ch
(TMR0, TMR1,
TMRX, TMRY)
Timer connection
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
8-bit PWM
16-bit FRT
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12/CSYNCI
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
Keyboard buffer
controller × 3ch
RAM
Port 6
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4/CLAMPO
P63/FTIB/CIN3/KIN3/VFBACKI
P62/FTIA/CIN2/KIN2/VSYNCI/TMIY
P61/FTOA/CIN1/KIN1/VSYNCO
P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
Port 1
WDT0, WDT1
P67/TMOX/CIN7/KIN7/IRQ7
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA0/A16/KIN8/CIN8
Port 2
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
P92/IRQ0
H8S/2000 CPU
Bus controller
NMI
STBY
RESO
Internal data bus
Clock pulse generator
EXTAL
VCCB
MD1
MD0
Internal address bus
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
RES
XTAL
Figure 1.1 (a) Internal Block Diagram of H8S/2148 Group
Rev. 4.00 Sep 27, 2006 page 7 of 1130
REJ09B0327-0400
P51/RxD0
P50/TxD0
Port A
Bus controller
Internal data bus
Internal address bus
VSS
VSS
VSS
Port 2
Port 9
Port 1
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
P37/D15/HDB7
Port 3
14-bit PWM
8-bit timer × 3ch
(TMR0, TMR1, TMRY)
Host interface
10-bit A/D
SCI × 3ch
(IrDA × 1ch)
Port B
P52/SCK0/SCL0
8-bit PWM
16-bit FRT
8-bit D/A
IIC × 2ch
(option)
P77/AN7/DA1
P76/AN6/DA0
P75/AN5
Port 7
AVref
AVCC
AVSS
P82/HIFSD
P81/CS2/GA20
P80/HA0
P86/IRQ5/SCK1/SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
Port 8
P71/AN1
P70/AN0
P43/TMCI1/HIRQ11
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
Keyboard buffer
controller × 3ch
RAM
P74/AN4
P73/AN3
P72/AN2
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12
P44/TMO1/HIRQ1
P27/A15/PW15
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P17/A7/PW7
P16/A6/PW6
WDT0, WDT1
Port 6
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
ROM
Port 4
P93/RD/IOR
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
H8S/2000 CPU
Interrupt
controller
Port 5
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
Clock pulse generator
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
RESO
VSS
VSS
VCC1
VCC2
Section 1 Overview
Figure 1.1 (b) Internal Block Diagram of H8S/2147N
Rev. 4.00 Sep 27, 2006 page 8 of 1130
REJ09B0327-0400
P36/D14/HDB6
P35/D13/HDB5
P34/D12/HDB4
P33/D11/HDB3
P32/D10/HDB2
P31/D9/HDB1
P30/D8/HDB0
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
Port A
Port 9
Interrupt
controller
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG
Port 1
WDT0, WDT1
RAM
Port 6
14-bit PWM
8-bit timer × 3ch
(TMR0, TMR1, TMRY)
SCI × 3ch
(IrDA × 1ch)
Port B
10-bit A/D
8-bit D/A
Port 5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P37/D15
P36/D14
P35/D13
P34/D12
P33/D11
P32/D10
P31/D9
P30/D8
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3
PB2/D2
PB1/D1
PB0/D0
P70/AN0
P73/AN3
P72/AN2
P71/AN1
AVSS
P77/AN7/DA1
P76/AN6/DA0
Port 7
AVref
AVCC
P82
P81
P80
P84/IRQ3/TxD1
P83
P86/IRQ5/SCK1
P85/IRQ4/RxD1
Port 8
P75/AN5
P74/AN4
P52/SCK0
P51/RxD0
P50/TxD0
Port 4
P47/PWX1
P46/PWX0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P17/A7
P16/A6
P15/A5
16-bit FRT
Port 3
P64/FTIC/CIN4/KIN4
P63/FTIB/CIN3/KIN3
P62/FTIA/CIN2/KIN2/TMIY
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
ROM
P67/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
PA7/A23/KIN15/CIN15
PA6/A22/KIN14/CIN14
PA5/A21/KIN13/CIN13
PA4/A20/KIN12/CIN12
PA3/A19/KIN11/CIN11
PA2/A18/KIN10/CIN10
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
Port 2
P97/WAIT
P96/φ/EXCL
P95/AS/IOS
P94/HWR
P93/RD
H8S/2000 CPU
Bus controller
NMI
STBY
RESO
Internal data bus
Clock pulse generator
RES
XTAL
EXTAL
MD1
MD0
Internal address bus
VCC1
VCC2 (VCL)
VSS
VSS
VSS
VSS
VSS
Section 1 Overview
Figure 1.1 (c) Internal Block Diagram of H8S/2144 Group
Rev. 4.00 Sep 27, 2006 page 9 of 1130
REJ09B0327-0400
Section 1 Overview
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
P42/TMRI0/SCK2/SDA1
P43/TMCI1/HIRQ11/HSYNCI
P44/TMO1/HIRQ1/HSYNCO
P45/TMRI1/HIRQ12/CSYNCI
P46/PWX0
P47/PWX1
PB7/D7
PB6/D6
VCC1
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
PB5/D5
PB4/D4
VSS
VSS
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
The pin arrangement of the H8S/2148 Group is shown in figure 1.2 (a), the pin arrangement of the
H8S/2147N is shown in figure 1.2 (b), and the pin arrangement of the H8S/2144 Group in figure
1.2 (c).
PW3/A3/P13
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
P41/TMO0/RxD2/IrRxD
PW2/A2/P12
77
49
P40/TMCI0/TxD2/IrTxD
PW1/A1/P11
78
48
PA0/A16/CIN8/KIN8
PW0/A0/P10
79
47
PA1/A17/CIN9/KIN9
CS4/D3/PB3
80
46
AVSS
CS3/D2/PB2
81
45
P77/AN7/DA1
HDB0/D8/P30
82
44
P76/AN6/DA0
HDB1/D9/P31
83
43
P75/AN5
HDB2/D10/P32
84
42
P74/AN4
HDB3/D11/P33
85
41
P73/AN3
HDB4/D12/P34
86
40
P72/AN2
HDB5/D13/P35
87
39
P71/AN1
HDB6/D14/P36
88
38
P70/AN0
HDB7/D15/P37
89
37
AVCC
HIRQ4/D1/PB1
90
36
AVref
HIRQ3/D0/PB0
91
35
P67/TMOX/CIN7/KIN7/IRQ7
VSS
92
34
P66/FTOB/CIN6/KIN6/IRQ6
HA0/P80
93
33
P65/FTID/CIN5/KIN5
GA20/CS2/P81
94
32
P64/FTIC/CIN4/KIN4/CLAMPO
HIFSD/P82
95
31
PA2/A18/CIN10/KIN10/PS2AC
P83
96
30
PA3/A19/CIN11/KIN11/PS2AD
TxD1/IRQ3/P84
97
29
P63/FTIB/CIN3/KIN3/VFBACKI
RxD1/IRQ4/P85
98
28
P62/FTIA/CIN2/KIN2/VSYNCI/TMIY
SCL1/SCK1/IRQ5/P86
99
27
P61/FTOA/CIN1/KIN1/VSYNCO
P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
ADTRG/IRQ2/ECS2/LWR/P90
IRQ1/P91
IRQ0/P92
IOR/ RD/P93
PS2BC/KIN12/CIN12/A20/PA4
PS2BD/KIN13/CIN13/A21/PA5
STBY
IOW/ HWR/P94
NMI
CS1/ IOS/ AS/P95
MD0
EXCL/φ/P96
MD1
SDA0/WAIT/P97
VCCB
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
8
TxD0/P50
7
RxD0/P51
6
SCL0/SCK0/P52
5
PS2CC/KIN14/CIN14/A22/PA6
4
PS2CD/KIN15/CIN15/A23/PA7
3
VCC2 (VCL)
2
EXTAL
RES
100
1
XTAL
RESO
FP-100B
TFP-100B
(Top View)
Figure 1.2 (a) Pin Arrangement of H8S/2148 Group (FP-100B, TFP-100B: Top View)
Rev. 4.00 Sep 27, 2006 page 10 of 1130
REJ09B0327-0400
P42/TMRI0/SCK2/SDA1
P43/TMCI1/HIRQ11
P44/TMO1/HIRQ1
P45/TMRI1/HIRQ12
P46/PWX0
P47/PWX1
PB7/D7
PB6/D6
VCC1
P27/A15/PW15
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
PB5/D5
PB4/D4
VSS
VSS
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
Section 1 Overview
PW3/A3/P13
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
P41/TMO0/RxD2/IrRxD
PW2/A2/P12
77
49
P40/TMCI0/TxD2/IrTxD
PW1/A1/P11
78
48
PA0/A16/CIN8/KIN8
PW0/A0/P10
79
47
PA1/A17/CIN9/KIN9
CS4/D3/PB3
80
46
AVSS
CS3/D2/PB2
81
45
P77/AN7/DA1
HDB0/D8/P30
82
44
P76/AN6/DA0
HDB1/D9/P31
83
43
P75/AN5
HDB2/D10/P32
84
42
P74/AN4
HDB3/D11/P33
85
41
P73/AN3
HDB4/D12/P34
86
40
P72/AN2
HDB5/D13/P35
87
39
P71/AN1
HDB6/D14/P36
88
38
P70/AN0
HDB7/D15/P37
89
37
AVCC
HIRQ4/D1/PB1
90
36
AVref
HIRQ3/D0/PB0
91
35
P67/CIN7/KIN7/IRQ7
VSS
92
34
P66/FTOB/CIN6/KIN6/IRQ6
HA0/P80
93
33
P65/FTID/CIN5/KIN5
GA20/CS2/P81
94
32
P64/FTIC/CIN4/KIN4
HIFSD/P82
95
31
PA2/A18/CIN10/KIN10/PS2AC
P83
96
30
PA3/A19/CIN11/KIN11/PS2AD
TxD1/IRQ3/P84
97
29
P63/FTIB/CIN3/KIN3
RxD1/IRQ4/P85
98
28
P62/FTIA/CIN2/KIN2/TMIY
SCL1/SCK1/IRQ5/P86
99
27
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
ADTRG/IRQ2/ECS2/LWR/P90
IRQ1/P91
IRQ0/P92
IOR/ RD/P93
VCC2
PS2BC/KIN12/CIN12/A20/PA4
STBY
PS2BD/KIN13/CIN13/A21/PA5
NMI
IOW/ HWR/P94
MD0
CS1/ IOS/ AS/P95
MD1
EXCL/φ/P96
VCCB
SDA0/WAIT/P97
8
VSS
7
TxD0/P50
6
RxD0/P51
5
SCL0/SCK0/P52
4
PS2CC/KIN14/CIN14/A22/PA6
3
PS2CD/KIN15/CIN15/A23/PA7
2
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
EXTAL
RES
100
1
XTAL
RESO
FP-100B
TFP-100B
(Top View)
Figure 1.2 (b) Pin Arrangement of H8S/2147N (FP-100B, TFP-100B: Top View)
Rev. 4.00 Sep 27, 2006 page 11 of 1130
REJ09B0327-0400
P42/TMRI0/SCK2
P43/TMCI1
P44/TMO1
P45/TMRI1
P46/PWX0
P47/PWX1
PB7/D7
PB6/D6
VCC1
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
PB5/D5
PB4/D4
VSS
VSS
P17/A7
P16/A6
P15/A5
P14/A4
Section 1 Overview
A3/P13
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
P41/TMO0/RxD2/IrRxD
A2/P12
77
49
P40/TMCI0/TxD2/IrTxD
A1/P11
78
48
PA0/A16/CIN8/KIN8
A0/P10
79
47
PA1/A17/CIN9/KIN9
D3/PB3
80
46
AVSS
D2/PB2
81
45
P77/AN7/DA1
D8/P30
82
44
P76/AN6/DA0
D9/P31
83
43
P75/AN5
D10/P32
84
42
P74/AN4
D11/P33
85
41
P73/AN3
D12/P34
86
40
P72/AN2
D13/P35
87
39
P71/AN1
D14/P36
88
38
P70/AN0
D15/P37
89
37
AVCC
D1/PB1
90
36
AVref
D0/PB0
91
35
P67/CIN7/KIN7/IRQ7
VSS
92
34
P66/FTOB/CIN6/KIN6/IRQ6
P80
93
33
P65/FTID/CIN5/KIN5
P81
94
32
P64/FTIC/CIN4/KIN4
P82
95
31
PA2/A18/CIN10/KIN10
P83
96
30
PA3/A19/CIN11/KIN11
TxD1/IRQ3/P84
97
29
P63/FTIB/CIN3/KIN3
RxD1/IRQ4/P85
98
28
P62/FTIA/CIN2/KIN2/TMIY
SCK1/IRQ5/P86
99
27
P61/FTOA/CIN1/KIN1
P60/FTCI/CIN0/KIN0
ADTRG/IRQ2/LWR/P90
IRQ1/P91
IRQ0/P92
RD/P93
KIN12/CIN12/A20/PA4
KIN13/CIN13/A21/PA5
STBY
HWR/P94
NMI
IOS/ AS/P95
MD0
EXCL/φ/P96
MD1
WAIT/P97
VCC1
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
8
TxD0/P50
7
RxD0/P51
6
SCK0/P52
5
KIN14/CIN14/A22/PA6
4
KIN15/CIN15/A23/PA7
3
VCC2 (VCL)
2
EXTAL
RES
100
1
XTAL
RESO
FP-100B
TFP-100B
(Top View)
Figure 1.2 (c) Pin Arrangement of H8S/2144 Group (FP-100B, TFP-100B: Top View)
Rev. 4.00 Sep 27, 2006 page 12 of 1130
REJ09B0327-0400
Section 1 Overview
1.3.2
Pin Functions in Each Operating Mode
Tables 1.2 (a), (b) and (c) show the pin functions of the H8S/2148 Group, H8S/2147N, and
H8S/2144 Group in each of the operating modes.
Table 1.2 (a) H8S/2148 Group Pin Functions in Each Operating Mode
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
1
RES
RES
RES
RES
2
XTAL
XTAL
XTAL
XTAL
3
EXTAL
EXTAL
EXTAL
EXTAL
4
VCCB
VCCB
VCCB
VCC
5
MD1
MD1
MD1
VSS
6
MD0
MD0
MD0
VSS
7
NMI
NMI
NMI
FA9
8
STBY
STBY
STBY
VCC
9
VCC2 (VCL)
VCC2 (VCL)
VCC2 (VCL)
VCC
10
PA7/CIN15/
KIN15/PS2CD
A23/PA7/CIN15/
KIN15/PS2CD
PA7/CIN15/
KIN15/PS2CD
NC
11
PA6/CIN14/
KIN14/PS2CC
A22/PA6/CIN14/
KIN14/PS2CC
PA6/CIN14/
KIN14/PS2CC
NC
12
P52/SCK0/SCL0 P52/SCK0/SCL0
P52/SCK0/SCL0
NC
13
P51/RxD0
P51/RxD0
P51/RxD0
FA17
14
P50/TxD0
P50/TxD0
P50/TxD0
NC
15
VSS
VSS
VSS
VSS
16
P97/WAIT/SDA0 P97/WAIT/SDA0
P97/SDA0
VCC
17
P96/φ/EXCL
P96/φ/EXCL
P96/φ/EXCL
NC
18
AS/IOS
AS/IOS
P95/CS1
FA16
19
HWR
HWR
P94/IOW
FA15
20
PA5/CIN13/
KIN13/PS2BD
A21/PA5/CIN13/
KIN13/PS2BD
PA5/CIN13/
KIN13/PS2BD
NC
21
PA4/CIN12/
KIN12/PS2BC
A20/PA4/CIN12/
KIN12/PS2BC
PA4/CIN12/
KIN12/PS2BC
NC
Rev. 4.00 Sep 27, 2006 page 13 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
FP-100B
TFP-100B
Expanded Modes
Single-Chip Modes
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
22
RD
RD
P93/IOR
WE
23
P92/IRQ0
P92/IRQ0
P92/IRQ0
VSS
24
P91/IRQ1
P91/IRQ1
P91/IRQ1
VCC
25
LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG
P90/IRQ2/ADTRG/
ECS2
VCC
26
P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
P60/FTCI/CIN0/
KIN0/TMIX/
HFBACKI
NC
27
P61/FTOA/CIN1/ P61/FTOA/CIN1/
KIN1/VSYNCO
KIN1/VSYNCO
P61/FTOA/CIN1/
KIN1/VSYNCO
NC
28
P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
P62/FTIA/CIN2/
KIN2/TMIY/
VSYNCI
NC
29
P63/FTIB/CIN3/
KIN3/VFBACKI
P63/FTIB/CIN3/
KIN3/VFBACKI
P63/FTIB/CIN3/
KIN3/VFBACKI
NC
30
PA3/CIN11/
KIN11/PS2AD
A19/PA3/CIN11/
KIN11/PS2AD
PA3/CIN11/
KIN11/PS2AD
NC
31
PA2/CIN10/
KIN10/PS2AC
A18/PA2/CIN10/
KIN10/PS2AC
PA2/CIN10/
KIN10/PS2AC
NC
32
P64/FTIC/CIN4/
KIN4/CLAMPO
P64/FTIC/CIN4/
KIN4/CLAMPO
P64/FTIC/CIN4/
KIN4/CLAMPO
NC
33
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
NC
34
P66/FTOB/CIN6/ P66/FTOB/CIN6/
KIN6/IRQ6
KIN6/IRQ6
P66/FTOB/CIN6/
KIN6/IRQ6
NC
35
P67/TMOX/CIN7/ P67/TMOX/CIN7/
KIN7/IRQ7
KIN7/IRQ7
P67/TMOX/CIN7/
KIN7/IRQ7
VSS
36
AVref
AVref
AVref
VCC
37
AVCC
AVCC
AVCC
VCC
38
P70/AN0
P70/AN0
P70/AN0
NC
39
P71/AN1
P71/AN1
P71/AN1
NC
40
P72/AN2
P72/AN2
P72/AN2
NC
41
P73/AN3
P73/AN3
P73/AN3
NC
Rev. 4.00 Sep 27, 2006 page 14 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
42
P74/AN4
P74/AN4
P74/AN4
NC
43
P75/AN5
P75/AN5
P75/AN5
NC
44
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
NC
45
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
NC
46
AVSS
AVSS
AVSS
VSS
47
PA1/CIN9/KIN9
A17/PA1/CIN9/
KIN9
PA1/CIN9/KIN9
NC
48
PA0/CIN8/KIN8
A16/PA0/CIN8/KIN8
PA0/CIN8/KIN8
NC
49
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
NC
50
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
NC
51
P42/TMRI0/
SCK2/SDA1
P42/TMRI0/
SCK2/SDA1
P42/TMRI0/
SCK2/SDA1
NC
52
P43/TMCI1/
HSYNCI
P43/TMCI1/
HSYNCI
P43/TMCI1/HIRQ11/
HSYNCI
NC
53
P44/TMO1/
HSYNCO
P44/TMO1/
HSYNCO
P44/TMO1/HIRQ1/
HSYNCO
NC
54
P45/TMRI1/
CSYNCI
P45/TMRI1/
CSYNCI
P45/TMRI1/HIRQ12/
CSYNCI
NC
55
P46/PWX0
P46/PWX0
P46/PWX0
NC
56
P47/PWX1
P47/PWX1
P47/PWX1
NC
57
PB7/D7
PB7/D7
PB7
NC
58
PB6/D6
PB6/D6
PB6
NC
59
VCC1
VCC1
VCC1
VCC
60
A15
A15/P27/PW15/
CBLANK
P27/PW15/
CBLANK
CE
61
A14
A14/P26/PW14
P26/PW14
FA14
62
A13
A13/P25/PW13
P25/PW13
FA13
63
A12
A12/P24/PW12
P24/PW12
FA12
64
A11
A11/P23/PW11
P23/PW11
FA11
Rev. 4.00 Sep 27, 2006 page 15 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
FP-100B
TFP-100B
Expanded Modes
Mode 1
Single-Chip Modes
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
65
A10
A10/P22/PW10
P22/PW10
FA10
66
A9
A9/P21/PW9
P21/PW9
OE
67
A8
A8/P20/PW8
P20/PW8
FA8
68
PB5/D5
PB5/D5
PB5
NC
69
PB4/D4
PB4/D4
PB4
NC
70
VSS
VSS
VSS
VSS
71
VSS
VSS
VSS
VSS
72
A7
A7/P17/PW7
P17/PW7
FA7
73
A6
A6/P16/PW6
P16/PW6
FA6
74
A5
A5/P15/PW5
P15/PW5
FA5
75
A4
A4/P14/PW4
P14/PW4
FA4
76
A3
A3/P13/PW3
P13/PW3
FA3
77
A2
A2/P12/PW2
P12/PW2
FA2
78
A1
A1/P11/PW1
P11/PW1
FA1
79
A0
A0/P10/PW0
P10/PW0
FA0
80
PB3/D3
PB3/D3
PB3/CS4
NC
81
PB2/D2
PB2/D2
PB2/CS3
NC
82
D8
D8
P30/HDB0
FO0
83
D9
D9
P31/HDB1
FO1
84
D10
D10
P32/HDB2
FO2
85
D11
D11
P33/HDB3
FO3
86
D12
D12
P34/HDB4
FO4
87
D13
D13
P35/HDB5
FO5
88
D14
D14
P36/HDB6
FO6
89
D15
D15
P37/HDB7
FO7
90
PB1/D1
PB1/D1
PB1/HIRQ4
NC
91
PB0/D0
PB0/D0
PB0/HIRQ3
NC
92
VSS
VSS
VSS
VSS
93
P80
P80
P80/HA0
NC
Rev. 4.00 Sep 27, 2006 page 16 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
FP-100B
TFP-100B
Expanded Modes
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Single-Chip Modes
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
94
P81
P81
P81/CS2/GA20
NC
95
P82
P82
P82/HIFSD
NC
96
P83
P83
P83
NC
97
P84/IRQ3/TxD1
P84/IRQ3/TxD1
P84/IRQ3/TxD1
NC
98
P85/IRQ4/RxD1
P85/IRQ4/RxD1
P85/IRQ4/RxD1
NC
99
P86/IRQ5/SCK1/ P86/IRQ5/SCK1/
SCL1
SCL1
P86/IRQ5/SCK1/
SCL1
NC
100
RESO
RESO
NC
RESO
Rev. 4.00 Sep 27, 2006 page 17 of 1130
REJ09B0327-0400
Section 1 Overview
Table 1.2 (b) H8S/2147N Pin Functions in Each Operating Mode
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
1
RES
RES
RES
RES
2
XTAL
XTAL
XTAL
XTAL
3
EXTAL
EXTAL
EXTAL
EXTAL
4
VCCB
VCCB
VCCB
VCC
5
MD1
MD1
MD1
VSS
6
MD0
MD0
MD0
VSS
7
NMI
NMI
NMI
FA9
8
STBY
STBY
STBY
VCC
9
VCC2
VCC2
VCC2
VCC
10
PA7/CIN15/
KIN15/PS2CD
A23/PA7/CIN15/
KIN15/PS2CD
PA7/CIN15/
KIN15/PS2CD
NC
11
PA6/CIN14/
KIN14/PS2CC
A22/PA6/CIN14/
KIN14/PS2CC
PA6/CIN14/
KIN14/PS2CC
NC
12
P52/SCK0/SCL0 P52/SCK0/SCL0
P52/SCK0/SCL0
NC
13
P51/RxD0
P51/RxD0
P51/RxD0
FA17
14
P50/TxD0
P50/TxD0
P50/TxD0
NC
15
VSS
VSS
VSS
VSS
16
P97/WAIT/SDA0 P97/WAIT/SDA0
P97/SDA0
VCC
17
φ/P96/EXCL
φ/P96/EXCL
P96/φ/EXCL
NC
18
AS/IOS
AS/IOS
P95/CS1
FA16
19
HWR
HWR
P94/IOW
FA15
20
PA5/CIN13/
KIN13/PS2BD
A21/PA5/CIN13/
KIN13/PS2BD
PA5/CIN13/
KIN13/PS2BD
NC
21
PA4/CIN12/
KIN12/PS2BC
A20/PA4/CIN12/
KIN12/PS2BC
PA4/CIN12/
KIN12/PS2BC
NC
22
RD
RD
P93/IOR
WE
23
P92/IRQ0
P92/IRQ0
P92/IRQ0
VSS
24
P91/IRQ1
P91/IRQ1
P91/IRQ1
VCC
Rev. 4.00 Sep 27, 2006 page 18 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
FP-100B
TFP-100B
Expanded Modes
Single-Chip Modes
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
25
LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG
P90/IRQ2/ADTRG/
ECS2
VCC
26
P60/FTCI/CIN0/
KIN0
P60/FTCI/CIN0/
KIN0
P60/FTCI/CIN0/
KIN0
NC
27
P61/FTOA/CIN1/ P61/FTOA/CIN1/
KIN1
KIN1
P61/FTOA/CIN1/
KIN1
NC
28
P62/FTIA/CIN2/
KIN2/TMIY
P62/FTIA/CIN2/
KIN2/TMIY
P62/FTIA/CIN2/
KIN2/TMIY
NC
29
P63/FTIB/CIN3/
KIN3
P63/FTIB/CIN3/
KIN3
P63/FTIB/CIN3/
KIN3
NC
30
PA3/CIN11/
KIN11/PS2AD
A19/PA3/CIN11/
KIN11/PS2AD
PA3/CIN11/
KIN11/PS2AD
NC
31
PA2/CIN10/
KIN10/PS2AC
A18/PA2/CIN10/
KIN10/PS2AC
PA2/CIN10/
KIN10/PS2AC
NC
32
P64/FTIC/CIN4/
KIN4
P64/FTIC/CIN4/
KIN4
P64/FTIC/CIN4/
KIN4
NC
33
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
NC
34
P66/FTOB/CIN6/ P66/FTOB/CIN6/
KIN6/IRQ6
KIN6/IRQ6
P66/FTOB/CIN6/
KIN6/IRQ6
NC
35
P67/CIN7/KIN7/
IRQ7
P67/CIN7/KIN7/
IRQ7
P67/CIN7/KIN7/
IRQ7
VSS
36
AVref
AVref
AVref
VCC
37
AVCC
AVCC
AVCC
VCC
38
P70/AN0
P70/AN0
P70/AN0
NC
39
P71/AN1
P71/AN1
P71/AN1
NC
40
P72/AN2
P72/AN2
P72/AN2
NC
41
P73/AN3
P73/AN3
P73/AN3
NC
42
P74/AN4
P74/AN4
P74/AN4
NC
43
P75/AN5
P75/AN5
P75/AN5
NC
44
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
NC
45
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
NC
Rev. 4.00 Sep 27, 2006 page 19 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
46
AVSS
AVSS
AVSS
VSS
47
PA1/CIN9/KIN9
A17/PA1/CIN9/
KIN9
PA1/CIN9/KIN9
NC
48
PA0/CIN8/KIN8
A16/PA0/CIN8/KIN8
PA0/CIN8/KIN8
NC
49
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
NC
50
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
NC
51
P42/TMRI0/
SCK2/SDA1
P42/TMRI0/
SCK2/SDA1
P42/TMRI0/
SCK2/SDA1
NC
52
P43/TMCI1
P43/TMCI1
P43/TMCI1/HIRQ11
NC
53
P44/TMO1
P44/TMO1
P44/TMO1/HIRQ1
NC
54
P45/TMRI1
P45/TMRI1
P45/TMRI1/HIRQ12
NC
55
P46/PWX0
P46/PWX0
P46/PWX0
NC
56
P47/PWX1
P47/PWX1
P47/PWX1
NC
57
PB7/D7
PB7/D7
PB7
NC
58
PB6/D6
PB6/D6
PB6
NC
59
VCC1
VCC1
VCC1
VCC
60
A15
A15/P27/PW15
P27/PW15
CE
61
A14
A14/P26/PW14
P26/PW14
FA14
62
A13
A13/P25/PW13
P25/PW13
FA13
63
A12
A12/P24/PW12
P24/PW12
FA12
64
A11
A11/P23/PW11
P23/PW11
FA11
65
A10
A10/P22/PW10
P22/PW10
FA10
66
A9
A9/P21/PW9
P21/PW9
OE
Flash Memory
Writer Mode
67
A8
A8/P20/PW8
P20/PW8
FA8
68
PB5/D5
PB5/D5
PB5
NC
69
PB4/D4
PB4/D4
PB4
NC
70
VSS
VSS
VSS
VSS
71
VSS
VSS
VSS
VSS
Rev. 4.00 Sep 27, 2006 page 20 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
72
A7
A7/P17/PW7
P17/PW7
FA7
73
A6
A6/P16/PW6
P16/PW6
FA6
74
A5
A5/P15/PW5
P15/PW5
FA5
75
A4
A4/P14/PW4
P14/PW4
FA4
76
A3
A3/P13/PW3
P13/PW3
FA3
77
A2
A2/P12/PW2
P12/PW2
FA2
78
A1
A1/P11/PW1
P11/PW1
FA1
79
A0
A0/P10/PW0
P10/PW0
FA0
80
PB3/D3
PB3/D3
PB3/CS4
NC
81
PB2/D2
PB2/D2
PB2/CS3
NC
82
D8
D8
P30/HDB0
FO0
83
D9
D9
P31/HDB1
FO1
84
D10
D10
P32/HDB2
FO2
85
D11
D11
P33/HDB3
FO3
86
D12
D12
P34/HDB4
FO4
87
D13
D13
P35/HDB5
FO5
88
D14
D14
P36/HDB6
FO6
89
D15
D15
P37/HDB7
FO7
90
PB1/D1
PB1/D1
PB1/HIRQ4
NC
91
PB0/D0
PB0/D0
PB0/HIRQ3
NC
92
VSS
VSS
VSS
VSS
93
P80
P80
P80/HA0
NC
94
P81
P81
P81/CS2/GA20
NC
95
P82
P82
P82/HIFSD
NC
96
P83
P83
P83
NC
97
P84/IRQ3/TxD1
P84/IRQ3/TxD1
P84/IRQ3/TxD1
NC
98
P85/IRQ4/RxD1
P85/IRQ4/RxD1
P85/IRQ4/RxD1
NC
99
P86/IRQ5/SCK1/ P86/IRQ5/SCK1/
SCL1
SCL1
P86/IRQ5/SCK1/
SCL1
NC
100
RESO
RESO
NC
RESO
Rev. 4.00 Sep 27, 2006 page 21 of 1130
REJ09B0327-0400
Section 1 Overview
Table 1.2 (c) H8S/2144 Group Pin Functions in Each Operating Mode
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
1
RES
RES
RES
RES
2
XTAL
XTAL
XTAL
XTAL
3
EXTAL
EXTAL
EXTAL
EXTAL
4
VCC1
VCC1
VCC1
VCC
5
MD1
MD1
MD1
VSS
6
MD0
MD0
MD0
VSS
7
NMI
NMI
NMI
FA9
8
STBY
STBY
STBY
VCC
9
VCC2 (VCL)
VCC2 (VCL)
VCC2 (VCL)
VCC
10
PA7/CIN15/
KIN15
A23/PA7/CIN15/
KIN15
PA7/CIN15/
KIN15
NC
11
PA6/CIN14/
KIN14
A22/PA6/CIN14/
KIN14
PA6/CIN14/
KIN14
NC
12
P52/SCK0
P52/SCK0
P52/SCK0
NC
13
P51/RxD0
P51/RxD0
P51/RxD0
FA17
14
P50/TxD0
P50/TxD0
P50/TxD0
NC
15
VSS
VSS
VSS
VSS
16
P97/WAIT
P97/WAIT
P97
VCC
17
φ/P96/EXCL
φ/P96/EXCL
P96/φ/EXCL
NC
18
AS/IOS
AS/IOS
P95
FA16
19
HWR
HWR
P94
FA15
20
PA5/CIN13/
KIN13
A21/PA5/CIN13/
KIN13
PA5/CIN13/
KIN13
NC
21
PA4/CIN12/
KIN12
A20/PA4/CIN12/
KIN12
PA4/CIN12/KIN12
NC
22
RD
RD
P93
WE
23
P92/IRQ0
P92/IRQ0
P92/IRQ0
VSS
24
P91/IRQ1
P91/IRQ1
P91/IRQ1
VCC
Rev. 4.00 Sep 27, 2006 page 22 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
FP-100B
TFP-100B
Expanded Modes
Single-Chip Modes
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
25
LWR/P90/IRQ2/
ADTRG
LWR/P90/IRQ2/
ADTRG
P90/IRQ2/ADTRG
VCC
26
P60/FTCI/CIN0/
KIN0
P60/FTCI/CIN0/
KIN0
P60/FTCI/CIN0/
KIN0
NC
27
P61/FTOA/
CIN1/KIN1
P61/FTOA/CIN1/
KIN1
P61/FTOA/CIN1/
KIN1
NC
28
P62/FTIA/CIN2/
KIN2/TMIY
P62/FTIA/CIN2/
KIN2/TMIY
P62/FTIA/CIN2/
KIN2/TMIY
NC
29
P63/FTIB/CIN3/
KIN3
P63/FTIB/CIN3/
KIN3
P63/FTIB/CIN3/
KIN3
NC
30
PA3/CIN11/
KIN11
A19/PA3/CIN11/
KIN11
PA3/CIN11/
KIN11
NC
31
PA2/CIN10/
KIN10
A18/PA2/CIN10/
KIN10
PA2/CIN10/
KIN10
NC
32
P64/FTIC/CIN4/
KIN4
P64/FTIC/CIN4/
KIN4
P64/FTIC/CIN4/
KIN4
NC
33
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
P65/FTID/CIN5/
KIN5
NC
34
P66/FTOB/CIN6/ P66/FTOB/CIN6/
KIN6/IRQ6
KIN6/IRQ6
P66/FTOB/CIN6/
KIN6/IRQ6
NC
35
P67/CIN7/KIN7/
IRQ7
P67/CIN7/KIN7/
IRQ7
P67/CIN7/KIN7/
IRQ7
VSS
36
AVref
AVref
AVref
VCC
37
AVCC
AVCC
AVCC
VCC
38
P70/AN0
P70/AN0
P70/AN0
NC
39
P71/AN1
P71/AN1
P71/AN1
NC
40
P72/AN2
P72/AN2
P72/AN2
NC
41
P73/AN3
P73/AN3
P73/AN3
NC
42
P74/AN4
P74/AN4
P74/AN4
NC
43
P75/AN5
P75/AN5
P75/AN5
NC
44
P76/AN6/DA0
P76/AN6/DA0
P76/AN6/DA0
NC
45
P77/AN7/DA1
P77/AN7/DA1
P77/AN7/DA1
NC
Rev. 4.00 Sep 27, 2006 page 23 of 1130
REJ09B0327-0400
Section 1 Overview
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
46
AVSS
AVSS
AVSS
VSS
47
PA1/CIN9/KIN9
A17/PA1/CIN9/KIN9
PA1/CIN9/KIN9
NC
48
PA0/CIN8/KIN8
A16/PA0/CIN8/KIN8
PA0/CIN8/KIN8
NC
49
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
P40/TMCI0/
TxD2/IrTxD
NC
50
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
P41/TMO0/
RxD2/IrRxD
NC
51
P42/TMRI0/
SCK2
P42/TMRI0/
SCK2
P42/TMRI0/
SCK2
NC
52
P43/TMCI1
P43/TMCI1
P43/TMCI1
NC
53
P44/TMO1
P44/TMO1
P44/TMO1
NC
54
P45/TMRI1
P45/TMRI1
P45/TMRI1
NC
55
P46/PWX0
P46/PWX0
P46/PWX0
NC
56
P47/PWX1
P47/PWX1
P47/PWX1
NC
57
PB7/D7
PB7/D7
PB7
NC
58
PB6/D6
PB6/D6
PB6
NC
59
VCC1
VCC1
VCC1
VCC
60
A15
A15/P27
P27
CE
61
A14
A14/P26
P26
FA14
62
A13
A13/P25
P25
FA13
63
A12
A12/P24
P24
FA12
64
A11
A11/P23
P23
FA11
65
A10
A10/P22
P22
FA10
66
A9
A9/P21
P21
OE
67
A8
A8/P20
P20
FA8
68
PB5/D5
PB5/D5
PB5
NC
69
PB4/D4
PB4/D4
PB4
NC
70
VSS
VSS
VSS
VSS
71
VSS
VSS
VSS
VSS
Rev. 4.00 Sep 27, 2006 page 24 of 1130
REJ09B0327-0400
Flash Memory
Writer Mode
Section 1 Overview
Pin Name
Pin No.
Expanded Modes
Single-Chip Modes
FP-100B
TFP-100B
Mode 1
Mode 2 (EXPE = 1)
Mode 3 (EXPE = 1)
Mode 2 (EXPE = 0)
Mode 3 (EXPE = 0)
Flash Memory
Writer Mode
72
A7
A7/P17
P17
FA7
73
A6
A6/P16
P16
FA6
74
A5
A5/P15
P15
FA5
75
A4
A4/P14
P14
FA4
76
A3
A3/P13
P13
FA3
77
A2
A2/P12
P12
FA2
78
A1
A1/P11
P11
FA1
79
A0
A0/P10
P10
FA0
80
PB3/D3
PB3/D3
PB3
NC
81
PB2/D2
PB2/D2
PB2
NC
82
D8
D8
P30
FO0
83
D9
D9
P31
FO1
84
D10
D10
P32
FO2
85
D11
D11
P33
FO3
86
D12
D12
P34
FO4
87
D13
D13
P35
FO5
88
D14
D14
P36
FO6
89
D15
D15
P37
FO7
90
PB1/D1
PB1/D1
PB1
NC
91
PB0/D0
PB0/D0
PB0
NC
92
VSS
VSS
VSS
VSS
93
P80
P80
P80
NC
94
P81
P81
P81
NC
95
P82
P82
P82
NC
96
P83
P83
P83
NC
97
P84/IRQ3/TxD1
P84/IRQ3/TxD1
P84/IRQ3/TxD1
NC
98
P85/IRQ4/RxD1
P85/IRQ4/RxD1
P85/IRQ4/RxD1
NC
99
P86/IRQ5/SCK1
P86/IRQ5/SCK1
P86/IRQ5/SCK1
NC
100
RESO
RESO
RESO
NC
Rev. 4.00 Sep 27, 2006 page 25 of 1130
REJ09B0327-0400
Section 1 Overview
1.3.3
Pin Functions
Table 1.3 summarizes the pin functions of this LSI.
Table 1.3
Pin Functions
Pin No.
Type
Symbol
Power
supply
VCC1
Clock
FP-100B
TFP-100B
I/O
Name and Function
Power supply: For connection to the power supply.
All VCC1 and VCC2* pins should be connected to
the system power supply.
VCC2
4 [H8S/2144 Input
Group only],
59
9*
VCL
9*
Input
Internal step-down voltage pin: A power supply
pin for the product, applicable to product lines that
have an internal step-down voltage. In the 5-V and
4-V versions, connect external capacitors to
stabilize the internal step-down voltage between
this pin and the VSS pin. Do not connect it to Vcc.
In the 3-V version, connect this pin and the VCC1
pin to the power supply for the system. For details,
See section 26, Electrical Characteristics.
VCCB
4 [H8S/2148 Input
Group and
H8S/2147N
only]
Input/output buffer power supply: Power supply
pin for the port A input/output buffer.
VSS
15, 70
71, 92
Input
Ground: All VSS pins should be connected to the
system power supply (0 V).
XTAL
2
Input
Connected to a crystal oscillator. See section 24,
Clock Pulse Generator, for typical connection
diagrams for a crystal oscillator and external clock
input.
EXTAL
3
Input
Connected to a crystal oscillator. The EXTAL pin
can also input an external clock. See section 24,
Clock Pulse Generator, for typical connection
diagrams for a crystal oscillator and external clock
input.
φ
17
Output System clock: Supplies the system clock to
external devices.
EXCL
17
Input
Rev. 4.00 Sep 27, 2006 page 26 of 1130
REJ09B0327-0400
External subclock input: Input a 32.768 kHz
external subclock.
Section 1 Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B
Operating
mode
control
MD1
MD0
5
6
I/O
Name and Function
Input
Mode pins: These pins set the operating mode.
The relation between the settings of pins MD1 and
MD0 and the operating mode is shown below.
These pins should not be changed while the MCU
is operating.
MD1
MD0
Operating
Mode
Description
0
1
Mode 1
Normal
Expanded mode with
on-chip ROM disabled
1
0
Mode 2
Advanced
Expanded mode with
on-chip ROM enabled or
single-chip mode
1
1
Mode 3
Normal
Expanded mode with
on-chip ROM enabled or
single-chip mode
System
control
Address
bus
Data bus
RES
1
Input
RESO
100
Output Reset output: Outputs reset signal to external
device.
STBY
8
Input
A23 to
A16
10, 11, 20,
21, 30, 31,
47, 48
Output Address bus (advanced): Outputs address when
16-Mbyte space is used.
A15 to
A0
60 to 67,
72 to 79
Output Address bus: These pins output an address.
D15 to
D8
89 to 82
Input/
output
Data bus (upper): Bidirectional data bus.
Used for 8-bit data and upper byte of 16-bit data.
D7 to
D0
57, 58, 68,
69, 80, 81,
90, 91
Input/
output
Data bus (lower): Bidirectional data bus.
Used for lower byte of 16-bit data.
Reset input: When this pin is driven low, the chip is
reset.
Standby: When this pin is driven low, a transition is
made to hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 27 of 1130
REJ09B0327-0400
Section 1 Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B
I/O
Name and Function
Bus control
WAIT
16
Input
Wait: Requests insertion of a wait state in the bus
cycle when accessing external 3-state address
space.
RD
22
Output Read: When this pin is low, it indicates that the
external address space is being read.
HWR
19
Output High write: When this pin is low, it indicates that
the external address space is being written to. The
upper half of the data bus is valid.
LWR
25
Output Low write: When this pin is low, it indicates that the
external address space is being written to. The
lower half of the data bus is valid.
AS/IOS
18
Output Address strobe: When this pin is low, it indicates
that address output on the address bus is valid.
NMI
7
Input
Nonmaskable interrupt: Requests a nonmaskable
interrupt.
IRQ0 to
IRQ7
23 to 25,
97 to 99,
34, 35
Input
Interrupt request 0 to 7: These pins request a
maskable interrupt.
FRT counter clock input: Input pin for an external
clock signal for the free-running counter (FRC).
Interrupt
signals
16-bit free- FTCI
running
timer (FRT) FTOA
26
Input
27
Output FRT output compare A output: The output
compare A output pin.
FTOB
34
Output FRT output compare B output: The output
compare B output pin.
FTIA
28
Input
FRT input capture A input: The input capture A
input pin.
FTIB
29
Input
FRT input capture B input: The input capture B
input pin.
FTIC
32
Input
FRT input capture C input: The input capture C
input pin.
FTID
33
Input
FRT input capture D input: The input capture D
input pin.
Rev. 4.00 Sep 27, 2006 page 28 of 1130
REJ09B0327-0400
Section 1 Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B
8-bit timer
(TMR0,
TMR1,
TMRX,
TMRY)
TMO0
TMO1
TMOX
50
53
35
Output Compare-match output: TMR0, TMR1, and TMRX
compare-match output pins.
TMCI0
TMCI1
49
52
Input
Counter external clock input: Input pins for the
external clock input to the TMR0 and TMR1
counters.
TMRI0
TMRI1
51
54
Input
Counter external reset input: TMR0 and TMR1
counter reset input pins.
TMIX
TMIY
26
28
Input
Counter external clock input and reset input:
Dual function as TMRX and TMRY counter clock
input pin and reset input pin.
PW15 to
PW0
60 to 67,
72 to 79
Output PWM timer output: PWM timer pulse output pins.
14-bit PWM PWX0
timer
PWX1
(PWMX)
55
56
Output PWMX timer output: PWM D/A pulse output pins.
Serial communication
interface
(SCI0, SCI1,
SCI2)
TxD0
TxD1
TxD2
14
97
49
Output Transmit data: Data output pins.
RxD0
RxD1
RxD2
13
98
50
Input
Receive data: Data input pins.
SCK0
SCK1
SCK2
12
99
51
Input/
output
Serial clock: Clock input/output pins.
SCI with
IrTxD
IrDA (SCI2) IrRxD
49
50
Output IrDA transmit data/receive data: Input and output
Input
pins for data encoded for IrDA use.
Keyboard
Buffer
controller
(PS2)
PS2AC
PS2BC
PS2CC
31
21
11
Input/
output
PS2 clock: Keyboard buffer controller
synchronization clock input/output pins.
PS2AD
PS2BD
PS2CD
30
20
10
Input/
output
PS2 data: Keyboard buffer controller data
input/output pins.
PWM timer
(PWM)
I/O
Name and Function
The SCK0 output type is NMOS push-pull in the
H8S/2148 Group and H8S/2147N, and is CMOS
output in the H8S/2144 Group.
Rev. 4.00 Sep 27, 2006 page 29 of 1130
REJ09B0327-0400
Section 1 Overview
Pin No.
Type
Symbol
Host
interface
(HIF)
HDB7 to
HDB0
FP-100B
TFP-100B
I/O
Name and Function
89 to 82
Input/
output
Host interface data bus: Bidirectional 8-bit bus for
accessing the host interface.
CS1,
CS2,
ECS2
CS3,
CS4
18, 94, 25
81, 80
Input
Chip select 1, 2, 3, and 4: Input pins for selecting
host interface channel 1 to 4.
IOR
22
Input
I/O read: Input pin that enables reading from the
host interface.
IOW
19
Input
I/O write: Input pin that enables writing to the host
interface.
HA0
93
Input
Command/data: Input pin that indicates whether
an access is a data access or command access.
GA20
94
Output GATE A20: A20 gate control signal output pin.
HIRQ11
HIRQ1
HIRQ12
HIRQ3
HIRQ4
52
53
54
91
90
Output Host interrupt 11, 1, 12, 3, and 4: Output pins for
interrupt requests to the host.
HIFSD
95
Input
Host interface shutdown: Control input pin used
to place host interface input/output pins in the highimpedance/cutoff state.
Keyboard
control
KIN0 to
KIN15
26 to 29,
Input
32 to 35, 48,
47, 31, 30,
21, 20, 11,
10
Keyboard input: Matrix keyboard input pins.
Normally, P10 to P17 and P20 to P27 are used as
key-scan outputs. This enables a maximum 16output × 16-input, 256-key matrix to be configured.
A/D
converter
(ADC)
AN7 to
AN0
45 to 38
Input
Analog input: A/D converter analog input pins.
CIN0 to
CIN15
26 to 29,
32 to 35,
48, 47, 31,
30, 21, 20,
11, 10
Input
Expansion A/D inputs: Expansion A/D input pins
can be connected to the A/D converter, but since
they are also used as digital input/output pins,
precision will fall.
ADTRG
25
Input
A/D conversion external trigger input: Pin for
input of an external trigger to start A/D conversion.
Rev. 4.00 Sep 27, 2006 page 30 of 1130
REJ09B0327-0400
Section 1 Overview
Pin No.
Type
Symbol
FP-100B
TFP-100B
D/A
converter
(DAC)
DA0
DA1
44
45
Output Analog output: D/A converter analog output pins.
A/D
converter
AVCC
37
Input
I/O
D/A
converter
Name and Function
Analog reference voltage: The analog power
supply pin for the A/D converter and D/A converter.
When the A/D and D/A converters are not used, this
pin should be connected to the system power
supply (+5 V or +3 V).
AVref
36
Input
Analog reference voltage: The reference power
supply pin for the A/D converter and D/A converter.
When the A/D and D/A converters are not used, this
pin should be connected to the system power
supply (+5 V or +3 V).
Timer
connection
2
I C bus
interface
(IIC)
(option)
AVSS
46
Input
Analog ground: The ground pin for the A/D
converter and D/A converter. This pin should be
connected to the system power supply (0 V).
VSYNCI,
HSYNCI,
CSYNCI,
VFBACKI,
HFBACKI
28
52
54
29
26
Input
Timer connection input: Timer connection
synchronous signal input pins.
VSYNCO,
HSYNCO,
CLAMPO,
CBLANK
27
53
32
60
Output Timer connection output: Timer connection
synchronous signal output pins.
SCL0
SCL1
12
99
Input/
output
2
2
I C clock input/output (channels 0 and 1): I C
clock I/O pins. These pins have a bus drive
function.
The SCL0 output form is NMOS open-drain
SDA0
SDA1
16
51
Input/
output
2
2
I C data input/output (channels 0 and 1): I C data
I/O pins. These pins have a bus drive function.
The SDA0 output form is NMOS open-drain.
Rev. 4.00 Sep 27, 2006 page 31 of 1130
REJ09B0327-0400
Section 1 Overview
Pin No.
Type
Symbol
I/O ports
P17 to
P10
FP-100B
TFP-100B
I/O
Name and Function
72 to 79
Input/
output
Port 1: Eight input/output pins. The data direction of
each pin can be selected in the port 1 data direction
register (P1DDR). These pins have built-in MOS
input pull-ups, and also have LED drive capability.
P27 to
P20
60 to 67
Input/
output
Port 2: Eight input/output pins. The data direction of
each pin can be selected in the port 2 data direction
register (P2DDR). These pins have built-in MOS
input pull-ups, and also have LED drive capability.
P37 to
P30
89 to 82
Input/
output
Port 3: Eight input/output pins. The data direction of
each pin can be selected in the port 3 data direction
register (P3DDR). These pins have built-in MOS
input pull-ups, and also have LED drive capability.
P47 to
P40
56 to 49
Input/
output
Port 4: Eight input/output pins. The data direction of
each pin can be selected in the port 4 data direction
register (P4DDR).
P52 to
P50
12 to 14
Input/
output
Port 5: Three input/output pins. The data direction
of each pin can be selected in the port 5 data
direction register (P5DDR). P52 is an NMOS pushpull output in the H8S/2148 Group and H8S/2147N,
and is a CMOS output in the H8S/2144 Group.
P67 to
P60
35 to 32
29 to 26
Input/
output
Port 6: Eight input/output pins. The data direction of
each pin can be selected in the port 6 data direction
register (P6DDR). These pins have built-in MOS
input pull-ups.
P77 to
P70
45 to 38
Input
Port 7: Eight input pins.
P86 to
P80
99 to 93
Input/
output
Port 8: Seven input/output pins. The data direction
of each pin can be selected in the port 8 data
direction register (P8DDR).
P97 to
P90
16 to 19
22 to 25
Input/
output
Port 9: Eight input/output pins. The data direction of
each pin (except P96) can be selected in the port 9
data direction register (P9DDR). P97 is an NMOS
push-pull output in the H8S/2148 Group and
H8S/2147N, and is a CMOS output in the H8S/2144
Group.
Rev. 4.00 Sep 27, 2006 page 32 of 1130
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Section 1 Overview
Pin No.
Type
Symbol
I/O ports
PA7 to
PA0
PB7 to
PB0
Note:
*
FP-100B
TFP-100B
I/O
Name and Function
10, 11, 20,
21, 30, 31,
47, 48
Input/
output
Port A: Eight input/output pins. The data direction
of each pin can be selected in the port A data
direction register (PADDR). These pins have built-in
MOS input pull-ups. These are the VCCB drive
pins. [H8S/2148 Group and H8S/2147N only]
57, 58, 68,
69, 80, 81,
90, 91
Input/
output
Port B: Eight input/output pins. The data direction
of each pin can be selected in the port B data
direction register (PBDDR). These pins have built-in
MOS input pull-ups.
In F-ZTAT and mask ROM versions of HD64F2148A, HD64F2147A, HD64F2144A,
HD6432148S, HD6432148SW, HD6432147S, HD6432147SW, HD6432144S,
HD6432143S pin NO.9 is VCL pin and is not VCC pin.
Rev. 4.00 Sep 27, 2006 page 33 of 1130
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Section 1 Overview
Rev. 4.00 Sep 27, 2006 page 34 of 1130
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Section 2 CPU
Section 2 CPU
2.1
Overview
The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is
ideal for realtime control.
2.1.1
Features
The H8S/2000 CPU has the following features.
• Upward-compatible with H8/300 and H8/300H CPUs
 Can execute H8/300 and H8/300H object programs
• General-register architecture
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit
registers)
• Sixty-five basic instructions
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 16-Mbyte address space
 Program: 16 Mbytes
 Data:
16 Mbytes (4 Gbytes architecturally)
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Section 2 CPU
• High-speed operation
 All frequently-used instructions execute in one or two states
 Maximum clock rate:
20 MHz
 8/16/32-bit register-register add/subtract: 50 ns
 8 × 8-bit register-register multiply:
600 ns
 16 ÷ 8-bit register-register divide:
600 ns
 16 × 16-bit register-register multiply:
1000 ns
 32 ÷ 16-bit register-register divide:
1000 ns
• Two CPU operating modes
 Normal mode
 Advanced mode
• Power-down state
 Transition to power-down state by SLEEP instruction
 CPU clock speed selection
2.1.2
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• Number of execution states
The number of execution states of the MULXU and MULXS instructions differ as follows.
Number of Execution States
Instruction
MULXU
MULXS
Mnemonic
H8S/2600
H8S/2000
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
There are also differences in the address space, EXR register functions, power-down state, etc.,
depending on the product.
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Section 2 CPU
2.1.3
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements.
• More general registers and control registers
 Eight 16-bit extended registers, and one 8-bit control register, have been added.
• Expanded address space
 Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
 Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
 The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Signed multiply and divide instructions have been added.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
2.1.4
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements.
• Additional control register
 One 8-bit control register has been added.
• Enhanced instructions
 Addressing modes of bit-manipulation instructions have been enhanced.
 Two-bit shift instructions have been added.
 Instructions for saving and restoring multiple registers have been added.
 A test and set instruction has been added.
• Higher speed
 Basic instructions execute twice as fast.
Rev. 4.00 Sep 27, 2006 page 37 of 1130
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16
Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected
by the mode pins of the microcontroller.
Normal mode
Maximum 64 kbytes for program
and data areas combined
CPU operating modes
Advanced mode
Maximum 16 Mbytes for
program and data areas
combined
Figure 2.1 CPU Operating Modes
(1) Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
Address Space: A maximum address space of 64 kbytes can be accessed.
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain
any value, even when the corresponding general register (Rn) is used as an address register. If the
general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)
or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding
extended register (En) will be affected.
Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of
effective addresses (EA) are valid.
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Section 2 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area
starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16
bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For
details of the exception vector table, see section 4, Exception Handling.
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.2 Exception Vector Table (Normal Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note
that this area is also used for the exception vector table.
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Section 2 CPU
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,
and the PC and condition-code register (CCR) are pushed onto the stack in exception handling,
they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the
stack. For details, see section 4, Exception Handling.
SP
PC
(16 bits)
SP
CCR
CCR*
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Note: * Ignored when returning.
Figure 2.3 Stack Structure in Normal Mode
(2) Advanced Mode
Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally
a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4
Gbytes for program and data areas combined).
Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as
the upper 16-bit segments of 32-bit registers or address registers.
Instruction Set: All instructions and addressing modes can be used.
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Section 2 CPU
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top
area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32
bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4).
For details of the exception vector table, see section 4, Exception Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.4 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses
an 8-bit absolute address included in the instruction code to specify a memory operand that
contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing
a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as
H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the
first part of this range is also the exception vector table.
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Section 2 CPU
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a
subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in
exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is
not pushed onto the stack. For details, see section 4, Exception Handling.
SP
Reserved
PC
(24 bits)
(a) Subroutine Branch
CCR
SP
PC
(24 bits)
(b) Exception Handling
Figure 2.5 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode.
H'0000
H'00000000
H'FFFF
Program area
H'00FFFFFF
Data area
Cannot be
used by
this LSI
H'FFFFFFFF
(a) Normal Mode
(b) Advanced Mode
Figure 2.6 Memory Map
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Section 2 CPU
2.4
Register Configuration
2.4.1
Overview
The CPU has the internal registers shown in figure 2.7. There are two types of registers: general
registers and control registers.
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
EXR* T — — — — I2 I1 I0
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
Legend:
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended control register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Note: * Does not affect operation in this LSI.
Figure 2.7 CPU Registers
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Section 2 CPU
2.4.2
General Registers
The CPU has eight 32-bit general registers. These general registers are all functionally alike and
can be used as both address registers and data registers. When a general register is used as a data
register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used
as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers.
Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
RH registers
(R0H to R7H)
ER registers
(ER0 to ER7)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.8 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the
stack.
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.9 Stack
2.4.3
Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),
and 8-bit condition-code register (CCR).
(1) Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR)
An 8-bit register. In this LSI, this register does not affect operation.
Bit 7—Trace Bit (T): This bit is reserved. In this LSI, this bit does not affect operation.
Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits are reserved. In this LSI, these bits do not
affect operation.
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Section 2 CPU
(3) Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted
regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details, refer to section 5, Interrupt Controller.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0
otherwise.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to appendix A.1, Instruction.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
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Section 2 CPU
2.4.4
Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
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Section 2 CPU
2.5
Data Formats
The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.
Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte
operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit
BCD data.
2.5.1
General Register Data Formats
Figure 2.10 shows the data formats in general registers.
Data Type
General Register
Data Format
1-bit data
RnH
7
0
7 6 5 4 3 2 1 0
Don’t care
Don’t care
7
0
7 6 5 4 3 2 1 0
4 3
7
0
Upper digit Lower digit
Don’t care
Don’t care
4 3
7
0
Upper digit Lower digit
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
RnL
RnH
RnL
RnH
7
0
Don’t care
MSB
Byte data
LSB
RnL
7
0
Don’t care
MSB
LSB
Figure 2.10 General Register Data Formats
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Section 2 CPU
Data Type
General Register
Word data
Rn
Word data
En
Data Format
15
0
MSB
15
0
MSB
Longword data
LSB
ERn
31
MSB
LSB
16 15
En
0
Rn
Legend:
ERn: General register ER
En:
General register E
Rn:
General register R
RnH: General register RH
RnL: General register RL
MSB: Most significant bit
LSB: Least significant bit
Figure 2.10 General Register Data Formats (cont)
Rev. 4.00 Sep 27, 2006 page 50 of 1130
REJ09B0327-0400
LSB
Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs but the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instruction fetches.
Data Type
Address
Data Format
7
1-bit data
Address L
Byte data
Address L MSB
Word data
7
0
6
5
4
2
1
0
LSB
Address 2M MSB
Address 2M + 1
Longword data
3
LSB
Address 2N MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2.11 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
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Section 2 CPU
2.6
Instruction Set
2.6.1
Overview
The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
BWL
5
Arithmetic
operations
Logic operations
WL
5
5
LDM* , STM*
3
3
MOVFPE* , MOVTPE*
L
ADD, SUB, CMP, NEG
BWL
B
ADDX, SUBX, DAA, DAS
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
4
TAS*
WL
B
AND, OR, XOR, NOT
BWL
19
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
8
Bit-manipulation
B
14
Branch
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc* , JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Total: 65 types
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP.
POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
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Section 2 CPU
2.6.2
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU
can use.
Table 2.2
Combinations of Instructions and Addressing Modes
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8, PC)
@(d:16, PC)
@@aa:8
—
B
BWL
—
BWL
—
—
—
—
POP, PUSH
—
—
—
—
—
—
—
—
—
—
—
—
—
LDM*3, STM*3
—
—
—
—
—
—
—
—
—
—
—
—
—
L
MOVFPE* ,
MOVTPE*1
—
—
—
—
—
—
—
B
—
—
—
—
—
—
ADD, CMP
—
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
ADDX, SUBX
B
B
—
—
—
—
—
—
—
—
—
—
—
—
ADDS, SUBS
—
L
—
—
—
—
—
—
—
—
—
—
—
—
INC, DEC
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
DAA, DAS
—
B
—
—
—
—
—
—
—
—
—
—
—
—
MULXU,
DIVXU
—
BW
—
—
—
—
—
—
—
—
—
—
—
—
MULXS,
DIVXS
—
BW
—
—
—
—
—
—
—
—
—
—
—
—
NEG
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
EXTU, EXTS
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
TAS*
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AND, OR,
XOR
NOT
BWL BWL
WL
WL
SUB
2
Logic
operations
@–ERn/@ERn+
BWL BWL BWL BWL BWL BWL
1
Arithmetic
operations
@(d:32, ERn)
MOV
@(d:16,ERn)
Data
transfer
@ERn
Instruction
#xx
Function
Rn
Addressing Modes
BWL BWL
—
BWL
—
Shift
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
Bit-manipulation
—
B
B
—
—
—
B
B
—
B
—
—
—
—
Branch
Bcc, BSR
—
—
—
—
—
—
—
—
—
JMP, JSR
—
—
—
—
—
—
—
—
—
—
—
RTS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 4.00 Sep 27, 2006 page 53 of 1130
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Section 2 CPU
Instruction
Rn
@ERn
@(d:16,ERn)
@(d:32, ERn)
@–ERn/@ERn+
@aa:8
@aa:16
@aa:24
@aa:32
@(d:8, PC)
@(d:16, PC)
@@aa:8
System
control
TRAPA
—
—
—
—
—
—
—
—
—
—
—
—
—
RTE
—
—
—
—
—
—
—
—
—
—
—
—
—
SLEEP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function
#xx
Addressing Modes
LDC
B
B
W
W
W
W
—
W
—
W
—
—
—
—
STC
—
B
W
W
W
W
—
W
—
W
—
—
—
—
ANDC, ORC,
XORC
B
—
—
—
—
—
—
—
—
—
—
—
—
—
NOP
Block data transfer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in this LSI.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
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Section 2 CPU
2.6.3
Table of Instructions Classified by Function
Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3
is defined below.
Operation Notation
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended control register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
Rd
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
¬
NOT (logical complement)
:8/:16/:24/:32
Note:
*
8-, 16-, 24-, or 32-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Instructions Classified by Function
Type
Instruction
Size*
Function
Data transfer
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a
general register and memory, or moves immediate data
to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack.
1
POP.W Rn is identical to MOV.W @SP+, Rn.
POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
PUSH.L ERn is identical to MOV.L ERn, @–SP.
3
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
3
STM*
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
LDM*
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Section 2 CPU
Type
Instruction
Size*
Function
Arithmetic
operations
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general
registers, or on immediate data and data in a general
register. (Immediate byte data cannot be subtracted
from byte data in a general register. Use the SUBX or
ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data
in two general registers, or on immediate data and data
in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2.
(Byte operands can be incremented or decremented by
1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a
32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general
registers: either 8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
1
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Section 2 CPU
Type
Instruction
Size*
Function
Arithmetic
operations
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general
registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit
remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR
bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of
data in a general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by padding with zeros on the left.
EXTS
W/L
TAS
B
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size,
or the lower 16 bits of a 32-bit register to longword size,
by extending the sign bit.
2
@ERd – 0, 1 → (<bit 7> of @ERd)*
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
1
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Section 2 CPU
Type
Instruction
Size*
Function
Logic
operations
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one’s complement (logical complement) of
general register contents.
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
A 1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
A 1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Shift
operations
1
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Type
Instruction
Size*
Function
Bitmanipulation
instructions
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory
operand to 1. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory
operand to 0. The bit number is specified by 3-bit
immediate data or the lower three bits of a general
register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory
operand. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory
operand and sets or clears the Z flag accordingly. The
bit number is specified by 3-bit immediate data or the
lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in
a general register or memory operand and stores the
result in the carry flag.
1
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general
register or memory operand and stores the result in the
carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the
result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Type
Instruction
Size*
Function
Bitmanipulation
instructions
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a
general register or memory operand and stores the
result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
1
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Type
Instruction
Size*
Function
Branch
instructions
Bcc
—
Branches to a specified address if a specified condition
is true. The branching conditions are listed below.
1
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine
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Section 2 CPU
Type
Instruction
Size*
Function
System
control
instructions
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
1
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves contents of a general register or memory or
immediate data to CCR or EXR. Although CCR and EXR
are 8-bit registers, word-size transfers are performed
between them and memory. The upper 8 bits are valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or
memory. Although CCR and EXR are 8-bit registers,
word-size transfers are performed between them and
memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with
immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate
data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with
immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
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Section 2 CPU
Type
Instruction
Size*
Function
Block data
transfer
instructions
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
1
Block transfer instruction. Transfers the number of data
bytes specified by R4L or R4 from locations starting at
the address indicated by ER5 to locations starting at the
address indicated by ER6. After the transfer, the next
instruction is executed.
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
2.6.4
Basic Instruction Formats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first four bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.12 shows examples of instruction formats.
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Section 2 CPU
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc
Figure 2.12 Instruction Formats (Examples)
2.6.5
Notes on Use of Bit-Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bitmanipulation, then write back the byte of data. Caution is therefore required when using these
instructions on a register containing write-only bits, or a port.
The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant
flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling
routine, etc.
2.7
Addressing Modes and Effective Address Calculation
2.7.1
Addressing Mode
The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of
these addressing modes. Arithmetic and logic instructions can use the register direct and
immediate modes. Data transfer instructions can use all addressing modes except program-counter
relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or
Rev. 4.00 Sep 27, 2006 page 65 of 1130
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Section 2 CPU
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.4
Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand in memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address
register contents and the sum is stored in the address register. The value added is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the register
value should be even.
• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the result becomes the address of a memory operand. The result is
also stored in the address register. The value subtracted is 1 for byte access, 2 for word access,
or 4 for longword access. For word or longword access, the register value should be even.
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32).
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.5 indicates the accessible absolute address ranges.
Table 2.5
Absolute Address Access Ranges
Absolute Address
Data address
Normal Mode
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
32 bits (@aa:32)
Program instruction
address
H'000000 to H'FFFFFF
24 bits (@aa:24)
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Section 2 CPU
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bitmanipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to
+32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should
be an even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
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Section 2 CPU
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or an instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
2.7.2
Effective Address Calculation
Table 2.6 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
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Table 2.6
Effective Address Calculation
No.
Addressing Mode and
Instruction Format
1
Register direct (Rn)
op
2
Effective Address
Calculation
Effective Address (EA)
Operand is general register
contents.
rm rn
Register indirect (@ERn)
31
0
3
24 23
0
Don’t
care
General register contents
op
31
r
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
31
0
General register contents
31
op
r
disp
31
0
0
Sign extension
4
24 23
Don’t
care
disp
Register indirect with post-increment or pre-decrement
•
Register indirect with post-increment @ERn+
31
0
op
31
24 23
0
Don’t
care
General register contents
r
1, 2, or
4
•
Register indirect with pre-decrement @–ERn
31
0
General register contents
31
op
24 23
Don’t
care
r
Operand
Size
Byte
Word
Longword
Rev. 4.00 Sep 27, 2006 page 70 of 1130
REJ09B0327-0400
Value
Added
1
2
4
1, 2, or
4
0
Section 2 CPU
No.
Addressing Mode and
Instruction Format
5
Absolute address
Effective Address
Calculation
Effective Address (EA)
@aa:8
31
op
abs
@aa:16
31
op
0
H'FFFF
24 23 16 15
Sign
extension
0
24 23
0
Don’t
care
abs
@aa:24
31
op
87
24 23
Don’t
care
Don’t
care
abs
@aa:32
op
31
abs
6
Immediate #xx:8/#xx:16/#xx:32
op
7
24 23
0
Don’t
care
Operand is immediate data.
IMM
Program-counter relative
@(d:8, PC)/@(d:16, PC)
0
23
PC contents
op
disp
23
Sign
extension
0
disp
31
24 23
0
Don’t
care
Rev. 4.00 Sep 27, 2006 page 71 of 1130
REJ09B0327-0400
Section 2 CPU
No.
Addressing Mode and
Instruction Format
8
Memory indirect @@aa:8
•
Effective Address
Calculation
Effective Address (EA)
Normal mode
op
abs
31
87
0
abs
H'000000
31
24 23
Don’t
care
16 15
0
H'00
0
15
Memory
contents
•
Advanced mode
op
abs
31
87
H'000000
31
abs
0
Memory contents
Rev. 4.00 Sep 27, 2006 page 72 of 1130
REJ09B0327-0400
0
31
24 23
Don’t
care
0
Section 2 CPU
2.8
Processing States
2.8.1
Overview
The CPU has five main processing states: the reset state, exception-handling state, program
execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the
processing states. Figure 2.15 indicates the state transitions.
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, interrupt, or trap
instruction.
Processing
states
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Sleep mode
Software standby
mode
Power-down state
CPU operation is stopped
to conserve power.*
Hardware standby
mode
Note: * The power-down state also includes a medium-speed mode, module stop mode,
sub-active mode, sub-sleep mode, and watch mode.
Figure 2.14 Processing States
Rev. 4.00 Sep 27, 2006 page 73 of 1130
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Section 2 CPU
End of bus request
Bus request
Program execution
state
End of bus
request
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
Bus
request
Bus-released state
End of
exception
handling
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Request for
exception
handling
Sleep mode
Interrupt
request
Exception-handling state
External interrupt
Software standby mode
RES = high
Reset state*1
STBY = high, RES = low
Hardware standby mode*2
Power-down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
3. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 25, Power-Down State.
Figure 2.15 State Transitions
2.8.2
Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are disabled in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 14,
Watchdog Timer (WDT).
Rev. 4.00 Sep 27, 2006 page 74 of 1130
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Section 2 CPU
2.8.3
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address
(vector) from the exception vector table and branches to that address.
Types of Exception Handling and Their Priority
Exception handling is performed for resets, interrupts, and trap instructions. Table 2.7 indicates
the types of exception handling and their priority. Trap instruction exception handling is always
accepted in the program execution state.
Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.
Table 2.7
Exception Handling Types and Priority
Priority
Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Interrupt
End of instruction
execution or end of
exception-handling
1
sequence*
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence.
Trap instruction
When TRAPA instruction
is executed
Exception handling starts when
a trap (TRAPA) instruction is
2
executed.*
Low
Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
2. Trap instruction exception handling is always accepted in the program execution state.
Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again,
reset exception handling starts. When reset exception handling starts the CPU fetches a start
address (vector) from the exception vector table and starts program execution from that address.
All interrupts, including NMI, are disabled during reset exception handling and after it ends.
Rev. 4.00 Sep 27, 2006 page 75 of 1130
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Section 2 CPU
Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2.16 shows the stack after exception handling ends.
Normal mode
SP
Advanced mode
CCR
CCR*
SP
PC
(16 bits)
CCR
PC
(24 bits)
Note: * Ignored when returning.
Figure 2.16 Stack Structure after Exception Handling (Examples)
2.8.4
Program Execution State
In this state the CPU executes program instructions in sequence.
2.8.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, all CPU internal operations are halted.
There is one other bus master in addition to the CPU: the data transfer controller (DTC).
For further details, refer to section 6, Bus Controller.
Rev. 4.00 Sep 27, 2006 page 76 of 1130
REJ09B0327-0400
Section 2 CPU
2.8.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,
software standby mode, hardware standby mode, subsleep mode, and watch mode. There are also
three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In
medium-speed mode, the CPU and other bus masters operate on a medium-speed clock. Module
stop mode permits halting of the operation of individual modules, other than the CPU. Subactive
mode, subsleep mode, and watch mode are power-down modes that use subclock input. For
details, refer to section 25, Power-Down State.
Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the low-power
control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop
immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
Software Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the PSS bit in the WDT1 timer
control/status register (TCSR) are both cleared to 0. In software standby mode, the CPU and clock
halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU
registers and on-chip RAM are retained. The I/O ports also remain in their existing states.
Hardware Standby Mode
A transition to hardware standby mode is made when the STBY pin goes low. In hardware
standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
Rev. 4.00 Sep 27, 2006 page 77 of 1130
REJ09B0327-0400
Section 2 CPU
2.9
Basic Timing
2.9.1
Overview
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge
of φ to the next is referred to as a “state.” The memory cycle or bus cycle consists of one, two, or
three states. Different methods are used to access on-chip memory, on-chip supporting modules,
and the external address space.
2.9.2
On-Chip Memory (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Figure 2.18 shows
the pin states.
Bus cycle
T1
φ
Internal address bus
Read
access
Address
Internal read signal
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.17 On-Chip Memory Access Cycle
Rev. 4.00 Sep 27, 2006 page 78 of 1130
REJ09B0327-0400
Section 2 CPU
Bus cycle
T1
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High impedance
Figure 2.18 Pin States during On-Chip Memory Access
Rev. 4.00 Sep 27, 2006 page 79 of 1130
REJ09B0327-0400
Section 2 CPU
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2.19 shows the
access timing for the on-chip supporting modules. Figure 2.20 shows the pin states.
Bus cycle
T1
T2
φ
Internal address bus
Address
Internal read signal
Read
access
Internal data bus
Read data
Internal write signal
Write
access
Internal data bus
Write data
Figure 2.19 On-Chip Supporting Module Access Cycle
Rev. 4.00 Sep 27, 2006 page 80 of 1130
REJ09B0327-0400
Section 2 CPU
Bus cycle
T1
T2
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High impedance
Figure 2.20 Pin States during On-Chip Supporting Module Access
2.9.4
External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or
three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to
section 6, Bus Controller.
Rev. 4.00 Sep 27, 2006 page 81 of 1130
REJ09B0327-0400
Section 2 CPU
2.10
Usage Note
2.10.1
TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. If the TAS
instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or
ER5 is used.
2.10.2
STM/LDM Instruction
ER7 is not used as the register that can be saved (STM)/restored (LDM) when using STM/LDM
instruction, because ER7 is the stack pointer. Two, three, or four registers can be saved/restored by
one STM/LDM instruction. The following ranges can be specified in the register list.
Two registers: ER0—ER1, ER2—ER3, or ER4—ER5
Three registers: ER0—ER2, or ER4—ER6
Four registers: ER0—ER3
The STM/LDM instruction including ER7 is not generated by the Renesas H8S and H8/300 series
C/C++compilers.
Rev. 4.00 Sep 27, 2006 page 82 of 1130
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
This LSI has three operating modes (modes 1 to 3). These modes enable selection of the CPU
operating mode and enabling/disabling of on-chip ROM, by setting the mode pins (MD1 and
MD0).
Table 3.1 lists the MCU operating modes.
Table 3.1
MCU Operating Mode Selection
MCU
Operating
Mode
MD0
CPU
Operating
Mode
MD1
Description
On-Chip
ROM
0
0
0
—
—
—
1
Normal
Expanded mode with on-chip ROM disabled
Disabled
1
0
Advanced
Expanded mode with on-chip ROM enabled
Enabled
1
2
Single-chip mode
3
1
Normal
Expanded mode with on-chip ROM enabled
Single-chip mode
The CPU’s architecture allows for 4 Gbytes of address space, but this LSI actually access a
maximum of 16 Mbytes.
Mode 1 is an externally expanded mode that allows access to external memory and peripheral
devices. With modes 2 and 3, operation begins in single-chip mode after reset release, but a
transition can be made to external expansion mode by setting the EXPE bit in MDCR.
This LSI can only be used in modes 1 to 3. These means that the mode pins must select one of
these modes. Do not changes the inputs at the mode pins during operation.
Rev. 4.00 Sep 27, 2006 page 83 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
3.1.2
Register Configuration
This LSI have a mode control register (MDCR) that indicates the inputs at the mode pins (MD1
and MD0), a system control register (SYSCR) and bus control register (BCR) that control the
operation of the MCU, and a serial/timer control register (STCR) that controls the operation of the
supporting modules. Table 3.2 summarizes these registers.
Table 3.2
MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R/W
Undetermined
H'FFC5
System control register
SYSCR
R/W
H'09
H'FFC4
Bus control register
BCR
R/W
H'D7
H'FFC6
Serial/timer control register
STCR
R/W
H'00
H'FFC3
Note:
*
Lower 16 bits of the address.
3.2
Register Descriptions
3.2.1
Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
EXPE
—
—
—
—
—
MDS1
MDS0
Initial value
—*
0
0
0
0
0
—*
—*
Read/Write
R/W*
—
—
—
—
—
R
R
Note: * Determined by pins MD1 and MD0.
MDCR is an 8-bit read-only register that indicates the operating mode setting and the current
operating mode of the MCU.
The EXPE bit is initialized in coordination with the mode pin states by a reset and in hardware
standby mode.
Rev. 4.00 Sep 27, 2006 page 84 of 1130
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Section 3 MCU Operating Modes
Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1
and cannot be modified. In modes 2 and 3, this bit has an initial value of 0, and can be read and
written.
Bit 7
EXPE
Description
0
Single chip mode is selected
1
Expanded mode is selected
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins
MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to MD1 and
MD0. MDS1 and MDS0 are read-only bits—they cannot be written to. The mode pin (MD1 and
MD0) input levels are latched into these bits when MDCR is read.
3.2.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
SYSCR is an 8-bit readable/writable register that performs selection of system pin functions, reset
source monitoring, interrupt control mode selection, NMI detected edge selection, supporting
module pin location selection, supporting module register access control, and RAM address space
control.
Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to
the description of the relevant modules (host interface, bus controller, watchdog timer, RAM,
etc.). For information on bits 5, 4, and 2, see section 5.2.1, System Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Chip Select 2 Enable (CS2E): Specifies the location of the host interface control pin
(CS2). For details, see section 18, Host Interface. The H8S/2144 Group does not incorporate a
host interface, so do not set this bit to 1 in the H8S/2144 Group.
Rev. 4.00 Sep 27, 2006 page 85 of 1130
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Section 3 MCU Operating Modes
Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode.
Bit 6
IOSE
Description
0
The AS/IOS pin functions as the address strobe pin (AS)
(Low output when accessing an external area)
The AS/IOS pin functions as the I/O strobe pin (IOS)
(Low output when accessing a specified address from H'(FF)F000 to H'(FF)FE4F)*
1
Note:
(Initial value)
*
In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version, the
address range is from H'(FF)F000 to H'(FF)F7FF.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
Description
0
A reset is generated by watchdog timer overflow
1
A reset is generated by an external reset
(Initial value)
Bit 1—Host Interface Enable (HIE): This bit controls CPU access to the host interface data
registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the
keyboard controller and MOS input pull-up control registers (KMIMR, KMPCR, and KMIMRA),
the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY,
TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR,
TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO,
TCONRS, and SEDGR).
Bit 1
HIE
Description
0
In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF,
CPU access to 8-bit timer (channel X and Y) data registers and control
registers, and timer connection control registers, is permitted
1
In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF,
CPU access to host interface data registers and control registers, and
keyboard controller and MOS input pull-up control registers, is permitted
Rev. 4.00 Sep 27, 2006 page 86 of 1130
REJ09B0327-0400
(Initial value)
Section 3 MCU Operating Modes
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
3.2.3
(Initial value)
Bus Control Register (BCR)
7
Bit
ICIS1
6
5
4
3
ICIS0 BRSTRM BRSTS1 BRSTS0
2
1
0
—
IOS1
IOS0
Initial value
1
1
0
1
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the I/O area range when the AS pin is designated for use as the I/O strobe. For details on bits 7
to 2, see section 6.2.1, Bus Control Register (BCR).
BCR is initialized to H'D7 by a reset and in hardware standby mode.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): These bits specify the addresses for which the
AS/IOS pin output goes low when IOSE = 1.
BCR
Bit 1
Bit 0
IOS1
IOS0
Description
0
0
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F03F
1
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F0FF
0
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)F3FF
1
The AS/IOS pin output goes low in accesses to addresses
H'(FF)F000 to H'(FF)FE4F*
(Initial value)
1
Note:
*
In the H8S/2148 F-ZTAT A-mask version and H8S/2147 F-ZTAT A-mask version, the
address range is from H'(FF)F000 to H'(FF)F7FF.
Rev. 4.00 Sep 27, 2006 page 87 of 1130
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Section 3 MCU Operating Modes
3.2.4
Serial Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS
IICX1
IICX0
IICE
FLSHE
—
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), an on-chip flash memory control (in F-ZTAT versions),
and also selects the TCNT input clock. For details of functions other than register access control,
see the descriptions of the relevant modules. If a module controlled by STCR is not used, do not
write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
2
Bits 7 to 5—I C Control (IICS, IICX1, IICX0): These bits control the bus buffer function of the
2
port A and the operation of the I C bus interface when the on-chip IIC option is included. For
details, see section 16.2.7, Serial/Timer Control Register (STCR).
2
2
Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data registers
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI control registers (SMR, BRR, and SCMR).
Bit 4
IICE
Description
0
Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for SCI1 control register access
(Initial value)
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for SCI2 control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for SCI0 control register access
1
Addresses H'(FF)FF88 and H'(FF)FF89, and H'(FF)FF8E and H'(FF)FF8F, are used
for IIC1 data register and control register access
Addresses H'(FF)FFA0 and H'(FF)FFA1, and H'(FF)FFA6 and H'(FF)FFA7, are used
for PWMX data register and control register access
Addresses H'(FF)FFD8 and H'(FF)FFD9, and H'(FF)FFDE and H'(FF)FFDF, are used
for IIC0 data register and control register access
Rev. 4.00 Sep 27, 2006 page 88 of 1130
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Section 3 MCU Operating Modes
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control
registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control
register (PCSR and SYSCR2).
Bit 3
FLSHE
Description
0
Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register
and supporting module control register access
(Initial value)
1
Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register
access (F-ZTAT version only)
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,
Timer Control Register (TCR).
3.3
Operating Mode Descriptions
3.3.1
Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries
bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.
3.3.2
Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.
They can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing
the ABW bit to 0 in the WSCR register makes port B a data bus.
Rev. 4.00 Sep 27, 2006 page 89 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
3.3.3
Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 functions as a data bus, and part of port 9 carries bus control signals. Clearing
the ABW bit to 0 in the WSCR register makes port B a data bus.
In this operating mode, the available amount of on-chip ROM in products with 64 kbytes or more
of ROM is limited to 56 kbytes.
3.4
Pin Functions in Each Operating Mode
The pin functions of ports 1 to 3, 9, A, and B vary depending on the operating mode. Table 3.3
shows their functions in each operating mode.
Table 3.3
Pin Functions in Each Mode
Port
Mode 1
Mode 2
Mode 3
Port 1
A
Port 2
A
P*/A
P*/A
P*/A
P*/A
Port A
P
Port 3
D
P*/D
P*/A
P*/D
P
P*/D
P*/D
P*/C
P*/D
P*/C
P*/C
P*/C
P
P*/C
Port B
Port 9
P96
P*/C
C*/P
P95 to P93
C
P*/C
P*/C
P92 to P91
P
P*/C
P
P*/C
P97
P90
Legend:
P: I/O port
A: Address bus output
D: Data bus I/O
C: Control signals, clock I/O
*: After reset
Rev. 4.00 Sep 27, 2006 page 90 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
3.5
Memory Map in Each Operating Mode
Figures 3.1 to 3.5 show memory maps for each of the operating modes.
The address space is 64 kbytes in modes 1 and 3 (normal modes), and 16 Mbytes in mode 2
(advanced mode).
The on-chip ROM capacity is 64 kbytes (H8S/2142, H8S/2147, and H8S/2147N), 96 kbytes
(H8S/2143), or 128 kbytes (H8S/2144 and H8S/2148), but only 56 kbytes are available in mode 3
(normal mode).
Do not access the reserved area and addresses of modules not supported by the product. Note that
normal operation is not guaranteed when these regions are accessed.
For details, see section 6, Bus Controller.
Rev. 4.00 Sep 27, 2006 page 91 of 1130
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Section 3 MCU Operating Modes
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'0000
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
H'0000
External address
space
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
On-chip ROM
H'DFFF
On-chip ROM
H'DFFF
External address
space
H'E080
H'E080
On-chip RAM*
On-chip RAM*
H'EFFF
H'E080
H'EFFF
H'EFFF
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
On-chip RAM
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 H8S/2148 (Except for F-ZTAT A-Mask Version) and H8S/2144 Memory Map in
Each Operating Mode
Rev. 4.00 Sep 27, 2006 page 92 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 2/EXPE = 0
(advanced single-chip mode)
H'000000
On-chip ROM
H'01FFFF
H'020000
On-chip ROM
H'01FFFF
External address
space
H'FFE080
H'FFE080
On-chip RAM*
On-chip RAM
H'FFEFFF
H'FFEFFF
External address
space
H'FFFE50
H'FFFEFF Internal I/O registers 2
On-chip RAM
H'FFFF00
(128 bytes)*
H'FFFF7F
H'FFFF80
Internal I/O registers 1
H'FFFFFF
H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O registers 2
On-chip RAM
(128 bytes)
Internal I/O registers 1
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 H8S/2148 (Except for F-ZTAT A-Mask Version) and H8S/2144 Memory Map in
Each Operating Mode (cont)
Rev. 4.00 Sep 27, 2006 page 93 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'0000
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
H'0000
External address
space
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
On-chip ROM
H'DFFF
On-chip ROM
H'DFFF
External address
space
H'E080
H'E080
On-chip RAM*
H'EFFF
H'E080
On-chip RAM*
External address
space
H'F800
Reserved area
H'FE4F
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
On-chip RAM
H'EFFF
H'EFFF
External address
space
H'F800
Reserved area
H'FE4F
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 H8S/2148 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
Rev. 4.00 Sep 27, 2006 page 94 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 2/EXPE = 0
(advanced single-chip mode)
H'000000
On-chip ROM
H'01FFFF
H'020000
On-chip ROM
H'01FFFF
External address
space
H'FFE080
H'FFE080
On-chip RAM*
H'FFEFFF
External address
space
H'FFF800
Reserved area
H'FFFE4F
H'FFFE50
H'FFFEFF Internal I/O registers 2
On-chip RAM
H'FFFF00
(128 bytes)*
H'FFFF7F
H'FFFF80
Internal I/O registers 1
H'FFFFFF
On-chip RAM
H'FFEFFF
H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O registers 2
On-chip RAM
(128 bytes)
Internal I/O registers 1
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.2 H8S/2148 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
(cont)
Rev. 4.00 Sep 27, 2006 page 95 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'0000
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
H'0000
External address
space
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
On-chip ROM
H'DFFF
On-chip ROM
H'DFFF
External address
space
H'E080
H'E080
H'E080
On-chip RAM*
On-chip RAM*
H'EFFF
H'EFFF
H'EFFF
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
On-chip RAM
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 H8S/2143 Memory Map in Each Operating Mode
Rev. 4.00 Sep 27, 2006 page 96 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 2/EXPE = 0
(advanced single-chip mode)
H'000000
On-chip ROM
H'017FFF
On-chip ROM
H'017FFF
Reserved area
H'01FFFF
H'020000
Reserved area
H'01FFFF
External address
space
H'FFE080
H'FFE080
On-chip RAM*
On-chip RAM
H'FFEFFF
H'FFEFFF
External address
space
H'FFFE50
H'FFFEFF Internal I/O registers 2
On-chip RAM
H'FFFF00
(128 bytes)*
H'FFFF7F
H'FFFF80
Internal I/O registers 1
H'FFFFFF
H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O registers 2
On-chip RAM
(128 bytes)
Internal I/O registers 1
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.3 H8S/2143 Memory Map in Each Operating Mode (cont)
Rev. 4.00 Sep 27, 2006 page 97 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'0000
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
H'0000
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
On-chip ROM
On-chip ROM
External address
space
H'DFFF
H'DFFF
External address
space
H'E080
H'E880
H'EFFF
H'E080
H'E080
Reserved area*
Reserved area*
On-chip RAM*
H'E880
H'EFFF
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
On-chip RAM*
Reserved area
H'E880
H'EFFF
On-chip RAM
External address
space
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.4 H8S/2147 (Except for F-ZTAT A-Mask Version), H8S/2147N, and H8S/2142
Memory Map in Each Operating Mode
Rev. 4.00 Sep 27, 2006 page 98 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 2/EXPE = 0
(advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
H'00FFFF
H'00FFFF
Reserved area
H'01FFFF
H'020000
Reserved area
H'01FFFF
External address
space
H'FFE080
H'FFE080
Reserved area*
H'FFE880
H'FFEFFF
On-chip RAM*
Reserved area
H'FFE880
H'FFEFFF
On-chip RAM
External address
space
H'FFFE50
H'FFFEFF Internal I/O registers 2
On-chip RAM
H'FFFF00
(128 bytes)*
H'FFFF7F
H'FFFF80
Internal I/O registers 1
H'FFFFFF
H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O registers 2
On-chip RAM
(128 bytes)
Internal I/O registers 1
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.4 H8S/2147 (Except for F-ZTAT A-Mask Version), H8S/2147N, and H8S/2142
Memory Map in Each Operating Mode (cont)
Rev. 4.00 Sep 27, 2006 page 99 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 1
(normal expanded mode
with on-chip ROM disabled)
H'0000
Mode 3/EXPE = 1
(normal expanded mode
with on-chip ROM enabled)
H'0000
Mode 3/EXPE = 0
(normal single-chip mode)
H'0000
On-chip ROM
On-chip ROM
External address
space
H'DFFF
H'DFFF
External address
space
H'E080
H'E880
H'EFFF
Reserved area*
On-chip RAM*
H'E080
H'E880
H'EFFF
External address
space
H'F800
Reserved area
H'FE4F
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Reserved area*
On-chip RAM*
H'E080
Reserved area
H'E880
H'EFFF
On-chip RAM
External address
space
H'F800
Reserved area
H'FE4F
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)*
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
H'FE50
H'FEFF Internal I/O registers 2
On-chip RAM
H'FF00
(128 bytes)
H'FF7F
H'FF80
Internal I/O registers 1
H'FFFF
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.5 H8S/2147 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
Rev. 4.00 Sep 27, 2006 page 100 of 1130
REJ09B0327-0400
Section 3 MCU Operating Modes
Mode 2/EXPE = 1
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 2/EXPE = 0
(advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
H'00FFFF
H'00FFFF
Reserved area
H'01FFFF
H'020000
H'01FFFF
External address
space
H'FFE080
Reserved area*
H'FFE880
H'FFEFFF
Reserved area
On-chip RAM*
H'FFE080
Reserved area
H'FFE880
H'FFEFFF
On-chip RAM
External address
space
H'FFF800
Reserved area
H'FFFE4F
H'FFFE50
H'FFFEFF Internal I/O registers 2
On-chip RAM
H'FFFF00
(128 bytes)*
H'FFFF7F
H'FFFF80
Internal I/O registers 1
H'FFFFFF
H'FFFE50
H'FFFEFF
H'FFFF00
H'FFFF7F
H'FFFF80
H'FFFFFF
Internal I/O registers 2
On-chip RAM
(128 bytes)
Internal I/O registers 1
Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.5 H8S/2147 F-ZTAT A-Mask Version Memory Map in Each Operating Mode
(cont)
Rev. 4.00 Sep 27, 2006 page 101 of 1130
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Section 3 MCU Operating Modes
Rev. 4.00 Sep 27, 2006 page 102 of 1130
REJ09B0327-0400
Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the
RES pin, or when the watchdog timer overflows.
1
Trace*
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1.
Interrupt
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
2
issued.*
Direct transition
Started by a direct transition resulting from execution of a
SLEEP instruction.
3
Trap instruction (TRAPA)*
Started by execution of a trap instruction (TRAPA).
Low
Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in
this LSI.) Trace exception handling is not executed after execution of an RTE
instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution state.
Rev. 4.00 Sep 27, 2006 page 103 of 1130
REJ09B0327-0400
Section 4 Exception Handling
4.1.2
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3
Exception Sources and Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Reset
Trace
Exception
sources
(Cannot be used in this LSI)
External interrupts: NMI, IRQ7 to IRQ0
Interrupts
Internal interrupts: interrupt sources in
on-chip supporting modules
Direct transition
Trap instruction
Figure 4.1 Exception Sources
Rev. 4.00 Sep 27, 2006 page 104 of 1130
REJ09B0327-0400
Section 4 Exception Handling
Table 4.2
Exception Vector Table
Vector Address*
1
Exception Source
Vector Number
Normal Mode
Advanced Mode
Reset
0
H'0000 to H'0001
H'0000 to H'0003
Reserved for system use
1
H'0002 to H'0003
H'0004 to H'0007
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
4
H'0008 to H'0009
H'0010 to H'0013
5
H'000A to H'000B
H'0014 to H'0017
6
H'000C to H'000D
H'0018 to H'001B
7
H'000E to H'000F
H'001C to H'001F
8
H'0010 to H'0011
H'0020 to H'0023
9
H'0012 to H'0013
H'0024 to H'0027
10
H'0014 to H'0015
H'0028 to H'002B
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
IRQ6
22
H'002C to H'002D
H'0058 to H'005B
IRQ7
23
H'002E to H'002F
H'005C to H'005F
24

103
H'0030 to H'0031

H'00CE to H'00CF
H'0060 to H'0063

H'019C to H'019F
Direct transition
External interrupt
NMI
Trap instruction (4 sources)
Reserved for system use
External interrupt
2
Internal interrupt*
Notes: 1. Lower 16 bits of the address.
2. For details on internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector
Table.
Rev. 4.00 Sep 27, 2006 page 105 of 1130
REJ09B0327-0400
Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers of on-chip supporting modules.
Immediately after a reset, interrupt control mode 0 is set.
Reset exception handling begins when the RES pin changes from low to high.
The MCUs can also be reset by overflow of the watchdog timer. For details, see section 14,
Watchdog Timer (WDT).
4.2.2
Reset Sequence
The MCU enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms when powering on. To
reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset,
see appendix D.1, Port States in Each Processing State.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
[1] The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
[2] The reset exception vector address is read and transferred to the PC, and program execution
starts from the address indicated by the PC.
Figures 4.2 and 4.3 show examples of the reset sequence.
Rev. 4.00 Sep 27, 2006 page 106 of 1130
REJ09B0327-0400
Section 4 Exception Handling
Fetch of
Vector Internal
first program
fetch processing instruction
φ
RES
Internal
address bus
(1)
(3)
Internal read
signal
Internal write
signal
High
Internal data
bus
(2)
(1)
(2)
(3)
(4)
(4)
Reset exception vector address ((1) = H'0000)
Start address (contents of reset exception vector address)
Start address ((3) = (2))
First program instruction
Figure 4.2 Reset Sequence (Mode 3)
Rev. 4.00 Sep 27, 2006 page 107 of 1130
REJ09B0327-0400
Section 4 Exception Handling
Vector fetch
φ
Internal
processing
Fetch of
first program
instruction
*
*
*
(1)
(3)
(5)
RES
Address bus
RD
High
HWR, LWR
(2)
D15 to D8
(1) (3)
(2) (4)
(5)
(6)
(4)
(6)
Reset exception vector address ((1) = H'0000, (3) = H'0001)
Start address (contents of reset exception vector address)
Start address ((5) = (2) (4))
First program instruction
Note: * 3 program wait states are inserted.
Figure 4.3 Reset Sequence (Mode 1)
4.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
Rev. 4.00 Sep 27, 2006 page 108 of 1130
REJ09B0327-0400
Section 4 Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by nine external sources (NMI and IRQ7 to IRQ0)
from 23 input pins (NMI, IRQ7 to IRQ0, and KIN15 to KIN0), and internal sources in the on-chip
supporting modules. Figure 4.4 shows the interrupt sources and the number of interrupts of each
type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), data
transfer controller (DTC), A/D converter (ADC), host interface (HIF), keyboard buffer controller
2
(PS2), and I C bus interface (option). Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The
interrupt controller has two interrupt control modes and can assign interrupts other than NMI and
address break to either three priority/mask levels to enable multiplexed interrupt control.
For details on interrupts, see section 5, Interrupt Controller.
External
interrupts
Interrupts
Internal
interrupts
NMI (1)
IRQ7 to IRQ0 (8)
WDT* (2)
FRT (7)
TMR (10)
SCI (12)
DTC (1)
ADC (1)
HIF (4)
PS2 (3)
IIC (3) (option)
Other (1)
Notes: Numbers in parentheses are the numbers of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at each counter overflow.
Figure 4.4 Interrupt Sources and Number of Interrupts
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Section 4 Exception Handling
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.3
Status of CCR and EXR after Trap Instruction Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
I2 to I0
T
0
1
—
—
—
1
1
1
—
—
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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Section 4 Exception Handling
4.5
Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP
CCR
CCR*
PC
(16 bits)
Interrupt control modes 0 and 1
Note: * Ignored on return.
Figure 4.5 (1) Stack Status after Exception Handling (Normal Mode)
SP
CCR
PC
(24 bits)
Interrupt control modes 0 and 1
Figure 4.5 (2) Stack Status after Exception Handling (Advanced Mode)
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Section 4 Exception Handling
4.6
Notes on Use of the Stack
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP: ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.6 shows an example of what
happens when the SP value is odd.
CCR
SP
R1L
SP
PC
PC
SP
H'FFEFFA
H'FFEFFB
H'FFEFFC
H'FFEFFD
H'FFEFFF
TRAP instruction executed MOV.B R1L, @–ER7
SP set to H'FFEFFF
Data saved above SP
Contents of CCR lost
Legend:
CCR: Condition-code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced
mode.
Figure 4.6 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
This LSI control interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Two interrupt control modes
 Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits
in the system control register (SYSCR).
• Priorities settable with ICR
 An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority
levels can be set for each module for all interrupts except NMI and address break.
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Twenty-three external interrupt pins (nine external sources)
 NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at
the NMI pin can be selected for the NMI interrupt.
 Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ7 to IRQ0
can be selected for interrupts IRQ7 to IRQ0.
 The IRQ6 interrupt is shared by the interrupt from the IRQ6 pin and eight external interrupt
inputs (KIN7 to KIN0), and the IRQ7 interrupt is shared by the interrupt from the IRQ7 pin
and eight external interrupt inputs (KIN15 to KIN8). KIN15 to KIN0 can be masked
individually by the user program.
• DTC control
 DTC activation is controlled by means of interrupts.
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Section 5 Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Interrupt
request
Vector
number
Priority
determination
I, UI
Internal interrupt
requests
SWDTEND to PS2IC
ICR
Interrupt controller
Legend:
ISCR:
IER:
ISR:
ICR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
Interrupt control register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
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CCR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Interrupt Controller Pins
Name
Symbol
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 7 to 0
IRQ7 to IRQ0 Input
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected.
Key input interrupt
requests 15 to 0
KIN15 to KIN0 Input
Maskable external interrupts: falling edge or
level sensing can be selected.
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Section 5 Interrupt Controller
5.1.4
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
System control register
SYSCR
R/W
H'09
H'FFC4
IRQ sense control register H
ISCRH
R/W
H'00
H'FEEC
IRQ sense control register L
ISCRL
R/W
H'00
H'FEED
IRQ enable register
IER
R/W
H'00
H'FFC2
IRQ status register
ISR
2
R/(W)*
H'00
Keyboard matrix interrupt mask KMIMR
register
R/W
H'BF
H'FEEB
3
H'FFF1*
Keyboard matrix interrupt mask KMIMRA
register A
R/W
H'FF
H'FFF3*
Interrupt control register A
ICRA
R/W
H'00
H'FEE8
Interrupt control register B
ICRB
R/W
H'00
H'FEE9
Interrupt control register C
ICRC
R/W
H'00
H'FEEA
Address break control register
ABRKCR
R/W
H'00
H'FEF4
Break address register A
BARA
R/W
H'00
H'FEF5
Break address register B
BARB
R/W
H'00
H'FEF6
Break address register C
BARC
R/W
H'00
H'FEF7
3
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, for flag clearing.
3. When setting KMIMR and KMIMRA, the HIE bit in SYSCR must be set to 1, and also
MSTP2 bit in MSTPCRL must be set to 0.
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Section 5 Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI, among other functions.
Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four
interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Interrupts are controlled by I bit
1
1
Interrupts are controlled by I and UI bits and ICR
0
2
Cannot be used in this LSI
1
3
Cannot be used in this LSI
1
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 2
NMIEG
Description
0
Interrupt request generated at falling edge of NMI input
1
Interrupt request generated at rising edge of NMI input
(Initial value)
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Section 5 Interrupt Controller
5.2.2
Interrupt Control Registers A to C (ICRA to ICRC)
Bit
7
6
5
4
3
2
1
0
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for
interrupts other than NMI and address break.
The correspondence between ICR settings and interrupt sources is shown in table 5.3.
The ICR registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—Interrupt Control Level (ICRn): Sets the control level for the corresponding interrupt
source.
Bit n
ICRn
Description
0
Corresponding interrupt source is control level 0 (non-priority)
1
Corresponding interrupt source is control level 1 (priority)
(Initial value)
Note: n = 7 to 0
Table 5.3
Correspondence between Interrupt Sources and ICR Settings
Bits
Register 7
6
5
4
3
2
1
ICRA
IRQ1
IRQ2
IRQ4
IRQ6
DTC
IRQ3
IRQ5
IRQ7
Watchdog Watchdog
timer 0
timer 1
—
—
8-bit
8-bit
8-bit
timer
timer
timer
channel 0 channel 1 channels
X, Y
IRQ0
ICRB
A/D
Freeconverter running
timer
ICRC
SCI
SCI
SCI
IIC
IIC
—
channel 0 channel 1 channel 2 channel 0 channel 1
(option) (option)
Rev. 4.00 Sep 27, 2006 page 118 of 1130
REJ09B0327-0400
—
0
HIF,
Keyboard
buffer
controller
—
Section 5 Interrupt Controller
5.2.3
IRQ Enable Register (IER)
Bit
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests
IRQ7 to IRQ0.
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
Description
0
IRQn interrupt disabled
1
IRQn interrupt enabled
(Initial value)
Note: n = 7 to 0
5.2.4
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
• ISCRH
Bit
15
14
13
12
11
10
9
8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• ISCRL
Bit
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 5 Interrupt Controller
ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.
ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to
IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB)
ISCRH Bits 7 to 0
ISCRL Bits 7 to 0
IRQ7SCB to
IRQ0SCB
IRQ7SCA to
IRQ0SCA
0
0
Interrupt request generated at IRQ7 to IRQ0 input low level
(Initial value)
1
Interrupt request generated at falling edge of IRQ7 to IRQ0 input
1
5.2.5
Description
0
Interrupt request generated at rising edge of IRQ7 to IRQ0 input
1
Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
IRQ Status Register (ISR)
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Bit
Note: * Only 0 can be written, to clear the flag.
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Bit n
IRQnF
Description
0
[Clearing conditions]
1
(Initial value)
•
Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
•
When interrupt exception handling is executed while low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high*
•
When IRQn interrupt exception handling is executed while falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)*
[Setting conditions]
•
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0)
•
When a falling edge occurs in IRQn input while falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
•
When a rising edge occurs in IRQn input while rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
•
When a falling or rising edge occurs in IRQn input while both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
Notes: n = 7 to 0
* When a product, in which a DTC is incorporated, is used in the following settings, the
corresponding flag bit is not automatically cleared even when exception handling, which
is a clear condition, is executed and the bit is held at 1.
(1) When DTCEA3 is set to 1 (ADI is set to an interrupt source), IRQ4F flag is not
automatically cleared.
(2) When DTCEA2 is set to 1 (ICIA is set to an interrupt source), IRQ5F flag is not
automatically cleared.
(3) When DTCEA1 is set to 1 (ICIB is set to an interrupt source), IRQ6F flag is not
automatically cleared.
(4) When DTCEA0 is set to 1 (OCIA is set to an interrupt source), IRQ7F flag is not
automatically cleared.
When activation interrupt sources of DTC and IRQ interrupts are used with the above
combinations, clear the interrupt flag by software in the interrupt handling routine of the
corresponding IRQ.
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Section 5 Interrupt Controller
5.2.6
Keyboard Matrix Interrupt Mask Register (KMIMR)
7
Bit
6
5
4
3
2
1
0
KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0
Initial value
1
0
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KMIMR is an 8-bit readable/writable register that performs mask control for the keyboard matrix
interrupt inputs (pins KIN7 to KIN0). To enable key-sense input interrupts from multiple pin
inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0.
KMIMR is initialized to H'BF by a reset and in hardware standby mode and only IRQ6 (KIN6)
input is enabled.
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control
key-sense input interrupt requests (KIN7 to KIN0).
Bits 7 to 0
KMIMR7 to
KMIMR0
Description
0
Key-sense input interrupt requests enabled
1
Key-sense input interrupt requests disabled (Initial value)*
Note:
5.2.7
*
However, the initial value of KMIMR6 is 0 because the KMIMR6 bit controls both IRQ6
interrupt request masking and key-sense input enabling.
Keyboard Matrix Interrupt Mask Register (KMIMRA)
Bit
7
6
5
4
3
2
1
0
KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KMIMRA is an 8-bit readable/writable register that performs mask control for the keyboard
matrix interrupt inputs (pins KIN15 to KIN8). To enable key-sense input interrupts from multiple
pin inputs in keyboard matrix scanning/sensing, clear the corresponding mask bits to 0.
KMIMRA is initialized to H'FF by a reset and in hardware standby mode.
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Section 5 Interrupt Controller
Bits 7 to 0—Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control
key-sense input interrupt requests (KIN15 to KIN8).
Bits 7 to 0
KMIMR15
to KMIMR8 Description
0
Key-sense input interrupt requests enabled
1
Key-sense input interrupt requests disabled (Initial value)
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0,
and registers KMIMR and KMIMRA.
KMIMR0 (initial value 1)
P60/KIN0
KMIMR5 (initial value 1)
P65/KIN5
IRQ6 internal signal
KMIMR6 (initial value 0)
P66/KIN6/IRQ6
KMIMR7 (initial value 1)
P67/KIN7/IRQ7
KMIMR8 (initial value 1)
PA0/KIN8
IRQ6E
IRQ6SC
IRQ6
interrupt
IRQ7 internal signal
KMIMR9 (initial value 1)
PA1/KIN9
KMIMR15 (initial value 1)
PA7/KIN15
Edge/level
selection
enable/disable
circuit
IRQ7E
IRQ7SC
Edge/level
selection
enable/disable
circuit
IRQ7
interrupt
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
and Registers KMIMR and KMIMRA
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Section 5 Interrupt Controller
If any of bits KMIMR15 to KMIMR8 is cleared to 0, interrupt input from the IRQ7 pin will be
ignored. When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins,
either low-level sensing or falling-edge sensing must be designated as the interrupt sense condition
for the corresponding interrupt source (IRQ6 or IRQ7).
5.2.8
Address Break Control Register (ABRKCR)
Bit
7
6
5
4
3
2
1
0
CMF
—
—
—
—
—
—
BIE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
—
R/W
ABRKCR is an 8-bit readable/writable register that performs address break control.
ABRKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Condition Match Flag (CMF): This is the address break source flag, used to indicate that
the address set by BAR has been prefetched. When the CMF flag and BIE flag are both set to 1, an
address break is requested.
Bit 7
CMF
Description
0
[Clearing condition]
When address break interrupt exception handling is executed
1
(Initial value)
[Setting condition]
When address set by BARA to BARC is prefetched while BIE = 1
Bits 6 to 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Break Interrupt Enable (BIE): Selects address break enabling or disabling.
Bit 0
BIE
Description
0
Address break disabled
1
Address break enabled
Rev. 4.00 Sep 27, 2006 page 124 of 1130
REJ09B0327-0400
(Initial value)
Section 5 Interrupt Controller
5.2.9
Break Address Registers A, B, C (BARA, BARB, BARC)
Bit
BARA
7
6
5
4
3
2
1
0
A23
A22
A21
A20
A19
A18
A17
A16
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Bit
A15
A14
A13
A12
A11
A10
A9
A8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BARB
7
6
5
4
3
2
1
0
A7
A6
A5
A4
A3
A2
A1
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Bit
BARC
BAR consists of three 8-bit readable/writable registers (BARA, BARB, and BARC), and is used to
specify the address at which an address break is to be executed.
Each of the BAR registers is initialized to H'00 by a reset and in hardware standby mode. They are
not initialized in software standby mode.
BARA Bits 7 to 0—Address 23 to 16 (A23 to A16)
BARB Bits 7 to 0—Address 15 to 8 (A15 to A8)
BARC Bits 7 to 1—Address 7 to 1 (A7 to A1)
These bits specify the address at which an address break is to be executed. BAR bits A23 to A1
are compared with internal address bus lines A23 to A1, respectively.
The address at which the first instruction byte is located should be specified as the break address.
Occurrence of the address break condition may not be recognized for other addresses.
In normal mode, no comparison is made with address lines A23 to A16.
BARC Bit 0—Reserved: This bit cannot be modified and is always read as 0.
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Section 5 Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts.
5.3.1
External Interrupts
There are nine external interrupt sources from 25 input pins (23 actual pins): NMI, IRQ7 to IRQ0,
and KIN15 to KIN0. KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the
IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore the
H8S/2148 Group or H8S/2144 Group chip from software standby mode.
NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt
control mode and the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be
used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts
Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to
IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt control level can be set with ICR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.3.
Rev. 4.00 Sep 27, 2006 page 126 of 1130
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Section 5 Interrupt Controller
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
S
Q
IRQn interrupt
request
R
IRQn input
Clear signal
Note: n: 7 to 0
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
Figure 5.4 shows the timing of IRQnF setting.
φ
IRQn
input pin
IRQnF
Figure 5.4 Timing of IRQnF Setting
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. Therefore, when a pin is used as an external interrupt input pin, clear the
corresponding DDR bit to 0 and do not use the pin as an I/O pin for another function. When the
IRQ6 pin is assigned as the IRQ6 interrupt input pin, then set the KMIMR6 bit to 0.
When the IRQ7 pin is used as the IRQ7 interrupt input pin, bits KMIMR15 to KMIMR8 must all
be set to 1. If any of these bits is cleared to 0, interrupt input from the IRQ7 pin will be ignored.
As interrupt request flags IRQ7F to IRQ0F are set when the setting condition is met, regardless of
the IER setting, only the necessary flags should be referenced.
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Section 5 Interrupt Controller
Interrupts KIN15 to KIN0
Interrupts KIN15 to KIN0 are requested by input signals at pins KIN15 to KIN 0. When any of
pins KIN15 to KIN0 are used as key-sense inputs, the corresponding KMIMR bits should be
cleared to 0 to enable those key-sense input interrupts. The remaining unused key-sense input
KMIMR bits should be set to 1 to disable those interrupts. Interrupts KIN15 to KIN8 correspond
to the IRQ7 interrupt, and interrupts KIN7 to KIN0 correspond to the IRQ6 interrupt. Interrupt
request generation pin conditions, interrupt request enabling, interrupt control level setting, and
interrupt request status indications, are all in accordance with the IRQ7 and IRQ6 interrupt
settings.
When pins KIN7 to KIN0 or KIN15 to KIN8 are used as key-sense interrupt input pins, either
low-level sensing or falling-edge sensing must be designated as the interrupt sense condition for
the corresponding interrupt source (IRQ6 or IRQ7).
5.3.2
Internal Interrupts
There are 43 sources for internal interrupts from on-chip supporting modules, plus one software
interrupt source (address break).
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set to
1, an interrupt request is issued to the interrupt controller.
• The interrupt control level can be set by means of ICR.
• The DTC can be activated by an FRT, TMR, SCI, or other interrupt request. When the DTC is
activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.
5.3.3
Interrupt Exception Vector Table
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities among modules can be set by means of ICR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
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Section 5 Interrupt Controller
Table 5.4
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Vector Address
Vector
Normal
Number Mode
Advanced
Mode
7
H'000E
H'00001C
16
H'0020
H'000040
ICRA7
IRQ1
17
H'0022
H'000044
ICRA6
IRQ2
18
H'0024
H'000048
ICRA5
IRQ3
19
H'0026
H'00004C
IRQ4
20
H'0028
H'000050
IRQ5
21
H'002A
H'000054
IRQ6, KIN7 to KIN0
22
H'002C
H'000058
IRQ7, KIN15 to KIN8
23
H'002E
H'00005C
Interrupt Source
NMI
IRQ0
External
pin
ICR
High
ICRA4
ICRA3
SWDTEND (software
activation interrupt end)
DTC
24
H'0030
H'000060
ICRA2
WOVI0 (interval timer)
Watchdog
timer 0
25
H'0032
H'000064
ICRA1
WOVI1 (interval timer)
Watchdog
timer 1
26
H'0034
H'000068
ICRA0
Address break (PC break)
—
27
H'0036
H'00006C
ADI (A/D conversion end)
A/D
28
H'0038
H'000070
Reserved
—
29
to
47
H'003A
to
H'005E
H'000074
to
H'0000BC
ICIA (input capture A)
Free-running 48
timer
49
H'0060
H'0000C0
ICIB (input capture B)
H'0062
H'0000C4
ICIC (input capture C)
50
H'0064
H'0000C8
ICID (input capture D)
51
H'0066
H'0000CC
OCIA (output compare A)
52
H'0068
H'0000D0
OCIB (output compare B)
53
H'006A
H'0000D4
FOVI (overflow)
54
H'006C
H'0000D8
Reserved
55
H'006E
H'0000DC
56
to
63
H'0070
to
H'007E
H'0000E0
to
H'0000FC
Reserved
—
Priority
ICRB7
ICRB6
Low
Rev. 4.00 Sep 27, 2006 page 129 of 1130
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Section 5 Interrupt Controller
Vector Address
Origin of
Interrupt
Source
Vector Normal
Number Mode
8-bit timer
channel 0
64
65
OVI0 (overflow)
66
H'0084
H'000108
Reserved
67
H'0086
H'00010C
68
H'0088
H'000110
69
H'008A
H'000114
OVI1 (overflow)
70
H'008C
H'000118
Reserved
71
H'008E
H'00011C
72
H'0090
H'000120
Interrupt Source
CMIA0 (compare-match A)
CMIB0 (compare-match B)
CMIA1 (compare-match A)
CMIB1 (compare-match B)
CMIAY (compare-match A)
CMIBY (compare-match B)
8-bit timer
channel 1
8-bit timer
channels
Y, X
Advanced
Mode
ICR
H'0080
H'000100
ICRB3 High
H'0082
H'000104
73
H'0092
H'000124
74
H'0094
H'000128
ICIX (input capture X)
75
H'0096
H'00012C
IBF1 (IDR1 reception completed) Host
IBF2 (IDR2 reception completed) interface
76
H'0098
H'000130
77
H'009A
H'000134
IBF3 (IDR3 reception completed)
78
H'009C
H'000138
IBF4 (IDR4 reception completed)
79
H'009E
H'00013C
80
H'00A0
H'000140
OVIY (overflow)
ERI0 (receive error 0)
RXI0 (reception completed 0)
SCI
channel 0
81
H'00A2
H'000144
TXI0 (transmit data empty 0)
82
H'00A4
H'000148
TEI0 (transmission end 0)
83
H'00A6
H'00014C
84
H'00A8
H'000150
ERI1 (receive error 1)
RXI1 (reception completed 1)
SCI
channel 1
85
H'00AA
H'000154
TXI1 (transmit data empty 1)
86
H'00AC
H'000158
TEI1 (transmission end 1)
87
H'00AE
H'00015C
88
H'00B0
H'000160
89
H'00B2
H'000164
ERI2 (receive error 2)
RXI2 (reception completed 2)
SCI
channel 2
TXI2 (transmit data empty 2)
90
H'00B4
H'000168
TEI2 (transmission end 2)
91
H'00B6
H'00016C
IICI0 (1-byte transmission/
reception completed)
IIC channel 0 92
(option)
H'00B8
H'000170
93
H'00BA
H'000174
DDCSWI (format switch)
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Priority
ICRB2
ICRB1
ICRB0
ICRC7
ICRC6
ICRC5
ICRC4
Low
Section 5 Interrupt Controller
Vector Address
Interrupt Source
Origin of
Interrupt
Source
IICI1 (1-byte transmission/
reception completed)
IIC channel 1 94
(option)
Reserved
PS2IA (reception completed A)
PS2IB (reception completed B)
PS2IC (reception completed C)
Keyboard
buffer
controller
(PS2)
Reserved
Reserved
—
Vector Normal
Number Mode
Advanced
Mode
ICR
H'00BC
H'000178
ICRC3 High
95
H'00BE
H'00017C
96
H'00C0
H'000180
97
H'00C2
H'000184
98
H'00C4
H'000188
99
H'00C6
H'00018C
100
to
103
H'00C8
to
H'00CE
H'000190
to
H'00019C
Priority
ICRB0
Low
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Section 5 Interrupt Controller
5.4
Address Breaks
5.4.1
Features
With this LSI, it is possible to identify the prefetch of a specific address by the CPU and generate
an address break interrupt, using the ABRKCR and BAR registers. When an address break
interrupt is generated, address break interrupt exception handling is executed.
This function can be used to detect the beginning of execution of a bug location in the program,
and branch to a correction routine.
5.4.2
Block Diagram
A block diagram of the address break function is shown in figure 5.5.
BAR
Comparator
ABRKCR
Match
signal
Control logic
Address break
interrupt request
Internal address
Prefetch signal
(internal signal)
Figure 5.5 Block Diagram of Address Break Function
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Section 5 Interrupt Controller
5.4.3
Operation
ABRKCR and BAR settings can be made so that an address break interrupt is generated when the
CPU prefetches the address set in BAR. This address break function issues an interrupt request to
the interrupt controller when the address is prefetched, and the interrupt controller determines the
interrupt priority. When the interrupt is accepted, interrupt exception handling is started on
completion of the currently executing instruction. With an address break interrupt, interrupt mask
control by the I and UI bits in the CPU’s CCR is ineffective.
The register settings when the address break function is used are as follows.
1. Set the break address in bits A23 to A1 in BAR.
2. Set the BIE bit in ABRKCR to 1 to enable address breaks. An address break will not be
requested if the BIE bit is cleared to 0.
When the setting condition occurs, the CMF flag in ABRKCR is set to 1 and an interrupt is
requested. If necessary, the source should be identified in the interrupt handling routine.
5.4.4
Usage Notes
• With the address break function, the address at which the first instruction byte is located
should be specified as the break address. Occurrence of the address break condition may not be
recognized for other addresses.
• In normal mode, no comparison is made with address lines A23 to A16.
• If a branch instruction (Bcc, BSR), jump instruction (JMP, JSR), RTS instruction, or RTE
instruction is located immediately before the address set in BAR, execution of this instruction
will output a prefetch signal for that address, and an address break may be requested. This can
be prevented by not making a break address setting for an address immediately following one
of these instructions, or by determining within the interrupt handling routine whether interrupt
handling was initiated by a genuine condition occurrence.
• As an address break interrupt is generated by a combination of the internal prefetch signal and
address, the timing of the start of interrupt exception handling depends on the content and
execution cycle of the instruction at the set address and the preceding instruction. Figure 5.6
shows some address timing examples.
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Section 5 Interrupt Controller
• Program area in on-chip memory, 1-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch
operation
Vector
fetch
Stack save
Internal Instruction
operation
fetch
φ
Address bus
H'0310
H'0312
H'0314
H'0316
H'0318
SP-2
SP-4
H'0036
Interrupt exception handling
NOP
NOP
NOP
execution execution execution
Break request
signal
H'0310
H'0312
H'0314
H'0316
NOP
NOP
NOP
NOP
Breakpoint
NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
• Program area in on-chip memory, 2-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch
operation
Vector
fetch
Stack save
Internal Instruction
operation
fetch
φ
Address bus
H'0310
H'0312
H'0314
NOP
execution
H'0316
H'0318
SP-2
SP-4
H'0036
Interrupt exception handling
MOV.W
execution
Break request
signal
H'0310
H'0312
H'0316
H'0318
NOP
MOV.W #xx:16,Rd
NOP
NOP
Breakpoint
MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
• Program area in external memory (2-state access, 16-bit-bus access),
1-state execution instruction at specified break address
Instruction
fetch
Instruction
fetch
H'0310
H'0312
Instruction
fetch
Internal
operation
Stack save
Vector
fetch
Internal
operation
φ
Address bus
H'0314
SP-2
SP-4
H'0036
Interrupt exception handling
NOP
execution
Break request
signal
H'0310
H'0312
H'0314
H'0316
NOP
NOP
NOP
NOP
Breakpoint
NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
Figure 5.6 Examples of Address Break Timing
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Section 5 Interrupt Controller
5.5
Interrupt Operation
5.5.1
Interrupt Control Modes and Interrupt Operation
Interrupt operations in this LSI differ depending on the interrupt control mode.
NMI and address break interrupts are accepted at all times except in the reset state and the
hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an
enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding
interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the
interrupt controller.
Table 5.5 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated
by the I and UI bits in the CPU’s CCR.
Table 5.5
Interrupt Control Modes
SYSCR
Interrupt
Priority Setting
Control Mode INTM1 INTM0 Register
Interrupt
Mask Bits Description
0
I
0
0
ICR
Interrupt mask control is
performed by the I bit
Priority can be set with ICR
1
1
ICR
I, UI
3-level interrupt mask control
is performed by the I and UI
bits
Priority can be set with ICR
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Section 5 Interrupt Controller
Figure 5.7 shows a block diagram of the priority decision circuit.
I
UI
ICR
Interrupt
source
Interrupt
acceptance control
and 3-level mask
control
Default priority
determination
Vector
number
Interrupt control modes
0 and 1
Figure 5.7 Block Diagram of Interrupt Control Operation
Interrupt Acceptance Control and 3-Level Control
In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is
performed by means of the I and UI bits in CCR, and ICR (control level).
Table 5.6 shows the interrupts selected in each interrupt control mode.
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Section 5 Interrupt Controller
Table 5.6
Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode
I
UI
Selected Interrupts
0
0
*
All interrupts (control level 1 has priority)
1
*
NMI and address break interrupts
0
*
All interrupts (control level 1 has priority)
1
0
NMI, address break and control level 1
interrupts
1
NMI, and address break interrupts
1
Legend:
*: Don’t care
Default Priority Determination
The priority is determined for the selected interrupt, and a vector number is generated.
If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.7 shows operations and control signal functions in each interrupt control mode.
Table 5.7
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control
3-Level Control
Setting
Interrupt
Control Mode
INTM1
INTM0
0
0
0
1
0
1
Default Priority
Determination
T
(Trace)
I
UI
ICR
O
IM
—
PR
O
—
O
IM
IM
PR
O
—
Legend:
O: Interrupt operation control performed
IM: Used as interrupt mask bit
PR: Sets priority
—: Not used
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Section 5 Interrupt Controller
5.5.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR, and ICR. Interrupts are enabled when the I bit is cleared to
0, and disabled when set to 1. Control level 1 interrupt sources have higher priority.
Figure 5.8 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only NMI and address break interrupt are accepted, and other interrupt requests
are held pending.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address break.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt generated?
Yes
Yes
NMI?
No
No
Control level 1
interrupt?
Hold pending
Yes
No
No
IRQ0?
Yes
IRQ0?
No
Yes
IRQ1?
Yes
No
IRQ1?
Yes
PS2IC?
PS2IC?
Yes
Yes
No
I = 0?
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.8 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.5.3
Interrupt Control Mode 1
Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by means of the I and UI bits in the CPU’s CCR, and ICR.
• Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when
set to 1.
• Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and
disabled when both the I bit and the UI bit are set to 1.
For example, if the interrupt enable bit for an interrupt request is set to 1, and H'20, H'00, and H'00
are set in ICRA, ICRB, and ICRC, respectively, (i.e. IRQ2 and IRQ3 interrupts are set to control
level 1 and other interrupts to control level 0), the situation is as follows:
• When I = 0, all interrupts are enabled
(Priority order: NMI > IRQ2 > IRQ3 > address break > IRQ0 > IRQ1 ...)
• When I = 1 and UI = 0, only NMI, IRQ2, IRQ3 and address break interrupts are enabled
• When I = 1 and UI = 1, only NMI and address break interrupts are enabled
Figure 5.9 shows the state transitions in these cases.
I←0
All interrupts enabled
Only NMI, IRQ2, IRQ3,
and address break
interrupts enabled
I ← 1, UI ← 0
I←0
UI ← 0
Exception handling execution
or UI ← 1
Exception handling execution
or I ← 1, UI ← 1
Only NMI interrupts and
address break enabled
Figure 5.9 Example of State Transitions in Interrupt Control Mode 1
Rev. 4.00 Sep 27, 2006 page 140 of 1130
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Section 5 Interrupt Controller
Figure 5.10 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.4 is selected.
3. The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only an NMI and address break interrupts are accepted, and other interrupt
requests are held pending.
An interrupt request set to interrupt control level 1 has priority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only an NMI and address break interrupts are
accepted, and other interrupt requests are held pending.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I and UI bits in CCR are set to 1. This disables all interrupts except NMI and address
break.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt generated?
Yes
Yes
NMI?
No
No
Control level 1
interrupt?
Hold pending
Yes
IRQ0?
Yes
No
No
IRQ0?
No
Yes
IRQ1?
No
IRQ1?
Yes
Yes
PS2IC?
PS2IC?
Yes
Yes
No
I = 0?
Yes
UI = 0?
I=0
No
No
Yes
Yes
Save PC and CCR
I ← 1, UI ← 1
Read vector address
Branch to interrupt handling routine
Figure 5.10 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 1
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Section 5 Interrupt Controller
5.5.4
Interrupt Exception Handling Sequence
Figure 5.11 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Rev. 4.00 Sep 27, 2006 page 143 of 1130
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Rev. 4.00 Sep 27, 2006 page 144 of 1130
REJ09B0327-0400
Figure 5.11 Interrupt Exception Handling
(1)
(2)
(4)
(3)
Instruction
prefetch
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination
Wait for end of instruction
Interrupt
acceptance
(5)
(7)
(8)
(9)
(10)
Vector fetch
(12)
(11)
Internal
operation
(14)
(13)
Interrupt handling
routine instruction
prefetch
(6) (8)
Saved PC and saved CCR
(9) (11) Vector address
(10) (12) Interrupt handling routine start address (vector
address contents)
(13)
Interrupt handling routine start address ((13) = (10) (12))
(14)
First instruction of interrupt handling routine
(6)
Stack
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.5.5
Interrupt Response Times
This LSI are capable of fast word access to on-chip memory, and high-speed processing can be
achieved by providing the program area in on-chip ROM and the stack area in on-chip RAM.
Table 5.8 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The symbols used in table
5.8 are explained in table 5.9.
Table 5.8
Interrupt Response Times
Number of States
No.
Item
Normal Mode
Advanced Mode
1
1
Interrupt priority determination*
3
3
2
Number of wait states until executing
2
instruction ends*
1 to 19+2·SI
1 to 19+2·SI
3
PC, CCR stack save
2·SK
2·SK
4
Vector fetch
SI
2·SI
5
3
Instruction fetch*
2·SI
2·SI
6
Internal processing*
2
2
11 to 31
12 to 32
4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
Table 5.9
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Number of States in Interrupt Handling Routine Execution
Object of Access
External Device
8-Bit Bus
Instruction fetch
16-Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
SI
1
4
6+2m
2
3+m
Branch address read
SJ
Stack manipulation
SK
Legend:
m: Number of wait states in an external device access
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Section 5 Interrupt Controller
5.6
Usage Notes
5.6.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.12 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0.
TCR write cycle by CPU
CMIA exception handling
φ
Internal
address bus
TCR address
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.12 Contention between Interrupt Generation and Disabling
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Section 5 Interrupt Controller
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
5.6.2
Instructions That Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts except NMI are disabled and the next instruction is always
executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.6.3
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the
following coding should be used.
L1:
EEPMOV.W
MOV.W
R4,R4
BNE
L1
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Section 5 Interrupt Controller
5.7
DTC Activation by Interrupt
5.7.1
Overview
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DTC
• Both of the above
For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer
Controller (DTC).
5.7.2
Block Diagram
Figure 5.13 shows a block diagram of the DTC and interrupt controller.
Interrupt
request
IRQ
interrupt
On-chip
supporting
module
Interrupt source
clear signal
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC
Clear signal
DTVECR
SWDTE
clear signal
Interrupt controller
Determination of
priority
Figure 5.13 Interrupt Control for DTC
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CPU interrupt
request vector
number
CPU
I, UI
Section 5 Interrupt Controller
5.7.3
Operation
The interrupt controller has three main functions in DTC control.
Selection of Interrupt Source: It is possible to select DTC activation request or CPU interrupt
request with the DTCE bit of DTCERA to DTCERE in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC performs the specified number of data transfers and the transfer counter reaches 0,
following the DTC data transfer the DTCE bit is cleared to 0 and an interrupt request is sent to the
CPU.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table,
for the respective priorities.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.10 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB
in the DTC.
Table 5.10 Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Source Selection/Clearing Control
DTCE
DISEL
DTC
CPU
0
*
×
∆
1
0
∆
×
1
∆
Legend:
∆: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
×: The relevant bit cannot be used.
*: Don’t care
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Section 5 Interrupt Controller
Usage Note
SCI, IIC, and A/D converter interrupt sources are cleared when the DTC reads or writes to the
prescribed register, and are not dependent upon the DISEL bit.
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Section 6 Bus Controller
Section 6 Bus Controller
6.1
Overview
This LSI have a built-in bus controller (BSC) that allows external address space bus specifications,
such as bus width and number of access states, to be set.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters: the CPU and data transfer controller (DTC).
6.1.1
Features
The features of the bus controller are listed below.
• Basic bus interface
 2-state access or 3-state access can be selected
 Program wait states can be inserted
• Burst ROM interface
 External space can be designated as ROM interface space
 1-state or 2-state burst access can be selected
• Idle cycle insertion
 An idle cycle can be inserted when an external write cycle immediately follows an external
read cycle
• Bus arbitration function
 Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
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Section 6 Bus Controller
6.1.2
Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
External bus control signals
Internal
control signals
Bus controller
Bus mode signal
WSCR
BCR
WAIT
Internal
data bus
Wait controller
CPU bus request signal
DTC bus request signal
Bus arbiter
CPU bus acknowledge signal
DTC bus acknowledge signal
Figure 6.1 Block Diagram of Bus Controller
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Section 6 Bus Controller
6.1.3
Pin Configuration
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Bus Controller Pins
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that address output on
address bus is enabled (when IOSE bit is 0)
I/O select
IOS
Output
I/O select signal (when IOSE bit is 1)
Read
RD
Output
Strobe signal indicating that external space is
being read
High write
HWR
Output
Strobe signal indicating that external space is
being written to, and that the upper data bus
(D15 to D8) is enabled
Low write
LWR
Output
Strobe signal indicating that external space is
being written to, and that the lower data bus
(D7 to D0) is enabled
Wait
WAIT
Input
Wait request signal when external 3-state
access space is accessed
6.1.4
Register Configuration
Table 6.2 summarizes the registers of the bus controller.
Table 6.2
Bus Controller Registers
Name
Abbreviation
R/W
Initial Value
Address*
Bus control register
BCR
R/W
H'D7
H'FFC6
Wait state control register
WSCR
R/W
H'33
H'FFC7
Note:
*
Lower 16 bits of the address.
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Section 6 Bus Controller
6.2
Register Descriptions
6.2.1
Bus Control Register (BCR)
Bit
7
6
5
4
3
2
1
0
ICIS1
ICIS0
—
IOS1
IOS0
Initial value
1
1
0
1
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRSTRM BRSTS1 BRSTS0
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the extent of the I/O area when the I/O strobe function has been selected for the AS pin.
BCR is initialized to H'D7 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit.
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0
Description
0
Idle cycle not inserted in case of successive external read and external write cycles
1
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst
ROM interface space. The selection applies to the entire external space.
Bit 5
BRSTRM
Description
0
Basic bus interface
1
Burst ROM interface
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(Initial value)
Section 6 Bus Controller
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
Description
0
Burst cycle comprises 1 state
1
Burst cycle comprises 2 states
(Initial value)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
Description
0
Max. 4 words in burst access
1
Max. 8 words in burst access
(Initial value)
Bit 2—Reserved: Do not write 0 to this bit.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.
6.2.2
Wait State Control Register (WSCR)
Bit
7
6
5
4
3
2
1
0
RAMS
RAM0
ABW
AST
WMS1
WMS0
WC1
WC0
Initial value
0
0
1
1
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access
states, wait mode, and number of wait states for external memory space. The on-chip memory and
internal I/O register bus width and number of access states are fixed, irrespective of the WSCR
settings.
WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Section 6 Bus Controller
Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits. Always write
0 when writing to these bits in the A-mask version.
Bit 5—Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access
space or 16-bit access space.
Bit 5
ABW
Description
0
External memory space is designated as 16-bit access space
1
External memory space is designated as 8-bit access space
(Initial value)
Bit 4—Access State Control (AST): Specifies whether the external memory space is 2-state
access space or 3-state access space, and simultaneously enables or disables wait state insertion.
Bit 4
AST
Description
0
External memory space is designated as 2-state access space
Wait state insertion in external memory space accesses is disabled
1
External memory space is designated as 3-state access space
Wait state insertion in external memory space accesses is enabled
(Initial value)
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0): These bits select the wait mode
when external memory space is accessed while the AST bit is set to 1.
Bit 3
Bit 2
WMS1
WMS0
Description
0
0
Program wait mode
1
Wait-disabled mode
0
Pin wait mode
1
Pin auto-wait mode
1
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(Initial value)
Section 6 Bus Controller
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): These bits select the number of program wait
states when external memory space is accessed while the AST bit is set to 1.
Bit 1
Bit 0
WC1
WC0
Description
0
0
No program wait states are inserted
1
1 program wait state is inserted in external memory space accesses
0
2 program wait states are inserted in external memory space accesses
1
3 program wait states are inserted in external memory space accesses
(Initial value)
1
6.3
Overview of Bus Control
6.3.1
Bus Specifications
The external space bus specifications consist of three elements: bus width, number of access
states, and wait mode and number of program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are
fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with the ABW bit.
Number of Access States: Two or three access states can be selected with the AST bit.
When 2-state access space is designated, wait insertion is disabled. The number of access states on
the burst ROM interface is determined without regard to the AST bit setting.
Wait Mode and Number of Program Wait States: When 3-state access space is designated by
the AST bit, the wait mode and the number of program wait states to be inserted automatically is
selected with WMS1, WMS0, WC1, and WC0. From 0 to 3 program wait states can be selected.
Table 6.3 shows the bus specifications for each basic bus interface area.
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Section 6 Bus Controller
Table 6.3
Bus Specifications for Each Area (Basic Bus Interface)
Bus Specifications (Basic Bus Interface)
ABW
AST
WMS1 WMS0 WC1
WC0
Bus Width
Access
States
Program
Wait States
0
0
—
—
—
—
16
2
0
1
0
1
—
—
16
3
0
—*
—*
0
0
3
0
1
1
0
—
—
1
0
1
—*
—*
—
6.3.2
*
1
0
2
1
3
—
8
—
—
8
0
0
1
Note:
1
2
0
3
0
3
0
1
1
0
2
1
3
Except when WMS1 = 0 and WMS0 = 1
Advanced Mode
The initial state of the external space is basic bus interface, three-state access space. In ROMenabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O
registers is external space. The on-chip RAM is enabled when the RAME bit in the system control
register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and
the corresponding space becomes external space.
6.3.3
Normal Mode
The initial state of the external memory space is basic bus interface, three-state access space. In
ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is
external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip
RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME
bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the onchip RAM is disabled and the corresponding space becomes external space.
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Section 6 Bus Controller
6.3.4
I/O Select Signal
In this LSI, an I/O select signal (IOS) can be output, with the signal output going low when the
designated external space is accessed.
Figure 6.2 shows an example of IOS signal output timing.
Bus cycle
T1
T2
T3
φ
Address bus
External address in IOS set range
IOS
Figure 6.2 IOS Signal Output Timing
Enabling or disabling of IOS signal output is controlled by the setting of the IOSE bit in SYSCR.
In expanded mode, this pin operates as the AS output pin after a reset, and therefore the IOSE bit
in SYSCR must be set to 1 in order to use this pin as the IOS signal output. See section 8, I/O
Ports, for details.
The range of addresses for which the IOS signal is output can be set with bits IOS1 and IOS0 in
BCR. The IOS signal address ranges are shown in table 6.4.
Table 6.4
IOS Signal Output Range Settings
IOS1
IOS0
IOS Signal Output Range
0
0
H'(FF)F000 to H'(FF)F03F
1
H'(FF)F000 to H'(FF)F0FF
0
H'(FF)F000 to H'(FF)F3FF
1
H'(FF)F000 to H'(FF)FE4F*
1
Note:
*
(Initial value)
In the H8S/2148 and H8S/2147 F-ZTAT A-mask version, the address range is from
H'(FF)F000 to H'(FF)F7FF.
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Section 6 Bus Controller
6.4
Basic Bus Interface
6.4.1
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with the ABW bit, the AST bit, and the WMS1, WMS0,
WC1, and WC0 bits (see table 6.3).
6.4.2
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
Upper data bus
Lower data bus
D15
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
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Section 6 Bus Controller
16-Bit Access Space
Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The
amount of data that can be accessed at one time is one byte or one word, and a longword access is
executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Lower data bus
Upper data bus
D15
D8 D7
D0
Byte size
• Even address
Byte size
• Odd address
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
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Section 6 Bus Controller
6.4.3
Valid Strobes
Table 6.5 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6.5
Area
8-bit access
space
Data Buses Used and Valid Strobes
Access Read/
Size
Write
Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
Lower Data Bus
(D7 to D0)
Byte
Read
—
RD
Valid
Port, etc.
Write
—
HWR
Even
RD
16-bit access Byte
space
Read
Odd
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Undefined
Odd
LWR
Undefined
Valid
Read
—
RD
Valid
Valid
Write
—
HWR, LWR Valid
Valid
Write
Word
Port, etc.
Legend:
Undefined: Undefined data is output.
Invalid:
Input state; input value is ignored.
Port, etc.: Pins are used as port or on-chip supporting module input/output pins, and not as data
bus pins.
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Section 6 Bus Controller
6.4.4
Basic Timing
8-Bit 2-State Access Space
Figure 6.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Figure 6.5 Bus Timing for 8-Bit 2-State Access Space
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Section 6 Bus Controller
8-Bit 3-State Access Space
Figure 6.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used.
Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
Write
D15 to D8
Valid
Figure 6.6 Bus Timing for 8-Bit 3-State Access Space
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Section 6 Bus Controller
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access space. When 16-bit access space is
accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data bus (D7 to
D0) for odd addresses.
Wait states cannot be inserted.
Bus cycle
T1
T2
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
Undefined
Figure 6.7 16-Bit, 2-State Access Space Bus Timing (1)
(Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T1
T2
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
HIgh
LWR
Write
D15 to D8
D7 to D0
Undefined
Valid
Figure 6.8 16-Bit, 2-State Access Space Bus Timing (2)
(Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T2
T1
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Figure 6.9 16-Bit, 2-State Access Space Bus Timing (3)
(Word Access)
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Section 6 Bus Controller
16-Bit, 3-State Access Space
Figures 6.10 to 6.12 show the bus timing for 16-bit, 3-state access space. When 16-bit access
space is accessed, the upper data bus (D15 to D8) is used for even addresses and the lower data
bus (D7 to D0) for odd addresses.
Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
Valid
D7 to D0
Undefined
Figure 6.10 16-Bit, 3-State Access Space Bus Timing (1)
(Even Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
Undefined
D7 to D0
Valid
Figure 6.11 16-Bit, 3-State Access Space Bus Timing (2)
(Odd Address Byte Access)
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Section 6 Bus Controller
Bus cycle
T1
T2
T3
φ
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Figure 6.12 16-Bit, 3-State Access Space Bus Timing (3)
(Word Access)
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Section 6 Bus Controller
6.4.5
Wait Control
When accessing external space, the MCU can extend the bus cycle by inserting one or more wait
states (TW). There are three ways of inserting wait states: program wait insertion, pin wait insertion
using the WAIT pin, and a combination of the two.
Program Wait Mode: In program wait mode, the number of TW states specified by bits WC1 and
WC0 are always inserted between the T2 and T3 states when external space is accessed.
Pin Wait Mode: In pin wait mode, the number of TW states specified by bits WC1 and WC0 are
always inserted between the T2 and T3 states when external space is accessed. If the WAIT pin is
low at the fall of φ in the last T2 or TW state, another TW state is inserted. If the WAIT pin is held
low, TW states are inserted until it goes high.
Pin wait mode is useful for inserting four or more wait states, or for changing the number of TW
states for different external devices.
Pin Auto-Wait Mode: In pin auto-wait mode, if the WAIT pin is low at the fall of φ in the T2
state, the number of TW states specified by bits WC1 and WC0 are inserted when external space is
accessed. No additional TW states are inserted even if the WAIT pin remains low. Pin auto-wait
mode can be used for an easy interface to low-speed memory, simply by routing the chip select
signal to the WAIT pin.
Figure 6.13 shows an example of wait state insertion timing.
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Section 6 Bus Controller
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS/IOS (IOSE = 0)
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Note:
Write data
indicates the timing of WAIT pin sampling using the φ clock.
Figure 6.13 Example of Wait State Insertion Timing
The settings after a reset are: 3-state access, insertion of 3 program wait states, and WAIT input
disabled.
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Section 6 Bus Controller
6.5
Burst ROM Interface
6.5.1
Overview
With this LSI, external space area 0 can be designated as burst ROM space, and burst ROM
interfacing can be performed.
External space can be designated as burst ROM space by means of the BRSTRM bit in BCR.
Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU
instruction fetches only. One or two states can be selected for burst access.
6.5.2
Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance
with the setting of the AST bit. Also, when the AST bit is set to 1, wait state insertion is possible.
One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in
BCR. Wait states cannot be inserted.
When the BRSTS0 bit in BCR is cleared to 0, burst access of up to 4 words is performed; when
the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6.14 (a) and (b). The timing
shown in figure 6.14 (a) is for the case where the AST and BRSTS1 bits are both set to 1, and that
in figure 6.14 (b) is for the case where both these bits are cleared to 0.
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Section 6 Bus Controller
Full access
T1
T2
Burst access
T3
T1
T2
T1
T2
φ
Only lower address changed
Address bus
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data
Read data
Figure 6.14 (a) Example of Burst ROM Access Timing (when AST = BRSTS1 = 1)
Full access
T1
T2
Burst access
T1
T1
φ
Only lower address changed
Address bus
AS/IOS (IOSE = 0)
RD
Data bus
Read data
Read data Read data
Figure 6.14 (b) Example of Burst ROM Access Timing (when AST = BRSTS1 = 0)
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Section 6 Bus Controller
6.5.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
6.6
Idle Cycle
6.6.1
Operation
When this LSI chip accesses external space, it can insert a 1-state idle cycle (TI) between bus
cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM, with a long output floating time, and
high-speed memory, I/O interfaces, and so on.
If an external write occurs after an external read while the ICIS0 bit in BCR is set to 1, an idle
cycle is inserted at the start of the write cycle. This is enabled in advanced mode and normal
mode.
Figure 6.15 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
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Section 6 Bus Controller
Bus cycle A
T1
T2
Bus cycle A
Bus cycle B
T3
T1
T2
T1
φ
φ
Address bus
Address bus
RD
RD
HWR, LWR
HWR, LWR
Data bus
Data bus
Long output
floating time
T2
Pin States in Idle Cycle
Table 6.6 shows pin states in an idle cycle.
Pin States in Idle Cycle
Pins
Pin State
A23 to A0, IOS
Contents of next bus cycle
D15 to D0
High impedance
AS
High
RD
High
HWR, LWR
High
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T1
(b) Idle cycle inserted
Figure 6.15 Example of Idle Cycle Operation
Table 6.6
TI
Data collision
(a) Idle cycle not inserted
6.6.2
T3
Bus cycle B
T2
Section 6 Bus Controller
6.7
Bus Arbitration
6.7.1
Overview
This LSI have a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and the DTC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.7.2
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
both bus masters, the bus request acknowledge signal is sent to the one with the higher priority.
When a bus master receives the bus request acknowledge signal, it takes possession of the bus
until that signal is canceled.
The order of priority of the bus masters is as follows:
(High)
DTC
>
CPU
(Low)
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Section 6 Bus Controller
6.7.3
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus
arbiter transfers the bus to the DTC. The timing for transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations.
See appendix A.5, Bus States during Instruction Execution, for timings at which the bus is not
transferred.
• If the CPU is in sleep mode, it transfers the bus immediately.
DTC
The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC does not release the bus until it has completed a series of processing operations.
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Section 7 Data Transfer Controller (DTC)
Section 7 Data Transfer Controller (DTC)
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
7.1
Overview
The H8S/2148 Group includes a data transfer controller (DTC). The DTC can be activated by an
interrupt or software, to transfer data.
7.1.1
Features
• Transfer possible over any number of channels
 Transfer information is stored in memory
 One activation source can trigger a number of data transfers (chain transfer)
• Wide range of transfer modes
 Normal, repeat, and block transfer modes available
 Incrementing, decrementing, and fixing of transfer source and destination addresses can be
selected
• Direct specification of 16-Mbyte address space possible
 24-bit transfer source and destination addresses can be specified
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
 An interrupt request can be issued to the CPU after one data transfer ends
 An interrupt request can be issued to the CPU after all specified data transfers have ended
• Activation by software is possible
• Module stop mode can be set
 The initial setting enables DTC registers to be accessed. DTC operation is halted by setting
module stop mode
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Section 7 Data Transfer Controller (DTC)
7.1.2
Block Diagram
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Internal address bus
On-chip
RAM
CPU interrupt
request
Register information
MRA MRB
CRA
CRB
DAR
SAR
DTC
Control logic
DTC activation
request
DTVECR
Interrupt
request
DTCERA
to
DTCERE
Interrupt controller
Internal data bus
Legend:
MRA, MRB: DTC mode registers A and B
CRA, CRB: DTC transfer count registers A and B
SAR:
DTC source address register
DAR:
DTC destination address register
DTCERA to DTCERE: DTC enable registers A to E
DTVECR: DTC vector register
Figure 7.1 Block Diagram of DTC
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Section 7 Data Transfer Controller (DTC)
7.1.3
Register Configuration
Table 7.1 summarizes the DTC registers.
Table 7.1
DTC Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
DTC mode register A
MRA
Undefined
DTC mode register B
MRB
—*
2
—*
3
—*
3
—*
DTC source address register
SAR
2
—*
Undefined
DTC destination address register
DAR
Undefined
DTC transfer count register A
CRA
2
—*
2
—*
DTC transfer count register B
CRB
—*
Undefined
3
—*
3
—*
DTC enable registers
DTCER*
R/W
H'00
H'FEEE to H'FEF2
DTC vector register
4
DTVECR*
R/W
H'00
H'FEF3
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
2
4
2
Undefined
Undefined
3
—*
3
—*
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.
They cannot be located in external memory space.
When the DTC is used, do not clear the RAME bit in SYSCR to 0.
4. The H8S/2144 Group and H8S/2147N do not include an on-chip DTC, and therefore the
DTCER and DTVECR register addresses should not be accessed by the CPU.
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Section 7 Data Transfer Controller (DTC)
7.2
Register Descriptions
7.2.1
DTC Mode Register A (MRA)
7
Bit
Initial value
Read/Write
6
5
4
3
2
1
0
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
Bit 6
SM1
SM0
Description
0
—
SAR is fixed
1
0
SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1
SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
Bit 4
DM1
DM0
Description
0
—
DAR is fixed
1
0
DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1
DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
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Section 7 Data Transfer Controller (DTC)
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
Bit 2
MD1
MD0
Description
0
0
Normal mode
1
Repeat mode
0
Block transfer mode
1
—
1
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS
Description
0
Destination side is repeat area or block area
1
Source side is repeat area or block area
Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz
Description
0
Byte-size transfer
1
Word-size transfer
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Section 7 Data Transfer Controller (DTC)
7.2.2
DTC Mode Register B (MRB)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CHNE
DISEL
—
—
—
—
—
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
Undefined
—
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer,
multiple data transfers can be performed consecutively in response to a single transfer request.
With data transfer for which CHNE is set to 1, there is no determination of the end of the specified
number of transfers, clearing of the interrupt source flag, or clearing of DTCER.
Bit 7
CHNE
Description
0
End of DTC data transfer (activation waiting state is entered)
1
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
Description
0
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
1
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: In the H8S/2148 Group these bits have no effect on DTC operation, and
should always be written with 0.
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Section 7 Data Transfer Controller (DTC)
7.2.3
DTC Source Address Register (SAR)
23
Bit
Initial value
Read/write
22
21
20
19
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
4
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DTC Destination Address Register (DAR)
Bit
Initial value
Read/write
23
22
21
20
19
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
4
3
2
1
0
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
— — — — —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
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Section 7 Data Transfer Controller (DTC)
7.2.5
DTC Transfer Count Register A (CRA)
15
Bit
Initial value
Read/Write
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
CRAH
CRAL
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, CRA is divided into two parts: the upper 8 bits (CRAH)
and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an
8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are transferred when the count reaches H'00. This operation is repeated.
7.2.6
DTC Transfer Count Register B (CRB)
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
— — — — — — — — — — — — — — — —
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
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Section 7 Data Transfer Controller (DTC)
7.2.7
DTC Enable Registers (DTCER)
Bit
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
Description
0
DTC activation by interrupt is disabled
(Initial value)
[Clearing conditions]
1
•
When data transfer ends with the DISEL bit set to 1
•
When the specified number of transfers end
DTC activation by interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
Note: n = 7 to 0
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated by the interrupt controller in each case.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
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Section 7 Data Transfer Controller (DTC)
7.2.8
DTC Vector Register (DTVECR)
7
Bit
6
5
4
3
2
0
1
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1
is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC
software activation. To clear the SWDTE bit by software, read SWDTE when set to 1, then write 0
in the bit.
Bit 7
SWDTE
Description
0
DTC software activation is disabled
(Initial value)
[Clearing condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
1
DTC software activation is enabled
[Holding conditions]
•
When data transfer ends with the DISEL bit set to 1
•
When the specified number of transfers end
•
During software-activated data transfer
Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits
specify a vector number for DTC software activation.
The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For
example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.
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Section 7 Data Transfer Controller (DTC)
7.2.9
Module Stop Control Register (MSTPCR)
MSTPCRH
7
Bit
6
5
4
3
MSTPCRL
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
Initial value
Read/Write
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle
and a transition is made to module stop mode. Note that 1 cannot be written to the MSTP14 bit
when the DTC is being activated. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 6—Module Stop (MSTP14): Specifies the DTC module stop mode.
MSTPCRH
Bit 6
MSTP14
Description
0
DTC module stop mode is cleared
1
DTC module stop mode is set
7.3
Operation
7.3.1
Overview
(Initial value)
When activated, the DTC reads register information that is already stored in memory and transfers
data on the basis of that register information. After the data transfer, it writes updated register
information back to memory. Pre-storage of register information in memory makes it possible to
transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to
perform a number of transfers with a single activation.
Figure 7.2 shows a flowchart of DTC operation.
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Section 7 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1?
Yes
No
Transfer counter = 0
or DISEL = 1?
Yes
No
Clear activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 7.2 Flowchart of DTC Operation
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 7.2 outlines the functions of the DTC.
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Section 7 Data Transfer Controller (DTC)
Table 7.2
DTC Functions
Address Registers
Transfer Mode
Activation Source
Transfer
Source
Transfer
Destination
•
Normal mode
•
24 bits
24 bits
 One transfer request transfers one
byte or one word
•
FRT ICI, OCI
•
8-bit timer CMI
 Memory addresses are incremented
or decremented by 1 or 2
•
Host interface IBF
•
SCI TXI or RXI
 Up to 65,536 transfers possible
•
A/D converter ADI
Repeat mode
•
IIC IICI
•
Software
•
 One transfer request transfers one
byte or one word
IRQ
 Memory addresses are incremented
or decremented by 1 or 2
 After the specified number of transfers
(1 to 256), the initial state resumes and
operation continues
•
Block transfer mode
 One transfer request transfers a block
of the specified size
 Block size is from 1 to 256 bytes or
words
 Up to 65,536 transfers possible
 A block area can be designated at either
the source or destination
7.3.2
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software (software
activation). An interrupt request can be directed to the CPU or DTC, as designated by the
corresponding DTCER bit. The interrupt request is directed to the DTC when the corresponding
bit is set to 1, and to the CPU when the bit is cleared to 0.
At the end of one data transfer (or the last of the consecutive transfers in the case of chain transfer)
the interrupt source or the corresponding DTCER bit is cleared. Table 7.3 shows activation
sources and DTCER clearing.
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Section 7 Data Transfer Controller (DTC)
The interrupt source flag for RXI0, for example, is the RDRF flag in SCI0.
Table 7.3
Activation Sources and DTCER Clearing
When DISEL Bit Is 0 and
Specified Number of Transfers
Have Not Ended
Activation
Source
Software
activation
SWDTE bit cleared to 0
Interrupt
activation
•
Corresponding DTCER bit held
at 1
•
Activation source flag cleared
to 0
When DISEL Bit Is 1 or
Specified Number of Transfers
Have Ended
•
SWDTE bit held at 1
•
Interrupt request sent to CPU
•
Corresponding DTCER bit cleared to 0
•
Activation source flag held at 1
•
Activation source interrupt request
sent to CPU
Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Source flag cleared
Clear
control
Clear
DTCER
Clear request
On-chip
supporting
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
DTC
Interrupt controller
CPU
Interrupt mask
Figure 7.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC is activated in accordance with the default priorities.
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Section 7 Data Transfer Controller (DTC)
7.3.3
DTC Vector Table
Figure 7.4 shows the correspondence between DTC vector addresses and register information.
Table 7.4 shows the correspondence between activation sources, vector addresses, and DTCER
bits. When the DTC is activated by software, the vector address is obtained from: H'0400 +
DTVECR[6:0] << 1 (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the
vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register information should be an integral multiple of four.
The configuration of the vector address is the same in both normal and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip
RAM.
DTC vector
address
Register information
start address
Register information
Chain transfer
Figure 7.4 Correspondence between DTC Vector Address and Register Information
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Section 7 Data Transfer Controller (DTC)
Table 7.4
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Interrupt Source
Origin of
Vector
Interrupt Source Number
Write to DTVECR
Software
IRQ0
External pin
Vector
Address
DTCE*
Priority
DTVECR H'0400 +
(Decimal
DTVECR
indication) [6:0] << 1
—
High
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
ADI (A/D conversion end)
A/D
28
H'0438
DTCEA3
ICIA (FRT input capture A)
FRT
48
H'0460
DTCEA2
ICIB (FRT input capture B)
49
H'0462
DTCEA1
OCIA (FRT output compare A)
52
H'0468
DTCEA0
OCIB (FRT output compare B)
54
H'046A
DTCEB7
CMIA0 (TMR0 compare-match A) TMR0
64
H'0480
DTCEB2
CMIB0 (TMR0 compare-match B)
65
H'0482
DTCEB1
CMIA1 (TMR1 compare-match A) TMR1
68
H'0488
DTCEB0
CMIB1 (TMR1 compare-match B)
69
H'048A
DTCEC7
CMIAY (TMRY compare-match A) TMRY
72
H'0490
DTCEC6
CMIBY (TMRY compare-match B)
IBF1 (IDR1 reception completed)
73
H'0492
DTCEC5
76
H'0498
DTCEC4
77
H'049A
DTCEC3
81
H'04A2
DTCEC2
82
H'04A4
DTCEC1
SCI channel 1
85
H'04AA
DTCEC0
86
H'04AC
DTCED7
SCI channel 2
89
H'04B2
DTCED6
90
H'04B4
DTCED5
HIF
IBF2 (IDR2 reception completed)
RXI0 (reception completed 0)
SCI channel 0
TXI0 (transmit data empty 0)
RXI1 (reception completed 1)
TXI1 (transmit data empty 1)
RXI2 (reception completed 2)
TXI2 (transmit data empty 2)
IICI0 (IIC0 1-byte transmission/
reception completed)
IIC0 (option)
92
H'04B8
DTCED4
IICI1 (IIC1 1-byte transmission/
reception completed)
IIC1 (option)
94
H'04BC
DTCED3
Note:
*
Low
DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
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Section 7 Data Transfer Controller (DTC)
7.3.4
Location of Register Information in Address Space
Figure 7.5 shows how the register information should be located in the address space.
Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address
of the register information (vector address contents). In chain transfer, locate the register
information in consecutive areas.
Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF).
Lower address
0
Register information
start address
Chain transfer
1
2
3
MRA
SAR
MRB
DAR
CRA
Register information
CRB
MRA
SAR
MRB
DAR
CRA
CRB
Register information
for 2nd transfer
in chain transfer
4 bytes
Figure 7.5 Location of DTC Register Information in Address Space
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Section 7 Data Transfer Controller (DTC)
7.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in
normal mode.
Table 7.5
Register Information in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register A
CRA
Transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 7.6 Memory Mapping in Normal Mode
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Section 7 Data Transfer Controller (DTC)
7.3.6
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial address register state specified by the transfer counter and repeat area resumes and transfer
is repeated. In repeat mode the transfer counter does not reach H'00, and therefore CPU interrupts
cannot be requested when DISEL = 0.
Table 7.6 lists the register information in repeat mode and figure 7.7 shows memory mapping in
repeat mode.
Table 7.6
Register Information in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Transfer count
DTC transfer count register B
CRB
Not used
SAR or
DAR
DAR or
SAR
Repeat area
Transfer
Figure 7.7 Memory Mapping in Repeat Mode
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Section 7 Data Transfer Controller (DTC)
7.3.7
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is specified as a block area.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified in the block area is restored. The other address register is
successively incremented or decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 7.7 lists the register information in block transfer mode and figure 7.8 shows memory
mapping in block transfer mode.
Table 7.7
Register Information in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Transfer source address
DTC destination address register
DAR
Transfer destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Block size count
DTC transfer count register B
CRB
Transfer counter
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Section 7 Data Transfer Controller (DTC)
First block
SAR or
DAR
·
·
·
Block area
DAR or
SAR
Transfer
Nth block
Figure 7.8 Memory Mapping in Block Transfer Mode
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Section 7 Data Transfer Controller (DTC)
7.3.8
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows memory mapping for chain transfer.
Source
Destination
Register information
CHNE = 1
DTC vector
address
Register information
start address
Register information
CHNE = 0
Source
Destination
Figure 7.9 Memory Mapping in Chain Transfer
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
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Section 7 Data Transfer Controller (DTC)
7.3.9
Operation Timing
Figures 7.10 to 7.12 show examples of DTC operation timing.
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Address
Read Write
Transfer
information read
Transfer
information write
Figure 7.10 DTC Operation Timing (Normal Mode or Repeat Mode)
φ
DTC activation
request
DTC request
Data transfer
Vector read
Address
Read Write Read Write
Transfer
information read
Transfer
information write
Figure 7.11 DTC Operation Timing (Block Transfer Mode, with Block Size of 2)
Rev. 4.00 Sep 27, 2006 page 201 of 1130
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Section 7 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information
read
Transfer
Transfer
information information
write
read
Transfer
information
write
Figure 7.12 DTC Operation Timing (Chain Transfer)
7.3.10
Number of DTC Execution States
Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of
states required for each execution phase.
Table 7.8
DTC Execution Phases
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operation
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N: Block size (initial setting of CRAH and CRAL)
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Section 7 Data Transfer Controller (DTC)
Table 7.9
Number of States Required for Each Execution Phase
Object of Access
OnOnChip Chip Internal I/O
RAM ROM Registers
External Devices
Bus width
32
16
8
16
8
Access states
Execution
phase
8
16
16
1
1
2
2
2
3
2
3
Vector read
SI
—
1
—
—
4
6+2m
2
3+m
Register
information
read/write
SJ
1
—
—
—
—
—
—
—
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Internal operation SM
1
1
1
1
1
1
1
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number for which the CHNE bit is set to one,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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Section 7 Data Transfer Controller (DTC)
7.3.11
Procedures for Using the DTC
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check that the SWDTE bit is 0.
4. Write 1 in the SWDTE bit and the vector number to DTVECR.
5. Check the vector number written to DTVECR.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 7 Data Transfer Controller (DTC)
7.3.12
Examples of Use of the DTC
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
Rev. 4.00 Sep 27, 2006 page 205 of 1130
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Section 7 Data Transfer Controller (DTC)
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
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Section 7 Data Transfer Controller (DTC)
7.4
Interrupts
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software-activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers
have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.5
Usage Notes
Module Stop
When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the
module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating.
When the DTC is placed in the module stop state, the DTCER registers must all be in the cleared
state when the MSTP14 bit is set to 1.
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
DTCE Bit Setting
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
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Section 7 Data Transfer Controller (DTC)
Rev. 4.00 Sep 27, 2006 page 208 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Section 8 I/O Ports
8.1
Overview
This LSI have ten I/O ports (ports 1 to 6, 8, 9, A, and B), and one input-only port (port 7).
Tables 8.1 to 8.3 summarize the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only port) and data registers (DR, ODR) that store output data.
Ports 1 to 3, 6, A, and B have a built-in MOS input pull-up function. For ports A and B, the on/off
status of the MOS input pull-up is controlled by DDR and ODR. Ports 1 to 3 and 6 have a MOS
input pull-up control register (PCR), in addition to DDR and DR, to control the on/off status of the
MOS input pull-ups.
Ports 1 to 6, 8, 9, A, and B can drive a single TTL load and 30 pF capacitive load. All the I/O
ports can drive a Darlington transistor when in output mode. Ports 1, 2, and 3 can drive an LED
(10 mA sink current).
PA4 to PA7 in port A have bus buffer drive capability. In the H8S/2148 Group and H8S/2147N,
P52 in port 5 and P97 in port 9 are NMOS push-pull outputs.
Note that the H8S/2144 Group and H8S/2147N have subset specifications that do not include
some supporting modules. For differences in pin functions, see table 8.1, H8S/2148 Group Port
Functions, table 8.2, H8S/2147N Port Functions, and table 8.3, H8S/2144 Group Port Functions.
Rev. 4.00 Sep 27, 2006 page 209 of 1130
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Section 8 I/O Ports
Table 8.1
H8S/2148 Group Port Functions
Expanded Modes
Port
Port 1
Description
Pins
• 8-bit I/O port P17 to P10/
• Built-in MOS A7 to A0/
PW7 to PW0
input pullups
Mode 1
Lower address When DDR = 0
output
(after reset): input
(A7 to A0)
port
• 8-bit I/O port P27/A15/PW15/
• Built-in MOS CBLANK
input pullP26/A14/PW14
ups
P25/A13/PW13
• LED drive
P24/A12/PW12
capability
P23/A11/PW11
Upper address When DDR = 0
output
(after reset): input
(A15 to A8)
port or timer
connection output
(CBLANK)
P21/A9/PW9
P20/A8/PW8
• 8-bit I/O port P37 to P30/
HDB7 to HDB0/
• Built-in MOS
D15 to D8
input pullups
I/O port also functioning as
PWM timer output (PW7 to
PW0)
I/O port also functioning as
PWM timer output (PW15
to PW8) and timer
connection output
(CBLANK)
When DDR = 1:
upper address
output (A15 to A8),
PWM timer output
(PW15 to PW8),
timer connection
output (CBLANK),
or output ports (P27
to P24)
P22/A10/PW10
Port 3
Mode 2, Mode 3
(EXPE = 0)
When DDR = 1:
lower address
output (A7 to A0) or
PWM timer output
(PW7 to PW0)
• LED drive
capability
Port 2
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Data bus input/output (D15 to D8)
• LED drive
capability
Rev. 4.00 Sep 27, 2006 page 210 of 1130
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I/O port also functioning as
host interface data bus
input/output (HDB7 to
HDB0)
Section 8 I/O Ports
Expanded Modes
Port
Port 4
Description
Pins
• 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1/
HIRQ12/CSYNCI
P44/TMO1/
HIRQ1/HSYNCO
P43/TMCI1/
HIRQ11/HSYNCI
P42/TMRI0/
SCK2/SDA1
P41/TMO0/
RxD2/IrRxD
P40/TMCI0/
TxD2/IrTxD
Port 5
• 3-bit I/O port P52/SCK0/SCL0
P51/RxD0
Mode 1
Mode 2, Mode 3
(EXPE = 1)
I/O port also functioning as 14-bit
PWM timer output (PWX1, PWX0),
8-bit timer 0 and 1 input/output
(TMCI0, TMRI0, TMO0, TMCI1,
TMRI1, TMO1), timer connection
input/output (HSYNCO, CSYNCI,
HSYNCI), SCI2 input/output (TxD2,
RxD2, SCK2), IrDA interface
input/output (IrTxD, IrRxD), and I2C
bus interface 1 (option) input/output
(SDA1)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as
14-bit PWM timer output
(PWX1, PWX0), 8-bit timer
0 and 1 input/output
(TMCI0, TMRI0, TMO0,
TMCI1, TMRI1, TMO1),
timer connection
input/output (HSYNCO,
CSYNCI, HSYNCI), host
interface host CPU
interrupt request output
(HIRQ12, HIRQ1,
HIRQ11), SCI2 input/
output (TxD2, RxD2,
SCK2), IrDA interface
input/output (IrTxD, IrRxD),
and I2C bus interface 1
(option) input/output
(SDA1)
I/O port also functioning as SCI0 input/output (TxD0, RxD0,
SCK0) and I2C bus interface 0 (option) input/output (SCL0)
P50/TxD0
Port 6
• 8-bit I/O port P67/IRQ7/TMOX/
KIN7/CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
P65/FTID/KIN5/
CIN5
I/O port also functioning as external interrupt input (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer X and Y input/output (TMOX, TMIX, TMIY), timer
connection input/output (CLAMPO, VFBACKI, VSYNCI,
VSYNCO, HFBACKI), key-sense interrupt input (KIN7 to KIN0),
and expansion A/D converter input (CIN7 to CIN0)
P64/FTIC/KIN4/
CIN4/CLAMPO
P63/FTIB/KIN3/
CIN3/VFBACKI
P62/FTIA/TMIY/
KIN2/CIN2/
VSYNCI
P61/FTOA/KIN1/
CIN1/VSYNCO
P60/FTCI/TMIX/
KIN0/CIN0/
HFBACKI
Rev. 4.00 Sep 27, 2006 page 211 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Expanded Modes
Port
Port 7
Description
Pins
• 8-bit I/O port P77/AN7/DA1
P76/AN6/DA0
Mode 1
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
Input port also functioning as A/D converter analog input (AN7 to
AN0) and D/A converter analog output (DA1, DA0)
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port 8
• 7-bit I/O port P86/IRQ5/SCK1/
SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
I/O port also functioning as external
interrupt input (IRQ5, IRQ4, IRQ3),
SCI1 input/output (TxD1, RxD1,
SCK1), and I2C bus interface 1
(option) input/output (SCL1)
I/O port also functioning as
external interrupt input
(IRQ5, IRQ4, IRQ3), SCI1
input/output (TxD1, RxD1,
SCK1), host interface
control input/output (CS2,
GA20, HA0, HIFSD), and
I2C bus interface 1 (option)
input/output (SCL1)
I/O port also functioning as
expanded data bus control input
(WAIT) and I2C bus interface 0
(option) input/output (SDA0)
I/O port also functioning as
I2C bus interface 0 (option)
input/output (SDA0)
P83
P82/HIFSD
P81/CS2/GA20
P80/HA0
Port 9
• 8-bit I/O port P97/WAIT/SDA0
P96/φ/EXCL
When DDR = When DDR = 0 (after reset): input port or EXCL
0: input port or input
EXCL input
When DDR = 1: φ output
When DDR =
1 (after reset):
φ output
P95/AS/IOS/CS1
Expanded data bus control output
(AS/IOS, HWR, RD)
P94/HWR/IOW
P93/RD/IOR
Rev. 4.00 Sep 27, 2006 page 212 of 1130
REJ09B0327-0400
I/O port also functioning as
host interface control input
(CS1, IOW, IOR)
Section 8 I/O Ports
Expanded Modes
Port
Port 9
Description
Pins
• 8-bit I/O port P92/IRQ0
Mode 1
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as external interrupt input (IRQ0, IRQ1)
P91/IRQ1
P90/LWR/IRQ2/
ADTRG/ECS2
Port A
• 8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
Port B
• 8-bit I/O port PB7/D7
PB6/D6
PB5/D5
I/O port also functioning as
expanded data bus control output
(LWR), external interrupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/output (D7 to D0)
I/O port also functioning as
external interrupt input
(IRQ2), A/D converter
external trigger input
(ADTRG), and host
interface control input
(ECS2)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8),
expansion A/D converter
input (CIN15 to CIN8), and
keyboard buffer controller
input/output (PS2CD,
PS2CC, PS2BD, PS2BC,
PS2AD, PS2AC)
I/O port also functioning as
HIF control input/output
pins (CS3, CS4, HIRQ3,
HIRQ4)
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
Rev. 4.00 Sep 27, 2006 page 213 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Table 8.2
H8S/2147N Port Functions
Expanded Modes
Port
Port 1
Description
Pins
• 8-bit I/O port P17 to P10/
• Built-in MOS A7 to A0/
PW7 to PW0
input pullups
Mode 1
Lower address When DDR = 0
output
(after reset): input
(A7 to A0)
port
• 8-bit I/O port P27/A15/PW15
• Built-in MOS P26/A14/PW14
input pullP25/A13/PW13
ups
P24/A12/PW12
• LED drive
P23/A11/PW11
capability
Upper address When DDR = 0
output
(after reset): input
(A15 to A8)
port
P21/A9/PW9
P20/A8/PW8
• 8-bit I/O port P37 to P30/
HDB7 to HDB0/
• Built-in MOS
D15 to D8
input pullups
I/O port also functioning as
PWM timer output (PW7 to
PW0)
I/O port also functioning as
PWM timer output (PW15
to PW8)
When DDR = 1:
upper address
output (A15 to A8),
PWM timer output
(PW15 to PW8), or
output ports (P27 to
P24)
P22/A10/PW10
Port 3
Mode 2, Mode 3
(EXPE = 0)
When DDR = 1:
lower address
output (A7 to A0) or
PWM timer output
(PW7 to PW0)
• LED drive
capability
Port 2
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Data bus input/output (D15 to D8)
I/O port also functioning as
host interface data bus
input/output (HDB7 to
HDB0)
I/O port also functioning as 14-bit
PWM timer output (PWX1, PWX0),
8-bit timer 0 and 1 input/output
(TMCI0, TMRI0, TMO0, TMCI1,
TMRI1, TMO1), SCI2 input/output
(TxD2, RxD2, SCK2), IrDA interface
input/output (IrTxD, IrRxD), and I2C
bus interface 1 (option) input/output
(SDA1)
I/O port also functioning as
14-bit PWM timer output
(PWX1, PWX0), 8-bit timer
0 and 1 input/output
(TMCI0, TMRI0, TMO0,
TMCI1, TMRI1, TMO1),
host interface host CPU
interrupt request output
(HIRQ12, HIRQ1,
HIRQ11), SCI2 input/
output (TxD2, RxD2,
SCK2), IrDA interface
input/output (IrTxD, IrRxD),
and I2C bus interface 1
(option) input/output
(SDA1)
• LED drive
capability
Port 4
• 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1/
HIRQ12
P44/TMO1/
HIRQ1
P43/TMCI1/
HIRQ11
P42/TMRI0/
SCK2/SDA1
P41/TMO0/
RxD2/IrRxD
P40/TMCI0/
TxD2/IrTxD
Rev. 4.00 Sep 27, 2006 page 214 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Expanded Modes
Port
Port 5
Description
Pins
• 3-bit I/O port P52/SCK0/SCL0
P51/RxD0
Mode 1
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as SCI0 input/output (TxD0, RxD0,
SCK0) and I2C bus interface 0 (option) input/output (SCL0)
P50/TxD0
Port 6
• 8-bit I/O port P67/IRQ7/KIN7/
CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
I/O port also functioning as external interrupt input (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to
KIN0), and expansion A/D converter input (CIN7 to CIN0)
P65/FTID/KIN5/
CIN5
P64/FTIC/KIN4/
CIN4
P63/FTIB/KIN3/
CIN3
P62/FTIA/TMIY/
KIN2/CIN2
P61/FTOA/KIN1/
CIN1
P60/FTCI/KIN0/
CIN0
Port 7
• 8-bit I/O port P77/AN7/DA1
P76/AN6/DA0
Input port also functioning as A/D converter analog input (AN7 to
AN0) and D/A converter analog output (DA1, DA0)
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port 8
• 7-bit I/O port P86/IRQ5/SCK1/
SCL1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82/HIFSD
P81/CS2/GA20
I/O port also functioning as external
interrupt input (IRQ5, IRQ4, IRQ3),
SCI1 input/output (TxD1, RxD1,
SCK1), and I2C bus interface 1
(option) input/output (SCL1)
I/O port also functioning as
external interrupt input
(IRQ5, IRQ4, IRQ3), SCI1
input/output (TxD1, RxD1,
SCK1), host interface
control input/output (CS2,
GA20, HA0, HIFSD), and
I2C bus interface 1 (option)
input/output (SCL1)
P80/HA0
Rev. 4.00 Sep 27, 2006 page 215 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Expanded Modes
Port
Port 9
Description
Pins
• 8-bit I/O port P97/WAIT/SDA0
Mode 1
Mode 2, Mode 3
(EXPE = 1)
I/O port also functioning as
expanded data bus control input
(WAIT) and I2C bus interface 0
(option) input/output (SDA0)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as
I2C bus interface 0 (option)
input/output (SDA0)
P96/φ/EXCL
When DDR = When DDR = 0 (after reset): input port or EXCL
0: input port or input
EXCL input
When DDR = 1: φ output
When DDR =
1 (after reset):
φ output
P95/AS/IOS/CS1
Expanded data bus control output
(AS/IOS, HWR, RD)
P94/HWR/IOW
I/O port also functioning as
host interface control input
(CS1, IOW, IOR)
P93/RD/IOR
P92/IRQ0
I/O port also functioning as external interrupt input (IRQ0, IRQ1)
P91/IRQ1
P90/LWR/IRQ2/
ADTRG/ECS2
Port A
• 8-bit I/O port PA7/A23/KIN15/
CIN15/PS2CD
PA6/A22/KIN14/
CIN14/PS2CC
PA5/A21/KIN13/
CIN13/PS2BD
PA4/A20/KIN12/
CIN12/PS2BC
PA3/A19/KIN11/
CIN11/PS2AD
PA2/A18/KIN10/
CIN10/PS2AC
PA1/A17/KIN9/
CIN9
PA0/A16/KIN8/
CIN8
I/O port also functioning as
expanded data bus control output
(LWR), external interrupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8),
expansion A/D
converter input
(CIN15 to
CIN8), and
keyboard
buffer
controller
input/output
(PS2CD,
PS2CC,
PS2BD,
PS2BC,
PS2AD,
PS2AC)
Rev. 4.00 Sep 27, 2006 page 216 of 1130
REJ09B0327-0400
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
expansion A/D
converter input
(CIN15 to CIN8),
and keyboard buffer
controller input/
output (PS2CD,
PS2CC, PS2BD,
PS2BC, PS2AD,
PS2AC)
I/O port also functioning as
external interrupt input
(IRQ2), A/D converter
external trigger input
(ADTRG), and host
interface control input
(ECS2)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8), expansion
A/D converter input (CIN15
to CIN8), and keyboard
buffer controller
input/output (PS2CD,
PS2CC, PS2BD, PS2BC,
PS2AD, PS2AC)
Section 8 I/O Ports
Expanded Modes
Port
Port B
Description
Pins
• 8-bit I/O port PB7/D7
PB6/D6
PB5/D5
Mode 1
Mode 2, Mode 3
(EXPE = 1)
In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/output (D7 to D0)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as
HIF control input/output
pins (CS3, CS4, HIRQ3,
HIRQ4)
PB4/D4
PB3/D3/CS4
PB2/D2/CS3
PB1/D1/HIRQ4
PB0/D0/HIRQ3
Rev. 4.00 Sep 27, 2006 page 217 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Table 8.3
H8S/2144 Group Port Functions
Expanded Modes
Port
Port 1
Description
Pins
• 8-bit I/O port P17 to P10/
• Built-in MOS A7 to A0
input pullups
Mode 1
Lower address When DDR = 0
output (A7 to (after reset): input
A0)
port
• 8-bit I/O port P27 to P20/
• Built-in MOS A15 to A8
input pullups
Upper address When DDR = 0
output (A15 to (after reset): input
A8)
port
Mode 2, Mode 3
(EXPE = 0)
I/O port
• 8-bit I/O port P37 to P30/
• Built-in MOS D15 to D8
input pullups
I/O port
When DDR = 1:
upper address
output (A15 to A8)
or output port (P27
to P24)
• LED drive
capability
Port 3
Single-Chip Mode
When DDR = 1:
lower address
output (A7 to A0)
• LED drive
capability
Port 2
Mode 2, Mode 3
(EXPE = 1)
Data bus input/output (D15 to D8)
I/O port
• LED drive
capability
Port 4
• 8-bit I/O port P47/PWX1
P46/PWX0
P45/TMRI1
I/O port also functioning as 14-bit PWM timer output (PWX1,
PWX0), 8-bit timer 0 and 1 input/output (TMCI0, TMRI0, TMO0,
TMCI1, TMRI1, TMO1), SCI2 input/output (TxD2, RxD2, SCK2),
and IrDA interface input/output (IrTxD, IrRxD)
P44/TMO1
P43/TMCI1
P42/TMRI0/SCK2
P41/TMO0/RxD2/
IrRxD
P40/TMCI0/
TxD2/IrTxD
Port 5
• 3-bit I/O port P52/SCK0
P51/RxD0
I/O port also functioning as SCI0 input/output (TxD0, RxD0,
SCK0)
P50/TxD0
Rev. 4.00 Sep 27, 2006 page 218 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Expanded Modes
Port
Port 6
Description
Pins
• 8-bit I/O port P67/IRQ7/KIN7/
CIN7
P66/IRQ6/FTOB/
KIN6/CIN6
Mode 1
Mode 2, Mode 3
(EXPE = 1)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port also functioning as external interrupt input (IRQ7, IRQ6),
FRT input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB),
8-bit timer Y input (TMIY), key-sense interrupt input (KIN7 to
KIN0), and expansion A/D converter input (CIN7 to CIN0)
P65/FTID/KIN5/
CIN5
P64/FTIC/KIN4/
CIN4
P63/FTIB/KIN3/
CIN3
P62/FTIA/TMIY/
KIN2/CIN2
P61/FTOA/KIN1/
CIN1
P60/FTCI/KIN0/
CIN0
Port 7
• 8-bit input
port
P77/AN7/DA1
P76/AN6/DA0
Input port also functioning as A/D converter analog input (AN7 to
AN0) and D/A converter analog output (DA1, DA0)
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
Port 8
• 7-bit I/O port P86/IRQ5/SCK1
P85/IRQ4/RxD1
I/O port also functioning as external interrupt input (IRQ5, IRQ4,
IRQ3) and SCI1 input/output (TxD1, RxD1, SCK1)
P84/IRQ3/TxD1
P83
P82
P81
P80
Rev. 4.00 Sep 27, 2006 page 219 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Expanded Modes
Port
Port 9
Description
Pins
• 8-bit I/O port P97/WAIT
Mode 1
Mode 2, Mode 3
(EXPE = 1)
I/O port also functioning as
expanded data bus control input
(WAIT)
Single-Chip Mode
Mode 2, Mode 3
(EXPE = 0)
I/O port
P96/φ/EXCL
When DDR = When DDR = 0 (after reset): input port or EXCL
0: input port or input
EXCL input
When DDR = 1: φ output
When DDR =
1 (after reset):
φ output
P95/AS/IOS
Expanded data bus control
output(AS/IOS, HWR, RD)
P94/HWR
I/O port
P93/RD
P92/IRQ0
I/O port also functioning as external interrupt input (IRQ0, IRQ1)
P91/IRQ1
P90/LWR/
IRQ2/ADTRG
I/O port also functioning as
expanded data bus control output
(LWR), external interrupt input
(IRQ2), and A/D converter external
trigger input (ADTRG)
I/O port also
functioning as
address output (A23
to A16), key-sense
interrupt input
(KIN15 to KIN8),
and expansion A/D
converter input
(CIN15 to CIN8)
Port A
• 8-bit I/O port PA7 to PA0/
A23 to A16/
KIN15 to KIN8/
CIN15 to CIN8
I/O port also
functioning as
key-sense
interrupt input
(KIN15 to
KIN8), and
expansion A/D
converter input
(CIN15 to
CIN8)
Port B
• 8-bit I/O port PB7 to PB0/
D7 to D0
In 8-bit bus mode (ABW = 1): I/O
port
In 16-bit bus mode (ABW = 0): data
bus input/output (D7 to D0)
Rev. 4.00 Sep 27, 2006 page 220 of 1130
REJ09B0327-0400
I/O port also functioning as
external interrupt input
(IRQ2) and A/D converter
external trigger input
(ADTRG)
I/O port also functioning as
key-sense interrupt input
(KIN15 to KIN8) and
expansion A/D converter
input (CIN15 to CIN8)
I/O port
Section 8 I/O Ports
8.2
Port 1
8.2.1
Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as address bus output pins (A7 to A0), and as
8-bit PWM output pins (PW7 to PW0) (H8S/2148 Group and H8S/2147N only). Port 1 functions
change according to the operating mode. Port 1 has a built-in MOS input pull-up function that can
be controlled by software.
Figure 8.1 shows the port 1 pin configuration.
Port 1
Port 1 pins
Pin functions in mode 1
P17/A7/PW7
A7 (Output)
P16/A6/PW6
A6 (Output)
P15/A5/PW5
A5 (Output)
P14/A4/PW4
A4 (Output)
P13/A3/PW3
A3 (Output)
P12/A2/PW2
A2 (Output)
P11/A1/PW1
A1 (Output)
P10/A0/PW0
A0 (Output)
Pin functions in modes 2 and 3 (EXPE = 1)
A7 (Output)/P17 (Input)/PW7 (Output)
A6 (Output)/P16 (Input)/PW6 (Output)
A5 (Output)/P15 (Input)/PW5 (Output)
A4 (Output)/P14 (Input)/PW4 (Output)
A3 (Output)/P13 (Input)/PW3 (Output)
A2 (Output)/P12 (Input)/PW2 (Output)
A1 (Output)/P11 (Input)/PW1 (Output)
A0 (Output)/P10 (Input)/PW0 (Output)
Pin functions in modes 2 and 3 (EXPE = 0)
P17 (I/O)/PW7 (Output)
P16 (I/O)/PW6 (Output)
P15 (I/O)/PW5 (Output)
P14 (I/O)/PW4 (Output)
P13 (I/O)/PW3 (Output)
P12 (I/O)/PW2 (Output)
P11 (I/O)/PW1 (Output)
P10 (I/O)/PW0 (Output)
Figure 8.1 Port 1 Pin Functions
Rev. 4.00 Sep 27, 2006 page 221 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.2.2
Register Configuration
Table 8.4 shows the port 1 register configuration.
Table 8.4
Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 1 data direction register
P1DDR
W
H'00
H'FFB0
Port 1 data register
P1DR
R/W
H'00
H'FFB2
Port 1 MOS pull-up control
register
P1PCR
R/W
H'00
H'FFAC
Note:
*
Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 1 pins are address outputs, regardless of the P1DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 1 pins are address outputs or PWM outputs when P1DDR bits are set
to 1, and input ports when cleared to 0.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 1 pins are output ports or PWM outputs when P1DDR bits are set to 1,
and input ports when cleared to 0.
Rev. 4.00 Sep 27, 2006 page 222 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Port 1 Data Register (P1DR)
Bit
Initial value
R/W
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read directly,
regardless of the actual pin states. If a port 1 read is performed while P1DDR bits are cleared to 0,
the pin states are read.
P1DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 1 MOS Pull-Up Control Register (P1PCR)
Bit
7
6
5
4
3
2
1
0
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1PCR is an 8-bit readable/writable register that controls the port 1 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3, the MOS input pull-up is turned on when a P1PCR bit is set to 1 while the
corresponding P1DDR bit is cleared to 0 (input port setting).
P1PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 223 of 1130
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Section 8 I/O Ports
8.2.3
Pin Functions in Each Mode
Mode 1
In mode 1, port 1 pins automatically function as address outputs. The port 1 pin functions are
shown in figure 8.2.
A7 (Output)
A6 (Output)
A5 (Output)
Port 1
A4 (Output)
A3 (Output)
A2 (Output)
A1 (Output)
A0 (Output)
Figure 8.2 Port 1 Pin Functions (Mode 1)
Modes 2 and 3 (EXPE = 1)
In modes 2 and 3 (when EXPE = 1), port 1 pins function as address outputs, PWM outputs, or
input ports, and input or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set
to 1, the corresponding pin functions as an address output or PWM output, and when cleared to 0,
as an input port.
The port 1 pin functions are shown in figure 8.3.
Rev. 4.00 Sep 27, 2006 page 224 of 1130
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Section 8 I/O Ports
Port 1
When P1DDR = 1
and PWOERA = 0
When P1DDR = 0
When P1DDR = 1
and PWOERA = 1
A7 (Output)
P17 (Input)
PW7 (Output)
A6 (Output)
P16 (Input)
PW6 (Output)
A5 (Output)
P15 (Input)
PW5 (Output)
A4 (Output)
P14 (Input)
PW4 (Output)
A3 (Output)
P13 (Input)
PW3 (Output)
A2 (Output)
P12 (Input)
PW2 (Output)
A1 (Output)
P11 (Input)
PW1 (Output)
A0 (Output)
P10 (Input)
PW0 (Output)
Figure 8.3 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 1 pins function as PWM outputs or I/O ports, and input
or output can be specified on a bit-by-bit basis. When a bit in P1DDR is set to 1, the
corresponding pin functions as a PWM output or output port, and when cleared to 0, as an input
port.
The port 1 pin functions are shown in figure 8.4.
Port 1
P1n: Input pin when P1DDR = 0,
output pin when P1DDR = 1
and PWOERA = 0
When P1DDR = 1
and PWOERA = 1
P17 (I/O)
PW7 (Output)
P16 (I/O)
PW6 (Output)
P15 (I/O)
PW5 (Output)
P14 (I/O)
PW4 (Output)
P13 (I/O)
PW3 (Output)
P12 (I/O)
PW2 (Output)
P11 (I/O)
PW1 (Output)
P10 (I/O)
PW0 (Output)
Figure 8.4 Port 1 Pin Functions (Modes 2 and 3 (EXPE = 0))
Rev. 4.00 Sep 27, 2006 page 225 of 1130
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Section 8 I/O Ports
8.2.4
MOS Input Pull-Up Function
Port 1 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis.
When a P1DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P1PCR bit to 1 turns
on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.5 summarizes the MOS input pull-up states.
Table 8.5
MOS Input Pull-Up States (Port 1)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1
Off
Off
Off
Off
2, 3
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
8.3
Port 2
8.3.1
Overview
Port 2 is an 8-bit I/O port. Port 2 pins also function as address bus output pins (A15 to A8), 8-bit
PWM output pins (PW15 to PW8) (H8S/2148 Group and H8S/2147N only), and the timer
connection output pin (CBLANK) (H8S/2148 Group only). Port 2 functions change according to
the operating mode. Port 2 has a built-in MOS input pull-up function that can be controlled by
software.
Figure 8.5 shows the port 2 pin configuration.
Rev. 4.00 Sep 27, 2006 page 226 of 1130
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Section 8 I/O Ports
Port 2
Port 2 pins
Pin functions in mode 1
P27/A15/PW15/CBLANK
A15 (Output)
P26/A14/PW14
A14 (Output)
P25/A13/PW13
A13 (Output)
P24/A12/PW12
A12 (Output)
P23/A11/PW11
A11 (Output)
P22/A10/PW10
A10 (Output)
P21/A9/PW9
A9 (Output)
P20/A8/PW8
A8 (Output)
Pin functions in modes 2 and 3 (EXPE = 1)
A15 (Output)/P27 (I/O)/PW15 (Output)/CBLANK (Output)
A14 (Output)/P26 (I/O)/PW14 (Output)
A13 (Output)/P25 (I/O)/PW13 (Output)
A12 (Output)/P24 (I/O)/PW12 (Output)
A11 (Output)/P23 (Input)/PW11 (Output)
A10 (Output)/P22 (Input)/PW10 (Output)
A9 (Output)/P21 (Input)/PW9 (Output)
A8 (Output)/P20 (Input)/PW8 (Output)
Pin functions in modes 2 and 3 (EXPE = 0)
P27 (I/O)/PW15 (Output)/CBLANK (Output)
P26 (I/O)/PW14 (Output)
P25 (I/O)/PW13 (Output)
P24 (I/O)/PW12 (Output)
P23 (I/O)/PW11 (Output)
P22 (I/O)/PW10 (Output)
P21 (I/O)/PW9 (Output)
P20 (I/O)/PW8 (Output)
Figure 8.5 Port 2 Pin Functions
Rev. 4.00 Sep 27, 2006 page 227 of 1130
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Section 8 I/O Ports
8.3.2
Register Configuration
Table 8.6 shows the port 2 register configuration.
Table 8.6
Port 2 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 2 data direction register
P2DDR
W
H'00
H'FFB1
Port 2 data register
P2DR
R/W
H'00
H'FFB3
Port 2 MOS pull-up control
register
P2PCR
R/W
H'00
H'FFAD
Note:
*
Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR)
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The address output pins maintain their output state in a transition to
software standby mode.
• Mode 1
The corresponding port 2 pins are address outputs, regardless of the P2DDR setting.
In hardware standby mode, the address outputs go to the high-impedance state.
• Modes 2 and 3 (EXPE = 1)
The corresponding port 2 pins are address outputs or PWM outputs when P2DDR bits are set
to 1, and input ports when cleared to 0. P27 to P24 are switched from address outputs to output
ports by setting the IOSE bit to 1.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
Rev. 4.00 Sep 27, 2006 page 228 of 1130
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Section 8 I/O Ports
• Modes 2 and 3 (EXPE = 0)
The corresponding port 2 pins are output ports or PWM outputs when P2DDR bits are set to 1,
and input ports when cleared to 0.
P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting.
Port 2 Data Register (P2DR)
Bit
Initial value
R/W
7
6
5
4
3
2
1
0
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20).
If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly,
regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0,
the pin states are read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 2 MOS Pull-Up Control Register (P2PCR)
Bit
7
6
5
4
3
2
1
0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2PCR is an 8-bit readable/writable register that controls the port 2 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3, the MOS input pull-up is turned on when a P2PCR bit is set to 1 while the
corresponding P2DDR bit is cleared to 0 (input port setting).
P2PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 229 of 1130
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Section 8 I/O Ports
8.3.3
Pin Functions in Each Mode
Mode 1
In mode 1, port 2 pins automatically function as address outputs. The port 2 pin functions are
shown in figure 8.6.
A15 (Output)
A14 (Output)
A13 (Output)
Port 2
A12 (Output)
A11 (Output)
A10 (Output)
A9 (Output)
A8 (Output)
Figure 8.6 Port 2 Pin Functions (Mode 1)
Modes 2 and 3 (EXPE = 1)
In modes 2 and 3 (when EXPE = 1), port 2 pins function as address outputs, PWM outputs, or I/O
ports, and input or output can be specified on a bit-by-bit basis. When a bit in P2DDR is set to 1,
the corresponding pin functions as an address output or PWM output, and when cleared to 0, as an
input port. P27 to P24 are switched from address outputs to output ports by setting the IOSE bit to
1. P27 can be used as an on-chip supporting module output pin regardless of the P27DDR setting,
but to ensure normal access to external space, P27 should not be set as an on-chip supporting
module output pin when port 2 pins are used as address output pins.
The port 2 pin functions are shown in figure 8.7.
Rev. 4.00 Sep 27, 2006 page 230 of 1130
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Section 8 I/O Ports
When P2DDR = 1
and PWOERB = 0
When P2DDR = 0
When P2DDR = 1
and PWOERB = 1
A15 (Output)/P27 (Output) P27 (Input)/CBLANK (Output) PW15 (Output)/CBLANK (Output)
Port 2
A14 (Output)/P26 (Output) P26 (Input)
PW14 (Output)
A13 (Output)/P25 (Output) P25 (Input)
PW13 (Output)
A12 (Output)/P24 (Output) P24 (Input)
PW12 (Output)
A11 (Output)
P23 (Input)
PW11 (Output)
A10 (Output)
P22 (Input)
PW10 (Output)
A9 (Output)
P21 (Input)
PW9 (Output)
A8 (Output)
P20 (Input)
PW8 (Output)
Figure 8.7 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 2 pins function as PWM outputs (P27 can also function
as the timer connection output (CBLANK)) or I/O ports, and input or output can be specified on a
bit-by-bit basis. When a bit in P2DDR is set to 1, the corresponding pin functions as a PWM
output or output port, and when cleared to 0, as an input port. P27 can be used as an on-chip
supporting module output pin regardless of the P27DDR setting.
The port 2 pin functions are shown in figure 8.8.
Port 2
P2n: Input pin when P2DDR = 0,
output pin when P2DDR = 1
and PWOERB = 0
When P2DDR = 1
and PWOERB = 1
P27 (I/O)/CBLANK (Output)
PW15 (Output)/CBLANK (Output)
P26 (I/O)
PW14 (Output)
P25 (I/O)
PW13 (Output)
P24 (I/O)
PW12 (Output)
P23 (I/O)
PW11 (Output)
P22 (I/O)
PW10 (Output)
P21 (I/O)
PW9 (Output)
P20 (I/O)
PW8 (Output)
Figure 8.8 Port 2 Pin Functions (Modes 2 and 3 (EXPE = 0))
Rev. 4.00 Sep 27, 2006 page 231 of 1130
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Section 8 I/O Ports
8.3.4
MOS Input Pull-Up Function
Port 2 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3, and can be specified as on or off on a bit-bybit basis.
When a P2DDR bit is cleared to 0 in mode 2 or 3, setting the corresponding P2PCR bit to 1 turns
on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.7 summarizes the MOS input pull-up states.
Table 8.7
MOS Input Pull-Up States (Port 2)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1
Off
Off
Off
Off
2, 3
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
Rev. 4.00 Sep 27, 2006 page 232 of 1130
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Section 8 I/O Ports
8.4
Port 3
8.4.1
Overview
Port 3 is an 8-bit I/O port. Port 3 pins also function as host data bus I/O pins (HDB7 to HDB0)
(H8S/2148 Group and H8S/2147N only), and as data bus I/O pins. Port 3 functions change
according to the operating mode. Port 3 has a built-in MOS input pull-up function that can be
controlled by software.
Figure 8.9 shows the port 3 pin configuration.
Port 3
Port 3 pins
Pin functions in modes 1, 2 and 3 (EXPE = 1)
P37/D15/HDB7
D15 (I/O)
P36/D14/HDB6
D14 (I/O)
P35/D13/HDB5
D13 (I/O)
P34/D12/HDB4
D12 (I/O)
P33/D11/HDB3
D11 (I/O)
P32/D10/HDB2
D10 (I/O)
P31/D9/HDB1
D9 (I/O)
P30/D8/HDB0
D8 (I/O)
Pin functions in modes 2 and 3 (EXPE = 0)
P37 (I/O)/HDB7 (I/O)
P36 (I/O)/HDB6 (I/O)
P35 (I/O)/HDB5 (I/O)
P34 (I/O)/HDB4 (I/O)
P33 (I/O)/HDB3 (I/O)
P32 (I/O)/HDB2 (I/O)
P31 (I/O)/HDB1 (I/O)
P30 (I/O)/HDB0 (I/O)
Figure 8.9 Port 3 Pin Functions
Rev. 4.00 Sep 27, 2006 page 233 of 1130
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Section 8 I/O Ports
8.4.2
Register Configuration
Table 8.8 shows the port 3 register configuration.
Table 8.8
Port 3 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 3 data direction register
P3DDR
W
H'00
H'FFB4
Port 3 data register
P3DR
R/W
H'00
H'FFB6
Port 3 MOS pull-up control
register
P3PCR
R/W
H'00
H'FFAE
Note:
*
Lower 16 bits of the address.
Port 3 Data Direction Register (P3DDR)
Bit
7
6
5
4
3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 1, 2, and 3 (EXPE = 1)
The input/output direction specified by P3DDR is ignored, and pins automatically function as
data I/O pins.
After a reset, and in hardware standby mode or software standby mode, the data I/O pins go to
the high-impedance state.
• Modes 2 and 3 (EXPE = 0)
The corresponding port 3 pins are output ports when P3DDR bits are set to 1, and input ports
when cleared to 0.
Rev. 4.00 Sep 27, 2006 page 234 of 1130
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Section 8 I/O Ports
Port 3 Data Register (P3DR)
7
6
5
4
3
2
1
0
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30).
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly,
regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0,
the pin states are read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 3 MOS Pull-Up Control Register (P3PCR)
Bit
7
6
5
4
3
2
0
1
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3PCR is an 8-bit readable/writable register that controls the port 3 built-in MOS input pull-ups
on a bit-by-bit basis.
In modes 2 and 3 (when EXPE = 0), the MOS input pull-up is turned on when a P3PCR bit is set
to 1 while the corresponding P3DDR bit is cleared to 0 (input port setting).
P3PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
The MOS input pull-up function cannot be used in slave mode (when the host interface is
enabled).
Rev. 4.00 Sep 27, 2006 page 235 of 1130
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Section 8 I/O Ports
8.4.3
Pin Functions in Each Mode
Modes 1, 2, and 3 (EXPE = 1)
In modes 1, 2, and 3 (when EXPE = 1), port 3 pins automatically function as data I/O pins. The
port 3 pin functions are shown in figure 8.10.
D15 (I/O)
D14 (I/O)
D13 (I/O)
Port 3
D12 (I/O)
D11(I/O)
D10 (I/O)
D9 (I/O)
D8 (I/O)
Figure 8.10 Port 3 Pin Functions (Modes 1, 2, and 3 (EXPE = 1))
Modes 2 and 3 (EXPE = 0)
In modes 2 and 3 (when EXPE = 0), port 3 functions as host interface data bus I/O pins (HDB7 to
HDB0) or as I/O ports. When the HI12E bit is set to 1 in SYSCR2 and a transition is made to
slave mode, port 3 functions as the host interface data bus. In slave mode, P3DR and P3DDR
should be cleared to H'00. When the HI12E bit is cleared to 0, port 3 functions as an I/O port, and
input or output can be specified on a bit-by-bit basis. When a bit in P3DDR is set to 1, the
corresponding pin functions as an output port, and when cleared to 0, as an input port.
The port 3 pin functions are shown in figure 8.11.
Rev. 4.00 Sep 27, 2006 page 236 of 1130
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Section 8 I/O Ports
P37 (I/O)/HDB7 (I/O)
P36 (I/O)/HDB6 (I/O)
P35 (I/O)/HDB5 (I/O)
P34 (I/O)/HDB4 (I/O)
Port 3
P33 (I/O)/HDB3 (I/O)
P32 (I/O)/HDB2 (I/O)
P31 (I/O)/HDB1 (I/O)
P30 (I/O)/HDB0 (I/O)
Figure 8.11 Port 3 Pin Functions (Modes 2 and 3 (EXPE = 0))
8.4.4
MOS Input Pull-Up Function
Port 3 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 2 and 3 (when EXPE = 0), and can be specified as on
or off on a bit-by-bit basis.
When a P3DDR bit is cleared to 0 in mode 2 or 3 (when EXPE = 0), setting the corresponding
P3PCR bit to 1 turns on the MOS input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.9 summarizes the MOS input pull-up states.
Table 8.9
MOS Input Pull-Up States (Port 3)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 3 (EXPE = 1) Off
Off
Off
Off
2, 3 (EXPE = 0)
Off
On/Off
On/Off
Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P3DDR = 0 and P3PCR = 1; otherwise off.
Rev. 4.00 Sep 27, 2006 page 237 of 1130
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Section 8 I/O Ports
8.5
Port 4
8.5.1
Overview
Port 4 is an 8-bit I/O port. Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0),
8-bit timer 0 and 1 (TMR0, TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1),
timer connection I/O pins (CSYNCI, HSYNCI, HSYNCO) (H8S/2148 Group only), SCI2 I/O pins
(TxD2, RxD2, SCK2), IrDA interface I/O pins (IrTxD, IrRxD), host interface output pins
(HIRQ12, HIRQ1, HIRQ11) (H8S/2148 Group and H8S/2147N only), and the IIC1 I/O pin
(SDA1) (option in H8S/2148 Group and H8S/2147N only). Port 4 pin functions are the same in all
operating modes.
Figure 8.12 shows the port 4 pin configuration.
Port 4 pins
P47 (I/O)/PWX1 (Output)
P46 (I/O)/PWX0 (Output)
P45 (I/O)/TMRI1 (Input)/HIRQ12 (Output)/CSYNCI (Input)
Port 4
P44 (I/O)/TMO1 (Output)/HIRQ1 (Output)/HSYNCO (Output)
P43 (I/O)/TMCI1 (Input)/HIRQ11 (Output)/HCYNCI (Input)
P42 (I/O)/TMRI0 (Input)/SCK2 (I/O)/SDA1 (I/O)
P41 (I/O)/TMO0 (Output)/RxD2 (Input)/IrRxD (Input)
P40 (I/O)/TMCI0 (Input)/TxD2 (Output)/IrTxD (Output)
Figure 8.12 Port 4 Pin Functions
8.5.2
Register Configuration
Table 8.10 shows the port 4 register configuration.
Table 8.10 Port 4 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 4 data direction register
P4DDR
W
H'00
H'FFB5
Port 4 data register
P4DR
R/W
H'00
H'FFB7
Note:
*
Lower 16 bits of the address.
Rev. 4.00 Sep 27, 2006 page 238 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Port 4 Data Direction Register (P4DDR)
Bit
7
6
5
4
3
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned.
When a bit in P4DDR is set to 1, the corresponding pin functions as an output port, and when
cleared to 0, as an input port.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. As 14-bit PWM and SCI2 are initialized in software standby mode, the
pin states are determined by the TMR0, TMR1, HIF, IIC1, P4DDR, and P4DR specifications.
Port 4 Data Register (P4DR)
Bit
7
6
5
4
3
2
1
0
P47DR
P46DR
P45DR
P44DR
P43DR
P42DR
P41DR
P40DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40).
If a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are read directly,
regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are cleared to 0,
the pin states are read.
P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.5.3
Pin Functions
Port 4 pins also function as 14-bit PWM output pins (PWX1, PWX0), 8-bit timer 0 and 1 (TMR0,
TMR1) I/O pins (TMCI0, TMRI0, TMO0, TMCI1, TMRI1, TMO1), timer connection I/O pins
(CSYNCI, HSYNCI, HSYNCO), SCI2 I/O pins (TxD2, RxD2, SCK2), IrDA interface I/O pins
Rev. 4.00 Sep 27, 2006 page 239 of 1130
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Section 8 I/O Ports
(IrTxD, IrRxD), host interface output pins (HIRQ12, HIRQ1, HIRQ11), and the IIC1 I/O pin
(SDA1). The port 4 pin functions are shown in table 8.11.
Table 8.11 Port 4 Pin Functions
Pin
Selection Method and Pin Functions
P47/PWX1
The pin function is switched as shown below according to the combination of
bit OEB in DACR of 14-bit PWM, and bit P47DDR.
OEB
0
P47DDR
Pin function
P46/PWX0
0
1
—
P47 input pin
P47 output pin
PWX1 output pin
The pin function is switched as shown below according to the combination of
bit OEA in DACR of 14-bit PWM, and bit P46DDR.
OEA
0
P46DDR
Pin function
P45/TMRI1/
HIRQ12/CSYNCI
1
1
0
1
—
P46 input pin
P46 output pin
PWX0 output pin
The pin function is switched as shown below according to the combination of
the operating mode and bit P45DDR.
P45DDR
0
Operating
mode
—
Not slave mode
Slave mode
P45 input pin
P45 output pin
HIRQ12 output pin
Pin function
1
TMRI1 input pin, CSYNCI input pin
When bits CCLR1 and CCLR0 in TCR1 of TMR1 are set to 1, this pin is used
as the TMRI1 input pin. It can also be used as the CSYNCI input pin.
P44/TMO1/
HIRQ1/HSYNCO
The pin function is switched as shown below according to the combination of
the operating mode, bits OS3 to OS0 in TCSR of TMR1, bit HOE in TCONRO
of the timer connection function, and bit P44DDR.
HOE
0
OS3 to OS0
1
All 0
—
—
—
P44DDR
0
Operating
mode
—
Not slave
mode
Slave
mode
—
—
P44
input pin
P44
output pin
HIRQ1
output pin
TMO1
output pin
HSYNCO
output pin
Pin function
Rev. 4.00 Sep 27, 2006 page 240 of 1130
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1
Not all 0
Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P43/TMCI1/
HIRQ11/HSYNCI
The pin function is switched as shown below according to the combination of
the operating mode and bit P43DDR.
P43DDR
0
Operating
mode
—
Not slave mode
Slave mode
P43 input pin
P43 output pin
HIRQ11 output pin
Pin function
1
TMCI1 input pin, HSYNCI input pin
When an external clock is selected with bits CKS2 to CKS0 in TCR1 of TMR1,
this pin is used as the TMCI1 input pin. It can also be used as the HSYNCI
input pin.
P42/TMRI0/
SCK2/SDA1
The pin function is switched as shown below according to the combination of
bit ICE in ICCR of IIC1, bits CKE1 and CKE0 in SCR of SCI2, bit C/A in SMR
of SCI2, and bit P42DDR.
ICE
0
CKE1
0
C/A
Pin function
1
0
1
—
0
1
—
—
0
—
—
—
0
CKE0
P42DDR
1
0
0
1
P42
P42
SCK2
SCK2
SCK2
input pin output pin output pin output pin input pin
—
SDA1
I/O pin
TMRI0 input pin
When this pin is used as the SDA1 I/O pin, bits CKE1 and CKE0 in SCR of
SCI2 and bit C/A in SMR of SCI2 must all be cleared to 0. SDA1 is an NMOSonly output, and has direct bus drive capability.
When bits CCLR1 and CCLR0 in TCR0 of TMR0 are set to 1, this pin is used
as the TMRI0 input pin.
Rev. 4.00 Sep 27, 2006 page 241 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P41/TMO0/RxD2/ The pin function is switched as shown below according to the combination of
IrRxD
bits OS3 to OS0 in TCSR of TMR0, bit RE in SCR of SCI2 and bit P41DDR.
OS3 to OS0
All 0
RE
P41DDR
Pin function
Not all 0
0
1
0
0
1
—
—
P41
input pin
P41
output pin
RxD2/IrRxD
input pin
TMO0
output pin
When this pin is used as the TMO0 output pin, bit RE in SCR of SCI2 must be
cleared to 0.
P40/TMCI0/TxD2/ The pin function is switched as shown below according to the combination of
IrTxD
bit TE in SCR of SCI2 and bit P40DDR.
TE
0
P40DDR
Pin function
1
0
1
—
P40
input pin
P40
output pin
TxD2/IrTxD
output pin
TMCI0 input pin
When an external clock is selected with bits CKS2 to CKS0 in TCR0 of TMR0,
this pin is used as the TMCI0 input pin.
Rev. 4.00 Sep 27, 2006 page 242 of 1130
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Section 8 I/O Ports
8.6
Port 5
8.6.1
Overview
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0), and the
IIC0 I/O pin (SCL0) (option in H8S/2148 Group and H8S/2147N only). In the H8S/2148 Group
and H8S/2147N, P52 and SCK0 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain
output. Port 5 pin functions are the same in all operating modes.
Figure 8.13 shows the port 5 pin configuration.
Port 5 pins
P52 (I/O)/SCK0 (I/O)/SCL0 (I/O)
Port 5
P51 (I/O)/RxD0 (Input)
P50 (I/O)/TxD0 (Output)
Figure 8.13 Port 5 Pin Functions
8.6.2
Register Configuration
Table 8.12 shows the port 5 register configuration.
Table 8.12 Port 5 Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port 5 data direction register
P5DDR
W
H'F8
H'FFB8
Port 5 data register
P5DR
R/W
H'F8
H'FFBA
Note:
*
Lower 16 bits of the address.
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Section 8 I/O Ports
Port 5 Data Direction Register (P5DDR)
7
6
5
4
3
—
—
—
—
—
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
Bit
2
1
0
P52DDR P51DDR P50DDR
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are
reserved.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. As SCI0 is initialized, the pin states are determined by the IIC0 ICCR,
P5DDR, and P5DR specifications.
Port 5 Data Register (P5DR)
7
6
5
4
3
2
1
0
—
—
—
—
—
P52DR
P51DR
P50DR
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Bit
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50).
If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly,
regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0,
the pin states are read.
Bits 7 to 3 are reserved; they cannot be modified and are always read as 1.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 244 of 1130
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Section 8 I/O Ports
8.6.3
Pin Functions
Port 5 pins also function as SCI0 I/O pins (TxD0, RxD0, SCK0) and the IIC0 I/O pin (SCL0). The
port 5 pin functions are shown in table 8.13.
Table 8.13 Port 5 Pin Functions
Pin
Selection Method and Pin Functions
P52/SCK0/SCL0
The pin function is switched as shown below according to the combination of
bits CKE1 and CKE0 in SCR of SCI0, bit C/A in SMR of SCI0, bit ICE in ICCR
of IIC0, and bit P52DDR.
ICE
0
CKE1
0
C/A
Pin function
1
0
1
—
0
1
—
—
0
—
—
—
—
0
CKE0
P52DDR
1
0
0
1
P52
P52
SCK0
SCK0
SCK0
input pin output pin output pin output pin input pin
SCL0
I/O pin
When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of
SCI0 and bit C/A in SMR of SCI0 must all be cleared to 0.
SCL0 is an NMOS open-drain output, and has direct bus drive capability.
In the H8S/2148 Group and H8S/2147N, when set as the P52 output pin or
SCK0 output pin, this pin is an NMOS push-pull output.
P51/RxD0
The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI0 and bit P51DDR.
RE
P51DDR
Pin function
P50/TxD0
0
1
0
1
—
P51 input pin
P51 output pin
RxD0 input pin
The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI0 and bit P50DDR.
TE
P50DDR
Pin function
0
1
0
1
—
P50 input pin
P50 output pin
TxD0 output pin
Rev. 4.00 Sep 27, 2006 page 245 of 1130
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Section 8 I/O Ports
8.7
Port 6
8.7.1
Overview
Port 6 is an 8-bit I/O port. Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins
(FTOA, FTOB, FTIA to FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX) (H8S/2148
Group only), the timer Y (TMRY) input pin (TMIY), timer connection I/O pins (HFBACKI,
VSYNCI, VSYNCO, VFBACKI, CLAMPO) (H8S/2148 Group only), key-sense interrupt input
pins (KIN7 to KIN0), expansion A/D converter input pins (CIN7 to CIN0), and external interrupt
input pins (IRQ7, IRQ6). In the H8S/2148 Group and H8S/2147N, the port 6 input level can be
switched in four stages. Port 6 pin functions are the same in all operating modes.
Figure 8.14 shows the port 6 pin configuration.
Port 6 pins
P67 (I/O)/TMOX (Output)/KIN7 (Input)/CIN7 (Input)/IRQ7 (Input)
P66 (I/O)/FTOB (Output)/KIN6 (Input)/CIN6 (Input)/IRQ6 (Input)
P65 (I/O)/FTID (Input)/KIN5 (Input)/CIN5 (Input)
Port 6
P64 (I/O)/FTIC (Input)/KIN4 (Input)/CIN4 (Input)/CLAMPO (Output)
P63 (I/O)/FTIB (Input)/KIN3 (Input)/CIN3 (Input)/VFBACKI (Input)
P62 (I/O)/FTIA (Input)/KIN2 (Input)/CIN2 (Input)/VSYNCI (Input)/TMIY (Input)
P61 (I/O)/FTOA (Output)/KIN1 (Input)/CIN1 (Input)/VSYNCO (Output)
P60 (I/O)/FTCI (Input)/KIN0 (Input)/CIN0 (Input)/HFBACKI (Input)/TMIX (Input)
Figure 8.14 Port 6 Pin Functions
Rev. 4.00 Sep 27, 2006 page 246 of 1130
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Section 8 I/O Ports
8.7.2
Register Configuration
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name
Abbreviation R/W
Initial Value
1
Address*
Port 6 data direction register
P6DDR
W
H'00
H'FFB9
Port 6 data register
P6DR
R/W
H'00
Port 6 MOS pull-up control register
KMPCR
R/W
H'00
H'FFBB
2
H'FFF2*
System control register 2
SYSCR2
R/W
H'00
H'FF83
Notes: 1. Lower 16 bits of the address.
2. KMPCR has the same address as TICRR/TCORAY of TMRX/TMRY. To select
KMPCR, set the HIE bit to 1 in SYSCR and set the MSTP2 bit to 0 in MSTPCRL.
Port 6 Data Direction Register (P6DDR)
Bit
7
6
5
4
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 6. P6DDR cannot be read; if it is, an undefined value will be returned.
Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P6DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 247 of 1130
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Section 8 I/O Ports
Port 6 Data Register (P6DR)
7
6
5
4
3
2
1
0
P67DR
P66DR
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60).
If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly,
regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0,
the pin states are read.
P6DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 6 MOS Pull-Up Control Register (KMPCR)
Bit
7
6
5
4
3
2
1
0
KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KMPCR is an 8-bit readable/writable register that controls the port 6 built-in MOS input pull-ups
on a bit-by-bit basis.
The MOS input pull-up is turned on when a KMPCR bit is set to 1 while the corresponding
P6DDR bit is cleared to 0 (input port setting).
KMPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 248 of 1130
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Section 8 I/O Ports
System Control Register 2 (SYSCR2) (H8S/2148 Group and H8S/2147N Only)
Bit
7
6
KWUL1 KWUL0
5
4
3
2
1
0
P6PUE
—
SDE
CS4E
CS3E
HI12E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit readable/writable register that controls port 6 input level selection and the
operation of host interface functions.
Only bits 7, 6, and 5 are described here. See section 18.2.2, System Control Register 2 (SYSCR2),
for information on bits 4 to 0.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level setting
can be changed by software, using these bits. The setting of these bits also changes the input level
of the pin functions multiplexed with port 6.
Bit 7
Bit 6
KWUL1
KWUL0
0
1
Description
0
Standard input level is selected as port 6 input level
1
Input level 1 is selected as port 6 input level
0
Input level 2 is selected as port 6 input level
1
Input level 3 is selected as port 6 input level
(Initial value)
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings.
Bit 5
P6PUE
Description
0
Standard current specification is selected for port 6 MOS input pull-up function
(Initial value)
1
Current-limit specification is selected for port 6 MOS input pull-up function
Rev. 4.00 Sep 27, 2006 page 249 of 1130
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Section 8 I/O Ports
8.7.3
Pin Functions
Port 6 pins also function as the 16-bit free-running timer (FRT) I/O pins (FTOA, FTOB, FTIA to
FTID, FTCI), timer X (TMRX) I/O pins (TMOX, TMIX), the timer Y (TMRY) input pin (TMIY),
timer connection I/O pins (HFBACKI, VSYNCI, VSYNCO, VFBACKI, CLAMPO), key-sense
interrupt input pins (KIN7 to KIN0), comparator input pins (CIN7 to CIN0), and external interrupt
input pins (IRQ7, IRQ6). In the H8S/2148 Group and H8S/2147N, the port 6 input level can be
switched in four stages. The port 6 pin functions are shown in table 8.15.
Table 8.15 Port 6 Pin Functions
Pin
Selection Method and Pin Functions
P67/TMOX/IRQ7/
KIN7/CIN7
The pin function is switched as shown below according to the combination of
bits OS3 to OS0 in TCSR of TMRX and bit P67DDR.
OS3 to OS0
All 0
P67DDR
Pin function
Not all 0
0
1
—
P67 input pin
P67 output pin
TMOX output pin
IRQ7 input pin, KIN7 input pin, CIN7 input pin
This pin is used as the IRQ7 input pin when bit IRQ7E is set to 1 in IER.
It can always be used as the KIN7 or CIN7 input pin.
P66/FTOB/IRQ6/
KIN6/CIN6
The pin function is switched as shown below according to the combination of
bit OEB in TOCR of the FRT and bit P66DDR.
OEB
0
P66DDR
Pin function
1
0
1
—
P66 input pin
P66 output pin
FTOB output pin
IRQ6 input pin, KIN6 input pin, CIN6 input pin
This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER.
It can always be used as the KIN6 or CIN6 input pin.
P65/FTID/KIN5/
CIN5
P65DDR
Pin function
0
1
P65 input pin
P65 output pin
FTID input pin, KIN5 input pin, CIN5 input pin
This pin can always be used as the FTID, KIN5, or CIN5 input pin.
Rev. 4.00 Sep 27, 2006 page 250 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P64/FTIC/KIN4/
CIN4/CLAMPO
The pin function is switched as shown below according to the combination of
bit CLOE in TCONRO of the timer connection function and bit P64DDR.
CLOE
0
P64DDR
Pin function
1
0
1
—
P64
input pin
P64
output pin
CLAMPO
output pin
FTIC input pin, KIN4 input pin, CIN4 input pin
This pin can always be used as the FTIC, KIN4, or CIN4 input pin.
P63/FTIB/KIN3/
CIN3/VFBACKI
P63DDR
Pin function
0
1
P63 input pin
P63 output pin
FTIB input pin, VFBACKI input pin, KIN3 input pin,
CIN3 input pin
This pin can always be used as the FTIB, KIN3, CIN3, or VFBACKI input pin.
P62/FTIA/TMIY/
KIN2/CIN2/
VSYNCI
P62DDR
Pin function
0
1
P62 input pin
P62 output pin
FTIA input pin, VSYNCI input pin, TMIY input pin,
KIN2 input pin, CIN2 input pin
This pin can always be used as the FTIA, TMIY, KIN2, CIN2, or VSYNCI input
pin.
P61/FTOA/KIN1/
CIN1/VSYNCO
The pin function is switched as shown below according to the combination of
bit OEA in TOCR of the FRT, bit VOE in TCONRO of the timer connection
function, and bit P61DDR.
VOE
0
OEA
P61DDR
Pin function
0
1
1
0
0
1
—
—
P61
input pin
P61
output pin
FTOA
output pin
VSYNCO
output pin
KIN1 input pin, CIN1 input pin
When this pin is used as the VSYNCO pin, bit OEA in TOCR of the FRT must
be cleared to 0.
This pin can always be used as the KIN1 or CIN1 input pin.
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P60/FTCI/TMIX/
KIN0/CIN0/
HFBACKI
P60DDR
Pin function
0
1
P60 input pin
P60 output pin
FTCI input pin, HFBACKI input pin, TMIX input pin,
KIN0 input pin, CIN0 input pin
This pin is used as the FTCI input pin when an external clock is selected with
bits CKS1 and CKS0 in TCR of the FRT.
It can always be used as the TMIX, KIN0, CIN0, or HFBACKI input pin.
8.7.4
MOS Input Pull-Up Function
Port 6 has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in any operating mode, and can be specified as on or off on a
bit-by-bit basis.
When a P6DDR bit is cleared to 0, setting the corresponding KMPCR bit to 1 turns on the MOS
input pull-up for that pin. The MOS input pull-up current specification can be changed by means
of the P6PUE bit. When a pin is designated as an on-chip supporting module output pin, the MOS
input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.16 summarizes the MOS input pull-up states.
Table 8.16 MOS Input Pull-Up States (Port 6)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 3
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P6DDR = 0 and KMPCR = 1; otherwise off.
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Section 8 I/O Ports
8.8
Port 7
8.8.1
Overview
Port 7 is an 8-bit input port. Port 7 pins also function as the A/D converter analog input pins (AN0
to AN7) and D/A converter analog output pins (DA0, DA1). Port 7 functions are the same in all
operating modes.
Figure 8.15 shows the port 7 pin configuration.
Port 7 pins
P77 (Input)/AN7 (Input)/DA1 (Output)
P76 (Input)/AN6 (Input)/DA0 (Output)
P75 (Input)/AN5 (Input)
P74 (Input)/AN4 (Input)
Port 7
P73 (Input)/AN3 (Input)
P72 (Input)/AN2 (Input)
P71 (Input)/AN1 (Input)
P70 (Input)/AN0 (Input)
Figure 8.15 Port 7 Pin Functions
8.8.2
Register Configuration
Table 8.17 shows the port 7 register configuration. Port 7 is an input-only port, and does not have
a data direction register or data register.
Table 8.17 Port 7 Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port 7 input data register
P7PIN
R
Undefined
2
H'FFBE*
Notes: 1. Lower 16 bits of the address.
2. P7PIN has the same address as PBDDR.
Rev. 4.00 Sep 27, 2006 page 253 of 1130
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Section 8 I/O Ports
Port 7 Input Data Register (P7PIN)
7
Bit
6
P77PIN P76PIN
5
P75PIN
4
3
2
P74PIN P73PIN P72PIN
1
0
P71PIN P70PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note: * Determined by the state of pins P77 to P70.
When a P7PIN read is performed, the pin states are always read.
P7PIN has the same address as PBDDR; if a write is performed, data will be written into PBDDR
and the port B setting will be changed.
8.8.3
Pin Functions
Port 7 pins also function as the A/D converter analog input pins (AN0 to AN7) and D/A converter
analog output pins (DA0, DA1).
Rev. 4.00 Sep 27, 2006 page 254 of 1130
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Section 8 I/O Ports
8.9
Port 8
8.9.1
Overview
Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the
IIC1 I/O pin (SCL1) (option in H8S/2148 Group and H8S/2147N only), HIF I/O pins (CS2,
GA20, HA0, HIFSD) (H8S/2148 Group and H8S/2147N only), and external interrupt input pins
(IRQ5 to IRQ3). Port 8 pin functions are the same in all operating modes. Figure 8.16 shows the
port 8 pin configuration.
Port 8 pins
P86 (I/O)/IRQ5 (Input)/SCK1 (I/O)/SCL1 (I/O)
P85 (I/O)/IRQ4 (Input)/RxD1 (Input)
P84 (I/O)/IRQ3 (Input)/TxD1 (Output)
Port 8
P83 (I/O)
P82 (I/O)/HIFSD (Input)
P81 (I/O)/CS2 (Input)/GA20 (Output)
P80 (I/O)/HA0 (Input)
Figure 8.16 Port 8 Pin Functions
8.9.2
Register Configuration
Table 8.18 summarizes the port 8 registers.
Table 8.18 Port 8 Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port 8 data direction register
P8DDR
W
H'80
2
H'FFBD*
Port 8 data register
P8DR
R/W
H'80
H'FFBF
Notes: 1. Lower 16 bits of the address.
2. P8DDR has the same address as PBPIN.
Rev. 4.00 Sep 27, 2006 page 255 of 1130
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Section 8 I/O Ports
Port 8 Data Direction Register (P8DDR)
Bit
7
—
6
5
4
3
2
1
0
P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
W
W
W
W
W
W
W
P8DDR is a 7-bit write-only register, the individual bits of which specify input or output for the
pins of port 8. P8DDR has the same address as PBPIN, and if read, the port B state will be
returned.
Setting a P8DDR bit to 1 makes the corresponding port 8 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P8DDR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port 8 Data Register (P8DR)
Bit
7
6
5
4
3
2
1
0
—
P86DR
P85DR
P84DR
P83DR
P82DR
P81DR
P80DR
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P8DR is a 7-bit readable/writable register that stores output data for the port 8 pins (P86 to P80). If
a port 8 read is performed while P8DDR bits are set to 1, the P8DR values are read directly,
regardless of the actual pin states. If a port 8 read is performed while P8DDR bits are cleared to 0,
the pin states are read.
P8DR is initialized to H'80 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.9.3
Pin Functions
Port 8 pins also function as SCI1 I/O pins (TxD1, RxD1, SCK1), the IIC1 I/O pin (SCL1), HIF
I/O pins (CS2, GA20, HA0, HIFSD), and external interrupt input pins (IRQ5 to IRQ3). The port 8
pin functions are shown in table 8.19.
Rev. 4.00 Sep 27, 2006 page 256 of 1130
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Section 8 I/O Ports
Table 8.19 Port 8 Pin Functions
Pin
Selection Method and Pin Functions
P86/IRQ5/SCK1/
SCL1
The pin function is switched as shown below according to the combination of
bits CKE1 and CKE0 in SCR of SCI1, bit C/A in SMR of SCI1, bit ICE in ICCR
of IIC1, and bit P86DDR.
ICE
0
CKE1
C/A
Pin function
1
0
1
—
0
1
—
—
0
—
—
—
—
0
CKE0
P86DDR
1
0
0
0
1
P86
P86
SCK1
SCK1
SCK1
input pin output pin output pin output pin input pin
SCL1
I/O pin
IRQ5 input pin
When the IRQ5E bit in IER is set to 1, this pin is used as the IRQ5 input pin.
When this pin is used as the SCL1 I/O pin, bits CKE1 and CKE0 in SCR of
SCI1 and bit C/A in SMR of SCI1 must all be cleared to 0. SCL1 is an NMOSonly output, and has direct bus drive capability.
P85/IRQ4/RxD1
The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI1 and bit P85DDR.
RE
P85DDR
Pin function
0
1
0
1
—
P85 input pin
P85 output pin
RxD1 input pin
IRQ4 input pin
When the IRQ4E bit in IER is set to 1, this pin is used as the IRQ4 input pin.
P84/IRQ3/TxD1
The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI1 and bit P84DDR.
TE
P84DDR
Pin function
0
1
0
1
—
P84 input pin
P84 output pin
TxD1 output pin
IRQ3 input pin
When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin.
Rev. 4.00 Sep 27, 2006 page 257 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P83
The pin function is switched as shown below according to bit P83DDR.
P83DDR
Pin function
P82/HIFSD
0
1
P83 input pin
P83 output pin
The pin function is switched as shown below according to the combination of
operating mode, bit SDE in SYSCR2, and bit P82DDR.
Operating
mode
Not slave mode
SDE
—
P82DDR
Pin function
P81/GA20/CS2
Slave mode
0
1
0
1
0
1
—
P82
input pin
P82
output pin
P82
input pin
P82
output pin
HIFSD
input pin
The pin function is switched as shown below according to the combination of
operating mode, bit CS2E in SYSCR, bit FGA20E in HICR of the HIF, and bit
P81DDR.
Operating
mode
Not slave mode
FGA20E
—
CS2E
—
P81DDR
Pin function
Slave mode
0
1
0
1
—
0
1
0
1
—
0
1
P81
input
pin
P81
output
pin
P81
input
pin
P81
output
pin
CS2
input
pin
P81
input
pin
GA20
output
pin
This pin should be used as the GA20 output pin or CS2 input pin only in mode
2 or 3 (EXPE = 0).
P80/HA0
The pin function is switched as shown below according to the combination of
operating mode and bit P80DDR.
Operating
mode
Not slave mode
P80DDR
Pin function
Slave mode
0
1
—
P80 input pin
P80 output pin
HA0 input pin
Rev. 4.00 Sep 27, 2006 page 258 of 1130
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Section 8 I/O Ports
8.10
Port 9
8.10.1
Overview
Port 9 is an 8-bit I/O port. Port 9 pins also function as external interrupt input pins (IRQ0 to
IRQ2), the A/D converter external trigger input pin (ADTRG), host interface input pins (ECS2,
CS1, IOW, IOR) (H8S/2148 Group and H8S/2147N only), the IIC0 I/O pin (SDA0) (option in
H8S/2148 Group and H8S/2147N only), the subclock input pin (EXCL), bus control signal I/O
pins (AS/IOS, RD, HWR, LWR, WAIT), and the system clock (φ) output pin. In H8S/2148 Group
and H8S/2147N, P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and
has direct bus drive capability.
Figure 8.17 shows the port 9 pin configuration.
Port 9
Port 9 pins
Pin functions in modes 1, 2 and 3 (EXPE = 1)
P97/WAIT/SDA0
WAIT (Input)/P97 (I/O)/SDA0 (I/O)
P96/φ/EXCL
φ (Output)/P96 (Input)/EXCL (Input)
P95/AS/IOS/CS1
AS (Output)/IOS (Output)
P94/HWR/IOW
HWR (Output)
P93/RD/IOR
RD (Output)
P92/IRQ0
P92 (I/O)/IRQ0 (Input)
P91/IRQ1
P91 (I/O)/IRQ1 (Input)
P90/LWR/IRQ2/ADTRG/ECS2
P90 (I/O)/LWR (Output)/IRQ2 (Input)/ADTRG (Input)
Pin functions in modes 2 and 3 (EXPE = 0)
P97 (I/O)/SDA0 (I/O)
P96 (Input)/φ (Output)/EXCL (Input)
P95 (I/O)/CS1 (Input)
P94 (I/O)/IOW (Input)
P93 (I/O)/IOR (Input)
P92 (I/O)/IRQ0 (Input)
P91 (I/O)/IRQ1 (Input)
P90 (I/O)/IRQ2 (Input)/ADTRG (Input)/ECS2 (Input)
Figure 8.17 Port 9 Pin Functions
Rev. 4.00 Sep 27, 2006 page 259 of 1130
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Section 8 I/O Ports
8.10.2
Register Configuration
Table 8.20 summarizes the port 9 registers.
Table 8.20 Port 9 Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port 9 data direction register
P9DDR
W
H'40/H'00*
H'FFC0
Port 9 data register
P9DR
R/W
H'00
2
H'FFC1
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port 9 Data Direction Register (P9DDR)
Bit
7
6
5
4
3
2
1
0
P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR
Mode 1
Initial value
0
1
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Modes 2 and 3
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P9DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 9. P9DDR cannot be read; if it is, an undefined value will be returned.
P9DDR is initialized to H'40 (mode 1) or H'00 (modes 2 and 3) by a reset and in hardware standby
mode. It retains its prior state in software standby mode.
• Modes 1, 2 and 3 (EXPE = 1)
Pin P97 functions as a bus control input (WAIT), the IIC0 I/O pin (SDA0), or an I/O port,
according to the wait mode setting. When P97 functions as an I/O port, it becomes an output
port when P97DDR is set to 1, and an input port when P97DDR is cleared to 0.
Pin P96 functions as the φ output pin when P96DDR is set to 1, and as the subclock input
(EXCL) or an input port when P96DDR is cleared to 0.
Pins P95 to P93 automatically become bus control outputs (AS/IOS, HWR, RD), regardless of
the input/output direction indicated by P95DDR to P93DDR.
Pins P92 and P91 become output ports when P92DDR and P91DDR are set to 1, and input
ports when P92DDR and P91DDR are cleared to 0.
Rev. 4.00 Sep 27, 2006 page 260 of 1130
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Section 8 I/O Ports
When the ABW bit in WSCR is cleared to 0, pin P90 becomes a bus control output (LWR),
regardless of the input/output direction indicated by P90DDR. When the ABW bit is 1, pin P90
becomes an output port if P90DDR is set to 1, and an input port if P90DDR is cleared to 0.
• Modes 2 and 3 (EXPE = 0)
When the corresponding P9DDR bits are set to 1, pin P96 functions as the φ output pin and
pins P97 and P95 to P90 become output ports. When P9DDR bits are cleared to 0, the
corresponding pins become input ports.
Port 9 Data Register (P9DR)
Bit
7
6
5
4
3
2
1
0
P97DR
P96DR
P95DR
P94DR
P93DR
P92DR
P91DR
P90DR
Initial value
0
—*
0
0
0
0
0
0
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Determined by the state of pin P96.
P9DR is an 8-bit readable/writable register that stores output data for the port 9 pins (P97 to P90).
With the exception of P96, if a port 9 read is performed while P9DDR bits are set to 1, the P9DR
values are read directly, regardless of the actual pin states. If a port 9 read is performed while
P9DDR bits are cleared to 0, the pin states are read.
P9DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
8.10.3
Pin Functions
Port 9 pins also function as external interrupt input pins (IRQ0 to IRQ2), the A/D converter trigger
input pin (ADTRG), HIF input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin (SDA0), the
subclock input pin (EXCL), bus control signal I/O pins (AS/IOS, RD, HWR, LWR, WAIT), and
the system clock (φ) output pin. The pin functions differ between the mode 1, 2, and 3 (EXPE = 1)
expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The port 9 pin functions
are shown in table 8.21.
Rev. 4.00 Sep 27, 2006 page 261 of 1130
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Section 8 I/O Ports
Table 8.21 Port 9 Pin Functions
Pin
Selection Method and Pin Functions
P97/WAIT/SDA0
The pin function is switched as shown below according to the combination of
operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR.
Operating
mode
Modes 1, 2, 3 (EXPE = 1)
WMS1
0
ICE
P97DDR
Pin function
Modes 2, 3 (EXPE = 0)
1
0
1
—
—
0
1
0
1
—
—
0
1
—
P97
input
pin
P97
output
pin
SDA0
I/O pin
WAIT
input
pin
P97
input
pin
P97
output
pin
SDA0
I/O pin
When this pin is set as the P97 output pin in the H8S/2148 Group and
H8S/2147N, it is an NMOS push-pull output. SDA0 is an NMOS open-drain
output, and has direct bus drive capability.
P96/φ/EXCL
The pin function is switched as shown below according to the combination of
bit EXCLE in LPWRCR and bit P96DDR.
P96DDR
0
EXCLE
Pin function
1
0
1
0
P96 input pin
EXCL input pin
φ output pin
When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.
P95/AS/IOS/CS1
The pin function is switched as shown below according to the combination of
operating mode, bit IOSE in SYSCR, bit HI12E in SYSCR2, and bit P95DDR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
HI12E
—
P95DDR
IOSE
Pin function
Modes 2, 3 (EXPE = 0)
0
—
1
0
1
—
0
1
—
—
—
AS
output pin
IOS
output pin
P95
input pin
P95
output pin
CS1
input pin
Rev. 4.00 Sep 27, 2006 page 262 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P94/HWR/IOW
The pin function is switched as shown below according to the combination of
operating mode, bit HI12E in SYSCR2, and bit P94DDR.
Operating
mode
—
P94DDR
—
0
1
—
HWR
output pin
P94
input pin
P94
output pin
IOW
input pin
0
1
The pin function is switched as shown below according to the combination of
operating mode, bit HI12E in SYSCR2, and bit P93DDR.
Operating
mode
HI12E
P93DDR
Pin function
P92/IRQ0
Modes 2, 3 (EXPE = 0)
HI12E
Pin function
P93/RD/IOR
Modes 1, 2, 3
(EXPE = 1)
P92DDR
Pin function
Modes 1, 2, 3
(EXPE = 1)
Modes 2, 3 (EXPE = 0)
—
0
1
—
0
1
—
RD output pin
P93 input pin
P93 output pin
IOR input pin
0
1
P92 input pin
P92 output pin
IRQ0 input pin
When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin.
P91/IRQ1
P91DDR
Pin function
0
1
P91 input pin
P91 output pin
IRQ1 input pin
When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin.
Rev. 4.00 Sep 27, 2006 page 263 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
P90/LWR/IRQ2/
ADTRG/ECS2
The pin function is switched as shown below according to the combination of
operating mode, bit ABW in WSCR, bits HI12E and CS2E in SYSCR2, bit
FGA20E in HICR, and bit P90DDR.
Operating
mode
ABW
Modes 1, 2, 3 (EXPE = 1)
0
Modes 2, 3 (EXPE = 0)
1
—
HI12E
—
FGA20E
—
1
CS2E
—
1
P90DDR
Pin function
—
0
Any one 0
1
0
1
1
—
LWR
P90
P90
P90
P90
ECS2
output pin input pin output pin input pin output pin input pin
IRQ2 input pin, ADTRG input pin
When the IRQ2E bit in IER is set to 1 in mode 1, 2, or 3 (EXPE = 1) with the
ABW bit in WSCR set to 1, or in mode 2 and 3 (EXPE = 0), this pin is used as
the IRQ2 input pin.
When TRGS1 and TRGS0 in ADCR of the A/D converter are both set to 1, this
pin is used as the ADTRG input pin.
Rev. 4.00 Sep 27, 2006 page 264 of 1130
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Section 8 I/O Ports
8.11
Port A
8.11.1
Overview
Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins
(PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD) (H8S/2148 Group and H8S/2147N only),
key-sense interrupt input pins (KIN15 to KIN8), expansion A/D converter input pins (CIN15 to
CIN8), and address output pins (A23 to A16). Port A pin functions are the same in all operating
modes. Figure 8.18 shows the port A pin configuration.
Port A
Port A pins
Pin functions in modes 1 and 2 (EXPE = 0) and mode 3
PA7/A23/KIN15/CIN15/PS2CD
PA7 (I/O)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O)
PA6/A22/KIN14/CIN14/PS2CC
PA6 (I/O)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O)
PA5/A21/KIN13/CIN13/PS2BD
PA5 (I/O)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O)
PA4/A20/KIN12/CIN12/PS2BC
PA4 (I/O)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O)
PA3/A19/KIN11/CIN11/PS2AD
PA3 (I/O)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O)
PA2/A18/KIN10/CIN10/PS2AC
PA2 (I/O)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O)
PA1/A17/KIN9/CIN9
PA1 (I/O)/KIN9 (Input)/CIN9 (Input)
PA0/A16/KIN8/CIN8
PA0 (I/O)/KIN8 (Input)/CIN8 (Input)
Pin functions in mode 2 (EXPE = 1)
PA7 (I/O)/A23 (Output)/KIN15 (Input)/CIN15 (Input)/PS2CD (I/O)
PA6 (I/O)/A22 (Output)/KIN14 (Input)/CIN14 (Input)/PS2CC (I/O)
PA5 (I/O)/A21 (Output)/KIN13 (Input)/CIN13 (Input)/PS2BD (I/O)
PA4 (I/O)/A20 (Output)/KIN12 (Input)/CIN12 (Input)/PS2BC (I/O)
PA3 (I/O)/A19 (Output)/KIN11 (Input)/CIN11 (Input)/PS2AD (I/O)
PA2 (I/O)/A18 (Output)/KIN10 (Input)/CIN10 (Input)/PS2AC (I/O)
PA1 (I/O)/A17 (Output)/KIN9 (Input)/CIN9 (Input)
PA0 (I/O)/A16 (Output)/KIN8 (Input)/CIN8 (Input)
Figure 8.18 Port A Pin Functions
Rev. 4.00 Sep 27, 2006 page 265 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.11.2
Register Configuration
Table 8.22 summarizes the port A registers.
Table 8.22 Port A Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port A data direction register
PADDR
W
H'00
2
H'FFAB*
Port A output data register
PAODR
R/W
H'00
H'FFAA
Port A input data register
PAPIN
R
Undefined
2
H'FFAB*
Notes: 1. Lower 16 bits of the address.
2. PADDR and PAPIN have the same address.
Port A Data Direction Register (PADDR)
Bit
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A.
Setting a PADDR bit to 1 makes the corresponding port A pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Output Data Register (PAODR)
Bit
7
6
5
4
3
2
1
0
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to
PA0). PAODR can always be read or written to, regardless of the contents of PADDR.
Rev. 4.00 Sep 27, 2006 page 266 of 1130
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Section 8 I/O Ports
PAODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Input Data Register (PAPIN)
Bit
7
6
5
4
3
2
1
0
PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note:
*
Determined by the state of pins PA7 to PA0.
Reading PAPIN always returns the pin states.
8.11.3
Pin Functions
Port A pins also function as keyboard buffer controller I/O pins (PS2AC, PS2AD, PS2BC,
PS2BD, PS2CC, PS2CD), key-sense interrupt input pins (KIN15 to KIN8), expansion A/D
converter input pins (CIN15 to CIN8), and address output pins (A23 to A16). The port A pin
functions are shown in table 8.23.
Table 8.23 Port A Pin Functions
Pin
Selection Method and Pin Functions
PA7/A23/PS2CD/
KIN15/CIN15
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA7DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
PA7DDR
IOSE
Pin function
0
0
Mode 2 (EXPE = 1)
1
1
—
0
0
1
1
—
—
—
—
—
0
1
—
PA7
input
pin
PA7
output
pin
PS2CD
output
pin
PA7
input
pin
A23
output
pin
PA7
output
pin
PS2CD
output
pin
KIN15 input pin, CIN15 input pin, PS2CD input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2CD, KIN15, or CIN15 input pin.
Rev. 4.00 Sep 27, 2006 page 267 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Pin
Selection Method and Pin Functions
PA6/A22/PS2CC/
KIN14/CIN14
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR2H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA6DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
0
Mode 2 (EXPE = 1)
1
0
1
PA6DDR
0
1
—
0
IOSE
—
—
—
—
0
1
—
PA6
input
pin
PA6
output
pin
PS2CC
output
pin
PA6
input
pin
A22
output
pin
PA6
output
pin
PS2CC
output
pin
Pin function
1
—
KIN14 input pin, CIN14 input pin, PS2CC input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2CC, KIN14, or CIN14 input pin.
PA5/A21/PS2BD/
KIN13/CIN13
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA5DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
0
Mode 2 (EXPE = 1)
1
0
1
PA5DDR
0
1
—
0
IOSE
—
—
—
—
0
1
—
PA5
input
pin
PA5
output
pin
PS2BD
output
pin
PA5
input
pin
A21
output
pin
PA5
output
pin
PS2BD
output
pin
Pin function
1
—
KIN13 input pin, CIN13 input pin, PS2BD input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2BD, KIN13, or CIN13 input pin.
Rev. 4.00 Sep 27, 2006 page 268 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
PA4/A20/PS2BC/
KIN12/CIN12
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR1H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA4DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
0
Mode 2 (EXPE = 1)
1
0
1
PA4DDR
0
1
—
0
IOSE
—
—
—
—
0
1
—
PA4
input
pin
PA4
output
pin
PS2BC
output
pin
PA4
input
pin
A20
output
pin
PA4
output
pin
PS2BC
output
pin
Pin function
1
—
KIN12 input pin, CIN12 input pin, PS2BC input pin
When the IICS bit in STCR is set to 1, this pin functions as a bus buffer. This
pin can always be used as the PS2BC, KIN12, or CIN12 input pin.
PA3/A19/PS2AD/
KIN11/CIN11
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA3DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
0
Mode 2 (EXPE = 1)
1
0
1
PA3DDR
0
1
—
0
IOSE
—
—
—
—
0
1
—
PA3
input
pin
PA3
output
pin
PS2AD
output
pin
PA3
input
pin
A19
output
pin
PA3
output
pin
PS2AD
output
pin
Pin function
1
—
KIN11 input pin, CIN11 input pin, PS2AD input pin
This pin can always be used as the PS2AD, KIN11, or CIN11 input pin.
Rev. 4.00 Sep 27, 2006 page 269 of 1130
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Section 8 I/O Ports
Pin
Selection Method and Pin Functions
PA2/A18/PS2AC/
KIN10/CIN10
The pin function is switched as shown below according to the combination of
operating mode, the KBIOE bit in KBCR0H of the keyboard buffer controller,
the IOSE bit in SYSCR, and bit PA2DDR.
Operating
mode
Modes 1, 2 (EXPE = 0), 3
KBIOE
0
Mode 2 (EXPE = 1)
1
0
1
PA2DDR
0
1
—
0
IOSE
—
—
—
—
0
1
—
PA2
input
pin
PA2
output
pin
PS2AC
output
pin
PA2
input
pin
A18
output
pin
PA2
output
pin
PS2AC
output
pin
Pin function
1
—
KIN10 input pin, CIN10 input pin, PS2AC input pin
This pin can always be used as the PS2AC, KIN10, or CIN10 input pin.
PA1/A17/KIN9/
CIN9
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA1DDR.
Operating
mode
Modes 1,
2 (EXPE = 0), 3
Mode 2 (EXPE = 1)
PA1DDR
0
1
0
IOSE
—
—
—
0
1
PA1
input pin
PA1
output pin
PA1
input pin
A17
output pin
PA1
output pin
Pin function
1
KIN9 input pin, CIN9 input pin
This pin can always be used as the KIN9 or CIN9 input pin.
PA0/A16/KIN8/
CIN8
The pin function is switched as shown below according to the combination of
operating mode, the IOSE bit in SYSCR, and bit PA0DDR.
Operating
mode
PA0DDR
IOSE
Pin function
Modes 1,
2 (EXPE = 0), 3
0
1
Mode 2 (EXPE = 1)
0
1
—
—
—
0
1
PA0
input pin
PA0
output pin
PA0
input pin
A16
output pin
PA0
output pin
KIN8 input pin, CIN8 input pin
This pin can always be used as the KIN8 or CIN8 input pin.
Rev. 4.00 Sep 27, 2006 page 270 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.11.4
MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in any operating mode, and can be specified as on or off on a
bit-by-bit basis.
When a PADDR bit is cleared to 0, setting the corresponding PAODR bit to 1 turns on the MOS
input pull-up for that pin. The MOS input pull-up for pins PA7 to PA4 is always off when IICS is
set to 1. When the keyboard buffer control pin function is selected for pins PA7 to PA2, the MOS
input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.24 summarizes the MOS input pull-up states.
Table 8.24 MOS Input Pull-Up States (Port A)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 3
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PADDR = 0 and PAODR = 1; otherwise off.
Rev. 4.00 Sep 27, 2006 page 271 of 1130
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Section 8 I/O Ports
8.12
Port B
8.12.1
Overview
Port B is an 8-bit I/O port. Port B pins also have HIF input/output pins (CS3, CS4, HIRQ3,
HIRQ4) (H8S/2148 Group and H8S/2147N only), and a data bus input/output function (as D7 to
D0). The pin functions depend on the operating mode.
Figure 8.19 shows the port B pin configuration.
Port B
Port B pins
Mode 1, modes 2 and 3 (EXPE = 1) when ABW = 0
PB7/D7
D7 (I/O)
PB6/D6
D6 (I/O)
PB5/D5
D5 (I/O)
PB4/D4
D4 (I/O)
PB3/D3/CS4
D3 (I/O)
PB2/D2/CS3
D2 (I/O)
PB1/D1/HIRQ4
D1 (I/O)
PB0/D0/HIRQ3
D0 (I/O)
Mode 1, modes 2 and 3 (EXPE = 1) when ABW = 1,
and mode 1, modes 2 and 3 (EXPE = 0)
PB7 (I/O)
PB6 (I/O)
PB5 (I/O)
PB4 (I/O)
PB3 (I/O)/CS4 (Input)
PB2 (I/O)/CS3 (Input)
PB1 (I/O)/HIRQ4 (Output)
PB0 (I/O)/HIRQ3 (Output)
Figure 8.19 Port B Pin Functions
Rev. 4.00 Sep 27, 2006 page 272 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.12.2
Register Configuration
Table 8.25 summarizes the port B registers.
Table 8.25 Port B Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
Port B data direction register
PBDDR
W
H'00
2
H'FFBE*
Port B output data register
PBODR
R/W
H'00
Port B input data register
PBPIN
R
Undefined
H'FFBC
3
H'FFBD*
Notes: 1. Lower 16 bits of the address.
2. PBDDR has the same address as P7PIN.
3. PBPIN has the same address as P8DDR.
Port B Data Direction Register (PBDDR)
Bit
7
6
5
4
3
2
1
0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR has the same address as P7PIN, and if read, the port 7 pin states will be
returned.
Setting a PBDDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 1, 2 and 3 (EXPE = 1)
When the ABW bit in WSCR is cleared to 0, port B pins automatically become data I/O pins
(D7 to D0), regardless of the input/output direction indicated by PBDDR. When the ABW bit
is 1, a port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if the bit is cleared to 0.
Data I/O pins go to the high-impedance state after a reset, and in hardware standby mode or
software standby mode.
Rev. 4.00 Sep 27, 2006 page 273 of 1130
REJ09B0327-0400
Section 8 I/O Ports
• Modes 2 and 3 (EXPE = 0)
A port B pin becomes an output port if the corresponding PBDDR bit is set to 1, and an input
port if the bit is cleared to 0.
Port B Output Data Register (PBODR)
Bit
7
6
5
4
3
2
1
0
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PBODR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBODR can always be read or written to, regardless of the contents of PBDDR.
PBODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port B Input Data Register (PBPIN)
Bit
7
6
5
4
3
2
1
0
PB7PIN PB6PIN PB5PIN PB4PIN PB3PIN PB2PIN PB1PIN PB0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note:
*
Determined by the state of pins PB7 to PB0.
Reading PBPIN always returns the pin states.
PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR
and the port 8 settings will change.
Rev. 4.00 Sep 27, 2006 page 274 of 1130
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Section 8 I/O Ports
8.12.3
Pin Functions
Port B pins also function as HIF input pins (CS3, CS4, HIRQ3, HIRQ4) [H8S/2148 Group and
H8S/2147N only] and data bus I/O pins (D7 to D0). The port B pin functions are shown in table
8.26.
Table 8.26 Port B Pin Functions
Pin
Selection Method and Pin Functions
PB7/D7
The pin function is switched as shown below according to the combination of
the operating mode, bit PB7DDR, and bit ABW in WSCR.
Operating
mode
ABW
PB7DDR
Pin function
PB6/D6
Modes 1, 2, 3
(EXPE = 1)
0
1
—
—
0
1
0
1
D7
I/O pin
PB7
input pin
PB7
output pin
PB7
input pin
PB7
output pin
The pin function is switched as shown below according to the combination of
the operating mode, bit PB6DDR, and bit ABW in WSCR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
Modes 2, 3
(EXPE = 0)
ABW
0
PB6DDR
—
0
1
0
1
D6
I/O pin
PB6
input pin
PB6
output pin
PB6
input pin
PB6
output pin
Pin function
PB5/D5
Modes 2, 3
(EXPE = 0)
1
—
The pin function is switched as shown below according to the combination of
the operating mode, bit PB5DDR, and bit ABW in WSCR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
Modes 2, 3
(EXPE = 0)
ABW
0
PB5DDR
—
0
1
0
1
D5
I/O pin
PB5
input pin
PB5
output pin
PB5
input pin
PB5
output pin
Pin function
1
—
Rev. 4.00 Sep 27, 2006 page 275 of 1130
REJ09B0327-0400
Section 8 I/O Ports
Pin
Selection Method and Pin Functions
PB4/D4
The pin function is switched as shown below according to the combination of
the operating mode, bit PB4DDR, and bit ABW in WSCR.
Operating
mode
0
PB4DDR
—
0
1
0
1
D4
I/O pin
PB4
input pin
PB4
output pin
PB4
input pin
PB4
output pin
1
—
The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and
bit PB3DDR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
HI12E
—
CS4E
—
ABW
0
PB3DDR
—
Pin function
PB2/D2/CS3
Modes 2, 3
(EXPE = 0)
ABW
Pin function
PB3/D3/CS4
Modes 1, 2, 3
(EXPE = 1)
D3
I/O pin
Modes 2, 3
(EXPE = 0)
Either cleared to 0
1
1
1
0
—
1
0
—
1
—
PB3
PB3
PB3
PB3
CS4
input pin output pin input pin output pin input pin
The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and
bit PB2DDR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
HI12E
—
CS3E
Either cleared to 0
1
—
—
—
ABW
0
PB2DDR
—
Pin function
Modes 2, 3
(EXPE = 0)
D2
I/O pin
Rev. 4.00 Sep 27, 2006 page 276 of 1130
REJ09B0327-0400
1
1
0
1
0
1
—
PB2
PB2
PB2
PB2
CS3
input pin output pin input pin output pin input pin
Section 8 I/O Ports
Pin
Selection Method and Pin Functions
PB1/D1/HIRQ4
The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS4E in SYSCR2, bit ABW in WSCR, and
bit PB1DDR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
HI12E
—
CS4E
PB0/D0/HIRQ3
Either cleared to 0
1
—
—
—
ABW
0
PB1DDR
—
Pin function
Modes 2, 3
(EXPE = 0)
D1
I/O pin
1
1
0
1
0
1
—
PB1
PB1
PB1
PB1
HIRQ4
input pin output pin input pin output pin output pin
The pin function is switched as shown below according to the combination of
the operating mode, bits HI12E and CS3E in SYSCR2, bit ABW in WSCR, and
bit PB0DDR.
Operating
mode
Modes 1, 2, 3
(EXPE = 1)
HI12E
—
CS3E
—
ABW
0
PB0DDR
—
Pin function
D0
I/O pin
Modes 2, 3
(EXPE = 0)
Either cleared to 0
1
1
0
1
—
1
0
—
1
—
PB0
PB0
PB0
PB0
HIRQ3
input pin output pin input pin output pin output pin
Rev. 4.00 Sep 27, 2006 page 277 of 1130
REJ09B0327-0400
Section 8 I/O Ports
8.12.4
MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS
input pull-up function can be used in modes 1, 2 and 3 (EXPE = 1) with the ABW bit in WSCR
set to 1, and in modes 2 and 3 (EXPE = 0), and can be specified as on or off on a bit-by-bit basis.
When a PBDDR bit is cleared to 0, setting the corresponding PBODR bit to 1 turns on the MOS
input pull-up for that pin. When a pin is designated as an on-chip supporting module output pin,
the MOS input pull-up is always off.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
prior state is retained in software standby mode.
Table 8.27 summarizes the MOS input pull-up states.
Table 8.27 MOS Input Pull-Up States (Port B)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 3 (EXPE = 1) with
ABW in WSCR = 0
Off
Off
Off
Off
On/Off
On/Off
1, 2, 3 (EXPE = 1) with
ABW in WSCR = 1, and
2, 3 (EXPE = 0)
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when PBDDR = 0 and PBODR = 1; otherwise off.
Rev. 4.00 Sep 27, 2006 page 278 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
Section 9 8-Bit PWM Timers
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
9.1
Overview
The H8/2148 Group has an on-chip pulse width modulation (PWM) timer module with sixteen
outputs. Sixteen output waveforms are generated from a common time base, enabling PWM
output with a high carrier frequency to be produced using pulse division. The PWM timer module
has sixteen 8-bit PWM data registers (PWDRs), and an output pulse with a duty cycle of 0 to
100% can be obtained as specified by PWDR and the port data register (P1DR or P2DR).
9.1.1
Features
The PWM timer module has the following features.
• Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20-MHz
operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output, and PWM output enable/disable control
Rev. 4.00 Sep 27, 2006 page 279 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
9.1.2
Block Diagram
Figure 9.1 shows a block diagram of the PWM timer module.
PWDR0
Comparator 1
PWDR1
P12/PW2
Comparator 2
PWDR2
P13/PW3
Comparator 3
PWDR3
P14/PW4
Comparator 4
PWDR4
Comparator 5
PWDR5
Comparator 6
PWDR6
Comparator 7
PWDR7
Comparator 8
PWDR8
P15/PW5
P16/PW6
P17/PW7
P20/PW8
P21/PW9
P22/PW10
Comparator 9
PWDR9
Comparator 10
PWDR10
Comparator 11
PWDR11
P24/PW12
Comparator 12
PWDR12
P25/PW13
Comparator 13
PWDR13
P26/PW14
Comparator 14
PWDR14
P27/PW15
Comparator 15
PWDR15
TCNT
Clock
selection
P23/PW11
PWDPRB
PWDPRA
PWOERB
PWOERA
P2DDR
P1DDR
P2DR
P1DR
Legend:
PWSL:
PWDR:
PWDPRA:
PWDPRB:
PWOERA:
PWOERB:
PCSR:
P1DDR:
P2DDR:
P1DR:
P2DR:
PWM register select
PWM data register
PWM data polarity register A
PWM data polarity register B
PWM output enable register A
PWM output enable register B
Peripheral clock select register
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
Module
data bus
φ/16
φ/8
φ/4
φ/2
φ
Internal clock
Figure 9.1 Block Diagram of PWM Timer Module
Rev. 4.00 Sep 27, 2006 page 280 of 1130
REJ09B0327-0400
Bus interface
Comparator 0
P11/PW1
Port/PWM output control
P10/PW0
PWSL
PCSR
Internal
data bus
Section 9 8-Bit PWM Timers
9.1.3
Pin Configuration
Table 9.1 shows the PWM output pin.
Table 9.1
Pin Configuration
Name
Abbreviation
I/O
Function
PWM output pin 0 to 15
PW0 to PW15
Output
PWM timer pulse output 0 to 15
9.1.4
Register Configuration
Table 9.2 lists the registers of the PWM timer module.
Table 9.2
PWM Timer Module Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
PWM register select
PWSL
R/W
H'20
H'FFD6
PWM data registers 0 to 15
PWDR0 to
PWDR15
R/W
H'00
H'FFD7
PWM data polarity register A
PWDPRA
R/W
H'00
H'FFD5
PWM data polarity register B
PWDPRB
R/W
H'00
H'FFD4
PWM output enable register A
PWOERA
R/W
H'00
H'FFD3
PWM output enable register B
PWOERB
R/W
H'00
H'FFD2
Port 1 data direction register
P1DDR
W
H'00
H'FFB0
Port 2 data direction register
P2DDR
W
H'00
H'FFB1
Port 1 data register
P1DR
R/W
H'00
H'FFB2
Port 2 data register
P2DR
R/W
H'00
H'FFB3
Peripheral clock select register
PCSR
R/W
H'00
H'FF82*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Note:
2
1. Lower 16 bits of the address.
2. Some registers in the 8-bit timer are assigned in the addresses as other registers. In
this case, register selection is performed by the FLSHE bit in the serial timer control
register (STCR).
Rev. 4.00 Sep 27, 2006 page 281 of 1130
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Section 9 8-Bit PWM Timers
9.2
Register Descriptions
9.2.1
PWM Register Select (PWSL)
Bit
7
6
PWCKE PWCKS
5
4
3
2
1
0
—
—
RS3
RS2
RS1
RS0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the
PWM data register.
PWSL is initialized to H'20 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,
together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the
PWM timer.
PWSL
PCSR
Bit 7
Bit 6
Bit 2
Bit 1
PWCKE
PWCKS
PWCKB
PWCKA
Description
0
—
—
—
Clock input is disabled
1
0
—
—
φ (system clock) is selected
1
0
0
φ/2 is selected
1
φ/4 is selected
0
φ/8 is selected
1
φ/16 is selected
1
(Initial value)
The PWM resolution, PWM conversion period, and carrier frequency depend on the selected
internal clock, and can be found from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
Thus, with a 20-MHz system clock (φ), the resolution, PWM conversion period, and carrier
frequency are as shown below.
Rev. 4.00 Sep 27, 2006 page 282 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz
Table 9.3
Internal Clock
Frequency
Resolution
PWM Conversion
Period
Carrier Frequency
φ
50 ns
12.8 µs
1250 kHz
φ/2
100 ns
25.6 µs
625 kHz
φ/4
200 ns
51.2 µs
312.5 kHz
φ/8
400 ns
102.4 µs
156.3 kHz
φ/16
800 ns
204.8 µs
78.1 kHz
Bit 5—Reserved: This bit is always read as 1 and cannot be modified.
Bit 4—Reserved: This bit is always read as 0 and cannot be modified.
Bits 3 to 0—Register Select (RS3 to RS0): These bits select the PWM data register.
Bit 3
Bit 2
Bit 1
Bit 0
RS3
RS2
RS1
RS0
Register Selection
0
0
0
0
PWDR0 selected
1
PWDR1 selected
1
1
0
1
1
0
0
1
1
0
1
0
PWDR2 selected
1
PWDR3 selected
0
PWDR4 selected
1
PWDR5 selected
0
PWDR6 selected
1
PWDR7 selected
0
PWDR8 selected
1
PWDR9 selected
0
PWDR10 selected
1
PWDR11 selected
0
PWDR12 selected
1
PWDR13 selected
0
PWDR14 selected
1
PWDR15 selected
Rev. 4.00 Sep 27, 2006 page 283 of 1130
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Section 9 8-Bit PWM Timers
9.2.2
PWM Data Registers (PWDR0 to PWDR15)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to
be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1
ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added
within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256
is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output
should be used.
PWDR is initialized to H'00 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
9.2.3
PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
PWDPRA
Bit
7
6
5
4
3
2
1
0
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
OS15
OS14
OS13
OS12
OS11
OS10
OS9
OS8
PWDPRB
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PWDPR is an 8-bit readable/writable register that controls the polarity of the PWM output.
Bits OS0 to OS15 correspond to outputs PW0 to PW15.
Rev. 4.00 Sep 27, 2006 page 284 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
PWDPR is initialized to H'00 by a reset and in hardware standby mode.
OS
Description
0
PWM direct output (PWDR value corresponds to high width of output)
1
PWM inverted output (PWDR value corresponds to low width of output)
9.2.4
PWM Output Enable Registers A and B (PWOERA and PWOERB)
(Initial value)
PWOERA
Bit
7
6
5
4
3
2
1
0
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PWOERB
Bit
OE15
OE14
OE13
OE12
OE11
OE10
OE9
OE8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PWOER is an 8-bit readable/writable register that switches between PWM output and port
output. Bits OE15 to OE0 correspond to outputs PW15 to PW0. To set a pin in the output state, a
setting in the port direction register is also necessary. Bits P17DDR to P10DDR correspond to
outputs PW7 to PW0, and bits P27DDR to P20DDR correspond to outputs PW15 to PW8.
PWOER is initialized to H'00 by a reset and in hardware standby mode.
DDR
OE
Description
0
0
Port input
1
Port input
0
Port output or PWM 256/256 output
1
PWM output (0 to 255/256 output)
1
(Initial value)
Rev. 4.00 Sep 27, 2006 page 285 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
9.2.5
Peripheral Clock Select Register (PCSR)
Bit
7
6
5
4
3
—
—
—
—
—
2
1
PWCKB PWCKA
0
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
—
PCSR is an 8-bit readable/writable register that selects the PWM timer input clock.
PCSR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 and 1—PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and
PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For
details, see section 9.2.1, PWM Register Select (PWSL).
Bit 0—Reserved: Do not set this bit to 1.
9.2.6
Port 1 Data Direction Register (P1DDR)
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port 1 on a bit-by-bit basis.
Port 1 pins are multiplexed with pins PW0 to PW7. The bit corresponding to a pin to be used for
PWM output should be set to 1.
For details on P1DDR, see section 8.2, Port 1.
Rev. 4.00 Sep 27, 2006 page 286 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
9.2.7
Port 2 Data Direction Register (P2DDR)
Bit
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port J on a bit-by-bit basis.
Port 2 pins are multiplexed with pins PW8 to PW15. The bit corresponding to a pin to be used for
PWM output should be set to 1.
For details on P2DDR, see section 8.3, Port 2.
9.2.8
Port 1 Data Register (P1DR)
Bit
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P1DR, see section 8.2, Port 1.
9.2.9
Port 2 Data Register (P2DR)
Bit
7
6
5
4
3
2
1
0
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P2DR, see section 8.3, Port 2.
Rev. 4.00 Sep 27, 2006 page 287 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
9.2.10
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 8-bit PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWM module stop mode.
MSTPCRH
Bit 3
MSTP11
Description
0
PWM module stop mode is cleared
1
PWM module stop mode is set
Rev. 4.00 Sep 27, 2006 page 288 of 1130
REJ09B0327-0400
(Initial value)
Section 9 8-Bit PWM Timers
9.3
Operation
9.3.1
Correspondence between PWM Data Register Contents and Output Waveform
The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16, as shown in table 9.4.
Table 9.4
Upper 4 Bits
0000
Duty Cycle of Basic Pulse
Basic Pulse Waveform (Internal)
0 1 2 3 4 5 6 7 8 9 A B C D E F 0
0001
0010
0011
0100
0101
0110
0111
..
.
1000
1001
1010
1011
1100
1101
1110
1111
Rev. 4.00 Sep 27, 2006 page 289 of 1130
REJ09B0327-0400
Section 9 8-Bit PWM Timers
The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in
table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the
resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are
0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same.
Table 9.5
Position of Pulses Added to Basic Pulses
Basic Pulse No.
Lower 4 Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
Yes
0010
Yes
0011
Yes
Yes
Yes
Yes
Yes
Yes
0100
Yes
Yes
0101
Yes
Yes
Yes
Yes
Yes
0110
Yes
Yes
Yes
Yes
Yes
Yes
0111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1000
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1001
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes
1010
Yes
Yes
Yes Yes Yes
Yes
Yes
Yes Yes Yes
1011
Yes
Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
1100
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
1101
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
1110
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
1111
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No additional pulse
Resolution width
Additional pulse provided
Additional pulse
Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000)
Rev. 4.00 Sep 27, 2006 page 290 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
Section 10 14-Bit PWM Timer (PWMX)
10.1
Overview
This LSI have an on-chip 14-bit pulse-width modulator (PWM) with two output channels.
Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
Both channels share the same counter (DACNT) and control register (DACR).
10.1.1
Features
The features of the 14-bit PWM (D/A) are listed below.
• The pulse is subdivided into multiple base cycles to reduce ripple.
• Two resolution settings and two base cycle settings are available
The resolution can be set equal to one or two system clock cycles. The base cycle can be set
equal to T × 64 or T × 256, where T is the resolution.
• Four operating rates
The two resolution settings and two base cycle settings combine to give a selection of four
operating rates.
Rev. 4.00 Sep 27, 2006 page 291 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of the PWM (D/A) module.
Internal clock
φ
Internal data bus
φ/2
Clock
Clock selection
Bus interface
Basic cycle
compare-match A
PWX0
Fine-adjustment
pulse addition A
PWX1
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Comparator
A
DADRA
Comparator
B
DADRB
Control logic
Basic cycle overflow
DACNT
DACR
Module data bus
Legend:
DACR:
DADRA:
DADRB:
DACNT:
PWM D/A control register ( 6 bits)
PWM D/A data register A (15 bits)
PWM D/A data register B (15 bits)
PWM D/A counter (14 bits)
Figure 10.1 PWM D/A Block Diagram
Rev. 4.00 Sep 27, 2006 page 292 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
10.1.3
Pin Configuration
Table 10.1 lists the pins used by the PWM (D/A) module.
Table 10.1 PWM Timer Input and Output Pins
Name
Abbr.
I/O
Function
PWM output pin 0
PWX0
Output
PWM output, channel A
PWM output pin 1
PWX1
Output
PWM output, channel B
10.1.4
Register Configuration
Table 10.2 lists the registers of the PWM (D/A) module.
Table 10.2 Register Configuration
Name
Abbreviation
R/W
Initial value
1
Address*
PWM D/A control register
DACR
R/W
H'30
PWM D/A data register A high
DADRAH
R/W
H'FF
H'FFA0*
2
H'FFA0*
PWM D/A data register A low
DADRAL
R/W
H'FF
PWM D/A data register B high
DADRBH
R/W
H'FF
PWM D/A data register B low
DADRBL
R/W
H'FF
PWM D/A counter high
DACNTH
R/W
H'00
H'FFA7*
2
H'FFA6*
PWM D/A counter low
DACNTL
R/W
H'03
H'FFA7*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
2
H'FFA1*
2
H'FFA6*
2
2
2
Notes: 1. Lower 16 bits of the address.
2. Registers in the 14-bit PWM timer are assigned to the same addresses as the other
registers. In this case, register selection is performed by the IICE bit in the serial timer
control register (STCR), and also the same addresses are shared by DADRAH and
DACR, and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT
or DADRB.
Rev. 4.00 Sep 27, 2006 page 293 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
10.2
Register Descriptions
10.2.1
PWM (D/A) Counter (DACNT)
DACNTH
DACNTL
Bit (CPU)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT (Counter)
7
6
5
4
3
2
1
0
8
9
10
11
12
13
—
—
— REGS
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
—
R/W
DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The
input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the
DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are
performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details.
DACNT functions as the time base for both PWM (D/A) channels. When a channel operates with
14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode, and by the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
Rev. 4.00 Sep 27, 2006 page 294 of 1130
REJ09B0327-0400
(Initial value)
Section 10 14-Bit PWM Timer (PWMX)
10.2.2
D/A Data Registers A and B (DADRA and DADRB)
DADRH
Bit (CPU)
Bit (Data)
DADRA
Initial value
DADRL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DADRB
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The CPU can read
and write the PWM (D/A) data register values, but since DADRA and DADRB are 16-bit
registers, data transfers between them and the CPU are performed using a temporary register
(TEMP). See section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM (D/A) data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution. To enable this operation, the data register must
be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
Rev. 4.00 Sep 27, 2006 page 295 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS
Description
0
Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1
Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
(Initial value)
DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
10.2.3
(Initial value)
PWM D/A Control Register (DACR)
7
6
5
4
3
2
1
0
TEST
PWME
—
—
OEB
OEA
OS
CKS
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Bit
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit
should be cleared to 0.
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Section 10 14-Bit PWM Timer (PWMX)
Bit 7
TEST
Description
0
PWM (D/A) in user state: normal operation
1
PWM (D/A) in test state: correct conversion results unobtainable
(Initial value)
Bit 6—PWM Enable (PWME): Starts or stops the PWM (D/A) counter (DACNT).
Bit 6
PWME
Description
0
DACNT operates as a 14-bit up-counter
1
DACNT halts at H'0003
(Initial value)
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Output Enable B (OEB): Enables or disables output on PWM (D/A) channel B.
Bit 3
OEB
Description
0
PWM (D/A) channel B output (at the PWX1 pin) is disabled
1
PWM (D/A) channel B output (at the PWX1 pin) is enabled
(Initial value)
Bit 2—Output Enable A (OEA): Enables or disables output on PWM (D/A) channel A.
Bit 2
OEA
Description
0
PWM (D/A) channel A output (at the PWX0 pin) is disabled
1
PWM (D/A) channel A output (at the PWX0 pin) is enabled
(Initial value)
Bit 1—Output Select (OS): Selects the phase of the PWM (D/A) output.
Bit 1
OS
Description
0
Direct PWM output
1
Inverted PWM output
(Initial value)
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Section 10 14-Bit PWM Timer (PWMX)
Bit 0—Clock Select (CKS): Selects the PWM (D/A) resolution. If the system clock (φ) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS
Description
0
Operates at resolution (T) = system clock cycle time (tcyc)
1
Operates at resolution (T) = system clock cycle time (tcyc) × 2
10.2.4
(Initial value)
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 14-bit PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWMX module stop mode.
MSTPCRH
Bit 3
MSTP11
Description
0
PWMX module stop mode is cleared
1
PWMX module stop mode is set
Rev. 4.00 Sep 27, 2006 page 298 of 1130
REJ09B0327-0400
(Initial value)
Section 10 14-Bit PWM Timer (PWMX)
10.3
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written and read as follows (taking the example of the CPU interface).
• Write
When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte
value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in
TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time using an MOV instruction (by word
access or two consecutive byte accesses), and the upper byte should always be accessed before the
lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is
accessed. Also note that a bit-manipulation instruction cannot be used to access these registers.
Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly.
Example 1: Write to DACNT
MOV.W R0, @DACNT
; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
; Transfer contents of DADRA to R0
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Section 10 14-Bit PWM Timer (PWMX)
Table 10.3 Read and Write Access Methods for 16-Bit Registers
Read
Write
Register Name
Word
Byte
Word
Byte
DADRA and DADRB
Yes
Yes
Yes
×
DACNT
Yes
×
Yes
×
Legend:
Yes: Permitted type of access. Word access includes successive byte accesses to the upper byte
(first) and lower byte (second).
×:
This type of access may give incorrect results.
Upper-Byte Write
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(
)
DACNTL
(
)
Lower-Byte Write
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(H'AA)
DACNTL
(H'57)
Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)
Rev. 4.00 Sep 27, 2006 page 300 of 1130
REJ09B0327-0400
Section 10 14-Bit PWM Timer (PWMX)
Upper-Byte Read
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(H'AA)
DACNTL
(H'57)
Lower-Byte Read
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(
)
DACNTL
(
)
Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT)
Rev. 4.00 Sep 27, 2006 page 301 of 1130
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Section 10 14-Bit PWM Timer (PWMX)
10.4
Operation
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1)
output pulses. Figure 10.4 shows the types of waveform output available.
1 conversion cycle
(T × 214 (= 16384))
tf
Basic cycle
(T × 64 or T × 256)
tL
Legend:
T: Resolution
m
TL = ∑ tLn (when OS = 0)
n=1
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 10.3 PWM D/A Operation
Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 10.4 indicates the range of DADR settings that give an output
waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
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Section 10 14-Bit PWM Timer (PWMX)
Table 10.4 Settings and Operation (Examples when φ = 10 MHz)
Resolution
T
CKS
(µs)
0
0.1
CFS
0
1
1
0.2
0
1
Note:
*
Base Conversion
Cycle
Cycle
(µs)
(µs)
6.4
25.6
12.8
51.2
1638.4
1638.4
3276.8
3276.8
Fixed DADR Bits
TL (if OS = 0)
TH (if OS = 1)
Bit Data
Precision
(Bits)
3 2 1 0
Conversion
Cycle*
(µs)
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14
1638.4
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
12
0 0
409.6
10
0 0 0 0
102.4
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14
1638.4
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
12
0 0
409.6
10
0 0 0 0
102.4
1. Always low (or high)
level output
(DADR = H'0001 to
H'03FD)
14
3276.8
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
12
0 0
819.2
10
0 0 0 0
204.8
1. Always low (or high)
level output
(DADR = H'0003 to
H'00FF)
14
3276.8
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
12
0 0
819.2
10
0 0 0 0
204.8
This column indicates the conversion cycle when specific DADR bits are fixed.
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Section 10 14-Bit PWM Timer (PWMX)
1. OS = 0 (DADR corresponds to TL)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tL1
tf2
tf255
tL2
tL3
tL255
tf256
tL256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL
Figure 10.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tL1
tf2
tL2
tf63
tL3
tL63
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tL1 + tL2 + tL3 + · · · + tL63 + tL64 = TL
Figure 10.4 (2) Output Waveform
Rev. 4.00 Sep 27, 2006 page 304 of 1130
REJ09B0327-0400
tf64
tL64
Section 10 14-Bit PWM Timer (PWMX)
2. OS = 1 (DADR corresponds to TH)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tH1
tf2
tf255
tH2
tH3
tH255
tf256
tH256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH
Figure 10.4 (3) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tH1
tf2
tH2
tf63
tH3
tH63
tf64
tH64
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tH1 + tH2 + tH3 + · · · + tH63 + tH64 = TH
Figure 10.4 (4) Output Waveform
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Section 10 14-Bit PWM Timer (PWMX)
Rev. 4.00 Sep 27, 2006 page 306 of 1130
REJ09B0327-0400
Section 11 16-Bit Free-Running Timer
Section 11 16-Bit Free-Running Timer
11.1
Overview
This LSI have a single-channel on-chip 16-bit free-running timer (FRT) module that uses a 16-bit
free-running counter as a time base. Applications of the FRT module include rectangular-wave
output (up to two independent waveforms), input pulse width measurement, and measurement of
external clock periods.
11.1.1
Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
 The free-running counter can be driven by an internal clock source (φ/2, φ/8, or φ/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
 Each comparator can generate an independent waveform.
• Four input capture channels
 The current count can be captured on the rising or falling edge (selectable) of an input
signal.
 The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
 The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
 Two compare-match interrupts, four input capture interrupts, and one overflow interrupt
can be requested independently.
• Special functions provided by automatic addition function
 The contents of OCRAR and OCRAF can be added to the contents of OCRA
automatically, enabling a periodic waveform to be generated without software intervention.
 The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling
input capture operations in this interval to be restricted.
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Section 11 16-Bit Free-Running Timer
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the free-running timer.
External
clock source
Internal
clock sources
φ/2
φ/8
φ/32
FTCI
Clock select
OCRA R/F (H/L)
+
Clock
OCRA (H/L)
Comparematch A
Comparator A
FTOA
Overflow
FTOB
Clear
Bus interface
FRC (H/L)
Module data bus
Comparator B
Comparematch B
OCRB (H/L)
Control
logic
Input capture
FTIA
ICRA (H/L)
ICRB (H/L)
FTIB
Internal
data bus
ICRC (H/L)
FTIC
ICRD (H/L)
FTID
+
Comparator M
Compare-match M
×1
×2
OCRDM L
TCSR
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend:
OCRA, B:
FRC:
ICRA, B, C, D:
TCSR:
Interrupt signals
Output compare register A, B (16 bits)
Free-running counter (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER: Timer interrupt enable register (8 bits)
TCR: Timer control register (8 bits)
TOCR: Timer output compare control
register (8 bits)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
Rev. 4.00 Sep 27, 2006 page 308 of 1130
REJ09B0327-0400
Section 11 16-Bit Free-Running Timer
11.1.3
Input and Output Pins
Table 11.1 lists the input and output pins of the free-running timer module.
Table 11.1 Free-Running Timer Input and Output Pins
Name
Abbreviation
I/O
Function
Counter clock input
FTCI
Input
FRC counter clock input
Output compare A
FTOA
Output
Output compare A output
Output compare B
FTOB
Output
Output compare B output
Input capture A
FTIA
Input
Input capture A input
Input capture B
FTIB
Input
Input capture B input
Input capture C
FTIC
Input
Input capture C input
Input capture D
FTID
Input
Input capture D input
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Section 11 16-Bit Free-Running Timer
11.1.4
Register Configuration
Table 11.2 lists the registers of the free-running timer module.
Table 11.2 Register Configuration
Initial Value
1
Address*
H'01
H'FF90
H'00
H'FF91
R/W
H'0000
H'FF92
OCRA
R/W
H'FFFF
Output compare register B
OCRB
R/W
H'FFFF
H'FF94*
3
H'FF94*
Timer control register
TCR
R/W
H'00
H'FF96
Timer output compare control
register
TOCR
R/W
H'00
H'FF97
Input capture register A
ICRA
R
H'0000
Input capture register B
ICRB
R
H'0000
H'FF98*
4
H'FF9A*
Input capture register C
ICRC
R
H'0000
4
H'FF9C*
Input capture register D
ICRD
R
H'0000
Output compare register AR
OCRAR
R/W
H'FFFF
H'FF9E
4
H'FF98*
Output compare register AF
OCRAF
R/W
H'FFFF
Output compare register DM
OCRDM
R/W
H'0000
H'FF9A*
4
H'FF9C*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Name
Abbreviation
R/W
Timer interrupt enable register
TIER
R/W
Timer control/status register
TCSR
R/(W)*
Free-running counter
FRC
Output compare register A
2
3
4
4
Notes: 1. Lower 16 bits of the address.
2. Bits 7 to 1 are read-only; only 0 can be written to clear the flags.
Bit 0 is readable/writable.
3. OCRA and OCRB share the same address. Access is controlled by the OCRS
bit in TOCR.
4. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and
OCRDM. Access is controlled by the ICRS bit in TOCR.
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Section 11 16-Bit Free-Running Timer
11.2
Register Descriptions
11.2.1
Free-Running Counter (FRC)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a
clock source. The clock source is selected by bits CKS1 and CKS0 in TCR.
FRC can also be cleared by compare-match A.
When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in TCSR is set to 1.
FRC is initialized to H'0000 by a reset and in hardware standby mode.
11.2.2
Output Compare Registers A and B (OCRA, OCRB)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flags (OCFA or OCFB) is set in TCSR.
In addition, if the output enable bit (OEA or OEB) in TOCR is set to 1, when OCR and FRC
values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is
output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB
output levels are 0 until the first compare-match.
OCR is initialized to H'FFFF by a reset and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 311 of 1130
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Section 11 16-Bit Free-Running Timer
11.2.3
Input Capture Registers A to D (ICRA to ICRD)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
There are four input capture registers, A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is
detected, the current FRC value is copied to the corresponding input capture register (ICRA to
ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to
1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to
perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR.
Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA =
1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as
transitions of the external input signal by setting IEDGA ≠ IEDGC. When IEDGA = IEDGC,
either the rising or falling edge is designated. See table 11.3.
Note: The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICF).
IEDGA BUFEA IEDGC
FTIA
Edge detect and
capture signal
generating circuit
ICRC
ICRA
Figure 11.2 Input Capture Buffering (Example)
Rev. 4.00 Sep 27, 2006 page 312 of 1130
REJ09B0327-0400
FRC
Section 11 16-Bit Free-Running Timer
Table 11.3 Buffered Input Capture Edge Selection (Example)
IEDGA
IEDGC
Description
0
0
Captured on falling edge of input capture A (FTIA)
1
Captured on both rising and falling edges of input capture A (FTIA)
1
(Initial value)
0
1
Captured on rising edge of input capture A (FTIA)
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (1.5φ). When triggering is enabled on both edges, the input capture pulse width should be
at least 2.5 system clock periods (2.5φ).
ICR is initialized to H'0000 by a reset and in hardware standby mode.
11.2.4
Output Compare Registers AR and AF (OCRAR, OCRAF)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRAR and OCRAF are 16-bit readable/writable registers.
When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use
of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added
alternately to OCRA, and the result is written to OCRA. The write operation is performed on the
occurrence of compare-match A. In the first compare-match A after the OCRAMS bit is set to 1,
OCRAF is added.
The operation due to compare-match A varies according to whether the compare-match follows
addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output
on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A
following addition of OCRAR.
When the OCRA automatically addition function is used, do not set internal clock φ/2 as the FRC
counter input clock together with an OCRAR (or OCRAF) value of H'0001 or less.
OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode.
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Section 11 16-Bit Free-Running Timer
11.2.5
Output Compare Register DM (OCRDM)
Bit
15
14
13
12
11
10
9
8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval.
A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are
H'0000.
OCRDM is initialized to H'0000 by a reset and in hardware standby mode.
11.2.6
Timer Interrupt Enable Register (TIER)
Bit
7
6
5
4
3
2
1
0
ICIAE
ICIBE
ICICE
ICIDE
OCIAE
OCIBE
OVIE
—
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture
interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
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Section 11 16-Bit Free-Running Timer
Bit 7
ICIAE
Description
0
Input capture interrupt request A (ICIA) is disabled
1
Input capture interrupt request A (ICIA) is enabled
(Initial value)
Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture
interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE
Description
0
Input capture interrupt request B (ICIB) is disabled
1
Input capture interrupt request B (ICIB) is enabled
(Initial value)
Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture
interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE
Description
0
Input capture interrupt request C (ICIC) is disabled
1
Input capture interrupt request C (ICIC) is enabled
(Initial value)
Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture
interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE
Description
0
Input capture interrupt request D (ICID) is disabled
1
Input capture interrupt request D (ICID) is enabled
(Initial value)
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE
Description
0
Output compare interrupt request A (OCIA) is disabled
1
Output compare interrupt request A (OCIA) is enabled
(Initial value)
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Section 11 16-Bit Free-Running Timer
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE
Description
0
Output compare interrupt request B (OCIB) is disabled
1
Output compare interrupt request B (OCIB) is enabled
(Initial value)
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE
Description
0
Timer overflow interrupt request (FOVI) is disabled
1
Timer overflow interrupt request (FOVI) is enabled
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
11.2.7
Timer Control/Status Register (TCSR)
Bit
7
6
5
4
3
2
1
0
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
CCLRA
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note: * Only 0 can be written in bits 7 to 1 to clear these flags.
TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.
TCSR is initialized to H'00 by a reset and in hardware standby mode.
Timing is described in section 11.3, Operation.
Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that
the old ICRA value has been moved into ICRC and the new FRC value has been transferred to
ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
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Section 11 16-Bit Free-Running Timer
Bit 7
ICFA
Description
0
[Clearing condition]
(Initial value)
Read ICFA when ICFA = 1, then write 0 in ICFA
1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to
ICRA
Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been
transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that
the old ICRB value has been moved into ICRD and the new FRC value has been transferred to
ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB
Description
0
[Clearing condition]
(Initial value)
Read ICFB when ICFB = 1, then write 0 in ICFB
1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been
transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the
signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is
not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt
signal (by setting the ICICE bit to 1).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC
Description
0
[Clearing condition]
(Initial value)
Read ICFC when ICFC = 1, then write 0 in ICFC
1
[Setting condition]
When an input capture signal is received
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Section 11 16-Bit Free-Running Timer
Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been
transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the
signal transition in FTID (input capture signal) specified by the IEDGD bit, ICFD is set but data is
not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt
by setting the ICIDE bit to 1.
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4
ICFD
Description
0
[Clearing condition]
(Initial value)
Read ICFD when ICFD = 1, then write 0 in ICFD
1
[Setting condition]
When an input capture signal is received
Bit 3—Output Compare Flag A (OCFA): This status flag indicates that the FRC value matches
the OCRA value. This flag must be cleared by software. It is set by hardware, however, and
cannot be set by software.
Bit 3
OCFA
Description
0
[Clearing condition]
(Initial value)
Read OCFA when OCFA = 1, then write 0 in OCFA
1
[Setting condition]
When FRC = OCRA
Bit 2—Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches
the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot
be set by software.
Bit 2
OCFB
Description
0
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 in OCFB
1
[Setting condition]
When FRC = OCRB
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
When FRC changes from H'FFFF to H'0000
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at comparematch A (when the FRC and OCRA values match).
Bit 0
CCLRA
Description
0
FRC clearing is disabled
1
FRC is cleared at compare-match A
11.2.8
(Initial value)
Timer Control Register (TCR)
Bit
7
6
5
4
3
2
1
0
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
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Section 11 16-Bit Free-Running Timer
Bit 7
IEDGA
Description
0
Capture on the falling edge of FTIA
1
Capture on the rising edge of FTIA
(Initial value)
Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B
signal (FTIB).
Bit 6
IEDGB
Description
0
Capture on the falling edge of FTIB
1
Capture on the rising edge of FTIB
(Initial value)
Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC
Description
0
Capture on the falling edge of FTIC
1
Capture on the rising edge of FTIC
(Initial value)
Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D
signal (FTID).
Bit 4
IEDGD
Description
0
Capture on the falling edge of FTID
1
Capture on the rising edge of FTID
(Initial value)
Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for
ICRA.
Bit 3
BUFEA
Description
0
ICRC is not used as a buffer register for input capture A
1
ICRC is used as a buffer register for input capture A
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bit 2
BUFEB
Description
0
ICRD is not used as a buffer register for input capture B
1
ICRD is used as a buffer register for input capture B
(Initial value)
Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal
clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to
the external clock input pin (FTCI).
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ/2 internal clock source
1
φ/8 internal clock source
0
φ/32 internal clock source
1
External clock source (rising edge)
1
11.2.9
(Initial value)
Timer Output Compare Control Register (TOCR)
Bit
7
6
ICRDMS OCRAMS
5
4
3
2
1
0
ICRS
OCRS
OEA
OEB
OLVLA
OLVLB
0
0
0
0
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.
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Section 11 16-Bit Free-Running Timer
Bit 7
ICRDMS
Description
0
The normal operating mode is specified for ICRD
1
The operating mode using OCRDM is specified for ICRD
(Initial value)
Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the
normal operating mode or in the operating mode using OCRAR and OCRAF.
Bit 6
OCRAMS
Description
0
The normal operating mode is specified for OCRA
1
The operating mode using OCRAR and OCRAF is specified for OCRA
(Initial value)
Bit 5—Input Capture Register Select (ICRS): The same addresses are shared by ICRA and
OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which
registers are selected when the shared addresses are read or written to. The operation of ICRA,
ICRB, and ICRC is not affected.
Bit 5
ICRS
Description
0
The ICRA, ICRB, and ICRC registers are selected
1
The OCRAR, OCRAF, and OCRDM registers are selected
(Initial value)
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS
Description
0
The OCRA register is selected
1
The OCRB register is selected
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal
(FTOA).
Bit 3
OEA
Description
0
Output compare A output is disabled
1
Output compare A output is enabled
(Initial value)
Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal
(FTOB).
Bit 2
OEB
Description
0
Output compare B output is disabled
1
Output compare B output is enabled
(Initial value)
Bit 1—Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in
response to compare-match A (signal indicating a match between the FRC and OCRA values).
When the OCRAMS bit is 1, this bit is ignored.
Bit 1
OLVLA
Description
0
0 output at compare-match A
1
1 output at compare-match A
(Initial value)
Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in
response to compare-match B (signal indicating a match between the FRC and OCRB values).
Bit 0
OLVLB
Description
0
0 output at compare-match B
1
1 output at compare-match B
(Initial value)
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Section 11 16-Bit Free-Running Timer
11.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and
module stop mode is entered. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode.
Bit 5
MSTPCRH
Description
0
FRT module stop mode is cleared
1
FRT module stop mode is set
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(Initial value)
Section 11 16-Bit Free-Running Timer
11.3
Operation
11.3.1
FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
Internal Clock
Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system clock (φ) can be
selected by making the appropriate setting in bits CKS1 and CKS0 in TCR. Figure 11.3 shows the
increment timing.
φ
Internal
clock
FRC input
clock
FRC
N–1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
External Clock
If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising
edge of the external clock signal.
The pulse width of the external clock signal must be at least 1.5 system clock (φ) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 11.4 shows the increment timing.
Rev. 4.00 Sep 27, 2006 page 325 of 1130
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Section 11 16-Bit Free-Running Timer
φ
External
clock input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
11.3.2
Output Compare Output Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the
timing of this operation for compare-match A.
φ
FRC
N
OCRA
N+1
N
N
N
Compare-match A
signal
Clear*
OLVLA
Output compare A
output pin FTOA
Note: * Vertical arrows (
) indicate instructions executed by software.
Figure 11.5 Timing of Output Compare A Output
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N+1
Section 11 16-Bit Free-Running Timer
11.3.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
Compare-match A
signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A
11.3.4
Input Capture Input Timing
Input Capture Input Timing
An internal input capture signal is generated from the rising or falling edge of the signal at the
input capture pin, as selected by the corresponding IEDGx (x = A to D) bit in TCR. Figure 11.7
shows the usual input capture timing when the rising edge is selected (IEDGx = 1).
φ
Input capture
input pin
Input capture
signal
Figure 11.7 Input Capture Signal Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one system clock (φ) period. Figure 11.8
shows the timing for this case.
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Section 11 16-Bit Free-Running Timer
ICRA/B/C/D read cycle
T1
T2
φ
Input capture
input pin
Input capture
signal
Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D Is Read)
Buffered Input Capture Input Timing
ICRC and ICRD can operate as buffers for ICRA and ICRB.
Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
φ
FTIA
Input capture
signal
FRC
n
ICRA
M
ICRC
m
n+1
N
N+1
n
n
N
M
M
n
Figure 11.9 Buffered Input Capture Timing (Usual Case)
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Section 11 16-Bit Free-Running Timer
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to
ICRC, however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,
input capture is delayed by one system clock (φ) period. Figure 11.10 shows the timing when
BUFEA = 1.
Read cycle:
CPU reads ICRA or ICRC
T1
T2
φ
FTIA
Input capture
signal
Figure 11.10 Buffered Input Capture Timing
(Input Capture Input when ICRA or ICRC Is Read)
11.3.5
Timing of Input Capture Flag (ICF) Setting
The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRx). Figure
11.11 shows the timing of this operation.
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Section 11 16-Bit Free-Running Timer
φ
Input capture
signal
ICFA/B/C/D
N
FRC
ICRA/B/C/D
N
Figure 11.11 Setting of Input Capture Flag (ICFA/B/C/D)
11.3.6
Setting of Output Compare Flags A and B (OCFA, OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last
state in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA
and OCFB.
φ
FRC
N
OCRA or OCRB
N+1
N
Compare-match
signal
OCFA or OCFB
Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB)
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Section 11 16-Bit Free-Running Timer
11.3.7
Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of this operation.
φ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Setting of Overflow Flag (OVF)
11.3.8
Automatic Addition of OCRA and OCRAR/OCRAF
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. The OCRA write timing is shown in figure 11.14.
φ
FRC
N
N+1
OCRA
N
N+A
OCRAR, F
A
Compare-match
signal
Figure 11.14 OCRA Automatic Addition Timing
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Section 11 16-Bit Free-Running Timer
11.3.9
ICRD and OCRDM Mask Signal Generation
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture function is generated.
The mask signal is set by the input capture signal. The mask signal setting timing is shown in
figure 11.15.
The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and
an FRC compare-match. The mask signal clearing timing is shown in figure 11.16.
φ
Input capture
signal
Input capture
mask signal
Figure 11.15 Input Capture Mask Signal Setting Timing
φ
FRC
N
ICRD +
OCRDM × 2
N+1
N
Compare-match
signal
Input capture
mask signal
Figure 11.16 Input Capture Mask Signal Clearing Timing
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Section 11 16-Bit Free-Running Timer
11.4
Interrupts
The free-running timer can request seven interrupts (three types): input capture A to D (ICIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.4 lists information about these interrupts.
Table 11.4 Free-Running Timer Interrupts
Interrupt
Description
DTC Activation
Priority
ICIA
Requested by ICFA
Possible
High
ICIB
Requested by ICFB
Possible
ICIC
Requested by ICFC
Not possible
ICID
Requested by ICFD
Not possible
OCIA
Requested by OCFA
Possible
OCIB
Requested by OCFB
Possible
FOVI
Requested by OVF
Not possible
Low
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Section 11 16-Bit Free-Running Timer
11.5
Sample Application
In the example below, the free-running timer is used to generate pulse outputs with a 50% duty
cycle and arbitrary phase relationship. The programming is as follows:
• The CCLRA bit in TCSR is set to 1.
• Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
H'FFFF
Counter clear
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 11.17 Pulse Output (Example)
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Section 11 16-Bit Free-Running Timer
11.6
Usage Notes
Application programmers should note that the following types of contention can occur in the freerunning timer.
Contention between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed.
Figure 11.18 shows this type of contention.
FRC write cycle
T1
T2
φ
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 11.18 FRC Write-Clear Contention
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Section 11 16-Bit Free-Running Timer
Contention between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented.
Figure 11.19 shows this type of contention.
FRC write cycle
T1
T2
φ
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M
Write data
Figure 11.19 FRC Write-Increment Contention
Contention between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is inhibited.
Figure 11.20 shows this type of contention.
Rev. 4.00 Sep 27, 2006 page 336 of 1130
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Section 11 16-Bit Free-Running Timer
If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in
the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of
the automatic addition is not written to OCRA.
Figure 11.21 shows this type of contention.
OCRA or OCRB write cycle
T1
T2
φ
Address
OCR address
Internal write signal
FRC
N
OCR
N
N+1
M
Write data
Compare-match
signal
Inhibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used)
Rev. 4.00 Sep 27, 2006 page 337 of 1130
REJ09B0327-0400
Section 11 16-Bit Free-Running Timer
φ
Address
OCRAR(OCRAF) address
Internal write signal
OCRAR (OCRAF)
Old data
New data
Compare-match
signal
Inhibited
FRC
N
OCRA
N
N+1
The compare-match signal is inhibited and
automatic addition does not occur.
Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match
(When Automatic Addition Function Is Not Used)
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Section 11 16-Bit Free-Running Timer
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to increment. This depends on
the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 11.5.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling
edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock can also cause FRC to increment.
Table 11.5 Switching of Internal Clock and FRC Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
FRC Operation
Switching from
low to low
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N+1
N
CKS bit rewrite
2
Switching from
low to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
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Section 11 16-Bit Free-Running Timer
No.
3
Timing of Switchover
by Means of CKS1
and CKS0 Bits
FRC Operation
Switching from
high to low
Clock before
switchover
Clock after
switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
4
Switching from
high to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated on the assumption that the switchover is a falling edge; FRC is incremented.
Rev. 4.00 Sep 27, 2006 page 340 of 1130
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Section 12 8-Bit Timers
Section 12 8-Bit Timers
12.1
Overview
This LSI include an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has
an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are
constantly compared with the TCNT value to detect compare-matches. The 8-bit timer module can
be used as a multifunction timer in a variety of applications, such as generation of a rectangularwave output with an arbitrary duty cycle.
The H8S/2148 Group also has two similar 8-bit timer channels (TMRX and TMRY), and the
H8S/2144 Group and H8S/2147N has one (TMRY). These channels can be used in a connected
configuration using the timer connection function. TMRX and TMRY have greater input/output
and interrupt function related restrictions than TMR0 and TMR1.
12.1.1
Features
• Selection of clock sources
 TMR0, TMR1: The counter input clock can be selected from six internal clocks and an
external clock (enabling use as an external event counter).
 TMRX, TMRY: The counter input clock can be selected from three internal clocks and an
external clock (enabling use as an external event counter).
• Selection of three ways to clear the counters
 The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two compare-match signals
 The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle.
(Note: TMRY does not have a timer output pin.)
• Cascading of the two channels (TMR0, TMR1)
 Operation as a 16-bit timer can be performed using channel 0 as the upper half and channel
1 as the lower half (16-bit count mode).
 Channel 1 can be used to count channel 0 compare-match occurrences (compare-match
count mode).
• Multiple interrupt sources for each channel
 TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be
requested independently.
 TMRX: One input capture source is available.
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Section 12 8-Bit Timers
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1).
TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input
capture function. For details, see section 13, Timer Connection.
External clock
sources
Internal clock
sources
TMCI0
TMCI1
TMR0
φ/8, φ/2
φ/64, φ/32
φ/1024, φ/256
TMR1
φ/8, φ/2
φ/64, φ/128
φ/1024, φ/2048
TMRX
φ
φ/2
φ/4
TMRY
φ/4
φ/256
φ/2048
Clock 1
Clock 0
Clock select
TCORA0
Compare-match A1
Compare-match A0 Comparator A0
TCNT0
Comparator A1
TCNT1
Clear 0
Clear 1
Compare-match B1
Compare-match B0 Comparator B0
TMO1
TMRI1
Comparator B1
Control logic
TCORB0
TCORB1
TCSR0
TCSR1
TCR0
TCR1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Figure 12.1 Block Diagram of 8-Bit Timer Module
Rev. 4.00 Sep 27, 2006 page 342 of 1130
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Internal bus
Overflow 1
Overflow 0
TMO0
TMRI0
TCORA1
Section 12 8-Bit Timers
12.1.3
Pin Configuration
Table 12.1 summarizes the input and output pins of the 8-bit timer module.
Table 12.1 8-Bit Timer Input and Output Pins
Channel
Name
Symbol*
I/O
Function
0
Timer output
TMO0
Output
Output controlled by compare-match
Timer clock input
TMCI0
Input
External clock input for the counter
Timer reset input
TMRI0
Input
External reset input for the counter
1
X
Y
Note:
*
Timer output
TMO1
Output
Output controlled by compare-match
Timer clock input
TMCI1
Input
External clock input for the counter
Timer reset input
TMRI1
Input
External reset input for the counter
Timer output
TMOX
Output
Output controlled by compare-match
Timer clock/
reset input
HFBACKI/TMIX Input
(TMCIX/TMRIX)
External clock/reset input for the
counter
Timer clock/reset
input
VSYNCI/TMIY Input
(TMCIY/TMRIY)
External clock/reset input for the
counter
The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel
number.
Channel X and Y I/O pins have the same internal configuration as channels 0 and 1,
and therefore the same abbreviations are used.
Rev. 4.00 Sep 27, 2006 page 343 of 1130
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Section 12 8-Bit Timers
12.1.4
Register Configuration
Table 12.2 summarizes the registers of the 8-bit timer module.
Table 12.2 8-Bit Timer Registers
Channel
Name
Abbreviation*
0
Timer control register 0
Timer control/status register 0
Time constant register A0
Time constant register B0
Time counter 0
Timer control register 1
Timer control/status register 1
Time constant register A1
Time constant register B1
Timer counter 1
Serial/timer control register
Module stop control register
TCR0
TCSR0
TCORA0
TCORB0
TCNT0
TCR1
TCSR1
TCORA1
TCORB1
TCNT1
STCR
MSTPCRH
MSTPCRL
TCONRS
TCRX
TCSRX
TCORAX
TCORBX
TCNTX
TCORC
TICRR
TICRF
TCRY
TCSRY
TCORAY
TCORBY
TCNTY
TISR
1
Common
X
Y
Timer connection register S
Timer control register X
Timer control/status register X
Time constant register AX
Time constant register BX
Timer counter X
Time constant register C
Input capture register R
Input capture register F
Timer control register Y
Timer control/status register Y
Time constant register AY
Time constant register BY
Timer counter Y
Timer input select register
3
R/W
Initial value
Address*
R/W
2
R/(W)*
R/W
R/W
R/W
R/W
2
R/(W)*
H'00
H'00
H'FF
H'FF
H'00
H'00
H'10
H'FF
H'FF
H'00
H'00
H'3F
H'FF
H'00
H'00
H'00
H'FF
H'FF
H'00
H'FF
H'00
H'00
H'00
H'00
H'FF
H'FF
H'00
H'FE
H'FFC8
H'FFCA
H'FFCC
H'FFCE
H'FFD0
H'FFC9
H'FFCB
H'FFCD
H'FFCF
H'FFD1
H'FFC3
H'FF86
H'FF87
H'FFFE
H'FFF0
H'FFF1
H'FFF6
H'FFF7
H'FFF4
H'FFF5
H'FFF2
H'FFF3
H'FFF0
H'FFF1
H'FFF2
H'FFF3
H'FFF4
H'FFF5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
R/(W)*
R/W
R/W
R/W
R/W
R
R
R/W
2
R/(W)*
R/W
R/W
R/W
R/W
1
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bits 7 to 5, to clear these flags.
3. The abbreviations TCR, TCSR, TCORA, TCORB, and TCNT are used in the text,
omitting the channel designation (0, 1, X, or Y).
Rev. 4.00 Sep 27, 2006 page 344 of 1130
REJ09B0327-0400
Section 12 8-Bit Timers
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits
for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access.
(Access is not divided into two 8-bit accesses.)
In the H8S/2148 Group, certain of the channel X and channel Y registers are assigned to the same
address. The TMRX/Y bit in TCONRS determines which register is accessed.
12.2
Register Descriptions
12.2.1
Timer Counter (TCNT)
TCNT0
TCNT1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNTX,TCNTY
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each TCNT is an 8-bit readable/writable up-counter.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
access.
TCNT increments on pulses generated from an internal or external clock source. This clock source
is selected by clock select bits CKS2 to CKS0 in TCR.
TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits
CCLR1 and CCLR0 in TCR select the method of clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1.
The timer counters are initialized to H'00 by a reset and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 345 of 1130
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Section 12 8-Bit Timers
12.2.2
Time Constant Register A (TCORA)
TCORA0
TCORA1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORAX, TCORAY
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORA is an 8-bit readable/writable register.
TCORA0 and TCORA1 comprise a single 16-bit register, so they can be accessed together by
word access.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is
disabled during the T2 state of a TCORA write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF by a reset and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 346 of 1130
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Section 12 8-Bit Timers
12.2.3
Time Constant Register B (TCORB)
TCORB0
TCORB1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORBX, TCORBY
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 comprise a single 16-bit
register, so they can be accessed together by word access.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is
disabled during the T2 state of a TCORB write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF by a reset and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 347 of 1130
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Section 12 8-Bit Timers
12.2.4
Timer Control Register (TCR)
Bit
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR is an 8-bit readable/writable register that selects the clock source and the time at which
TCNT is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in hardware standby mode.
For details of the timing, see section 12.3, Operation.
Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt
request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value.
Bit 7
CMIEB
Description
0
CMFB interrupt request (CMIB) is disabled
1
CMFB interrupt request (CMIB) is enabled
(Initial value)
Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt
request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1.
Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value.
Bit 6
CMIEA
Description
0
CMFA interrupt request (CMIA) is disabled
1
CMFA interrupt request (CMIA) is enabled
Rev. 4.00 Sep 27, 2006 page 348 of 1130
REJ09B0327-0400
(Initial value)
Section 12 8-Bit Timers
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request
(OVI) is enabled or disabled when the OVF flag in TCSR is set to 1.
Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.
Bit 5
OVIE
Description
0
OVF interrupt request (OVI) is disabled
1
OVF interrupt request (OVI) is enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which
the timer counter is cleared: by compare-match A or B, or by an external reset input.
Bit 4
Bit 3
CCLR1
CCLR0
Description
0
0
Clearing is disabled
1
Cleared on compare-match A
0
Cleared on compare-match B
1
Cleared on rising edge of external reset input
1
(Initial value)
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REJ09B0327-0400
Section 12 8-Bit Timers
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
The input clock can be selected from either six or three clocks, all divided from the system clock
(φ). The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1, because of the cascading function.
TCR
STCR
Bit 2 Bit 1 Bit 0 Bit 1
Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0
1
0
0
0
—
—
Clock input disabled
0
0
1
—
0
φ/8 internal clock source, counted on the falling edge
0
0
1
—
1
φ/2 internal clock source, counted on the falling edge
0
1
0
—
0
φ/64 internal clock source, counted on the falling
edge
0
1
0
—
1
φ/32 internal clock source, counted on the falling
edge
0
1
1
—
0
φ/1024 internal clock source, counted on the falling
edge
0
1
1
—
1
1
0
0
—
—
φ/256 internal clock source, counted on the falling
edge
Counted on TCNT1 overflow signal*
0
0
0
—
—
Clock input disabled
0
0
1
0
—
φ/8 internal clock source, counted on the falling edge
0
0
1
1
—
φ/2 internal clock source, counted on the falling edge
0
1
0
0
—
φ/64 internal clock source, counted on the falling
edge
0
1
0
1
—
φ/128 internal clock source, counted on the falling
edge
0
1
1
0
—
φ/1024 internal clock source, counted on the falling
edge
0
1
1
1
—
1
0
0
—
—
φ/2048 internal clock source, counted on the falling
edge
Counted on TCNT0 compare-match A*
Rev. 4.00 Sep 27, 2006 page 350 of 1130
REJ09B0327-0400
(Initial value)
(Initial value)
Section 12 8-Bit Timers
TCR
STCR
Bit 2 Bit 1 Bit 0 Bit 1
Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
X
Y
0
0
0
—
—
Clock input disabled
(Initial value)
0
0
1
—
—
Counted on φ internal clock source
0
1
0
—
—
φ/2 internal clock source, counted on the falling edge
0
1
1
—
—
φ/4 internal clock source, counted on the falling edge
1
0
0
—
—
Clock input disabled
0
0
0
—
—
Clock input disabled
0
0
1
—
—
φ/4 internal clock source, counted on the falling edge
0
1
0
—
—
φ/256 internal clock source, counted on the falling
edge
0
1
1
—
—
φ/2048 internal clock source, counted on the falling
edge
(Initial value)
1
0
0
—
—
Clock input disabled
Common 1
0
1
—
—
External clock source, counted at rising edge
1
1
0
—
—
External clock source, counted at falling edge
1
1
1
—
—
External clock source, counted at both rising and
falling edges
Note:
*
If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this
setting.
Rev. 4.00 Sep 27, 2006 page 351 of 1130
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Section 12 8-Bit Timers
12.2.5
Timer Control/Status Register (TCSR)
TCSR0
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
—
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICF
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICIE
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
TCSR1
Bit
TCSRX
Bit
TCSRY
Bit
Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags.
TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture
status in TMRX only), and controls compare-match output.
TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset
and in hardware standby mode.
Rev. 4.00 Sep 27, 2006 page 352 of 1130
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Section 12 8-Bit Timers
Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
Bit 7
CMFB
Description
0
[Clearing conditions]
1
(Initial value)
•
Read CMFB when CMFB = 1, then write 0 in CMFB
•
When the DTC is activated by a CMIB interrupt
[Setting condition]
When TCNT = TCORB
Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and
TCORA match.
Bit 6
CMFA
Description
0
[Clearing conditions]
1
(Initial value)
•
Read CMFA when CMFA = 1, then write 0 in CMFA
•
When the DTC is activated by a CMIA interrupt
[Setting condition]
When TCNT = TCORA
Bit 5 —Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed
from H'FF to H'00).
Bit 5
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
When TCNT overflows from H'FF to H'00
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Section 12 8-Bit Timers
TCSR0
Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests by
compare-match A.
Bit 4
ADTE
Description
0
A/D converter start requests by compare-match A are disabled
1
A/D converter start requests by compare-match A are enabled
(Initial value)
TCSR1
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
TCSRX
Bit 4—Input Capture Flag (ICF): Status flag that indicates detection of a rising edge followed
by a falling edge in the external reset signal after the ICST bit in TCONRI has been set to 1.
Bit 4
ICF
Description
0
[Clearing condition]
(Initial value)
Read ICF when ICF = 1, then write 0 in ICF
1
[Setting condition]
When a rising edge followed by a falling edge is detected in the external reset signal
after the ICST bit in TCONRI has been set to 1
TCSRY
Bit 4—Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of the interrupt
request by ICF (ICIX) when the ICF bit in TCSRX is set to 1.
Bit 4
ICIE
Description
0
Interrupt request by ICF (ICIX) is disabled
1
Interrupt request by ICF (ICIX) is enabled
Rev. 4.00 Sep 27, 2006 page 354 of 1130
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(Initial value)
Section 12 8-Bit Timers
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare-match of TCOR and TCNT.
OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the
effect of compare-match A on the output level, and both of them can be controlled independently.
Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If comparematches occur simultaneously, the output changes according to the compare-match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare-match occurs.
Bit 3
Bit 2
OS3
OS2
Description
0
0
No change when compare-match B occurs
1
0 is output when compare-match B occurs
0
1 is output when compare-match B occurs
1
Output is inverted when compare-match B occurs (toggle output)
1
(Initial value)
Bit 1
Bit 0
OS1
OS0
Description
0
0
No change when compare-match A occurs
1
0 is output when compare-match A occurs
0
1 is output when compare-match A occurs
1
Output is inverted when compare-match A occurs (toggle output)
1
(Initial value)
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Section 12 8-Bit Timers
12.2.6
Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS
IICX1
IICX0
IICE
FLSHE
—
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and
also selects the TCNT input clock.
For details on functions not related to the 8-bit timers, see section 3.2.4, Serial Timer Control
Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is
not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
2
Bits 7 to 4—I C Control (IICS, IICX1, IICX0, IICE): These bits control the bus buffer function
2
of port A and the operation of the I C bus interface when the IIC option is included on-chip. See
section 16.2.7, Serial/Timer Control Register (STCR), for details.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting module
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details..
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,
Timer Control Register (TCR).
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Section 12 8-Bit Timers
12.2.7
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections
3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data
registers and control registers, and timer connection control registers.
Bit 1
HIE
Description
0
CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is enabled
(Initial value)
1
CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is disabled
12.2.8
Timer Connection Register S (TCONRS)
Bit
7
6
5
4
3
2
1
0
TMRX/Y ISGENE HOMOD1HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY
registers and timer connection operation.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.
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Section 12 8-Bit Timers
Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2148 Group, some of the TMRX
registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to
H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2144 Group
and H8S/2147N, there is no control of TMRY register access by this bit.
Accessible Registers
Bit 7
TMRX/Y
H'FFF1
H'FFF2
H'FFF3
H'FFF4
H'FFF5
H'FFF6
H'FFF7
0
TMRX
(Initial value) TCRX
TMRX
TMRX
TMRX
TMRX
TMRX
TMRX
TMRX
TCSRX
TICRR
TICRF
TCNTX
TCORC
TCORAX TCORBX
1
TMRY
TMRY
TMRY
TMRY
TMRY
TMRY
TCRY
TCSRY
TCORAY TCORBY TCNTY
12.2.9
H'FFF0
TISR
Input Capture Register (TICR) [TMRX Additional Function]
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
—
—
TICR is an 8-bit internal register to which the contents of TCNT are transferred on the falling edge
of external reset input. The CPU cannot read or write to TICR directly.
The TICR function is used in timer connection. For details, see section 13, Timer Connection.
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Section 12 8-Bit Timers
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is
continually compared with the value in TCNT. When a match is detected, a compare-match C
signal is generated. Note, however, that comparison is disabled during the T2 state of a TCORC
write cycle and a TICR input capture cycle.
TCORC is initialized to H'FF by a reset and in hardware standby mode.
The TCORC function is used in timer connection. For details, see section 13, Timer Connection.
12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions]
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TICRR and TICRF are 8-bit read-only registers. When the ICST bit in TCONRI is set to 1,
TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external
reset input. When one capture operation ends, the ICST bit is cleared to 0.
TICRR and TICRF are each initialized to H'00 by a reset and in hardware standby mode.
The TICRR and TICRF functions are used in timer connection. For details, see section 12.3.6,
Input Capture Operation, and section 13, Timer Connection.
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Section 12 8-Bit Timers
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
IS
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the
counter.
TISR is initialized to H'FE by a reset and in hardware standby mode.
Bits 7 to 1—Reserved: Do not write 0 to these bits.
Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer
clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source
for the counter.
Bit 0
IS
Description
0
IVG signal is selected (H8S/2148 Group)
(Initial value)
External clock/reset input is disabled (H8S/2144 Group and H8S/2147N)
1
VSYNCI/TMIY (TMCIY/TMRIY) is selected
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Section 12 8-Bit Timers
12.2.13 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP12 bit or MSTP8 bit is set to 1, 8-bit timer operation is halted on channels 0 and 1
or channels X and Y, respectively, and a transition is made to module stop mode. For details, see
section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer (channel 0/1) module stop
mode.
MSTPCRH
Bit 4
MSTP12
Description
0
8-bit timer (channel 0/1) module stop mode is cleared
1
8-bit timer (channel 0/1) module stop mode is set
(Initial value)
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer (channel X/Y) and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8
Description
0
8-bit timer (channel X/Y) and timer connection module stop mode is cleared
1
8-bit timer (channel X/Y) and timer connection module stop mode
is set
(Initial value)
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Section 12 8-Bit Timers
12.3
Operation
12.3.1
TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock
An internal clock created by dividing the system clock (φ) can be selected by setting bits CKS2 to
CKS0 in TCR. Figure 12.2 shows the count timing.
φ
Internal clock
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.2 Count Timing for Internal Clock Input
External Clock
Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR: at the rising
edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 12.3 shows the timing of incrementation at both edges of an external clock signal.
Rev. 4.00 Sep 27, 2006 page 362 of 1130
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Section 12 8-Bit Timers
φ
External clock
input pin
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.3 Count Timing for External Clock Input
12.3.2
Compare-Match Timing
Setting of Compare-Match Flags A and B (CMFA, CMFB)
The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the
TCOR and TCNT values match. The compare-match signal is generated at the last state in which
the match is true, just before the timer counter is updated.
Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the
next incrementation clock input. Figure 12.4 shows this timing.
φ
TCNT
N
TCOR
N
N+1
Compare-match
signal
CMF
Figure 12.4 Timing of CMF Setting
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Section 12 8-Bit Timers
Timer Output Timing
When compare-match A or B occurs, the timer output changes as specified by the output select
bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0,
be set to 1, or toggle.
Figure 12.5 shows the timing when the output is set to toggle at compare-match A.
φ
Compare-match A
signal
Timer output
pin
Figure 12.5 Timing of Timer Output
Timing of Compare-Match Clear
TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation.
φ
Compare-match
signal
TCNT
N
H'00
Figure 12.6 Timing of Compare-Match Clear
12.3.3
TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.7 shows the timing of this operation.
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Section 12 8-Bit Timers
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4
Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.8 shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.8 Timing of OVF Setting
12.3.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer
mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (comparematch count mode). In this case, the timer operates as described below.
Rev. 4.00 Sep 27, 2006 page 365 of 1130
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Section 12 8-Bit Timers
16-Bit Count Mode
When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
• Setting of compare-match flags
 The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
 The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
• Counter clear specification
 If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear
by the TMRI0 pin has also been set.
 The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot
be cleared independently.
• Pin output
 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with
the 16-bit compare-match conditions.
 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with
the lower 8-bit compare-match conditions.
Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts compare-match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
Usage Note
If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock
pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop operating.
Simultaneous setting of these two modes should therefore be avoided.
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Section 12 8-Bit Timers
12.3.6
Input Capture Operation
TMRX has input capture registers of TICR, TICRR, and TICRF. Narrow pulse width can be
measured with TICRR and TICRF, using one capture operation controlled by the ICST bit in the
TCONRI register of the timer connection. When TMRIX detects a rising and falling edge
successively after the ICST bit has been set to 1, the values of TCNT at that time are transferred to
TICRR and TICRF and ICST bit is cleared to 0.
The TMRIX input signal can be selected by setting other bits in the TCONRI register.
(1) Input capture input timing
Figure 12.9 shows the timing of the input capture operation.
φ
TMRIX
Input capture
signal
TCNTX
n+1
n
TICRR
M
TICRF
m
n
N
N +1
n
m
N
Figure 12.9 Timing of Input Capture Operation
If the input capture signal enters while TICRR and TICRF are being read, it is internally delayed
one system clock (φ) period. Figure 12.10 shows the timing of this operation.
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Section 12 8-Bit Timers
TICRR, TICRF read cycle
T1
T2
φ
TMRIX
Input capture
signal
Figure 12.10 Timing of Input Capture Signal
(When Input Capture Input Signal Enters while TICRR and TICRF Are Being Read)
(2) Input capture signal input selection
Input capture input signal (TMRIX) in TMRX is switched by setting bits in the TCONRI register.
Figure 12.11 and Table 12.3 show the input capture signal selections.
See section 13.2.1, Timer Connection Register I (TCONRI), for details.
TMRX
TMIX pin
Polarity
inversion
TMRI1 pin
Polarity
inversion
TMCI1 pin
Polarity
inversion
HFINV,
HIINV
Signal
selector
SIMOD1,
SIMOD0
TMRIX
ICST
Figure 12.11 Switching of Input Capture Signal
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Section 12 8-Bit Timers
Table 12.3 Input Capture Signal Selection
TCONRI
Bit 4
Bit 7
Bit 6
Bit 3
Bit 1
ICST
SIMOD1
SIMOD0
HFINV
HIINV
Description
0
—
—
—
—
Input capture function not used
1
0
0
0
—
TMIX pin input signal
1
—
Inverted signal of TMIX pin input
1
1
12.4
1
—
0
TMRI1 pin input signal
—
1
Inverted signal of TMRI1 pin input
—
0
TMCI1 pin input signal
—
1
Inverted signal of TMCI1 pin input
Interrupt Sources
The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: compare-match
A and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An
interrupt is requested when the corresponding interrupt enable bit is set in TCR or TCSR.
Independent signals are sent to the interrupt controller for each interrupt. It is also possible to
activate the DTC by means of CMIA and CMIB interrupts from TMR0, TMR1 and TMRY.
An overview of 8-bit timer interrupt sources is given in tables 12.4 to 12.6.
Table 12.4 TMR0 and TMR1 8-Bit Timer Interrupt Sources
Interrupt source
Description
DTC Activation
Interrupt Priority
CMIA
Requested by CMFA
Possible
High
CMIB
Requested by CMFB
Possible
OVI
Requested by OVF
Not possible
Low
Table 12.5 TMRX 8-Bit Timer Interrupt Source
Interrupt source
Description
DTC Activation
ICIX
Requested by ICF
Not possible
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Section 12 8-Bit Timers
Table 12.6 TMRY 8-Bit Timer Interrupt Sources
Interrupt source
Description
DTC Activation
Interrupt Priority
CMIA
Requested by CMFA
Possible
High
CMIB
Requested by CMFB
Possible
OVI
Requested by OVF
Not possible
12.5
Low
8-Bit Timer Application Example
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle,
as shown in figure 12.12. The control bits are set as follows:
• In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a
TCORA compare-match.
• In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and
0 output at a TCORB compare-match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.12 Pulse Output (Example)
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Section 12 8-Bit Timers
12.6
Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer module.
12.6.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.13 shows
this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.13 Contention between TCNT Write and Clear
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Section 12 8-Bit Timers
12.6.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 12.14 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.14 Contention between TCNT Write and Increment
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Section 12 8-Bit Timers
12.6.3
Contention between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.15 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
TCOR write cycle by CPU
T1
T2
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare-match signal
Inhibited
Figure 12.15 Contention between TCOR Write and Compare-Match
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Section 12 8-Bit Timers
12.6.4
Contention between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 12.7.
Table 12.7 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
12.6.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.8 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 12.8, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
Erroneous incrementation can also happen when switching between internal and external clocks.
Rev. 4.00 Sep 27, 2006 page 374 of 1130
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Section 12 8-Bit Timers
Table 12.8 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from low
1
to low*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit rewrite
2
Switching from low
2
to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
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Section 12 8-Bit Timers
No.
3
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from high
3
to low*
Clock before
switchover
Clock after
switchover
*4
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
4
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
Notes: 1.
2.
3.
4.
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
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Section 13 Timer Connection
Section 13 Timer Connection
Provided in the H8S/2148 Group; not provided in the H8S/2144 Group and H8S/2147N.
13.1
Overview
The H8S/2148 Group allows interconnection between a combination of input signals, the
input/output of the single free-running timer (FRT) channel and the three 8-bit timer channels
(TMR1, TMRX, and TMRY). This capability can be used to implement complex functions such as
PWM decoding and clamp waveform output. All the timers are initially set for independent
operation.
13.1.1
Features
The features of the timer connection facility are as follows.
• Five input pins and four output pins, all of which can be designated for phase inversion.
Positive logic is assumed for all signals used within the timer connection facility.
• An edge-detection circuit is connected to the input pins, simplifying signal input detection.
• TMRX can be used for PWM input signal decoding and clamp waveform generation.
• An external clock signal divided by TMR1 can be used as the FRT capture input signal.
• An internal synchronization signal can be generated using the FRT and TMRY.
• A signal generated/modified using an input signal and timer connection can be selected and
output.
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the timer connection facility.
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Figure 13.1 Block Diagram of Timer Connection Facility
HFBACKI/
FTCI/TMIX
CSYNCI/
TMRI1
HSYNCI/
TMCI1
FTID
FTIC
VFBACKI/
FTIB
VSYNCI/
FTIA/TMIY
Phase
inversion
Phase
inversion
Phase
inversion
Phase
inversion
Phase
inversion
Edge
detection
Edge
detection
Edge
detection
Edge
detection
Edge
detection
IHI
signal
selection
IVI
signal
selection
FRT
input
selection
IVI signal
READ
flag
IHI signal
READ
flag
16-bit FRT
VSYNC modify
FTOA
ICR +1C
compare match
ICR
8-bit TMRX
PWM decoding
PDC signal
TMRI
CMA
TMO
CMB
CMB
TMCI
8-bit TMR1 TMO
CLAMP waveform generation
CM1C
TMRI
TMCI
TMR1
input
selection
CBLANK waveform
generation
SET RES
2f H mask generation
2f H mask/flag
CMA(R)
FTIB OCRA +VR, +VF
FTIC ICRD +1M, +2M CMA(F)
compare match
FTOB
FTID
CM1M CM2M
FTIA
SET
sync
RES
CL1 signal
CL2 signal
CL3 signal
RES
VSYNC
generation
SET
CL
signal
selection
CL4 signal
FRT
output
selection
phase
inversion
phase
inversion
Phase
inversion
TMO1
output
selection
TMRI/TMCI
8-bit TMRY
TMO
IVO signal
Phase
inversion
CL4 generation
IHO
signal
selection
TMIY
signal
selection
IVG signal
IVO
signal
selection
CLAMPO/
FTIC
TMOX
HSYNCO/
TMO1
CBLANK
IHG signal
VSYNCO/
FTOA
Section 13 Timer Connection
Section 13 Timer Connection
13.1.3
Input and Output Pins
Table 13.1 lists the timer connection input and output pins.
Table 13.1 Timer Connection Input and Output Pins
Name
Abbreviation
Input/
Output
Vertical synchronization
signal input pin
VSYNCI
Input
Vertical synchronization signal
input pin or FTIA input pin/TMIY
input pin
Horizontal synchronization
signal input pin
HSYNCI
Input
Horizontal synchronization signal
input pin or TMCI1 input pin
Composite synchronization
signal input pin
CSYNCI
Input
Composite synchronization signal
input pin or TMRI1 input pin
Spare vertical synchronization
signal input pin
VFBACKI
Input
Spare vertical synchronization
signal input pin or FTIB input pin
Spare horizontal
synchronization signal input
pin
HFBACKI
Input
Spare horizontal synchronization
signal input pin or FTCI input
pin/TMIX input pin
Vertical synchronization
signal output pin
VSYNCO
Output
Vertical synchronization signal
output pin or FTOA output pin
Horizontal synchronization
signal output pin
HSYNCO
Output
Horizontal synchronization signal
output pin or TMO1 output pin
Clamp waveform output pin
CLAMPO
Output
Clamp waveform output pin or
FTIC input pin
Blanking waveform output pin
CBLANK
Output
Blanking waveform output pin
Function
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Section 13 Timer Connection
13.1.4
Register Configuration
Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed
when the HIE bit in SYSCR is 0.
Table 13.2 Register Configuration
Name
Abbreviation
R/W
Initial Value
1
Address*
Timer connection register I
TCONRI
R/W
H'00
H'FFFC
Timer connection register O
TCONRO
R/W
H'00
H'FFFD
Timer connection register S
TCONRS
R/W
H'00
H'FFFE
Edge sense register
SEDGR
2
R/(W)*
3
H'00*
H'FFFF
Module stop control register
MSTPRH
R/W
H'3F
H'FF86
MSTPRL
R/W
H'FF
H'FF87
Notes: 1. Lower 16 bits of the address.
2. Bits 7 to 2: Only 0 can be written to clear the flags.
3. Bits 1 and 0: Undefined (reflect the pin states).
13.2
Register Descriptions
13.2.1
Timer Connection Register I (TCONRI)
Bit
7
6
5
SIMOD1 SIMOD0 SCONE
4
3
2
1
0
ICST
HFINV
VFINV
HIINV
VIINV
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRI is an 8-bit readable/writable register that controls connection between timers, the signal
source for synchronization signal input, phase inversion, etc.
TCONR1 is initialized to H'00 by a reset and in hardware standby mode.
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Section 13 Timer Connection
Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 7
Bit 6
SIMOD1
SIMOD0
Mode
0
0
No signal
1
S-on-G mode
1
Description
(Initial value)
IHI Signal
IVI Signal
HFBACKI input
VFBACKI input
CSYNCI input
PDC input
0
Composite mode
HSYNCI input
PDC input
1
Separate mode
HSYNCI input
VSYNCI input
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 5
Description
SCONE
Mode
FTIA
FTIB
FTIC
FTID
TMCI1 TMRI1
0
Normal connection (Initial value) FTIA
input
FTIB
input
FTIC
input
FTID
input
TMCI1 TMRI1
input
input
1
Synchronization signal
connection mode
TMO1
signal
VFBACKI IHI
input
signal
IVI
signal
IHI
signal
IVI
inverse
signal
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 4
ICST
Description
0
The TICRR and TICRF input capture functions are stopped
(Initial value)
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
1
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
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Section 13 Timer Connection
Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchronization signal (VSYNCI).
Bit 3
HFINV
Description
0
The HFBACKI pin state is used directly as the HFBACKI input
1
The HFBACKI pin state is inverted before use as the HFBACKI input
(Initial value)
Bit 2
VFINV
Description
0
The VFBACKI pin state is used directly as the VFBACKI input
1
The VFBACKI pin state is inverted before use as the VFBACKI input
(Initial value)
Bit 1
HIINV
Description
0
The HSYNCI and CSYNCI pin states are used directly as the HSYNCI
and CSYNCI inputs
1
(Initial value)
The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Bit 0
VIINV
Description
0
The VSYNCI pin state is used directly as the VSYNCI input
1
The VSYNCI pin state is inverted before use as the VSYNCI input
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(Initial value)
Section 13 Timer Connection
13.2.2
Timer Connection Register O (TCONRO)
Bit
7
6
5
4
3
2
HOE
VOE
CLOE
CBOE
HOINV
VOINV
1
0
CLOINV CBOINV
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion,
etc.
TCONRO is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 4—Output Enable (HOE, VOE, CLOE, CBOE): These bits control
enabling/disabling of horizontal synchronization signal (HSYNCO), vertical synchronization
signal (VSYNCO), clamp waveform (CLAMPO), and blanking waveform (CBLANK) output.
When output is disabled, the state of the relevant pin is determined by the port DR and DDR, FRT,
TMR, and PWM settings.
Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some
FRT and TMR input signal sources are determined by the SCONE bit in TCONRI.
Bit 7
HOE
Description
0
The P44/TMO1/HIRQ1/HSYNCO pin functions as the P44/TMO1/
HIRQ1 pin
1
The P44/TMO1/HIRQ1/HSYNCO pin functions as the HSYNCO pin
(Initial value)
Bit 6
VOE
Description
0
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the P61/FTOA/
KIN1/CIN1 pin
1
The P61/FTOA/KIN1/CIN1/VSYNCO pin functions as the VSYNCO pin
(Initial value)
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Section 13 Timer Connection
Bit 5
CLOE
Description
0
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the
P64/FTIC/KIN4/CIN4 pin
1
The P64/FTIC/KIN4/CIN4/CLAMPO pin functions as the CLAMPO pin
(Initial value)
Bit 4
CBOE
Description
0
The P27/A15/PW15/CBLANK pin functions as the P27/A15/PW15 pin
1
In mode 1 (expanded mode with on-chip ROM disabled):
The P27/A15/PW15/CBLANK pin functions as the A15 pin
(Initial value)
In modes 2 and 3 (modes with on-chip ROM enabled):
The P27/A15/PW15/CBLANK pin functions as the CBLANK pin
Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,
CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal
(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),
and the blank waveform (CBLANK).
Bit 3
HOINV
Description
0
The IHO signal is used directly as the HSYNCO output
1
The IHO signal is inverted before use as the HSYNCO output
(Initial value)
Bit 2
VOINV
Description
0
The IVO signal is used directly as the VSYNCO output
1
The IVO signal is inverted before use as the VSYNCO output
(Initial value)
Bit 1
CLOINV
Description
0
The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the
CLAMPO output
1
The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as
the CLAMPO output
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(Initial value)
Section 13 Timer Connection
Bit 0
CBOINV
Description
0
The CBLANK signal is used directly as the CBLANK output
1
The CBLANK signal is inverted before use as the CBLANK output
13.2.3
(Initial value)
Timer Connection Register S (TCONRS)
Bit
7
6
5
4
3
2
1
0
TMRX/Y ISGENE HOMOD1 HOMOD0VOMOD1 VOMOD0 CLMOD1 CLMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRS is an 8-bit readable/writable register that selects 8-bit timer TMRX/TMRY access and
the synchronization signal output signal source and generation method.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8S/2148 Group, some of the TMRX
registers and the TMRY registers are assigned to the same memory space addresses (H'FFF0 to
H'FFF5), and the TMRX/Y bit determines which registers are accessed. In the H8S/2144 Group
and H8S/2147N, there is no control of TMRY register access by this bit.
Bit 7
TMRX/Y
Description
0
The TMRX registers are accessed at addresses H'FFF0 to H'FFF5
1
The TMRY registers are accessed at addresses H'FFF0 to H'FFF5
(Initial value)
Bit 6—Internal Synchronization Signal Select (ISGENE): Selects internal synchronization
signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals.
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Section 13 Timer Connection
Bits 5 and 4—Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1,
HOMOD0): These bits select the signal source and generation method for the IHO signal.
Bit 6
Bit 5
Bit 4
ISGENE
HOMOD1
HOMOD0
Description
0
0
0
The IHI signal (without 2fH modification) is selected
(Initial value)
1
The IHI signal (with 2fH modification) is selected
0
The CL1 signal is selected
1
1
1
0
0
The IHG signal is selected
1
1
0
1
Bits 3 and 2—Vertical Synchronization Output Mode Select 1 and 0 (VOMOD1, VOMOD0):
These bits select the signal source and generation method for the IVO signal.
Bit 6
Bit 3
Bit 2
ISGENE
VOMOD1
VOMOD0
Description
0
0
0
The IVI signal (without fall modification or
IHI synchronization) is selected
1
1
0
1
The IVI signal (without fall modification, with IHI
synchronization) is selected
0
The IVI signal (with fall modification, without IHI
synchronization) is selected
1
The IVI signal (with fall modification and IHI
synchronization) is selected
0
The IVG signal is selected
1
1
(Initial value)
0
1
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Section 13 Timer Connection
Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
Bit 6
Bit 1
Bit 0
ISGENE
CLMOD1
CLMOD2
Description
0
0
0
The CL1 signal is selected
1
The CL2 signal is selected
0
The CL3 signal is selected
1
(Initial value)
1
1
0
0
The CL4 signal is selected
1
1
0
1
13.2.4
Edge Sense Register (SEDGR)
Bit
Initial value
Read/Write
7
6
5
VEDG
HEDG
CEDG
0
0
0
R/(W)*1
R/(W)*1
R/(W)*1
4
3
2
HFEDG VFEDG PREQF
0
R/(W)*1
0
R/(W)*1
0
R/(W)*1
1
0
IHI
IVI
—*2
—*2
R
R
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
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Section 13 Timer Connection
Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin.
Bit 7
VEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in VEDG after reading VEDG = 1
1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
Bit 6
HEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in HEDG after reading HEDG = 1
1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
Bit 5—CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin.
Bit 5
CEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in CEDG after reading CEDG = 1
1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
Bit 4—HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin.
Bit 4
HFEDG
Description
0
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
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(Initial value)
Section 13 Timer Connection
Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.
Bit 3
VFEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in VFEDG after reading VFEDG = 1
1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH
modification condition. The generation of a falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH modification condition. For details, see section
13.3.4, IHI Signal 2fH Modification.
Bit 2
PREQF
Description
0
[Clearing condition]
(Initial value)
When 0 is written in PREQF after reading PREQF = 1
1
[Setting condition]
When an IHI signal 2fH modification condition is detected
Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and
phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IHI signal at positive
phase by modifying TCONRI.
Bit 1
IHI
Description
0
The IHI signal is low
1
The IHI signal is high
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Section 13 Timer Connection
Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and
phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IVI signal at positive
phase by modifying TCONRI.
Bit 0
IVI
Description
0
The IVI signal is low
1
The IVI signal is high
13.2.5
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit
timer channels 0 and 1, and 8-bit timer channels X and Y and timer connection, respectively, halt
and enter module stop mode. See section 25.5., Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode.
MSTPCRH
Bit 5
MSTP13
Description
0
FRT module stop mode is cleared
1
FRT module stop mode is set
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(Initial value)
Section 13 Timer Connection
MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop
mode.
MSTPCRH
Bit 4
MSTP12
Description
0
8-bit timer channel 0 and 1 module stop mode is cleared
1
8-bit timer channel 0 and 1 module stop mode is set
(Initial value)
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8
Description
0
8-bit timer channel X and Y and timer connection module stop mode is cleared
1
8-bit timer channel X and Y and timer connection module stop mode is
set
13.3
Operation
13.3.1
PWM Decoding (PDC Signal Generation)
(Initial value)
The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is
reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using
TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold.
Examples of TCR and TCORB settings are shown in tables 13.3 and 13.4, and the timing chart is
shown in figure 13.2.
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Section 13 Timer Connection
Table 13.3 Examples of TCR Settings
Bit(s)
Abbreviation
Contents
Description
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match and overflow are
disabled
5
OVIE
0
4 and 3
CCLR1, CCLR0
11
TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
2 to 0
CKS2 to CKS0
001
Incremented on internal clock: φ
Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings
φ:10 MHz
φ: 12 MHz
φ: 16 MHz
φ: 20 MHz
H'07
0.8 µs
0.67 µs
0.5 µs
0.4 µs
H'0F
1.6 µs
1.33 µs
1 µs
0.8 µs
H'1F
3.2 µs
2.67 µs
2 µs
1.6 µs
H'3F
6.4 µs
5.33 µs
4 µs
3.2 µs
H'7F
12.8 µs
10.67 µs
8 µs
6.4 µs
IHI signal is tested
at compare-match
IHI signal
PDC signal
TCNT
TCORB
(threshold)
Counter reset
caused by
IHI signal
Counter clear
caused by
TCNT overflow
At the 2nd compare-match,
IHI signal is not tested
Figure 13.2 Timing Chart for PWM Decoding
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Section 13 Timer Connection
13.3.2
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
The timer connection facility and TMRX can be used to generate signals with different duty cycles
and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal).
Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4
signal can be generated using TMRY.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1
and the CL2 signal can be specified by TCORA.
The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI
signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3
signal can also fall when the IHI signal rises.
TCNT in TMRX is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI signal).
The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or
more in TCORA when internal clock φ is selected as the TMRX counter clock, and a value or
H'01 or more when φ/2 is selected. When internal clock φ is selected, the CL1 signal pulse width
is (TCORA set value +3 ±0.5). When the CL2 signal is used, the setting must be made so that this
pulse width is greater than the IHI signal pulse width.
The value to be used as the CL3 signal pulse width is written in TCORC. The TICR register in
TMRX captures the value of TCNT at the inverse of the external reset signal edge (in this case, the
falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of
the contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes
the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall.
Examples of TMRX TCR settings are the same as those in table 13.3. The clamp waveform timing
charts are shown in figures 13.3 and 13.4.
Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and
their fall is synchronized with the system clock, the pulse width variation is equivalent to the
resolution of the system clock.
Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse
width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to
the resolution of the system clock.
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Section 13 Timer Connection
IHI signal
CL1 signal
CL2 signal
TCNT
TCORA
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
IHI signal
CL3 signal
TCNT
TICR+TCORC
TICR
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)
13.3.3
Measurement of 8-Bit Timer Divided Waveform Period
The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the
period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of inverted
IVI signal, the rise and fall of the IHI signal divided waveform can be virtually synchronized with
the IVI signal. This enables period measurement to be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(inverted IVI signal). The value to be used as the division factor is written in TCORA, and the
TMO output method is specified by the OS bits in TCSR. Examples of TCR and TCSR settings
are shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal
divided waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform
is given by (ICRD(3) – ICRD(2)) × the resolution.
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Section 13 Timer Connection
Table 13.5 Examples of TCR and TCSR Settings
Register
Bit(s)
Abbreviation
Contents Description
TCR in TMR1
7
CMIEB
0
6
CMIEA
0
5
OVIE
0
4 and 3 CCLR1, CCLR0
11
TCNT is cleared by the rising edge
of the external reset signal (inverted
IVI signal)
2 to 0
CKS2 to CKS0
101
TCNT is incremented on the rising
edge of the external clock (IHI
signal)
3 to 0
OS3 to OS0
0011
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): division by 512
TCSR in TMR1
Interrupts due to compare-match
and overflow are disabled
or
TCR in FRT
6
IEDGB
1001
when TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: division by
256
0/1
0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
TCSR in FRT
1 and 0 CKS1, CKS0
01
FRC is incremented on internal
clock: φ/8
0
0
FRC clearing is disabled
CCLRA
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Section 13 Timer Connection
IVI signal
IHI signal
divided
waveform
ICRB(4)
ICRB(3)
ICRB(2)
ICRB(1)
FRC
ICRB
Figure 13.5 Timing Chart for Measurement of IVI Signal and
IHI Signal Divided Waveform Periods
13.3.4
IHI Signal and 2fH Modification
By using the timer connection FRT, even if there is a part of the IHI signal with twice the
frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of
the IHI signal must be approximately 30% or less, or approximately 70% or above.
The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data
captured in ICRD in the FRT, and compare-matches generated at these points. The interval
between the two compare-matches is called a mask interval. A value equivalent to approximately
1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the
rise of the IHI signal.
Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the
IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When
2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture
is also disabled during these intervals.
Examples of FRT TCR settings are shown in table 13.6, and the 2fH modification timing chart is
shown in figure 13.6.
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Section 13 Timer Connection
Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in FRT
4
IEDGD
1
FRC value is transferred to ICRD on
the rising edge of input capture input
D (IHI signal)
1 and 0
CKS1, CKS0
01
FRC is incremented on internal clock:
φ/8
TCSR in FRT
0
CCLRA
0
FRC clearing is disabled
TCOR in FRT
7
ICRDMS
1
ICRD is set to the operating mode in
which OCRDM is used
OCRDM7 to 0
H'01 to H'FF Specifies the period during which
ICRD operation is masked
OCRDM in FRT 7 to 0
IHI signal
(without 2fH
modification)
IHI signal
(with 2fH
modification)
Mask interval
ICRD + OCRDM × 2
ICRD + OCRDM
FRC
ICRD
Figure 13.6 2fH Modification Timing Chart
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Section 13 Timer Connection
13.3.5
IVI Signal Fall Modification and IHI Synchronization
By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the
specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized
with the rise of the IHI signal.
To perform 8-bit timer divided waveform period measurement, TCNT in TMR1 is set to count
external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is
written in TCORB.
Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the
IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When
fall modification is selected, a reset is performed on a TMR1 TCORB compare-match.
The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal,
regardless of whether or not fall modification is selected.
Examples of TMR1 TCORB, TCR, and TCSR settings are shown in table 13.7, and the fall
modification/IHI synchronization timing chart is shown in figure 13.7.
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Section 13 Timer Connection
Table 13.7 Examples of TCORB, TCR, and TCSR Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in
TMR1
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match and
overflow are disabled
5
OVIE
0
4 and 3
CCLR1,
CCLR0
11
TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
2 to 0
CKS2 to CKS0
101
TCNT is incremented on the rising edge of
the external clock (IHI signal)
3 to 0
OS3 to OS0
0011
Not changed by compare-match B; output
inverted by compare-match A (toggle
output)
TCSR in
TMR1
or
TOCRB in TMR1
1001
when TCORB ≤ TCORA, 1 output on
compare-match B, 0 output on comparematch A
H'03
(example)
Compare-match on the 4th (example) rise
of the IHI signal after the rise of the
inverse of the IVI signal
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)
TCNT
0
1
2
3
4
5
TCNT = TCORB (3)
Figure 13.7 Fall Modification/IHI Synchronization Timing Chart
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Section 13 Timer Connection
13.3.6
Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
By using the timer connection FRT and TMRY, it is possible to automatically generate internal
signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is
synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the
IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in
synchronization with the IHG signal.
The contents of OCRA in the FRT are updated by the automatic addition of the contents of
OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the
0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of
the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR
addition, and reset by a compare-match after an OCRAF addition.
The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and
to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set
so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and
the rise of the IVG signal can be treated in the same way as a TCORA compare-match.
The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG
signal, and has a 1 interval of 6 system clock periods.
Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF,
and TCR in the FRT, are shown in table 13.8, and the IHG signal/IVG signal timing chart is
shown in figure 13.8.
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Section 13 Timer Connection
Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR
Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in
TMRY
7
CMIEB
0
Interrupts due to compare-match and
overflow are disabled
6
CMIEA
0
5
OVIE
0
4 and 3
CCLR1,
CCLR0
01
2 to 0
CKS2 to CKS0 001
TCNT is incremented on internal clock:
φ/4
3 to 0
OS3 to OS0
0110
0 output on compare-match B
1 output on compare-match A
TOCRA in
TMRY
H'3F
(example)
IHG signal period = φ × 256
TOCRB in
TMRY
H'03
(example)
IHG signal 1 interval = φ × 16
01
FRC is incremented on internal clock: φ/8
OCRAR in FRT
H'7FEF
(example)
IVG signal 0
interval =
φ × 262016
OCRAF in FRT
H'000F
(example)
IVG signal 1
interval = φ × 128
1
OCRA is set to the operating mode in
which OCRAR and OCRAF are used
TCSR in
TMRY
TCR in FRT
TOCR in FRT
1 and 0
6
CKS1,
CKS0
OCRAMS
TCNT is cleared by compare-match A
IVG signal period =
φ × 262144 (1024
times IHG signal)
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Section 13 Timer Connection
IVG signal
OCRA (1) =
OCRA (0) +
OCRAF
OCRA (2) =
OCRA (1) +
OCRAR
OCRA (3) =
OCRA (2) +
OCRAF
OCRA (4) =
OCRA (3) +
OCRAR
OCRA
FRC
6 system clocks
6 system clocks
6 system clocks
CL4
signal
IHG
signal
TCORA
TCORB
TCNT
Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart
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Section 13 Timer Connection
13.3.7
HSYNCO Output
With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IHI signal source and the waveform required by external
circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9.
Table 13.9 Meaning of HSYNCO Output in Each Mode
Mode
IHI Signal
IHO Signal
Meaning of IHO Signal
No signal
HFBACKI
input
IHI signal (without
2fH modification)
HFBACKI input is output directly
IHI signal (with 2fH
modification)
Meaningless unless there is a double-frequency
part in the HFBACKI input
CL1 signal
HFBACKI input 1 interval is changed before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
CSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification)
Double-frequency part of CSYNCI input (composite
synchronization signal) is eliminated before output
CL1 signal
CSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
HSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification)
Double-frequency part of HSYNCI input (composite
synchronization signal) is eliminated before output
CL1 signal
HSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
HSYNCI input (horizontal synchronization signal) is
output directly
IHI signal (with 2fH
modification)
Meaningless unless there is a double-frequency
part in the HSYNCI input (horizontal
synchronization signal)
CL1 signal
HSYNCI input (horizontal synchronization signal) 1
interval is changed before output
IHG signal
Internal synchronization signal is output
S-on-G
mode
CSYNCI
input
Composite HSYNCI
mode
input
Separate
mode
HSYNCI
input
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Section 13 Timer Connection
13.3.8
VSYNCO Output
With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IVI signal source and the waveform required by external
circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10.
Table 13.10 Meaning of VSYNCO Output in Each Mode
Mode
IVI Signal
IVO Signal
Meaning of IVO Signal
No signal
VFBACKI
input
IVI signal (without fall
modification or IHI
synchronization)
VFBACKI input is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VFBACKI input is
synchronized with HFBACKI input
IVI signal (with fall
modification, without IHI
synchronization)
VFBACKI input fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VFBACKI input fall is modified and signal is
synchronized with HFBACKI input before
output
IVG signal
Internal synchronization signal is output
IVI signal (without fall
modification or IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated
before output
IVI signal (without fall
modification, with IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, and
signal is synchronized with CSYNCI/HSYNCI
input before output
IVI signal (with fall
modification, without IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, and
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, fall is
modified, and signal is synchronized with
CSYNCI/HSYNCI input before output
IVG signal
Internal synchronization signal is output
S-on-G
PDC signal
mode or
composite
mode
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Section 13 Timer Connection
Mode
IVI Signal
IVO Signal
Meaning of IVO Signal
Separate
mode
VSYNCI
input
IVI signal (without fall
modification or IHI
synchronization)
VSYNCI input (vertical synchronization signal)
is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VSYNCI input (vertical
synchronization signal) is synchronized with
HSYNCI input (horizontal synchronization
signal)
IVI signal (with fall
modification, without IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified and signal is synchronized with
HSYNCI input (horizontal synchronization
signal) before output
IVG signal
Internal synchronization signal is output
13.3.9
CBLANK Output
Using the signals generated/selected with timer connection, it is possible to generate a waveform
based on the composite synchronization signal (blanking waveform).
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the
IVO signal.
The composition logic is shown in figure 13.9.
HFBACKI input (positive)
VFBACKI input (positive)
Falling edge sensing
Reset
Rising edge sensing
Set
Q
CBLANK signal
(positive)
IVO signal (positive)
Figure 13.9 CBLANK Output Waveform Generation
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Section 13 Timer Connection
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
14.1
Overview
This LSI have an on-chip watchdog timer with two channels (WDT0, WDT1) for monitoring
system operation. The WDT outputs an overflow signal (RESO) if a system crash prevents the
CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can
also generate an internal reset signal or internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
14.1.1
Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• Internal reset or internal interrupt generated when the timer counter overflows
 WOVI interrupt generation in interval timer mode
 Choice of internal reset or NMI interrupt generation in watchdog timer mode
• RESO output in watchdog timer mode
 In watchdog timer mode, a low-level signal is output from the RESO pin when the counter
overflows (when internal reset is selected)
• Choice of 8 (WDT0) or 16 (WDT1) counter input clocks
 Maximum WDT interval: system clock period × 131072 × 256
 Subclock can be selected for the WDT1 input counter
Maximum interval when the subclock is selected: subclock period × 256 × 256
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Section 14 Watchdog Timer (WDT)
14.1.2
Block Diagram
Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1.
WOVI0
(interrupt request
signal)
RESO signal*1
Interrupt
control
Overflow
Clock
Clock
select
Reset
control
Internal reset
signal*1
Internal clock
source
TCNT
TCSR
Module bus
Bus
interface
Internal bus
Internal NMI
interrupt request
signal*2
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
WDT0
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (a) Block Diagram of WDT0
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Section 14 Watchdog Timer (WDT)
Internal NMI
(interrupt request
signal)*2
Interrupt
control
RESO signal*1
Overflow
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
select
Clock
Reset
control
Internal reset
signal*1
Internal clock
source
TCNT
φSUB/2
φSUB/4
φSUB/8
φSUB/16
φSUB/32
φSUB/64
φSUB/128
φSUB/256
TCSR
Bus
interface
Module bus
Internal bus
WOVI1
(interrupt request
signal)
WDT1
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
Notes: 1. RESO pin output goes low when the internal reset signal is generated by overflow of TCNT
in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over
the internal reset signal.
2. The internal NMI interrupt request signal can be output independently by either WDT0 or
WDT1. The interrupt controller does not distinguish between NMI interrupt requests from
WDT0 and WDT1.
Figure 14.1 (b) Block Diagram of WDT1
14.1.3
Pin Configuration
Table 14.1 describes the WDT input pin.
Table 14.1 WDT Pin
Name
Symbol
I/O
Function
Reset output pin
RESO
Output
Watchdog timer mode counter overflow signal
output
External subclock input pin
EXCL
Input
WDT1 prescaler counter input clock
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Section 14 Watchdog Timer (WDT)
14.1.4
Register Configuration
The WDT has four registers, as summarized in table 14.2. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 14.2 WDT Registers
Address*
1
Channel
0
1
Common
Name
Abbreviation R/W
Initial Value
Write*
H'00
H'FFA8
H'FFA8
2
Read
Timer control/status
register 0
TCSR0
R/(W)*
Timer counter 0
TCNT0
R/W
H'00
H'FFA8
H'FFA9
Timer control/status
register 1
TCSR1
3
R/(W)*
H'00
H'FFEA
H'FFEA
Timer counter 1
TCNT1
R/W
H'00
H'FFEA
H'FFEB
System control
register
SYSCR
R/W
H'09
H'FFC4
H'FFC4
3
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 14.2.4, Notes on Register Access.
3. Only 0 can be written in bit 7, to clear the flag.
14.2
Register Descriptions
14.2.1
Timer Counter (TCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (RESO) output,
an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, depending
on the mode selected by the WT/IT bit and RST/NMI bit.
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Section 14 Watchdog Timer (WDT)
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details
see section 14.2.4, Notes on Register Access.
14.2.2
Timer Control/Status Register (TCSR)
• TCSR0
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
RSTS
RST/NMI
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear the flag.
• TCSR1
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
PSS
RST/NMI
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details
see section 14.2.4, Notes on Register Access.
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Section 14 Watchdog Timer (WDT)
Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
1
•
Write 0 in the TME bit
•
Read TCSR when OVF = 1*, then write 0 in OVF
(Initial value)
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.)
Note:
*
When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read
at least twice.
Bit 6—Timer Mode Select (WT/IT
IT):
IT Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI
interrupt when TCNT overflows. When internal reset is selected in watchdog timer mode, a lowlevel signal is output from the RESO pin.
Bit 6
WT/IT
IT
Description
0
Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when
TCNT overflows
(Initial value)
1
Watchdog timer mode: Generates a reset or NMI interrupt when TCNT overflows
At the same time, a low-level signal is output from the RESO pin (when internal reset
is selected)
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT counts
Rev. 4.00 Sep 27, 2006 page 412 of 1130
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(Initial value)
Section 14 Watchdog Timer (WDT)
TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1.
TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For
details, see the description of the CKS2 to CKS0 bits below.
WDT1 TCSR
Bit 4
PSS
Description
0
TCNT counts φ-based prescaler (PSM) divided clock pulses
1
TCNT counts φSUB-based prescaler (PSS) divided clock pulses
(Initial value)
Bit 3—Reset or NMI (RST/NMI
NMI):
NMI Specifies whether an internal reset or NMI interrupt is
requested on TCNT overflow in watchdog timer mode.
Bit 3
RST/NMI
NMI
Description
0
An NMI interrupt is requested
1
An internal reset is requested
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,
obtained by dividing the system clock (φ), or subclock (φSUB) for input to TCNT.
• WDT0 input clock selection
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Clock
Overflow Period* (when φ = 20 MHz)
0
0
0
φ/2 (Initial value)
25.6 µs
1
φ/64
819.2 µs
0
φ/128
1.6 ms
1
φ/512
6.6 ms
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
0
φ/32768
419.4 ms
1
φ/131072
1.68 s
1
1
0
1
Note:
*
Description
The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
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Section 14 Watchdog Timer (WDT)
• WDT1 input clock selection
Bit 4
Bit 2
Bit 1
Bit 0
PSS
CKS2
CKS1
CKS0
Clock
Overflow Period* (when φ = 20 MHz
and φSUB = 32.768 kHz)
0
0
0
0
φ/2 (Initial value)
25.6 µs
1
φ/64
819.2 µs
0
φ/128
1.6 ms
1
φ/512
6.6 ms
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
0
φ/32768
419.4 ms
1
φ/131072
1.68 s
0
φSUB/2
15.6 ms
1
φSUB/4
31.3 ms
0
φSUB/8
62.5 ms
1
φSUB/16
125 ms
0
φSUB/32
250 ms
1
φSUB/64
500 ms
0
φSUB/128
1s
1
φSUB/256
2s
1
1
0
1
1
0
0
1
1
0
1
Note:
14.2.3
*
Description
The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a
Rev. 4.00 Sep 27, 2006 page 414 of 1130
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Section 14 Watchdog Timer (WDT)
read-only bit. It is set to 1 by an external reset, and when the RST/NMI bit is 1, is cleared to 0 by
an internal reset due to watchdog timer overflow.
Bit 3
XRST
Description
0
Reset is generated by watchdog timer overflow
1
Reset is generated by external reset input
14.2.4
(Initial value)
Notes on Register Access
The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult
to write to. The procedures for writing to and reading these registers are given below.
Writing to TCNT and TCSR (Example of WDT0)
These registers must be written to by a word transfer instruction. They cannot be written to with
byte transfer instructions.
Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
8 7
H'5A
Address: H'FFA8
0
Write data
TCSR write
15
Address: H'FFA8
8 7
H'A5
0
Write data
Figure 14.2 Format of Data Written to TCNT and TCSR (Example of WDT0)
Reading TCNT and TCSR (Example of WDT0)
These registers are read in the same way as other registers. The read addresses are H'FFA8 for
TCSR, and H'FFA9 for TCNT.
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Section 14 Watchdog Timer (WDT)
14.3
Operation
14.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, an
internal reset or NMI interrupt request is generated.
When the RST/NMI bit is set to 1, the chip is reset for 518 system clock periods (518 φ) by a
counter overflow, and at the same time a low-level signal is output from the RESO pin for 132
states. This is illustrated in figure 14.3. The system can be reset using this RESO signal.
When the RST/NMI bit cleared to 0, an NMI interrupt request is generated by a counter overflow.
In this case, the RESO output signal remains high.
An internal reset request from the watchdog timer and reset input from the RES pin are handled
via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR.
If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request
and an NMI pin interrupt request must therefore be avoided.
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Section 14 Watchdog Timer (WDT)
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
H'00 written
to TCNT
OVF = 1*
WT/IT = 1 H'00 written
TME = 1 to TCNT
RESO and internal
reset generated
RESO signal
132 system
clock periods
Internal reset signal
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
OVF: Overflow flag
518 system
clock periods
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
Figure 14.3 Operation in Watchdog Timer Mode (RST/NMI
NMI = 1)
14.3.2
Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 14.4. This function can be used to
generate interrupt requests at regular intervals.
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Section 14 Watchdog Timer (WDT)
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 14.4 Operation in Interval Timer Mode
14.3.3
Timing of Setting of Overflow Flag (OVF)
The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an
interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5.
If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF
bit in TCSR is set to 1 and at the same time an NMI interrupt is requested.
φ
TCNT
H'FF
Overflow signal
(internal signal)
OVF
Figure 14.5 Timing of OVF Setting
Rev. 4.00 Sep 27, 2006 page 418 of 1130
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H'00
Section 14 Watchdog Timer (WDT)
14.3.4
RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI
bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a
low-level signal is output from the RESO pin. The timing is shown in figure 14.6.
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
132 states
518 states
Figure 14.6 RESO Signal Output Timing
14.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in
watchdog timer mode, an overflow generates an NMI interrupt request.
Rev. 4.00 Sep 27, 2006 page 419 of 1130
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Section 14 Watchdog Timer (WDT)
14.5
Usage Notes
14.5.1
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.7 shows this operation.
TCNT write cycle
T1
T2
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.7 Contention between TCNT Write and Increment
14.5.2
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
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Section 14 Watchdog Timer (WDT)
14.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
14.5.4
System Reset by RESO Signal
If the RESO output signal is input to the chip’s RES pin, the chip will not be initialized correctly.
Ensure that the RESO signal is not logically input to the chip’s RES pin. When resetting the entire
system with the RESO signal, use a circuit such as that shown in figure 14.8.
Chip
Reset input
Reset signal to entire system
RES
RESO
Figure 14.8 Sample Circuit for System Reset by RESO Signal
14.5.5
Counter Value in Transitions between High-Speed Mode, Subactive Mode, and
Watch Mode
If the mode is switched between high-speed mode and subactive mode or between high-speed
mode and watch mode when WDT1 is used as a realtime clock counter, an error will occur in the
counter value when the internal clock is switched.
When the mode is switched from high-speed mode to subactive mode or watch mode, the
increment timing is delayed by approximately 2 or 3 clock cycles when the WDT1 control clock is
switched from the main clock to the subclock.
Also, since the main clock oscillator is halted during subclock operation, when the mode is
switched from watch mode or subactive mode to high-speed mode, the clock is not supplied until
internal oscillation stabilizes. As a result, after oscillation is started, counter incrementing is halted
during the oscillation stabilization time set by bits STS2 to STS0 in SBYCR, and there is a
corresponding discrepancy in the counter value.
Rev. 4.00 Sep 27, 2006 page 421 of 1130
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Section 14 Watchdog Timer (WDT)
Caution is therefore required when using WDT1 as the realtime clock counter.
No error occurs in the counter value while WDT1 is operating in the same mode.
14.5.6
OVF Flag Clear Condition
To clear OVF flag in WOVI handling routine, read TCSR when OVF = 1, then write with 0 to
OVF, as stated above. When WOVI is masked and OVF flag is poling, if contention between OVF
flag set and TCSR read is occurred, OVF = 1 is read but OVF can not be cleared by writing with 0
to OVF.
In this case, reading TCSR when OVF = 1 two times meet the requirements of OVF clear
condition. Please read TCSR when OVF = 1 two times before writing with 0 to OVF.
LOOP
BTST.B
#7, @TCSR
BEQ
LOOP
; if OVF=1, exit from loop
MOV.B
@TCSR, R0L
; OVF=1 read again
MOV.W
#H'A521, R0
; OVF flag clear
MOV.W
R0,@TCSR
;
Rev. 4.00 Sep 27, 2006 page 422 of 1130
REJ09B0327-0400
; OVF flag read
:
Section 15 Serial Communication Interface (SCI, IrDA)
Section 15 Serial Communication Interface (SCI, IrDA)
15.1
Overview
This LSI are equipped with a 3-channel serial communication interface (SCI). The SCI can handle
both asynchronous and clocked synchronous serial communication. A function is also provided for
serial communication between processors (multiprocessor communication function).
One of the three SCI channels can transmit and receive IrDA communication waveforms based on
IrDA specification version 1.0.
15.1.1
Features
SCI features are listed below.
• Choice of asynchronous or synchronous serial communication mode
Asynchronous mode:
 Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
 A multiprocessor communication function is provided that enables serial data
communication with a number of processors
 Choice of 12 serial data transfer formats
Data length:
7 or 8 bits
Stop bit length:
1 or 2 bits
Parity:
Even, odd, or none
Multiprocessor bit:
1 or 0
 Receive error detection: Parity, overrun, and framing errors
 Break detection:
Break can be detected by reading the RxD pin level
directly in case of a framing error
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Section 15 Serial Communication Interface (SCI, IrDA)
Synchronous mode:
 Serial data communication is synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
 One serial data transfer format
Data length:
8 bits
 Receive error detection: Overrun errors detected
• Full-duplex communication capability
 The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
 Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• LSB-first or MSB-first transfer can be selected
 This selection can be made regardless of the communication mode (with the exception of
7-bit data transfer in asynchronous mode)*
Note: * LSB-first transfer is used in the examples in this section.
• Built-in baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Capability of transmit and receive clock output
 The P86/SCK1 and P42/SCK2 pins are CMOS type outputs
 The P52/SCK0 pin is an NMOS push-pull type output in the H8S/2148 Group and
H8S/2147N, and is a CMOS output in the H8S/2144 Group (When the P52/SCK0 pin is
used as an output in the H8S/2148 Group and H8S/2147N, external pull-up resistor must be
connected in order to output high level)
• The transmit-data-empty interrupt and receive-data-full interrupt can activate the data transfer
controller (DTC) to execute data transfer
• Four interrupt sources
 Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive
error) that can issue requests independently
 The transmit-data-empty interrupt and receive-data-full interrupt can activate the data
transfer controller (DTC) to execute data transfer
Rev. 4.00 Sep 27, 2006 page 424 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
15.1.2
Block Diagram
Bus interface
Figure 15.1 shows a block diagram of the SCI.
Module data bus
RDR
RxD
TxD
RSR
TDR
TSR
BRR
φ
Baud rate
generator
Transmission/
reception control
Parity generation
Parity check
SCK
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
SCMR
SSR
SCR
SMR
Internal
data bus
φ/4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Serial interface mode register
Bit rate register
Figure 15.1 Block Diagram of SCI
Rev. 4.00 Sep 27, 2006 page 425 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
15.1.3
Pin Configuration
Table 15.1 shows the serial pins used by the SCI.
Table 15.1 SCI Pins
Channel
Pin Name
Symbol*
I/O
Function
0
Serial clock pin 0
SCK0
I/O
SCI0 clock input/output
Receive data pin 0
RxD0
Input
SCI0 receive data input
Transmit data pin 0
TxD0
Output
SCI0 transmit data output
1
2
Note:
15.1.4
*
Serial clock pin 1
SCK1
I/O
SCI1 clock input/output
Receive data pin 1
RxD1
Input
SCI1 receive data input
Transmit data pin 1
TxD1
Output
SCI1 transmit data output
Serial clock pin 2
SCK2
I/O
SCI2 clock input/output
Receive data pin 2
RxD2/IrRxD
Input
SCI2 receive data input
(normal/IrDA)
Transmit data pin 2
TxD2/IrTxD
Output
SCI2 transmit data output
(normal/IrDA)
The abbreviations SCK, RxD, and TxD are used in the text, omitting the channel
number.
Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.2 SCI Registers
Channel
Name
Abbreviation
R/W
Initial Value Address*
0
Serial mode register 0
SMR0
R/W
H'00
Bit rate register 0
BRR0
R/W
H'FF
H'FFD8*
3
H'FFD9*
Serial control register 0
SCR0
R/W
H'00
H'FFDA
H'FF
H'FFDB
H'84
H'FFDC
H'FFDD
3
H'FFDE*
1
2
Transmit data register 0
TDR0
R/W
Serial status register 0
SSR0
R/(W)*
Receive data register 0
RDR0
R
H'00
Serial interface mode register 0
SCMR0
R/W
H'F2
Serial mode register 1
SMR1
R/W
H'00
Bit rate register 1
BRR1
R/W
H'FF
2
3
H'FF88*
3
H'FF89*
3
Serial control register 1
SCR1
R/W
H'00
H'FF8A
Transmit data register 1
TDR1
R/W
H'FF
H'FF8B
Serial status register 1
SSR1
R/(W)*
H'84
H'FF8C
Receive data register 1
RDR1
R
H'00
Serial interface mode register 1
SCMR1
R/W
H'F2
H'FF8D
3
H'FF8E*
Serial mode register 2
SMR2
R/W
H'00
Bit rate register 2
BRR2
R/W
H'FF
H'FFA0*
3
H'FFA1*
Serial control register 2
SCR2
R/W
H'00
H'FFA2
Transmit data register 2
TDR2
R/W
H'FF
H'FFA3
SSR2
2
R/(W)*
H'84
H'FFA4
Serial status register 2
Common
1
2
3
Receive data register 2
RDR2
R
H'00
H'FFA5
Serial interface mode register 2
SCMR2
R/W
H'F2
H'FFA6*
Keyboard comparator control
register
KBCOMP
R/W
H'00
H'FEE4
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
3
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
3. Some serial communication interface registers are assigned to the same addresses as
other registers. In this case, register selection is performed by the IICE bit in the serial
timer control register (STCR).
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Section 15 Serial Communication Interface (SCI, IrDA)
15.2
Register Descriptions
15.2.1
Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
15.2.2
Receive Data Register (RDR)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, continuous receive operations can be
performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Rev. 4.00 Sep 27, 2006 page 428 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
15.2.3
Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then
sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR to
TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not
performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
15.2.4
Transmit Data Register (TDR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and
starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR during serial transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.2.5
Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Communication Mode (C/A
A): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7
C/A
A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
7-bit data*
1
Note:
*
(Initial value)
When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSBfirst/MSB-first selection is not available.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multiprocessor format is used, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
1
Note:
*
(Initial value)
When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
Bit 4—Parity Mode (O/E
E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity
bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is
used.
Bit 4
O/E
E
Description
0
Even parity*
2
Odd parity*
1
1
(Initial value)
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP
Description
0
1 stop bit*
2
2 stop bits*
1
1
(Initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.8, Bit Rate Register (BRR).
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
1
15.2.6
(Initial value)
Serial Control Register (SCR)
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
1
Transmit-data-empty interrupt (TXI) request enabled
Note:
*
(Initial value)
TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
Description
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
enabled
Note:
*
RXI and ERI interrupt request cancellation can be performed by reading 1 from the
RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
Description
0
Transmission disabled*
2
Transmission enabled*
1
1
(Initial value)
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmission format before setting the TE
bit to 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
Description
0
Reception disabled*
2
Reception enabled*
1
1
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SMR setting must be performed to decide the reception format before setting the RE bit
to 1.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR
set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
•
When the MPIE bit is cleared to 0
•
When data with MPB = 1 is received
Multiprocessor interrupts enabled*
1
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note:
*
When receive data including MPB = 0 is received, receive data transfer from RSR to
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR,
is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is
set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
Transmit-end interrupt (TEI) request enabled*
1
Note:
*
(Initial value)
TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
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Section 15 Serial Communication Interface (SCI, IrDA)
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1
Bit 0
CKE1
CKE0
Description
0
0
Asynchronous mode
Internal clock/SCK pin functions as I/O port*
Synchronous mode
Internal clock/SCK pin functions as serial clock
1
output*
Asynchronous mode
Internal clock/SCK pin functions as clock output*
Synchronous mode
Internal clock/SCK pin functions as serial clock
output
Asynchronous mode
External clock/SCK pin functions as clock input*
Synchronous mode
External clock/SCK pin functions as serial clock
input
3
External clock/SCK pin functions as clock input*
1
1
0
1
Asynchronous mode
Synchronous mode
1
2
3
External clock/SCK pin functions as serial clock
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
15.2.7
Serial Status Register (SSR)
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Bit
Note:
*
Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
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Section 15 Serial Communication Interface (SCI, IrDA)
SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
Description
0
[Clearing conditions]
1
•
When 0 is written in TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
(Initial value)
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data can be written to TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
Description
0
[Clearing conditions]
1
(Initial value)
•
When 0 is written in RDRF after reading RDRF = 1
•
When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
1
(Initial value)*
When 0 is written in ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1*
2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
Description
0
[Clearing condition]
(Initial value)*
When 0 is written in FER after reading FER = 1
1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends,
2
and the stop bit is 0*
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
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1
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER
Description
0
[Clearing condition]
(Initial value)*
1
When 0 is written in PER after reading PER = 1
1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
2
match the parity setting (even or odd) specified by the O/E bit in SMR*
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
Description
0
[Clearing conditions]
1
•
When 0 is written in TDRE after reading TDRE = 1
•
When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
(Initial value)
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
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Section 15 Serial Communication Interface (SCI, IrDA)
Bit 1—Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format
in asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
Description
0
[Clearing condition]
(Initial value)*
When data with a 0 multiprocessor bit is received
1
[Setting condition]
When data with a 1 multiprocessor bit is received
Note:
*
Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
1
Data with a 1 multiprocessor bit is transmitted
Rev. 4.00 Sep 27, 2006 page 440 of 1130
REJ09B0327-0400
(Initial value)
Section 15 Serial Communication Interface (SCI, IrDA)
15.2.8
Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR
settings in synchronous mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
φ = 2 MHz
φ = 2.097152 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
150
1
103
0.16
1
300
0
207
0.16
600
0
103
1200
0
2400
4800
φ = 2.4576 MHz
N
Error
(%)
–0.04 1
174
108
0.21
1
0
217
0.21
0.16
0
108
0.21
51
0.16
0
54
0
25
0.16
0
0
12
0.16
0
9600
—
—
—
19200
—
—
31250
0
38400
—
φ = 3 MHz
N
Error
(%)
–0.26 1
212
0.03
127
0.00
1
155
0.16
0
255
0.00
1
77
0.16
0
127
0.00
0
155
0.16
–0.70 0
63
0.00
0
77
0.16
26
1.14
0
31
0.00
0
38
0.16
13
–2.48 0
15
0.00
0
19
–2.34
0
6
–2.48 0
7
0.00
0
9
–2.34
—
—
—
—
0
3
0.00
0
4
–2.34
1
0.00
—
—
—
—
—
—
0
2
0.00
—
—
—
—
—
0
1
0.00
—
—
—
n
n
Operating Frequency φ (MHz)
φ = 3.6864 MHz
φ = 4 MHz
φ = 4.9152 MHz
φ = 5 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
—
—
—
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70 0
4
0.00
38400
0
2
0.00
—
—
—
0
3
0.00
3
1.73
Rev. 4.00 Sep 27, 2006 page 442 of 1130
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0
Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ (MHz)
φ = 6 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
106
150
2
300
φ = 6.144 MHz
φ = 7.3728 MHz
φ = 8 MHz
N
Error
(%)
n
N
Error
(%)
–0.44 2
108
0.08
2
130
77
0.16
2
79
0.00
2
1
155
0.16
1
159
0.00
1
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34 0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34 0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
—
—
—
0
7
0.00
38400
0
4
–2.34 0
4
0.00
0
5
0.00
—
—
—
n
N
Error
(%)
–0.07 2
141
0.03
95
0.00
2
103
0.16
191
0.00
1
207
0.16
n
Operating Frequency φ (MHz)
φ = 9.8304 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
174
150
2
300
φ = 10 MHz
N
Error
(%)
–0.26 2
177
127
0.00
2
1
255
0.00
600
1
127
1200
0
255
2400
0
4800
φ = 12 MHz
φ = 12.288 MHz
N
Error
(%)
n
N
Error
(%)
–0.25 2
212
0.03
2
217
0.08
129
0.16
2
155
0.16
2
159
0.00
2
64
0.16
2
77
0.16
2
79
0.00
0.00
1
129
0.16
1
155
0.16
1
159
0.00
0.00
1
64
0.16
1
77
0.16
1
79
0.00
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36 0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
19
–2.34 0
19
0.00
31250
0
9
–1.70 0
9
0.00
0
11
0.00
11
2.40
38400
0
7
0.00
7
1.73
0
9
–2.34 0
9
0.00
n
0
n
0
0
Rev. 4.00 Sep 27, 2006 page 443 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ (MHz)
φ = 14 MHz
φ = 14.7456 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
248
150
2
300
φ = 16 MHz
φ = 17.2032 MHz
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
–0.17 3
64
0.70
3
70
0.03
3
75
0.48
181
0.16
2
191
0.00
2
207
0.16
2
223
0.00
2
90
0.16
2
95
0.00
2
103
0.16
2
111
0.00
600
1
181
0.16
1
191
0.00
1
207
0.16
1
223
0.00
1200
1
90
0.16
1
95
0.00
1
103
0.16
1
111
0.00
2400
0
181
0.16
0
191
0.00
0
207
0.16
0
223
0.00
4800
0
90
0.16
0
95
0.00
0
103
0.16
0
111
0.00
9600
0
45
–0.93 0
47
0.00
0
51
0.16
0
55
0.00
19200
0
22
–0.93 0
23
0.00
0
25
0.16
0
27
0.00
31250
0
13
0.00
0
14
–1.70 0
15
0.00
0
16
1.20
38400
—
—
—
0
11
0.00
12
0.16
0
13
0.00
n
0
Operating Frequency φ (MHz)
φ = 18 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
3
79
150
2
300
φ = 19.6608 MHz
φ = 20 MHz
N
Error
(%)
n
N
Error
(%)
–0.12 3
86
0.31
3
88
–0.25
233
0.16
2
255
0.00
3
64
0.16
2
116
0.16
2
127
0.00
2
129
0.16
600
1
233
0.16
1
255
0.00
2
64
0.16
1200
1
116
0.16
1
127
0.00
1
129
0.16
2400
0
233
0.16
0
255
0.00
1
64
0.16
4800
0
116
0.16
0
127
0.00
0
129
0.16
9600
0
58
–0.69 0
63
0.00
0
64
0.16
19200
0
28
1.02
0
31
0.00
0
32
–1.36
31250
0
17
0.00
0
19
–1.70 0
19
0.00
38400
0
14
–2.34 0
15
0.00
15
1.73
n
Rev. 4.00 Sep 27, 2006 page 444 of 1130
REJ09B0327-0400
0
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode)
Operating Frequency φ (MHz)
φ = 2 MHz
Bit Rate
φ = 4 MHz
(bits/s)
n
N
n
N
110
3
70
—
—
250
2
124
2
500
1
249
2
1k
1
124
2.5 k
0
5k
φ = 8 MHz
φ = 10 MHz
φ = 16 MHz
n
N
n
N
n
N
249
3
124
—
—
3
249
124
2
249
—
—
3
1
249
2
124
—
—
199
1
99
1
199
1
0
99
0
199
1
99
10 k
0
49
0
99
0
25 k
0
19
0
39
0
50 k
0
9
0
19
100 k
0
4
0
250 k
0
1
0
0*
500 k
1M
φ = 20 MHz
n
N
124
—
—
2
249
—
—
249
2
99
2
124
1
124
1
199
1
249
199
0
249
1
99
1
124
79
0
99
0
159
0
199
0
39
0
49
0
79
0
99
9
0
19
0
24
0
39
0
49
0
3
0
7
0
9
0
15
0
19
0
1
0
3
0
4
0
7
0
9
0
0*
0
1
0
3
0
4
0
1
0
0*
2.5 M
5M
0
0*
Legend:
Blank: Cannot be set.
—: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Note: As far as possible, the setting should be made so that the error is no more than 1%.
Rev. 4.00 Sep 27, 2006 page 445 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
The BRR setting is found from the following equations.
Asynchronous mode:
N=
φ
64 ×
22n–1
×B
× 106 – 1
Synchronous mode:
N=
Where B:
N:
φ:
n:
φ
× 106 – 1
8 × 22n–1 × B
Bit rate (bits/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is found from the following equation:


φ × 106
Error (%) = 
– 1 × 100
2n–1
(N
+
1)
×
B
×
64
×
2


Rev. 4.00 Sep 27, 2006 page 446 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6
and 15.7 show the maximum bit rates with external clock input.
Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
19.6608
614400
0
0
20
625000
0
0
Rev. 4.00 Sep 27, 2006 page 447 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
19.6608
4.9152
307200
20
5.0000
312500
Rev. 4.00 Sep 27, 2006 page 448 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
15.2.9
Serial Interface Mode Register (SCMR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W
R/W
—
R/W
SCMR is an 8-bit readable/writable register used to select SCI functions.
SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3
SDIR
Description
0
TDR contents are transmitted LSB-first
(Initial value)
Receive data is stored in RDR LSB-first
1
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Rev. 4.00 Sep 27, 2006 page 449 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in
SMR.
Bit 2
SINV
Description
0
TDR contents are transmitted without modification
(Initial value)
Receive data is stored in RDR without modification
1
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be
written in this bit.
Bit 0
SMIF
Description
0
Normal SCI mode
1
Reserved mode
(Initial value)
15.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bit MSTP7, MSTP6, or MSTP5 is set to 1, SCI0, SCI1, or SCI2 operation, respectively,
stops at the end of the bus cycle and a transition is made to module stop mode. For details, see
section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 4.00 Sep 27, 2006 page 450 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode.
MSTPCRL
Bit 7
MSTP7
Description
0
SCI0 module stop mode is cleared
1
SCI0 module stop mode is set
(Initial value)
Bit 6—Module Stop (MSTP6): Specifies the SCI1 module stop mode.
MSTPCRL
Bit 6
MSTP6
Description
0
SCI1 module stop mode is cleared
1
SCI1 module stop mode is set
(Initial value)
Bit 5—Module Stop (MSTP5): Specifies the SCI2 module stop mode.
MSTPCRL
Bit 5
MSTP5
Description
0
SCI2 module stop mode is cleared
1
SCI2 module stop mode is set
(Initial value)
Rev. 4.00 Sep 27, 2006 page 451 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
15.2.11 Keyboard Comparator Control Register (KBCOMP)
7
6
5
4
3
2
1
0
IrE
IrCKS2
IrCKS1
IrCKS0
KBADE
KBCH2
KBCH1
KBCH0
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KBCOMP is an 8-bit readable/writable register that selects the functions of SCI2 and the A/D
converter.
KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—IrDA Enable (IrE): Specifies normal SCI operation or IrDA operation for SCI2
input/output.
Bit 7
IrE
Description
0
The TxD2/IrTxD and RxD2/IrRxD pins function as TxD2 and RxD2
1
The TxD2/IrTxD and RxD2/IrRxD pins function as IrTxD and IrRxD
(Initial value)
Bits 6 to 4—IrDA Clock Select 2 to 0 (IrCKS2 to IrCKS0): These bits specify the high pulse
width in IrTxD output pulse encoding when the IrDA function is enabled.
Bit 6
Bit 5
Bit 4
IrCKS2
IrCKS1
IrCKS0
Description
0
0
0
B × 3/16 (3/16 of the bit rate)
1
φ/2
1
1
0
1
0
φ/4
1
φ/8
0
φ/16
1
φ/32
0
φ/64
1
φ/128
(Initial value)
Bits 3 to 0—Keyboard Comparator Control: See the description in section 20, A/D converter.
Rev. 4.00 Sep 27, 2006 page 452 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
15.3
Operation
15.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using SMR
as shown in table 15.8. The SCI clock is determined by a combination of the C/A bit in SMR and
the CKE1 and CKE0 bits in SCR, as shown in table 15.9.
Asynchronous Mode:
• Data length: Choice of 7 or 8 bits
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source
 When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency as
the bit rate can be output
 When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate
generator is not used)
Synchronous Mode:
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source
 When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
 When external clock is selected:
The built-in baud rate generator is not used, and the SCI operates on the input serial clock
Rev. 4.00 Sep 27, 2006 page 453 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.8 SMR Settings and Serial Transfer Format Selection
SMR Settings
SCI Transfer Format
Bit 7
Bit 6
Bit 2
Bit 5
Bit 3
C/A
A
CHR
MP
PE
STOP
Mode
0
0
0
0
0
Asynchronous
mode
1
1
Data
Length
Multiprocessor
Bit
Parity
Bit
Stop Bit
Length
8-bit data
No
No
1 bit
2 bits
0
Yes
1
1
0
0
1
0
2 bits
7-bit data
No
1 bit
Yes
1 bit
1
2 bits
1
0
1
1
1
—
—
—
0
—
1
—
0
—
1
—
—
1 bit
2 bits
Asynchronous
mode (multiprocessor format)
8-bit data
Yes
No
1 bit
2 bits
7-bit data
1 bit
2 bits
Synchronous mode 8-bit data
No
None
Table 15.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
SCI Transfer Clock
Bit 7
Bit 1
Bit 0
C/A
A
CKE1
CKE0
Mode
0
0
0
Asynchronous
mode
1
1
0
Clock
Source
SCK Pin Function
Internal
SCI does not use SCK pin
Outputs clock with same frequency as bit
rate
External
Inputs clock with frequency of 16 times
the bit rate
Internal
Outputs serial clock
External
Inputs serial clock
1
1
0
0
1
1
Synchronous
mode
0
1
Rev. 4.00 Sep 27, 2006 page 454 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
15.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-bycharacter basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
Idle state
(mark state)
LSB
1
Serial
data
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity Stop bit(s)
bit
1 bit,
or none
1 or
2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 4.00 Sep 27, 2006 page 455 of 1130
REJ09B0327-0400
Section 15 Serial Communication Interface (SCI, IrDA)
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected by settings in SMR.
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
STOP
0
1
0
1
S
8-bit data
P
STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
Rev. 4.00 Sep 27, 2006 page 456 of 1130
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3
4
5
6
7
8
9
10
11
12
Section 15 Serial Communication Interface (SCI, IrDA)
Clock
Either an internal clock generated by the built-in baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table
15.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 15.3 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Data Transfer Operations
SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation is uncertain.
Rev. 4.00 Sep 27, 2006 page 457 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.4 shows a sample SCI initialization flowchart.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. This is not
necessary if an external clock is
used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completed>
Figure 15.4 Sample SCI Initialization Flowchart
Rev. 4.00 Sep 27, 2006 page 458 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for
serial transmission.
The following procedure should be used for serial data transmission.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 15.5 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a TEI interrupt request is generated.
Figure 15.6 shows an example of the operation for transmission in asynchronous mode.
Rev. 4.00 Sep 27, 2006 page 460 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
handling, ensure that the ORER,
PER ∨ FER ∨ ORER = 1?
PER, and FER flags are all
[3]
cleared to 0. Reception cannot
No
Error handling
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1?
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
Figure 15.7 Sample Serial Reception Data Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
[3]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
No
Break?
Yes
Framing error handling
Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 15.7 Sample Serial Reception Data Flowchart (cont)
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Section 15 Serial Communication Interface (SCI, IrDA)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in RSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
b. Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
c. Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error* is detected in the error check, the operation is as shown in table 15.11.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
Rev. 4.00 Sep 27, 2006 page 464 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Table 15.11 Receive Errors and Conditions for Occurrence
Receive Error
Abbreviation
Occurrence Condition
Data Transfer
Overrun error
ORER
When the next data reception is Receive data is not
completed while the RDRF flag transferred from RSR to
in SSR is set to 1
RDR
Framing error
FER
When the stop bit is 0
Parity error
PER
When the received data differs Receive data is transferred
from the parity (even or odd) set from RSR to RDR
in SMR
Receive data is transferred
from RSR to RDR
Figure 15.8 shows an example of the operation for reception in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 15.9 shows an example of inter-processor communication using a multiprocessor format.
Data Transfer Format
There are four data transfer formats.
When a multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 15.10.
Clock
See the section on asynchronous mode.
Rev. 4.00 Sep 27, 2006 page 466 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
ID transmission cycle:
receiving station
specification
(MPB = 0)
Data transmission cycle:
data transmission to
receiving station specified
by ID
Legend:
MPB: Multiprocessor bit
Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Data Transfer Operations
Multiprocessor Serial Data Transmission: Figure 15.10 shows a sample flowchart for
multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
Rev. 4.00 Sep 27, 2006 page 467 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
[1] [1] SCI initialization:
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmitdata-empty interrupt (TXI)
request, and data is written to
TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart
Rev. 4.00 Sep 27, 2006 page 468 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit
One multiprocessor bit (MPBT value) is output.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a transmit-end interrupt (TEI) request is generated.
Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format.
Rev. 4.00 Sep 27, 2006 page 469 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
1
Start
bit
0
Multiprocessor Stop
bit
bit
Data
D0
D1
D7
0/1
1
Start
bit
0
Multiproces- Stop
1
sor bit bit
Data
D0
D1
D7
0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt handling
routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 15.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for
multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Rev. 4.00 Sep 27, 2006 page 470 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start reception
Read MPIE bit in SCR
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1?
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station’s ID?
Yes
[5] Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
[5]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont)
Rev. 4.00 Sep 27, 2006 page 472 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Figure 15.13 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID2
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
Data2
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 15.13 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 4.00 Sep 27, 2006 page 473 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.4
Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 15.14 shows the general format for synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Don’t care
Note: * High except in continuous transfer
Figure 15.14 Data Format in Synchronous Communication
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
In synchronous serial communication, one character consists of data output starting with the LSB
and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial
clock.
Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
Rev. 4.00 Sep 27, 2006 page 474 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive
operations in units of one character, select an external clock as the clock source.
Data Transfer Operations
SCI Initialization (Synchronous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 15.15 shows a sample SCI initialization flowchart.
Rev. 4.00 Sep 27, 2006 page 475 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
[3] Write a value corresponding to the bit
rate to BRR. This is not necessary if an
external clock is used.
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE bit and RE bit should both be cleared
to 0 or set to 1 simultaneously.
Figure 15.15 Sample SCI Initialization Flowchart
Rev. 4.00 Sep 27, 2006 page 476 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for
serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR.
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
<End>
Figure 15.16 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is held in a constant state.
Figure 15.17 shows an example of SCI operation in transmission.
Rev. 4.00 Sep 27, 2006 page 478 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
TXI interrupt
and TDRE flag
request generated
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.17 Example of SCI Operation in Transmission
Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to check that the
ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive
operations will be possible.
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Section 15 Serial Communication Interface (SCI, IrDA)
[1]
Initialization
Start reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1?
No
Error handling
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DTC is
activated by a receive-data-full
interrupt (RXI) request and the
RDR value is read.
<End>
[3]
Error handling
Overrun error handling
Clear ORER flag in SSR to 0
<End>
Figure 15.18 Sample Serial Reception Flowchart
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Section 15 Serial Communication Interface (SCI, IrDA)
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 15.19 shows an example of SCI operation in reception.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 15.19 Example of SCI Operation in Reception
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20
shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
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Section 15 Serial Communication Interface (SCI, IrDA)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to
1.
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
Yes
[3]
Error handling
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1?
Yes
[5] Serial transmission/reception
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to
0, then set both these bits to 1 simultaneously.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR and clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive-datafull interrupt (RXI) request and the
RDR value is read.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 15 Serial Communication Interface (SCI, IrDA)
15.3.5
IrDA Operation
Figure 15.21 shows a block diagram of the IrDA function.
When the IrDA function is enabled with bit IrE in KBCOMP, the SCI channel 2 TxD2 and RxD2
signals are subjected to waveform encoding/decoding conforming to IrDA specification version
1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is
possible to implement infrared transmission/reception conforming to the IrDA specification
version 1.0 system.
In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600
bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in the this
LSI does not include a function for varying the transfer rate automatically, the transfer rate setting
must be changed by software.
IrDA
TxD2/IrTxD
Pulse encoder
RxD2/IrRxD
Pulse decoder
SCI2
TxD
RxD
KBCOMP
Figure 15.21 Block Diagram of IrDA Function
Transmission
In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the
IrDA interface (see figure 15.22).
When the serial data is 0, a high-level pulses of 3/16 the bit rate (interval equivalent to the width
of one bit) is output (initial value). The high-level pulse can be varied according to the setting of
bits IrCKS2 to IrCKS0 in KBCOMP.
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Section 15 Serial Communication Interface (SCI, IrDA)
The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) ×
bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set as the
minimum high-level pulse width at 1.41 µs or above.
When the serial data is 1, no pulse is output.
UART frame
Data
Start
bit
1
0
1
0
0
Stop
bit
1
0
Transmission
1
1
0
Reception
IR frame
Data
Start
bit
0
1
0
1
Bit
interval
0
0
Stop
bit
1
1
0
1
Pulse width is 1.6 µs
to 3/16 bit interval
Figure 15.22 IrDA Transmit/Receive Operations
Reception
In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the
SCI.
When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit
interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will
be identified as a 0 signal.
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Section 15 Serial Communication Interface (SCI, IrDA)
High-Level Pulse Width Selection
Table 15.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this
LSI operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit
rate in transmission.
Table 15.12 Bit IrCKS2 to IrCKS0 Settings
Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row)
Operating
Frequency
φ (MHz)
2400
9600
19200
38400
57600
115200
78.13
19.53
9.77
4.88
3.26
1.63
2
010
010
010
010
010
—
2.097152
010
010
010
010
010
—
2.4576
010
010
010
010
010
—
3
011
011
011
011
011
—
3.6864
011
011
011
011
011
011
4.9152
011
011
011
011
011
011
5
011
011
011
011
011
011
6
100
100
100
100
100
100
6.144
100
100
100
100
100
100
7.3728
100
100
100
100
100
100
8
100
100
100
100
100
100
9.8304
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
Legend:
—: An SCI bit rate setting cannot be mode.
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Section 15 Serial Communication Interface (SCI, IrDA)
15.4
SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 15.13 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Table 15.13 SCI Interrupt Sources
Channel
Interrupt
Source
Description
DTC Activation
Priority*
0
ERI
Receive error (ORER, FER, or PER)
Not possible
High
RXI
Receive data register full (RDRF)
Possible
TXI
Transmit data register empty (TDRE)
Possible
TEI
Transmit end (TEND)
Not possible
ERI
Receive error (ORER, PER, or PER)
Not possible
RXI
Receive data register full (RDRF)
Possible
TXI
Transmit data register empty (TDRE)
Possible
TEI
Transmit end (TEND)
Not possible
ERI
Receive error (ORER, PER, or PER)
Not possible
RXI
Receive data register full (RDRF)
Possible
TXI
Transmit data register empty (TDRE)
Possible
TEI
Transmit end (TEND)
Not possible
1
2
Note:
*
Low
The table shows the initial state immediately after a reset. Relative channel priorities
can be changed by the interrupt controller.
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
Rev. 4.00 Sep 27, 2006 page 486 of 1130
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Section 15 Serial Communication Interface (SCI, IrDA)
TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance,
and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be
accepted in this case.
15.5
Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously
If a number of receive errors occur at the same time, the state of the status flags in SSR is as
shown in table 15.14. If there is an overrun error, data is not transferred from RSR to RDR, and
the receive data is lost.
Table 15.14 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR to RDR
Receive Errors
1
1
0
0
X
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
X
Overrun error + framing error +
parity error
Notes: O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
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Section 15 Serial Communication Interface (SCI, IrDA)
Break Detection and Processing
When a framing error (FER) is detected, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
Sending a Break
The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by
DR and DDR. This feature can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
Receive Error Flags and Transmit Operations (Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
base clock. This is illustrated in figure 15.23.
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Section 15 Serial Communication Interface (SCI, IrDA)
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 15.23 Receive Data Sampling Timing in Asynchronous Mode
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = 0.5 –
Where M:
N:
D:
L:
F:
1
D – 0.5
(1 + F) × 100%
– (L – 0.5)F –
2N
N
.......... (1)
Receive margin (%)
Ratio of bit rate to clock (N = 16)
Clock duty (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
M = 0.5 –
1
× 100%
2 × 16
= 46.875%
.......... (2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
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Section 15 Serial Communication Interface (SCI, IrDA)
Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI).
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
Note: When operating on an external clock, set t > 4 states.
Figure 15.24 Example of Synchronous Transmission by DTC
Rev. 4.00 Sep 27, 2006 page 490 of 1130
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D7
2
Section 16 I C Bus Interface [Option]
2
Section 16 I C Bus Interface [Option]
2
A two-channel I C bus interface is available as an option in the H8S/2148 Group and H8S/2147N.
2
The I C bus interface is not available for the H8S/2144 Group. Observe the following notes when
using this option.
1. For mask-ROM versions, a W is added to the part number in products in which this optional
function is used.
Examples: HD6432147SWFA
2. The product number is identical for F-ZTAT versions. However, be sure to inform your
Renesas sales representative if you will be using this option.
16.1
Overview
2
A two-channel I C bus interface is available for the H8S/2148 Group and H8S/2147N as an
2
2
option. The I C bus interface conforms to and provides a subset of the Philips I C bus (inter-IC
2
bus) interface functions. The register configuration that controls the I C bus differs partly from the
Philips configuration, however.
2
Each I C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
16.1.1
Features
• Selection of addressing format or non-addressing format
 I C bus format: addressing format with acknowledge bit, for master/slave operation
2
 Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I C bus interface (I C bus format)
2
2
• Two ways of setting slave address (I C bus format)
2
• Start and stop conditions generated automatically in master mode (I C bus format)
2
• Selection of acknowledge output levels when receiving (I C bus format)
2
• Automatic loading of acknowledge bit when transmitting (I C bus format)
2
• Wait function in master mode (I C bus format)
2
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
Rev. 4.00 Sep 27, 2006 page 491 of 1130
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2
Section 16 I C Bus Interface [Option]
• Wait function in slave mode (I C bus format)
2
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
 Data transfer end (including transmission mode transition with I C bus format and address
reception after loss of master arbitration)
2
 Address match: when any slave address matches or the general call address is received in
2
slave receive mode (I C bus format)
 Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
 Two pins—P52/SCL0 and P97/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
 Two pins—P86/SCL1 and P42/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
• Automatic switching from formatless mode to I C bus format (channel 0 only)
2
 Formatless operation (no start/stop conditions, non-addressing mode) in slave mode
 Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
 Automatic switching from formatless mode to I C bus format on the fall of the SCL pin
2
16.1.2
Block Diagram
2
Figure 16.1 shows a block diagram of the I C bus interface.
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different specifications for permissible applied
voltages. For details, see section 26, Electrical Characteristics.
Rev. 4.00 Sep 27, 2006 page 492 of 1130
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2
Section 16 I C Bus Interface [Option]
Formatless dedicated
clock (channel 0 only)
φ
PS
ICCR
SCL
Clock
control
Noise
canceler
Bus state
decision
circuit
SDA
ICSR
Arbitration
decision
circuit
ICDRT
Output data
control
circuit
ICDRS
Internal data bus
ICMR
ICDRR
Noise
canceler
Address
comparator
SAR, SARX
Interrupt
generator
Legend:
ICCR: I2C bus control register
ICMR: I2C bus mode register
ICSR: I2C bus status register
ICDR: I2C bus data register
SAR: Slave address register
SARX: Second slave address register X
PS:
Prescaler
Interrupt
request
2
Figure 16.1 Block Diagram of I C Bus Interface
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2
Section 16 I C Bus Interface [Option]
Vcc
VCC
SCL
SCL
SDA
SDA
SCL in
SDA in
SCL
SDA
SDA out
(Master)
SCL in
H8S/2148 Group and
H8S/2147N chip
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
SCL
SDA
SCL out
SCL in
(Slave 1)
(Slave 2)
2
Figure 16.2 I C Bus Interface Connections
(Example: H8S/2148 Group and H8S/2147N Chip as Master)
16.1.3
Input/Output Pins
2
Table 16.1 summarizes the input/output pins used by the I C bus interface.
2
Table 16.1 I C Bus Interface Pins
Channel
Name
Abbreviation*
I/O
Function
0
Serial clock
SCL0
I/O
IIC0 serial clock input/output
Serial data
SDA0
I/O
IIC0 serial data input/output
Formatless serial
clock
VSYNCI
Input
IIC0 formatless serial clock input
Serial clock
SCL1
I/O
IIC1 serial clock input/output
Serial data
SDA1
I/O
IIC1 serial data input/output
1
Note:
*
In the text, the channel subscript is omitted, and only SCL and SDA are used.
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Section 16 I C Bus Interface [Option]
16.1.4
Register Configuration
2
Table 16.2 summarizes the registers of the I C bus interface.
Table 16.2 Register Configuration
Abbreviation
R/W
Initial Value
Address*
2
ICCR0
R/W
H'01
H'FFD8
2
ICSR0
R/W
H'00
H'FFD9
2
ICDR0
R/W
—
I C bus mode register
ICMR0
R/W
H'00
2
H'FFDE*
2
H'FFDF*
Slave address register
SAR0
R/W
H'00
Second slave address
register
SARX0
R/W
H'01
H'FFDF*
2
H'FFDE*
2
ICCR1
R/W
H'01
H'FF88
2
ICSR1
R/W
H'00
H'FF89
2
ICDR1
R/W
—
I C bus mode register
2
ICMR1
R/W
H'00
2
H'FF8E*
2
H'FF8F*
Slave address register
SAR1
R/W
H'00
Second slave address
register
SARX1
R/W
H'01
H'FF8F*
2
H'FF8E*
Serial/timer control
register
STCR
R/W
H'00
H'FFC3
DDC switch register
DDCSWR
R/W
H'0F
H'FEE6
Module stop control
register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Channel
Name
0
I C bus control register
I C bus status register
I C bus data register
2
1
I C bus control register
I C bus status register
I C bus data register
Common
1
2
2
Notes: 1. Lower 16 bits of the address.
2
2. The register that can be written or read depends on the ICE bit in the I C bus control
2
register. The slave address register can be accessed when ICE = 0, and the I C bus
mode register can be accessed when ICE = 1.
2
The I C bus interface registers are assigned to the same addresses as other registers.
Register selection is performed by means of the IICE bit in the serial/timer control
register (STCR).
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Section 16 I C Bus Interface [Option]
16.2
Register Descriptions
16.2.1
I C Bus Data Register (ICDR)
2
Bit
7
6
5
4
3
2
1
0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• ICDRR
Bit
ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
• ICDRS
Bit
ICDRS7 ICDRS6 ICDRR5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0
Initial value
—
—
—
—
—
—
—
—
Read/Write
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
• ICDRT
Bit
ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0
Initial value
—
—
—
—
—
—
—
—
Read/Write
W
W
W
W
W
W
W
W
—
—
TDRE
RDRF
• TDRE, RDRF (internal flags)
Bit
Initial value
0
0
Read/Write
—
—
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Section 16 I C Bus Interface [Option]
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or
written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF.
If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is assigned to the same address as SARX, and can be written and read only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
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Section 16 I C Bus Interface [Option]
TDRE
Description
0
The next transmit data is in ICDR (ICDRT), or transmission cannot
be started
(Initial value)
[Clearing conditions]
•
When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
•
When a stop condition is detected in the bus line state after a stop condition is
2
issued with the I C bus format or serial format selected
•
When a stop condition is detected with the I C bus format selected
•
In receive mode (TRS = 0)
2
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
1
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
•
In transmit mode (TRS = 1), when a start condition is detected in the bus line state
2
after a start condition is issued in master mode with the I C bus format or serial
format selected
•
At the first transmit mode setting (TRS = 1) (first transmit mode setting only) after
2
the mode is switched from I C bus mode to formatless mode
•
When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
•
When detecting a start condition and then switching from slave receive mode (TRS
= 0) state to transmit mode (TRS = 1) (first transmit mode switching only).
RDRF
Description
0
The data in ICDR (ICDRR) is invalid
(Initial value)
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode
1
The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)
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Section 16 I C Bus Interface [Option]
16.2.2
Slave Address Register (SAR)
Bit
7
6
5
4
3
2
1
0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
2
differing from the addresses of other slave devices connected to the I C bus.
Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit,
slave mode only, start/stop conditions not detected
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
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Section 16 I C Bus Interface [Option]
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
Operating Mode
0
0
0
I C bus format
2
•
1
I C bus format
•
SAR slave address recognized
•
SARX slave address ignored
0
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
Synchronous serial format
•
16.2.3
*
SAR and SARX slave addresses ignored
0
0
Formatless mode (start/stop conditions not detected)
0
1
•
1
0
1
1
Acknowledge bit used
Formatless mode* (start/stop conditions not detected)
•
Note:
(Initial value)
2
1
1
SAR and SARX slave addresses recognized
2
1
No acknowledge bit
2
Do not set this mode when automatic switching to the I C bus format is performed by
means of the DDCSWR setting.
Second Slave Address Register (SARX)
Bit
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
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Section 16 I C Bus Interface [Option]
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
2
SVAX0, differing from the addresses of other slave devices connected to the I C bus.
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode: non-addressing format with or without acknowledge bit, slave mode only,
start/stop conditions not detected
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
16.2.4
2
I C Bus Mode Register (ICMR)
Bit
7
6
5
4
3
2
1
0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
2
Do not set this bit to 1 when the I C bus format is used.
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Section 16 I C Bus Interface [Option]
Bit 7
MLS
Description
0
MSB-first
1
LSB-first
(Initial value)
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
2
and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the
fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred
consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the
WAIT setting.
The setting of this bit is invalid in slave mode.
Bit 6
WAIT
Description
0
Data and acknowledge bits transferred consecutively
1
Wait inserted between data and acknowledge bits
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(Initial value)
2
Section 16 I C Bus Interface [Option]
Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel
1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode.
They should be set according to the required transfer rate.
STCR
Bit 5 or 6 Bit 5 Bit 4 Bit 3
Transfer Rate
IICX
CKS2 CKS1 CKS0 Clock
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note:
*
φ=
5 MHz
φ=
8 MHz
φ=
10 MHz
φ=
16 MHz
φ=
20 MHz
0
φ/28
179 kHz
286 kHz
357 kHz
571 kHz*
1
φ/40
125 kHz
200 kHz
250 kHz
400 kHz
714 kHz*
500 kHz*
0
φ/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz*
1
φ/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
0
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
φ/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
0
φ/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
0
φ/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
φ/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
0
φ/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
φ/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
2
Outside the I C bus interface specification range (normal mode: max. 100 kHz; highspeed mode: max. 400 kHz).
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
2
transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
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Section 16 I C Bus Interface [Option]
Bit 2
Bit 1
Bit 0
BC2
BC1
BC0
Synchronous Serial Format
I C Bus Format
0
0
0
8
9
1
1
2
0
2
3
1
3
4
0
4
5
1
5
6
0
6
7
1
7
8
1
1
0
1
Bits/Frame
2
(Initial value)
2
16.2.5
I C Bus Control Register (ICCR)
Bit
7
6
5
4
3
2
1
0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
W
Note: * Only 0 can be written, to clear the flag.
2
ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
2
acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
2
2
Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
2
operations are enabled. When ICE is cleared to 0, the I C bus interface module is halted and its
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
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Section 16 I C Bus Interface [Option]
Bit 7
ICE
Description
0
I C bus interface module disabled, with SCL and SDA signal pins set to port function
(Initial value)
2
2
I C bus interface module internal states initialized
SAR and SARX can be accessed
2
1
I C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
2
2
Bit 6—I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C
bus interface to the CPU.
Bit 6
IEIC
Description
0
Interrupts disabled
1
Interrupts enabled
(Initial value)
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
2
MST selects whether the I C bus interface operates in master mode or slave mode.
2
TRS selects whether the I C bus interface operates in transmit mode or receive mode.
2
In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
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Section 16 I C Bus Interface [Option]
Bit 5
Bit 4
MST
TRS
Operating Mode
0
0
Slave receive mode
1
Slave transmit mode
0
Master receive mode
1
Master transmit mode
1
(Initial value)
Bit 5
MST
Description
0
Slave mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software
2
2. When bus arbitration is lost after transmission is started in I C bus format master
mode
1
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Bit 4
TRS
0
Description
Receive mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)
2
3. When bus arbitration is lost after transmission is started in I C bus format master
mode
4. When the SW bit in DDCSWR changes from 1 to 0
1
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
and 4)
2
3. When a 1 is received as the R/W bit of the first frame in I C bus format slave mode
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Section 16 I C Bus Interface [Option]
Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
2
acknowledge bit returned from the receiving device when using the I C bus format is to be ignored
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
In the H8S/2148 Group and H8S/2147N, the DTC can be used to perform continuous transfer. The
DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the
other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on
completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE
bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the
acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the
acknowledge bit is 1.
When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified
number of data transfers have been executed. Consequently, interrupts are not generated during
continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the
ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled.
Depending on the receiving device, the acknowledge bit may be significant, in indicating
completion of processing of the received data, for instance, or may be fixed at 1 and have no
significance.
Bit 3
ACKE
Description
0
The value of the acknowledge bit is ignored, and continuous transfer
is performed
1
If the acknowledge bit is 1, continuous transfer is interrupted
(Initial value)
2
Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA)
is busy or free. In master mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, use a MOV instruction to
2
write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I C bus
interface must be set to master transmit mode before issuing a start condition. MST and TRS
should both be set to 1 before writing 1 in BBSY and 0 in SCP.
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Section 16 I C Bus Interface [Option]
Bit 2
BBSY
Description
0
Bus is free
(Initial value)
[Clearing condition]
When a stop condition is detected
1
Bus is busy
[Setting condition]
When a start condition is detected
2
2
Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.
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Section 16 I C Bus Interface [Option]
Bit 1
IRIC
0
Description
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing conditions]
1. When 0 is written in IRIC after reading IRIC = 1
2. When ICDR is written or read by the DTC
(When the TDRE or RDRF flag is cleared to 0)
(This is not always a clearing condition; see the description of DTC operation for details)
1
Interrupt requested
[Setting conditions]
•
I2C bus format master mode
1. When a start condition is detected in the bus line state after a start condition is issued
(when the TDRE flag is set to 1 because of first frame transmission)
2. When a wait is inserted between the data and acknowledge bit when WAIT = 1
3. At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse when no wait is inserted, (WAIT=0) and,
when a wait is inserted (WAIT=1), at the fall of the 8th transmit/receive clock pulse)
4. When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
5. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
•
I2C bus format slave mode
1. When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or stop
condition detection
(when the TDRE or RDRF flag is set to 1)
2. When the general call address is detected
(when FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or stop
condition detection
(when the TDRE or RDRF flag is set to 1)
3. When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
4. When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
•
Synchronous serial format, and formatless mode
1. At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
2. When a start condition is detected with serial format selected
3. When the SW bit is set to 1 in DDCSWR
Except the above, when the conditions to set the TDRE or RDRF internal flag to 1 is generated
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Section 16 I C Bus Interface [Option]
2
When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a
retransmission start condition or stop condition after a slave address (SVA) or general call address
2
match in I C bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in
continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the
specified number of ICDR reads or writes have been completed.
Table 16.3 shows the relationship between the flags and the transfer states.
Table 16.3 Flags and Transfer States
MST TRS
BBSY ESTP STOP IRTR
AASX AL
AAS
ADZ
ACKB State
1/0
1/0
0
0
0
0
0
0
0
0
0
Idle state (flag clearing
required)
1
1
0
0
0
0
0
0
0
0
0
Start condition issuance
1
1
1
0
0
1
0
0
0
0
0
Start condition established
1
1/0
1
0
0
0
0
0
0
0
0/1
Master mode wait
1
1/0
1
0
0
1
0
0
0
0
0/1
Master mode transmit/
receive end
0
0
1
0
0
0
1/0
1
1/0
1/0
0
Arbitration lost
0
0
1
0
0
0
0
0
1
0
0
SAR match by first frame in
slave mode
0
0
1
0
0
0
0
0
1
1
0
General call address match
0
0
1
0
0
0
1
0
0
0
0
SARX match
0
1/0
1
0
0
0
0
0
0
0
0/1
Slave mode
transmit/receive end
(except after SARX match)
0
1/0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
Slave mode
transmit/receive end (after
SARX match)
0
1/0
0
1/0
1/0
0
0
0
0
0
0/1
Stop condition detected
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Section 16 I C Bus Interface [Option]
Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not stored.
Bit 0
SCP
Description
0
Writing 0 issues a start or stop condition, in combination with the BBSY flag
1
Reading always returns a value of 1
(Initial value)
Writing is ignored
16.2.6
2
I C Bus Status Register (ICSR)
Bit
7
6
5
4
3
2
1
0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note: * Only 0 can be written, to clear the flags.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
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Section 16 I C Bus Interface [Option]
Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
2
detected during frame transfer in I C bus format slave mode.
Bit 7
ESTP
Description
0
No error stop condition
(Initial value)
[Clearing conditions]
1. When 0 is written in ESTP after reading ESTP = 1
2. When the IRIC flag is cleared to 0
•
1
2
In I C bus format slave mode
Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
•
In other modes
No meaning
Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
2
detected after completion of frame transfer in I C bus format slave mode.
Bit 6
STOP
Description
0
No normal stop condition
(Initial value)
[Clearing conditions]
1. When 0 is written in STOP after reading STOP = 1
2. When the IRIC flag is cleared to 0
•
1
2
In I C bus format slave mode
Normal stop condition detected
[Setting condition]
When a stop condition is detected after completion of frame transfer
•
In other modes
No meaning
2
Bit 5—I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
2
(IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the
source is completion of reception/transmission of one frame in continuous transmission/reception
for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1
at the same time.
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Section 16 I C Bus Interface [Option]
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Bit 5
IRTR
Description
0
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing conditions]
1. When 0 is written in IRTR after reading IRTR = 1
2. When the IRIC flag is cleared to 0
1
Continuous transfer state
[Setting conditions]
•
2
In I C bus interface slave mode
When the TDRE or RDRF flag is set to 1 when AASX = 1
•
In other modes
When the TDRE or RDRF flag is set to 1
2
Bit 4—Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
Description
0
Second slave address not recognized
(Initial value)
[Clearing conditions]
1. When 0 is written in AASX after reading AASX = 1
2. When a start condition is detected
3. In master mode
1
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX = 0
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Section 16 I C Bus Interface [Option]
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
2
I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at
2
nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL
0
Description
Bus arbitration won
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AL after reading AL = 1
1
Arbitration lost
[Setting conditions]
1. If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
2. If the internal SCL line is high at the fall of SCL in master transmit mode
2
Bit 2—Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
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Section 16 I C Bus Interface [Option]
Bit 2
AAS
Description
0
Slave address or general call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in AAS after reading AAS = 1
3. In master mode
1
Slave address or general call address recognized
[Setting condition]
When the slave address or general call address is detected in slave receive mode while
FS = 0
2
Bit 1—General Call Address Recognition Flag (ADZ): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ
Description
0
General call address not recognized
(Initial value)
[Clearing conditions]
1. When ICDR data is written (transmit mode) or read (receive mode)
2. When 0 is written in ADZ after reading ADZ = 1
3. In master mode
1
General call address recognized
[Setting condition]
When the general call address is detected in slave receive mode while FSX = 0 or FS = 0
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Section 16 I C Bus Interface [Option]
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
When this bit is written to, the acknowledge data transmitted at the receipt is rewritten regardless
of the TRS value. The data loaded fom the receiving device is retained, therefore take care of
using bit-manipulation instructions.
Bit 0
ACKB
Description
0
Receive mode: 0 is output at acknowledge output timing
(Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data (signal
is 0)
1
Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
16.2.7
Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS
IICX1
IICX0
IICE
FLSHE
—
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
STCR is an 8-bit readable/writable register that controls register access, the I C interface operating
mode (when the on-chip IIC option is included), and on-chip flash memory (F-ZTAT versions),
2
and selects the TCNT input clock source. For details of functions not related to the I C bus
interface, see section 3.2.4, Serial Timer Control Register (STCR), and the descriptions of the
relevant modules. If a module controlled by STCR is not used, do not write 1 to the corresponding
bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
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Section 16 I C Bus Interface [Option]
2
Bit 7—I C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of
2
output buffer as SCL and SDA. This bit is used when implementing the I C interface by software
only.
Bit 7
IICS
Description
0
PA7 to PA4 are normal I/O pins
1
PA7 to PA4 are I/O pins with bus driving capability
(Initial value)
2
Bits 6 and 5—I C Transfer Select 1 and 0 (IICX1 and 0): This bit, together with bits CKS2 to
2
CKS0 in ICMR, selects the transfer rate in master mode. For details, see section 16.2.4, I C Bus
Mode Register (ICMR).
2
2
Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE
Description
0
CPU access to I C bus interface data and control registers is disabled
1
2
(Initial value)
2
CPU access to I C bus interface data and control registers is enabled
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers, the power-down mode control registers, and the supporting module
control registers. See section 3.2.4, Serial Timer Control Register (STCR), for details.
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register (TCR).
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Section 16 I C Bus Interface [Option]
16.2.8
DDC Switch Register (DDCSWR)
Bit
7
6
5
4
3
2
1
0
SWE
SW
IE
IF
CLR3
CLR2
CLR1
CLR0
Initial value
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/(W)*1
W*2
W*2
W*2
W*2
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
DDCSWR is an 8-bit readable/writable register that is used to initialize IIC and controls IIC
internal latch clearance.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC
2
channel 0 from formatless mode to the I C bus format.
Bit 7
SWE
Description
0
Automatic switching of IIC channel 0 from formatless mode to I C bus format is
disabled
(Initial value)
1
Automatic switching of IIC channel 0 from formatless mode to I C bus format is
enabled
2
2
2
Bit 6—DDC Mode Switch (SW): Selects either formatless mode or the I C bus format for IIC
channel 0.
Bit 6
SW
Description
0
IIC channel 0 is used with the I C bus format
2
[Clearing conditions]
1. When 0 is written by software
2. When a falling edge is detected on the SCL pin when SWE = 1
1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
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(Initial value)
2
Section 16 I C Bus Interface [Option]
Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when automatic format switching is executed for IIC channel 0.
Bit 5
IE
Description
0
Interrupt when automatic format switching is executed is disabled
1
Interrupt when automatic format switching is executed is enabled
(Initial value)
Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the
CPU when automatic format switching is executed for IIC channel 0.
Bit 4
IF
Description
0
No interrupt is requested when automatic format switching is executed
(Initial value)
[Clearing condition]
When 0 is written in IF after reading IF = 1
1
An interrupt is requested when automatic format switching is executed
[setting condition]
When a falling edge is detected on the SCL pin when SWE = 1
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit-manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
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Section 16 I C Bus Interface [Option]
Bit 3
Bit 2
Bit 1
Bit 0
CLR3
CLR2
CLR1
CLR0
Description
0
0
—
—
Setting prohibited
1
0
0
Setting prohibited
1
IIC0 internal latch cleared
0
IIC1 internal latch cleared
1
IIC0 and IIC1 internal latches cleared
—
Invalid setting
1
1
—
16.2.9
—
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at
the end of the bus cycle, and a transition is made to module stop mode. For details, see section
25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 4—Module Stop (MSTP4): Specifies IIC channel 0 module stop mode.
MSTPCRL
Bit 4
MSTP4
Description
0
IIC channel 0 module stop mode is cleared
1
IIC channel 0 module stop mode is set
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(Initial value)
2
Section 16 I C Bus Interface [Option]
MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode.
MSTPCRL
Bit 3
MSTP3
Description
0
IIC channel 1 module stop mode is cleared
1
IIC channel 1 module stop mode is set
16.3
Operation
16.3.1
I C Bus Data Format
(Initial value)
2
2
2
The I C bus interface has serial and I C bus formats.
2
The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures
16.3 (a) and (b). The first frame following a start condition always consists of 8 bits.
IIC channel 0 only is capable of formatless operation, as shown in figure 16.4.
The serial format is a non-addressing format with no acknowledge bit. Although start and stop
conditions must be issued, this format can be used as a synchronous serial format. This is shown in
figure 16.5.
2
Figure 16.6 shows the I C bus timing.
The symbols used in figures 16.3 to 16.6 are explained in table 16.4.
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Section 16 I C Bus Interface [Option]
(a) I2C bus format (FS = 0 or FSX = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
Legend:
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
m
(b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
m1
1
m2
Legend:
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
2
2
Figure 16.3 I C Bus Data Formats (I C Bus Formats)
IIC0 only, FS = 0 or FSX = 0
DATA
A
8
1
DATA
n
A
A/A
1
1
1
Legend:
n: transfer bit count (n = 1 to 8)
m: transfer frame count (m ≥ 1)
m
Figure 16.4 Formatless
FS = 1 and FSX = 1
S
DATA
DATA
P
1
8
n
1
1
m
2
Legend:
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
Figure 16.5 I C Bus Data Format (Serial Format)
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Section 16 I C Bus Interface [Option]
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
8
DATA
9
A
1-7
8
DATA
9
A/A
P
2
Figure 16.6 I C Bus Timing
2
Table 16.4 I C Bus Data Format Symbols
Legend
S
Start condition. The master device drives SDA from high to low while SCL is high
SLA
Slave address, by which the master device selects a slave device
R/W
Indicates the direction of data transfer: from the slave device to the master device
when R/W is 1, or from the master device to the slave device when R/W is 0
A
Acknowledge. The receiving device (the slave in master transmit mode, or the master
in master receive mode) drives SDA low to acknowledge a transfer
DATA
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or
LSB-first format is selected by bit MLS in ICMR
P
Stop condition. The master device drives SDA from low to high while SCL is high
16.3.2
Master Transmit Operation
2
In I C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR write operations, are described below.
(1) Set the ICE bit in ICCR to l. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in STCR, according to the operation mode.
(2) Read the BBSY flag to confirm that the bus is free.
(3) Set the MST and TRS bits to 1 in ICCR to select master transmit mode.
(4) Write 1 to BBSY and 0 to SCP. This switches SDA from high to low when SCL is high, and
generates the start condition.
(5) When the start condition is generated, the IRIC and IRTR flags are set to 1. If the IEIC bit in
ICCR has been set to l, an interrupt request is sent to the CPU.
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Section 16 I C Bus Interface [Option]
(6) Write data to ICDR (slave address + R/W)
2
With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame
data following the start condition indicates the 7-bit slave address and transmit/receive
direction.
Then clear the IRIC flag to indicate the end of transfer.
Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRlC flag is
cleared, the end of transfer cannot be identified.
The master device sequentially sends the transmit clock and the data written to ICDR with the
timing shown in figure 16.7. The selected slave device (i.e., the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
(7) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
(8) Read the ACKB bit to confirm that ACKB is 0. When the slave device has not returned an
acknowledge signal and ACKB remains 1, execute the transmit end processing described in
step (12) and perform transmit operation again.
(9) Write the next data to be transmitted in ICDR. To indicate the end of data transfer, clear the
IRIC flag to 0.
As described in step (6) above, writing to ICDR and clearing of the IRIC flag must be
executed continuously so that no interrupt is inserted.
The next frame is transmitted in synchronization with the internal clock.
(10) When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
(11) Read the ACKB bit of ICSR. Confirm that the slave device has returned an acknowledge
signal and ACKB is 0. When more data is to be transmitted, return to step (9) to execute next
transmit operation. If the slave device has not returned an acknowledge signal and ACKB is 1,
execute the transmit end processing described in step (12).
(12) Clear the IRIC flag to 0. Write BBSY and SCP of ICCR to 0. By doing so, SDA is changed
from low to high while SCL is high and the transmit stop condition is generated.
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Section 16 I C Bus Interface [Option]
Start condition
generation
SCL
(master output)
1
SDA
(master output)
bit 7
2
bit 6
3
bit 5
4
bit 4
5
6
bit 3
bit 2
bit 1
8
1
9
2
bit 7
bit 0
R/W
Slave address
SDA
(slave output)
7
[7]
bit 6
Data 1
A
[5]
IRIC
IRTR
ICDR
address + R/W
Note: Data write
timing in ICDR
ICDR Writing
prohibited
Data 1
ICDR Writing
enable
User processing [4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
[6] ICDR write
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 16.7 Example of Master Transmit Mode Operation Timing
(MLS = WAIT = 0)
16.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The receive procedure and operations by which data is sequentially received in synchronization
with ICDR read operations, are described below.
(1) Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
(2) When ICDR is read (dummy data read), reception is started and the receive clock is output,
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC f1ag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
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Section 16 I C Bus Interface [Option]
(3) The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this
point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
is cleared. If the first frame is the final reception frame, execute the end processing as
described in (l0).
(4) Clear the IRIC flag to 0 to release from the wait state.
The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an
acknowledge signal.
(5) When one frame of data has been transmitted, the IRIC and IRTR flags are set to 1 at the rise
of the 9th transmit clock pulse.
The master device continues to output the receive clock for the next receive data.
(6) Read the ICDR receive data.
(7) Clear the IRIC flag to indicate the next wait.
From clearing of the IRIC flag to completion of data transmission as described in steps (5),
(6), and (7), must be performed within the time taken to transfer one byte, because releasing
of the wait state as described in step (4) (or (9)).
(8) The IRIC flag is set to 1 at the fall of the 8th one-frame reception clock pulse. SCL is
automatically fixed low in synchronization with the internal clock until the IRIC flag is
cleared. If this frame is the final reception frame, execute the end processing as described in
(l0).
(9) Clear the IRIC flag to 0 to release from the wait state. The master device outputs the 9th
reception clock pulse, sets SDA to low, and returns an acknowledge signal.
By repeating steps (5) to (9) above, more data can be received.
(l0) Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception.
Set the TRS bit of ICCR to 1 to change receive mode to transmit mode.
(11) Clear the IRIC flag to release from the wait state.
(12) When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
reception clock pulse.
(13) Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear
the IRIC flag to 0.
Clear the IRIC flag only when WAIT = 0.
(If the stop-condition generation command is executed after clearing the IRIC flag to 0 and
then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be
generated.)
(14) Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and
generates the stop condition.
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Section 16 I C Bus Interface [Option]
Master transmit mode
Master receive mode
SCL
(master output)
9
1
2
3
4
5
6
7
8
SDA
(slave output)
A
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Data 1
9
[3]
SDA
(master output)
1
2
Bit7
Bit6
3
4
5
Bit5
Bit4
Bit3
Data 2
[5]
A
IRIC
IRTR
ICDR
Data 1
[2] IRIC clear
[1] TRS cleared to 0 [2] ICDR read
(dummy read)
WAIT set to 1
ACKB cleared to 0
User processing
[4] IRIC clear
[6] ICDR read
(Data 1)
[7] IRIC clear
Figure 16.8 (a) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
SCL
(master output)
8
SDA
(slave output)
Bit0
Data 2
9
[8]
SDA
(master output)
1
2
3
4
5
6
7
8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Data 3
[5]
9
1
2
Bit7
[8]
A
Bit6
Data 4
[5]
A
IRIC
IRTR
ICDR
Data 1
User processing
[9] IRIC clear
Data 2
[6] ICDR read
(Data 2)
[7] IRIC clear
Data 3
[9] IRIC Clear
[6] ICDR read
(Data 3)
[7] IRIC clear
Figure 16.8 (b) Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1)
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Section 16 I C Bus Interface [Option]
16.3.4
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
[2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1.
[3] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
[4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
[5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
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Section 16 I C Bus Interface [Option]
Start condition
generation
SCL
(master output)
1
2
3
Bit 7
Bit 6
Bit 5
4
5
6
Bit 4
Bit 3
Bit 2
7
8
9
1
2
SCL
(slave output)
SDA
(master output)
Slave address
SDA
(slave output)
Bit 1
Bit 0
R/W
Bit 7
Bit 6
Data 1
[4]
A
RDRF
IRIC
Interrupt request
generation
ICDRS
Address + R/W
ICDRR
User processing
Address + R/W
[5] ICDR read
[5] IRIC clear
Figure 16.9 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0)
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Section 16 I C Bus Interface [Option]
SCL
(master output)
7
8
Bit 1
Bit 0
9
1
2
3
4
5
6
7
8
9
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCL
(slave output)
SDA
(master output)
Data 1
SDA
(slave output)
Bit 7
Bit 6
[4]
Data 2
A
[4]
A
RDRF
IRIC
ICDRS
Data 1
ICDRR
Data 1
User processing
Interrupt
request
generation
Interrupt
request
generation
[5] ICDR read
Data 2
Data 2
[5] IRIC clear
Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)
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Section 16 I C Bus Interface [Option]
16.3.5
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
[2] When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At
the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set
to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is
written.
[3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.
The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR
flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The
slave device sequentially sends the data written into ICDR in accordance with the clock output
by the master device at the timing shown in figure 16.11.
[4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device
drives SCL low from the fall of the transmit clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this
acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine
whether the transfer operation was performed normally. When the TDRE internal flag is 0, the
data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
[5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted
into ICDR. The TDRE internal flag is cleared to 0.
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from
low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is
cleared to 0.
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Section 16 I C Bus Interface [Option]
Slave receive mode
SCL
(master output)
8
Slave transmit mode
9
1
2
3
4
5
6
7
8
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
2
SCL
(slave output)
SDA
(slave output)
SDA
(master output) R/W
Bit 7
Data 1
[2]
Bit 6
Data 2
A
TDRE
Interrupt
request
generation
IRIC
[3]
Interrupt
request
generation
Interrupt
request
generation
Data 1
ICDRT
ICDRS
Data 2
Data 1
User processing
[3] IRIC
clear
[3] ICDR write
[3] ICDR write
Data 2
[5] IRIC
clear
[5] ICDR write
Figure 16.11 Example of Slave Transmit Mode Operation Timing (MLS = 0)
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2
Section 16 I C Bus Interface [Option]
16.3.6
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.12 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
7
8
9
1
SDA
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
8
9
1
SDA
8
A
1
IRIC
User processing
Clear
IRIC
Clear Write to ICDR (transmit)
IRIC or read ICDR (receive)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Figure 16.12 IRIC Setting Timing and SCL Control
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2
Section 16 I C Bus Interface [Option]
16.3.7
2
Automatic Switching from Formatless Mode to I C Bus Format
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating
2
mode. Switching from formatless mode to the I C bus format (slave mode) is performed
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
• A common data pin (SDA) for formatless and I C bus format operation
2
• Separate clock pins for formatless operation (VSYNCI) and I C bus format operation (SCL)
2
• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
• Settings of bits other than TRS in ICCR that allow I C bus format operation
2
2
Automatic switching is performed from formatless mode to the I C bus format when the SW bit in
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
2
from the I C bus format to formatless mode is achieved by having software set the SW bit in
DDCSWR to 1.
2
In formatless mode, bits (such as MSL and TRS) that control the I C bus interface operating mode
2
must not be modified. When switching from the I C bus format to formatless mode, set the TRS
bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless
2
mode, then set the SW bit to 1. After automatic switching from formatless mode to the I C bus
format (slave mode), in order to wait for slave address reception, the TRS bit is automatically
cleared to 0.
2
If a falling edge is detected on the SCL pin during formatless operation, the I C bus interface
2
operating mode is switched to the I C bus format without waiting for a stop condition to be
detected.
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2
Section 16 I C Bus Interface [Option]
16.3.8
Operation Using the DTC
2
The I C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 16.5 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 16.5 Examples of Operation Using the DTC
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Slave address + Transmission by
R/W bit
DTC (ICDR write)
transmission/
reception
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read
—
Processing by
CPU (ICDR read)
—
—
Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write
—
—
Processing by
DTC (ICDR write)
—
Last frame
processing
Not necessary
Reception by
CPU (ICDR read)
Not necessary
Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
Not necessary
2nd time: End
condition issuance
by CPU
Automatic clearing Not necessary
on detection of end
condition during
transmission of
dummy data (H'FF)
Setting of
number of DTC
transfer data
frames
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Transmission:
Reception: Actual
Actual data count data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Item
Master Transmit
Mode
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Section 16 I C Bus Interface [Option]
16.3.9
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or
SDA input
signal
D
C
Q
Latch
D
Q
Match
detector
Latch
Internal
SCL or
SDA
signal
System clock
period
Sampling
clock
Figure 16.13 Block Diagram of Noise Canceler
16.3.10 Sample Flowcharts
2
Figures 16.14 to 16.17 show sample flowcharts for using the I C bus interface in each mode.
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Section 16 I C Bus Interface [Option]
Start
[1] Initialize
Initialize
[2] Test the status of the SCL and SDA lines.
Read BBSY in ICCR
No
BBSY = 0?
Yes
[3] Select master transmit mode.
Set MST = 1 and
TRS = 1 in ICCR
[4] Start condition issuance
Write BBSY = 1
and SCP = 0 in ICCR
[5] Wait for a start condition generation
Read IRIC in ICCR
No
IRIC = 1?
Yes
[6] Set transmit data for the first byte (slave
address + R/W).
(After writing ICDR, clear IRIC
immediately)
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
ACKB = 0?
No
[8] Test the acknowledge bit, transferred from
slave device.
Yes
Transmit mode?
No
Master receive mode
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC
immediately)
Read IRIC in ICCR
No
[10] Wait for 1 byte to be transmitted.
IRIC = 1?
Yes
Read ACKB in ICSR
[11] Test for end of transfer
No
End of transmission
or ACKB = 1?
Yes
Clear IRIC in ICCR
[12] Stop condition issuance
Write BBSY = 0
and SCP = 0 in ICCR
End
Figure 16.14 Flowchart for Master Transmit Mode (Example)
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Section 16 I C Bus Interface [Option]
Master receive operation
Set TRS = 0 in ICCR
[1] Select receive mode
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
[2] Start receiving. The first read is a dummy
read. After reading ICDR, please clear
IRIC immediately.
Read ICDR
Clear IRIC in ICCR
[3] Wait for 1 byte to be received.
(8th clock falling edge)
Read IRIC in ICCR
No
IRIC = 1?
Yes
Last receive ?
Yes
No
No
Clear IRIC in ICCR
[4] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Read IRIC in ICCR
[5] Wait for 1 byte to be received.
(9th clock risig edge)
IRIC = 1?
Yes
[6] Read the receive data.
Read ICDR
No
Clear IRIC in ICCR
[7] Clear IRIC
Read IRIC in ICCR
[8] Wait for the next data to be received.
(8th clock falling edge)
IRIC = 1?
Yes
Yes
Last receive ?
No
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
[9] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[10] Set ACKB = 1 so as to return no
acknowledge, or set TRS = 1 so as not
to issue extra clock.
[11] Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Read IRIC in ICCR
No
[12] Wait for 1 byte to be received.
IRIC = 1?
Yes
Set WAIT = 0 in ICMR
Read ICDR
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0.)
Clear IRIC in ICCR
Write BBSY = 0
and SCP = 0 in ICCR
[14] Stop condition issuance.
End
Figure 16.15 Flowchart for Master Receive Mode (Example)
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Section 16 I C Bus Interface [Option]
Start
Initialize
Set MST = 0
and TRS = 0 in ICCR
[1]
Set ACKB = 0 in ICSR
Read IRIC in ICCR
[2]
No
IRIC = 1?
Yes
Read AAS and ADZ in ICSR
AAS = 1
and ADZ = 0?
No
General call address processing
* Description omitted
Yes
Read TRS in ICCR
No
TRS = 0?
Slave transmit mode
Yes
Last receive?
No
Read ICDR
Yes
[3]
[1] Select slave receive mode.
[2] Wait for the first byte to be received (slave
address).
Clear IRIC in ICCR
[3] Start receiving. The first read is a dummy read.
Read IRIC in ICCR
No
[4] Wait for the transfer to end.
[4]
IRIC = 1?
[5] Set acknowledge data for the last receive.
[6] Start the last receive.
Yes
[7] Wait for the transfer to end.
Set ACKB = 0 in ICSR
[5]
Read ICDR
[6]
[8] Read the last receive data.
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7]
IRIC = 1?
Yes
Read ICDR
[8]
Clear IRIC in ICCR
End
Figure 16.16 Flowchart for Slave Receive Mode (Example)
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Section 16 I C Bus Interface [Option]
Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
[1]
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
Clear IRIC in ICCR
[3] Test for end of transfer.
[4] Select slave receive mode.
Read IRIC in ICCR
No
[2]
[5] Dummy read (to release the SCL line).
IRIC = 1?
Yes
Read ACKB in ICSR
No
[3]
End
of transmission
(ACKB = 1)?
Yes
Set TRS = 0 in ICCR
[4]
Read ICDR
[5]
Clear IRIC in ICCR
End
Figure 16.17 Flowchart for Slave Transmit Mode (Example)
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Section 16 I C Bus Interface [Option]
16.3.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2)
clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization:
The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR)
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, ICSR, and DDCSWR registers
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• When initialization is performed by means of the DDCSWR register, the write data for bits
CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written
to simultaneously using an MOV instruction. Do not use a bit-manipulation instruction such as
BCLR. Similarly, when clearing is required again, all the bits must be written to
simultaneously in accordance with the setting.
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
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Section 16 I C Bus Interface [Option]
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state by setting of bit CLR3 to CLR0 or by clearing ICE
bit.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state by setting of bit CLR3 to CLR0 or by clearing
ICE bit.
4. Initialize (re-set) the IIC registers.
16.4
Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
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Section 16 I C Bus Interface [Option]
2
Table 16.6 I C Bus Timing (SCL and SDA Output)
Item
Symbol
Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28tcyc to 256tcyc
ns
SCL output high pulse width
tSCLHO
0.5tSCLO
ns
Figure 26.28
(reference)
SCL output low pulse width
tSCLLO
0.5tSCLO
ns
SDA output bus free time
tBUFO
0.5tSCLO –1tcyc
ns
Start condition output hold time
tSTAHO
0.5tSCLO –1tcyc
ns
Retransmission start condition output
setup time
tSTASO
1tSCLO
ns
Stop condition output setup time
tSTOSO
0.5tSCLO +2tcyc
ns
Data output setup time (master)
tSDASO
1tSCLLO –3tcyc
ns
1tSCLL –(6tcyc or 12tcyc*)
tSDAHO
3tcyc
Data output setup time (slave)
Data output hold time
Note:
*
ns
6tcyc when IICX is 0, 12tcyc when 1.
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
2
therefore depends on the system clock cycle tcyc, as shown in I C Bus Timing in section 26,
2
Electrical Characteristics, and as shown in table 26.10. Note that the I C bus interface AC
timing specifications will not be met with a system clock frequency of less than 5 MHz.
• The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high2
speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
2
the time determined by the input clock of the I C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
2
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Section 16 I C Bus Interface [Option]
Table 16.7 Permissible SCL Rise Time (tSr) Values
Time Indication
2
I C Bus
Specification φ =
(Max.)
5 MHz
tcyc
IICX Indication
0
1
7.5tcyc
17.5tcyc
φ=
8 MHz
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
Standard
mode
1000 ns
1000 ns 937 ns
750 ns
468 ns
375 ns
High-speed
mode
300 ns
300 ns
300 ns
300 ns
300 ns
Standard
mode
1000 ns
1000 ns 1000 ns
1000 ns 1000 ns 875 ns
High-speed
mode
300 ns
300 ns
300 ns
300 ns
300 ns
300 ns
300 ns
• The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
2
table 16.6. However, because of the rise and fall times, the I C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
2
2
tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
2
permits this output timing for use as slave devices connected to the I C bus.
2
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
2
timing permits this output timing for use as slave devices connected to the I C bus.
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Section 16 I C Bus Interface [Option]
2
Table 16.8 I C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
2
Item
tSCLHO
tSCLLO
tBUFO
tcyc
Indication
0.5tSCLO
(–tSr)
0.5tSCLO
(–tSf )
Standard
mode
I C Bus
SpecifitSr/tSf
Influence cation φ =
(Max.)
(Min.)
5 MHz
φ=
8 MHz
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
–1000
4000
4000
4000
4000
4000
4000
High-speed –300
mode
600
950
950
950
950
950
Standard
mode
–250
4700
4750
4750
4750
4750
4750
High-speed –250
mode
1300
1
1
1
1
1
1000* 1000* 1000* 1000* 1000*
4700
1
1
1
1
1
3800* 3875* 3900* 3938* 3950*
1300
750*
825*
850*
888*
900*
4000
4550
4625
4650
4688
4700
600
800
875
900
938
950
4700
9000
9000
9000
9000
9000
600
2200
2200
2200
2200
2200
4000
4400
4250
4200
4125
4100
600
1350
1200
1150
1075
1050
250
3100
3325
3400
3513
3550
High-speed –300
mode
100
400
625
700
813
850
Standard
mode
250
1300
2200
2500
2950
3100
100
1
1
1
–1400* –500* –200* 250
0.5tSCLO
Standard
–1tcyc (–tSr ) mode
–1000
High-speed –300
mode
tSTAHO
0.5tSCLO
Standard
–1tcyc (–tSf ) mode
–250
High-speed –250
mode
tSTASO
1tSCLO (–tSr ) Standard
mode
–1000
High-speed –300
mode
tSTOSO
0.5tSCLO
Standard
+2tcyc (–tSr ) mode
–1000
High-speed –300
mode
3
Standard
tSDASO
1tSCLLO*
(master) –3tcyc (–tSr ) mode
tSDASO
(slave)
3
1tSCLL*
2
–12tcyc*
(–tSr )
–1000
–1000
High-speed –300
mode
1
1
1
1
1
400
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Section 16 I C Bus Interface [Option]
Time Indication (at Maximum Transfer Rate) [ns]
2
Item
tcyc
Indication
tSDAHO
3tcyc
I C Bus
SpecifitSr/tSf
Influence cation φ =
(Max.)
(Min.)
5 MHz
φ=
8 MHz
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
0
0
600
375
300
188
150
High-speed 0
mode
0
600
375
300
188
150
Standard
mode
2
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
2
maximum transfer rate; therefore whether or not the I C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL
−6tcyc).
2
3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
• Note on ICDR Read at End of Master Reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
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Section 16 I C Bus Interface [Option]
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Stop condition
Start condition
(a)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
ICDR reading
prohibited
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
• Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition issuance is done and determined the start condition, write the transmit data to ICDR,
as shown below.
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Section 16 I C Bus Interface [Option]
[1] Wait for end of 1-byte transfer
IRIC = 1 ?
No
[1]
[2] Determine whether SCL is low
Yes
Clear IRIC in ICSR
Start condition
issuance?
[3] Issue restart condition instruction for retransmission
[4] Determine whether start condition is generated or not
No
Other processing
[5] Set transmit data (slave address + R/W)
Yes
SCL = Low ?
Note: Program so that processing from [3] to [5] is
executed continuously.
[2]
Read SCL pin
No
Yes
Write BBSY = 1,
SCP = 0 (ICSR)
IRIC = 1 ?
[3]
No
[4]
Yes
[5]
Write transmit data to ICDR
Start condition
(retransmission)
9
SCL
SDA
ACK
bit 7
IRIC
[3] Start condition
instruction issuance
[1] IRIC determination
[2] Determination
of SCL = low
[4] IRIC
determination
[5] ICDR write
(next transmit data)
Figure 16.19 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
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Section 16 I C Bus Interface [Option]
• Notes on I C Bus Interface Stop Condition Instruction Issuance
2
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition instruction after reading SCL and determining it
to be low, as shown below.
SCL
9th clock
VIH
High period secured
As waveform rise is late,
SCL is detected as low
SDA
Stop condition
IRIC
[1] Determination of SCL = low
[2] Stop condition instruction issuance
Figure 16.20 Timing of Stop Condition Issuance
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Section 16 I C Bus Interface [Option]
• Notes on WAIT Function
 Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
 Error phenomenon
Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.
 Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.)
ASD
A
SCL
9
BC2–BC0
0
Transmit/receive data
1
2
7
3
6
4
5
5
4
6
3
Transmit/receive
data
A
7
2
1
8
SCL =
‘L’ confirm
9
0
1
2
7
IRIC clear
IRIC
(operation
example)
IRIC flag clear available
IRIC flag clear available
IRIC flag clear unavailable
Figure 16.21 IRIC Flag Clear Timing on WAIT Operation
Rev. 4.00 Sep 27, 2006 page 550 of 1130
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3
6
5
When BC2-0 ≥ 2
IRIC clear
2
Section 16 I C Bus Interface [Option]
• Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
2
In a transmit operation in the slave mode of the I C bus interface, do not read the ICDR register
or read or write to the ICCR register during the period indicated by the shaded portion in figure
16.22.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
ICCR register, is completed before the next slave address receive operation starts.
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Waveforms if
problem occurs
SDA
SCL
TRS
R/W
8
Bit 7
A
9
Address received
Data transmission
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
ICDR write
Detection of 9th clock
cycle rising edge
Figure 16.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode
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Section 16 I C Bus Interface [Option]
• Notes on TRS Bit Setting in Slave Mode
From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the
rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 16.23)
2
in the slave mode of the I C bus interface, the value set in the TRS bit in the ICCR register is
effective immediately.
However, at other times (indicated as (b) in figure 16.23) the value set in the TRS bit is put on
hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than
taking effect immediately.
This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no
acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an
address receive operation following a restart condition input with no stop condition
intervening.
When receiving an address in the slave mode, clear the TRS bit to 0 during the period
indicated as (a) in figure 16.23.
To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS
bit to 0 and then perform a dummy read of the ICDR register.
(a)
Resumption condition
(b)
A
SDA
SCL
(a) TRS bit
8
9
1
2
3
4
5
6
7
8
9
Address reception
Data
transmission
(b) TRS bit
Period in which TRS bit setting is retained
TRS bit effective value
Detection of rise of 9th
transmit/receive clock
TRS bit setting value
Detection of rise of 9th
transmit/receive clock
Figure 16.23 TRS Bit Setting Timing in Slave Mode
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Section 16 I C Bus Interface [Option]
• Notes on Arbitration Lost in Master Mode
2
The I C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
2
register, the I C bus interface erroneously recognizes that the address call has occurred. (See
figure 16.24.)
2
In multi-master mode, a bus conflict could happen. When The I C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
• Arbitration is lost
• The AL flag in ICSR is set to 1
I2
C bus interface
(Master transmit mode)
S
SLA
A
R/W
DATA1
Transmit data match
Transmit timing match
Other device
(Master transmit mode)
S
SLA
A
R/W
Transmit data does not match
DATA2
A
DATA3
A
Data contention
I2C bus interface
(Slave receive mode)
S
SLA
A
R/W
• Receive address is ignored
SLA
R/W
A
DATA4
A
• Automatically transferred to slave
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device
Figure 16.24 Diagram of Erroneous Operation when Arbitration is Lost
2
Though it is prohibited in the normal I C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit
when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1
according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
(b) Set the MST bit to 1.
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Section 16 I C Bus Interface [Option]
(c) To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
• Notes on Interrupt Occurrence after ACKB Reception
 Conditions to cause this failure
The IRIC flag is set to 1 when both of the following conditions are satisfied.
• 1 is received as the acknowledge bit for transmit data and the ACKB bit in ICSR is set
to 1
• Rising edge of the 9th transmit/receive clock is input to the SCL pin
When the above two conditions are satisfied in slave receive mode, an unnecessary
interrupt occurs.
Figure 16.25 shows the note on interrupt occurrence in slave mode after receiving 1 as the
acknowledge bit (ACKB = 1).
(1) For the last transmit data in master transmit mode or slave transmit mode, 1 is received
as the acknowledge bit.
If the ACKE bit in ICCR is set to 1 at this time, the ACKB bit in ICSR is set to 1.
(2) After switching to slave receive mode, the start condition is input, and address
reception is performed next.
(3) Even if the received address does not match the address set in SAR or SARX, the IRIC
flag is set to 1 at the rise of the 9th transmit/receive clock, thus causing an interrupt to
occur.
Note that if the slave address matches, an interrupt is to be generated at the rise of the 9th
transmit/receive clock as normal operation, so this is not erroneous operation.
 Restriction
2
In a transmit operation of the I C bus interface module, carry out the following
countermeasures.
(1) After 1 is received as the acknowledge bit for transmit data, clear the ACKE bit in
ICCR to 0 to clear the ACKB bit to 0.
(2) To enable acknowledge bit reception afterwards, set the ACKE bit to 1 again.
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Section 16 I C Bus Interface [Option]
Master transmit mode or
slave transmit mode
Stop
condition
Slave reception mode
Start
condition
(2) Address that does not match is received.
SDA
N
SCL
8
Address
1
9
2
3
4
5
6
7
8
A
Data
9
1
2
ACKB bit
IRIC flag
Stop condition
detection
(1) Acknowledge bit is received
and the ACKB bit is set to 1.
Countermeasure:
Clear the ACKE bit to 0 to clear
the ACKB bit.
(3) Unnecessary interrupt occurs
(received address is invalid).
Figure 16.25 Note on Interrupt Occurrence in Slave Mode after ACKB = 1 Reception
Rev. 4.00 Sep 27, 2006 page 555 of 1130
REJ09B0327-0400
2
Section 16 I C Bus Interface [Option]
• Notes on TRS Bit Setting and ICDR Register Access
Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are
satisfied.
 Master mode
Figure 16.26 shows the notes on ICDR reading (TRS = 1) in master mode.
(1) When previously received 2-bytes data remains in ICDR unread (ICDRS are full).
(2) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(3) Sets to receive mode (TRS = 0), after transmitting Rev.1 frame of issued start condition
by master mode.
 Slave mode
Figure 16.27 shows the notes on ICDR writing (TRS = 0) in slave mode.
(1) Writes ICDR register in receive mode (TRS = 0), after entering the start condition by
slave mode (TDRE = 0 state).
Address match with Rev.1 frame, receive 1 by R/W bit, and switches to transmit mode
(TRS = 1).
When these conditions are satisfied, the low fixation of the SCL pins is cancelled
without ICDR register access after Rev.1 frame is transferred.
 Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).
Rev. 4.00 Sep 27, 2006 page 556 of 1130
REJ09B0327-0400
2
Section 16 I C Bus Interface [Option]
Along with ICDRS: ICDRR transfer
Stop condition
SDA
Cancel condition of SCL =
Low fixation is set.
Start condition
Address
A
SCL
8
1
9
2
3
4
5
6
7
8
A
Data
9
1
2
3
(3) TRS = 0
TRS bit
(2) RDRF = 0
RDRF bit
ICDRS data
full
(1) ICDRS data full
TRS = 0 setting
ICDR read
Detection of 9th clock rise
(TRS = 1)
Figure 16.26 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
Along with ICDRS: ICDRR transfer
Stop condition
Cancel condition of SCL =
Low fixation
Start condition
Address
A
SDA
SCL
8
1
9
2
3
4
A
5
6
8
7
9
Data
1
2
3
4
(2) TRS = 1
TRS bit
TDRE bit
(1) TDRE = 0
ICDR write
TRS = 0 setting
Automatic TRS = 1 setting by
receiving R/W = 1
Figure 16.27 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
Rev. 4.00 Sep 27, 2006 page 557 of 1130
REJ09B0327-0400
2
Section 16 I C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 558 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Section 17 Keyboard Buffer Controller
Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group.
17.1
Overview
The H8S/2148 Group and H8S/2147N have three on-chip keyboard buffer controller channels,
designated 0, 1, and 2. The keyboard buffer controller is provided with functions conforming to
the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line,
providing economical use of connectors, board surface area, etc. Figure 17.1 shows how the
keyboard buffer controller is connected.
17.1.1
Features
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
Rev. 4.00 Sep 27, 2006 page 559 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Vcc
Vcc
System side
Keyboard side
KCLK in
KCLK in
Clock
KCLK out
KCLK out
KD in
KD in
Data
KD out
KD out
Keyboard buffer controller
(H8S/2148 Group and
H8S/2147N chip)
I/F
Figure 17.1 Keyboard Buffer Controller Connection
Rev. 4.00 Sep 27, 2006 page 560 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.1.2
Block Diagram
Figure 17.2 shows a block diagram of the keyboard buffer controller.
Internal
data bus
KCLK
(PS2AC,
PS2BC,
PS2CC)
KDI
Control
logic
KCLKI
KBCRH
Parity
Bus interface
KD
(PS2AD,
PS2BD,
PS2CD)
Module data bus
KBBR
KDO
KCLKO
KBCRL
Register counter value
KB interrupt
Legend:
KD:
KCLK:
KBBR:
KBCRH:
KBCRL:
KBC data I/O pin
KBC clock I/O pin
Keyboard data buffer register
Keyboard control register H
Keyboard control register L
Figure 17.2 Block Diagram of Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 561 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.1.3
Input/Output Pins
Table 17.1 lists the input/output pins used by the keyboard buffer controller.
Table 17.1 Keyboard Buffer Controller Input/Output Pins
Channel
Name
Abbreviation*
I/O
Function
0
KBC clock I/O pin (KCLK0)
PS2AC
I/O
KBC clock input/output
KBC data I/O pin (KD0)
PS2AD
I/O
KBC data input/output
KBC clock I/O pin (KCLK1)
PS2BC
I/O
KBC clock input/output
KBC data I/O pin (KD1)
PS2BD
I/O
KBC data input/output
KBC clock I/O pin (KCLK2)
PS2CC
I/O
KBC clock input/output
KBC data I/O pin (KD2)
PS2CD
I/O
KBC data input/output
1
2
Note:
*
17.1.4
These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK
and data I/O pins as KD, omitting the channel designations.
Register Configuration
Table 17.2 lists the registers of the keyboard buffer controller.
Table 17.2 Keyboard Buffer Controller Registers
1
Name
Abbreviation
R/W
0
Keyboard control register H
KBCRH0
2
R/(W)*
H'70
H'FED8
Keyboard control register L
KBCRL0
R/W
H'70
H'FED9
Keyboard data buffer register
KBBR0
R
H'00
H'FEDA
Keyboard control register H
KBCRH1
R/(W)*
H'70
H'FEDC
Keyboard control register L
KBCRL1
R/W
H'70
H'FEDD
Keyboard data buffer register
KBBR1
R
H'00
H'FEDE
Keyboard control register H
KBCRH2
2
R/(W)*
H'70
H'FEE0
Keyboard control register L
KBCRL2
R/W
H'70
H'FEE1
Keyboard data buffer register
KBBR2
R
H'00
H'FEE2
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
1
2
Common
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bits 2 and 1, to clear the flags.
Rev. 4.00 Sep 27, 2006 page 562 of 1130
REJ09B0327-0400
Initial Value
Address*
Channel
2
Section 17 Keyboard Buffer Controller
17.2
Register Descriptions
17.2.1
Keyboard Control Register H (KBCRH)
Bit
7
6
5
4
3
2
1
0
KBIOE
KCLKI
KDI
KBFSEL
KBIE
KBF
PER
KBS
Initial value
0
1
1
1
0
0
0
0
Read/Write
R/W
R
R
R/W
R/W
R/(W)*
R/(W)*
R
Note:
*
Only 0 can be written, to clear the flags.
KBCRH is an 8-bit readable/writable register that indicates the operating status of the keyboard
buffer controller.
KBCRH is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode. Bits 6, 5, and 2 to 0 are also initialized when KBIOE is
cleared to 0.
Bit 7—Keyboard In/Out Enable (KBIOE): Selects whether or not the keyboard buffer
controller is used. When KBIOE is set to 1, the keyboard buffer controller is enabled for
transmission and reception and the port pins function as KCLK and KD I/O pins. When KBIOE is
cleared to 0, the keyboard buffer controller stops functioning and the port pins go to the highimpedance state.
Bit 7
KBIOE
Description
0
The keyboard buffer controller is non-operational (KCLK and KD signal pins have
port functions)
(Initial value)
1
The keyboard buffer controller is enabled for transmission and reception (KCLK and
KD signal pins are in the bus drive state)
Bit 6—Keyboard Clock In (KCLKI): Monitors the KCLK I/O pin. This bit cannot be modified.
Bit 6
KCLKI
Description
0
KCLK I/O pin is low
1
KCLK I/O pin is high
(Initial value)
Rev. 4.00 Sep 27, 2006 page 563 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Bit 5—Keyboard Data In (KDI): Monitors the KDI I/O pin. This bit cannot be modified.
Bit 5
KDI
Description
0
KD I/O pin is low
1
KD I/O pin is high
(Initial value)
Bit 4—Keyboard Buffer Register Full Select (KBFSEL): Selects whether the KBF bit is used
as the keyboard buffer register full flag or as the KCLK fall interrupt flag, When KBFSEL is
cleared to 0, the KBE bit in the KBCRL register should be cleared to 0 to disable reception.
Bit 4
KBFSEL
Description
0
KBF bit is used as KCLK fall interrupt flag
1
KBF bit is used as keyboard buffer register full flag
(Initial value)
Bit 3—Keyboard Interrupt Enable (KBIE): Enables or disables interrupts from the keyboard
buffer controller to the CPU.
Bit 3
KBIE
Description
0
Interrupt requests are disabled
1
Interrupt requests are enabled
(Initial value)
Bit 2—Keyboard Buffer Register Full (KBF): Indicates that data reception has been completed
and the received data is in the keyboard data buffer register (KBBR).
Bit 2
KBF
Description
0
[Clearing condition]
(Initial value)
Read KBF when KBF =1, then write 0 in KBF
1
[Setting conditions]
•
When data has been received normally and has been transferred to KBBR
(keyboard buffer register full flag)
•
When a KCLK falling edge is detected (while KBFSEL = 0) (KCLK interrupt flag)
Rev. 4.00 Sep 27, 2006 page 564 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER
Description
0
[Clearing condition]
(Initial value)
Read PER when PER =1, then write 0 in PER
1
[Setting condition]
When an odd parity error occurs
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS
Description
0
0 stop bit received
1
1 stop bit received
17.2.2
(Initial value)
Keyboard Control Register L (KBCRL)
Bit
7
6
5
4
3
2
1
0
KBE
KCLKO
KDO
—
RXCR3
RXCR2
RXCR1
RXCR0
Initial value
0
1
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R
R
R
R
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE
Description
0
Loading of receive data into KBBR is disabled
1
Loading of receive data into KBBR is enabled
(Initial value)
Rev. 4.00 Sep 27, 2006 page 565 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output.
Bit 6
KCLKO
Description
0
Keyboard buffer controller clock I/O pin is low
1
Keyboard buffer controller clock I/O pin is high
(Initial value)
Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output.
Bit 5
KDO
Description
0
Keyboard buffer controller data I/O pin is low
1
Keyboard buffer controller data I/O pin is high
(Initial value)
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Bits 3 to 0—Receive Counter (RXCR3 to RXCR0): These bits indicate the received data bit.
Their value is incremented on the fall of KCLK. These bits cannot be modified.
The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns
to 0000 after a stop bit is received.
Bit 3
Bit 2
Bit 1
Bit 0
RXCR3
RXCR2
RXCR1
RXCR0
Receive Data Contents
0
0
0
0
—
1
Start bit
1
1
0
1
1
0
0
1
1
—
0
KB0
1
KB1
0
KB2
1
KB3
0
KB4
1
KB5
0
KB6
1
KB7
0
Parity bit
1
—
—
—
Rev. 4.00 Sep 27, 2006 page 566 of 1130
REJ09B0327-0400
(Initial value)
Section 17 Keyboard Buffer Controller
17.2.3
Keyboard Data Buffer Register (KBBR)
Bit
7
6
5
4
3
2
1
0
KB7
KB6
KB5
KB4
KB3
KB2
KB1
KB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
KBBR is a read-only register that stores receive data. Its value is valid only when KBF = 1.
KBBR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep
mode, and module stop mode, and when KBIOE is cleared to 0.
17.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable register, performs module stop mode control.
When the MSTP2 bit is set to 1, the keyboard buffer controller halts and enters module stop mode.
See section 25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies keyboard buffer controller module stop
mode.
MSTPCRL
Bit 2
MSTP2
Description
0
Keyboard buffer controller module stop mode is cleared
1
Keyboard buffer controller module stop mode is set
(Initial value)
Rev. 4.00 Sep 27, 2006 page 567 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.3
Operation
17.3.1
Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on the H8S/2148 Group chip (system) side. KD receives a start bit, 8 data bits (LSB-first),
an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample
receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.
Rev. 4.00 Sep 27, 2006 page 568 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Start
Set KBIOE bit
[1]
Read KBCRH
[2]
KCLKI
and KDI bits both
1?
No
Yes
Set KBE bit
[3]
[1] Set the KBIOE bit to 1 in
KBCRL.
[2] Read KBCRH, and if the
KCLKI and KDI bits are
both 1, set the KBE bit
(receive enabled state).
Keyboard side in data
transmission state.
Execute receive abort
processing.
[3] Detect the start bit output
on the keyboard side and
receive data in
synchronization with the fall
of KCLK.
Receive enabled state
KBF = 1?
[4] When a stop bit is received,
the keyboard buffer
controller drives KCLK low
to disable keyboard
transmission (automatic I/O
inhibit).
If the KBIE bit is set to 1 in
KBCRH, an interrupt
request is sent to the CPU
at the same time.
No
[4]
Yes
PER = 0?
No
Yes
KBS = 1?
No
[5] Perform receive data
processing.
Yes
Read KBBR
Error handling
Receive data processing
Clear KBF flag
(receive enabled state)
[6]
[5]
[6] Clear the KBF flag to 0 in
KBCRL. At the same time,
the system automatically
drives KCLK high, setting
the receive enabled state.
The receive operation can be
continued by repeating steps
[3] to [6].
Figure 17.3 Sample Receive Processing Flowchart
Rev. 4.00 Sep 27, 2006 page 569 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Receive processing/
error handling
KCLK
(pin state)
1
KD
(pin state)
Start
bit
2
0
3
1
9
7
10
Flag cleared
11
Parity bit Stop bit
KCLK
(input)
KCLK
(output)
Automatic I/O inhibit
KB7 to KB0 Previous data
KB0
KB1
Receive data
PER
KBS
KBF
[1] [2] [3]
[4] [5]
[6]
Figure 17.4 Receive Timing
17.3.2
Transmit Operation
In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an
output on the H8S/2148 Group and H8S/2147N chip (system) side. KD outputs a start bit, 8 data
bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK
is high. A sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in
figure 17.6.
Rev. 4.00 Sep 27, 2006 page 570 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Start
Set KBIOE bit
[1]
Read KBCRH
[2]
KCLKI
and KDI bits both
1?
Yes
Set I/O inhibit (KCLKO = 0)
[1] Set the KBE bit to 1 in KBCRH, and the
KBIOE bit to 1 in KBCRL.
[2] Read KBCRH, and if the KCLKI and
KDI bits are both 1, write 0 in the
KCLKO bit (set I/O inhibit).
No
2
[3] Write 0 in the KBE bit (disable KBBR
receive operation).
KDO remains at 1
[4] Write 0 in the KDO bit (set start bit).
KBE = 0
(KBBR reception disabled)
[3]
[5] Write 1 in the KCLKO bit (clear I/O
inhibit).
Wait
Set start bit (KDO = 0)
Set I/O inhibit (KCLKO = 1)
[4]
KCLKO remains at 0
[5]
KDO remains at 0
i=0
[6]
Read KBCRH
KCLKI = 0?
No
Yes
[6] Read KBCRH, and when KCLKI = 0,
set the transmit data in the KDO bit
(LSB-first). Next, set the parity bit and
stop bit in the KDO bit.
[7] After transmitting the stop bit, read
KBCRL and confirm that KDI = 0
(receive completed notification from the
keyboard).
[8] Read KBCRH. Confirm that the KCLKI
and KDI bits are both 1.
The transmit operation can be continued
by repeating steps [2] to [8].
Set transmit data
(KDO = D(i))
Read KBCRH
KCLKI = 1?
No
Yes
i=i+1
No
i > 9?
Yes
Read KBCRH
KCLKI = 1?
No
Notes: i = 0 to 7: Transmit data
i = 8: Parity bit
i = 9: Stop bit
Yes
1
Figure 17.5 Sample Transmit Processing Flowchart
Rev. 4.00 Sep 27, 2006 page 571 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
1
Read KBCRH
No
KCLKI = 0?
2
Yes
*
[7]
No
KDI = 0?
Keyboard side in data
transmission state.
Execute receive abort
processing.
Yes
[8]
Read KBCRH
Error handling
No
KCLK = 1?
Yes
Transmit end state
(KCLK = high, KD = high)
To receive operation or
transmit operation
Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low.
Figure 17.5 Sample Transmit Processing Flowchart (cont)
KCLK
(pin state)
1
KD
(pin state)
KCLK
(output)
Start bit
2
8
9
10
11
0
1
7
Parity bit Stop bit
0
1
7
Parity bit Stop bit
I/O inhibit
KD
(output)
Start bit
KCLK
(input)
Receive
completed
notification
KD
(input)
[1] [2] [3]
[4] [5]
[6]
[7]
Figure 17.6 Transmit Timing
Rev. 4.00 Sep 27, 2006 page 572 of 1130
REJ09B0327-0400
[8]
Section 17 Keyboard Buffer Controller
17.3.3
Receive Abort
The H8S/2148 Group and H8S/2147N device (system side) can forcibly abort transmission from
the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the
system holds the clock low. During reception, the keyboard also outputs a clock for
synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is
low at this time, the keyboard judges that there is an abort request from the system, and data
transmission from the keyboard is aborted. Thus the system can abort reception by holding the
clock low for a certain period. A sample receive abort processing flowchart is shown in figure
17.7, and the receive abort timing in figure 17.8.
Rev. 4.00 Sep 27, 2006 page 573 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
[1] Read KBCRL, and if KBF = 1,
perform processing 1.
Start
[2] Read KBCRH, and if the value of
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
Receive state
Read KBCRL
No
KBF = 0?
[1]
Yes
Read KBCRH
Processing 1
No
RXCR3 to RXCR0 ≥
B'1001?
Yes
Disable receive abort
requests
[3]
[2]
KCLKO = 0
(receive abort request)
Retransmit
command transmission
(data)?
[3] If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
No
Yes
KBE = 0
(disable KBBR reception
and clear receive counter)
KBE = 0
(disable KBBR reception
and clear receive counter)
Set start bit
(KDO = 0)
KBE = 1
(enable KB operation)
Clear I/O inhibit
(KCLKO = 1)
Clear I/O inhibit
(KCLKO = 1)
Transmit data
To transmit operation
To receive operation
Figure 17.7 Sample Receive Abort Processing Flowchart
Rev. 4.00 Sep 27, 2006 page 574 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
Processing 1
Receive operation ends
normally
[1]
[1] On the system side, drive the KCLK pin low,
setting the I/O inhibit state.
Receive data processing
Clear KBF flag
(KCLK = H)
Transmit enabled state.
If there is transmit data,
the data is transmitted.
Figure 17.7 Sample Receive Abort Processing Flowchart (cont)
Keyboard side monitors clock during
receive operation (transmit operation
as seen from keyboard), and aborts
receive operation during this period.
Reception in progress
KCLK
(pin state)
Transmit operation
Receive abort request
Start bit
KD
(pin state)
KCLK
(input)
KCLK
(output)
KD
(input)
KD
(output)
Figure 17.8 Receive Abort and Transmit Start (Transmission/Reception Switchover)
Timing
Rev. 4.00 Sep 27, 2006 page 575 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.3.4
KCLKI and KDI Read Timing
Figure 17.9 shows the KCLKI and KDI read timing.
T1
T2
φ*
Internal read
signal
KCLK, KD
(pin state)
KCLKI, KDI
(register)
Internal data bus
(read data)
Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.9 KCLKI and KDI Read Timing
Rev. 4.00 Sep 27, 2006 page 576 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.3.5
KCLKO and KDO Write Timing
Figure 17.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
T1
T2
φ*
Internal write
signal
KCLKO, KDO
(register)
KCLK, KD
(pin state)
Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.10 KCLKO and KDO Write Timing
Rev. 4.00 Sep 27, 2006 page 577 of 1130
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Section 17 Keyboard Buffer Controller
17.3.6
KBF Setting Timing and KCLK Control
Figure 17.11 shows the KBF setting timing and the KCLK pin states.
φ*
KCLK
(pin)
11th fall
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
H'010
H'000
KBF
KCLK
(output)
Automatic I/O inhibit
Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
Rev. 4.00 Sep 27, 2006 page 578 of 1130
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Section 17 Keyboard Buffer Controller
17.3.7
Receive Timing
Figure 17.12 shows the receive timing.
φ*
KCLK (pin)
KD (pin)
Internal
KCLK (KCLKI)
Falling edge
signal
RXCR3 to
RXCR0
N
N+1
N+2
Internal KD
(KDI)
KBBR7 to
KBBR0
Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active
mode.
Figure 17.12 Receive Counter and KBBR Data Load Timing
Rev. 4.00 Sep 27, 2006 page 579 of 1130
REJ09B0327-0400
Section 17 Keyboard Buffer Controller
17.3.8
KCLK Fall Interrupt Operation
In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used
as a flag for the interrupt generated by the fall of KCLK input.
Figure 17.13 shows the setting method and an example of operation.
Start
Set KBIOE
KBE = 0
(KBBR reception
disabled)
KBFSEL = 0
KBIE = 1
(KCLK falling edge
interrupts enabled)
KCLK
(pin state)
KBF bit
KCLK pin
fall detected?
No
Yes
KBF = 1
(interrupt generated)
Interrupt
generated
Cleared
by software
Interrupt
generated
Interrupt handling
Clear KBF
Note: The KBF setting timing is the same as the timing of KBF setting and KCLK automatic I/O inhibit bit
generation in figure 17.11. When the KBF bit is used as the KCLK input fall interrupt flag, the
automatic I/O inhibit function does not operate.
Figure 17.13 Example of KCLK Input Fall Interrupt Operation
Rev. 4.00 Sep 27, 2006 page 580 of 1130
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Section 17 Keyboard Buffer Controller
17.3.9
Usage Note
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1.
Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit
operates and the KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1
T2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
KBIOE
Falling edge
signal
KBFSEL
KBE
KBF
Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing
Rev. 4.00 Sep 27, 2006 page 581 of 1130
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Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 582 of 1130
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Section 18 Host Interface
Section 18 Host Interface
Provided in the H8S/2148 Group and H8S/2147N; not provided in the H8S/2144 Group.
18.1
Overview
The H8S/2148 Group and H8S/2147N have an on-chip host interface (HIF) that enables
connection to an ISA bus, widely used as the internal bus in personal computers. The host
interface provides a four-channel parallel interface between the on-chip CPU and a host processor.
The host interface is available only when the HI12E bit is set to 1 in SYSCR2. This mode is called
slave mode, because it is designed for a master-slave communication system in which the
H8S/2148 Group and H8S/2147N chip is slaved to a host processor.
18.1.1
Features
The features of the host interface are summarized below.
The host interface consists of 8-byte data registers, 4-byte status registers, a 2-byte control
register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via
seven control signals from the host processor (CS1, CS2 or ECS2, CS3, CS4, HA0, IOR, and
IOW), six output signals to the host processor (GA20, HIRQ1, HIRQ11, HIRQ12, HIRQ3, and
HIRQ4), and an 8-bit bidirectional command/data bus (HDB7 to HDB0). The CS1, CS2 (or
ECS2), CS3, and CS4 signals select one of the four interface channels.
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Section 18 Host Interface
18.1.2
Block Diagram
Figure 18.1 shows a block diagram of the host interface.
Internal interrupt signals
IBF4 IBF3 IBF2 IBF1
CS1
CS2/ECS2
CS3
CS4
IOR
IOW
HA0
HDB7 to HDB0
IDR1
ODR1
Control logic
STR1
IDR2
ODR2
Fast
A20 gate
control
HICR
IDR3
ODR3
STR3
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
IDR4
ODR4
Port 4, port 8, port B
STR4
HIFSD
HICR2
Bus
interface
Internal data bus
Legend:
IDR1: Input data register 1
IDR2: Input data register 2
ODR1: Output data register 1
ODR2: Output data register 2
STR1: Status register 1
STR2: Status register 2
HICR: Host interface control register 1
IDR3:
IDR4:
ODR3:
ODR4:
STR3:
STR4:
HICR2:
Input data register 3
Input data register 4
Output data register 3
Output data register 4
Status register 3
Status register 4
Host interface control register 2
Figure 18.1 Block Diagram of Host Interface
Rev. 4.00 Sep 27, 2006 page 584 of 1130
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Module data bus
Host
interrupt
request
Host data bus
STR2
Section 18 Host Interface
18.1.3
Input and Output Pins
Table 18.1 lists the input and output pins of the host interface module.
Table 18.1
Host Interface Input/Output Pins
Name
Abbreviation
Port
I/O
Function
I/O read
IOR
P93
Input
Host interface read signal
I/O write
IOW
P94
Input
Host interface write signal
Chip select 1
CS1
P95
Input
Host interface chip select signal for IDR1,
ODR1, STR1
Chip select 2*
CS2
P81
Input
ECS2
P90
Host interface chip select signal for IDR2,
ODR2, STR2
Chip select 3
CS3
PB2
Input
Host interface chip select signal for IDR3,
ODR3, STR3
Chip select 4
CS4
PB3
Input
Host interface chip select signal for IDR4,
ODR4, STR4
Command/data
HA0
P80
Input
Host interface address select signal.
In host read access, this signal selects the
status registers (STR1 to STR4) or data
registers (ODR1 to ODR4). In host write
access to the data registers (IDR1 to IDR3,
and IDTR4), this signal indicates whether
the host is writing a command or data.
Data bus
HDB7 to HDB0 P37 to I/O
P30
Host interface data bus
Host interrupt 1
HIRQ1
P44
Output
Interrupt output 1 to host
Host interrupt 11
HIRQ11
P43
Output
Interrupt output 11 to host
Host interrupt 12
HIRQ12
P45
Output
Interrupt output 12 to host
Host interrupt 3
HIRQ3
PB0
Output
Interrupt output 3 to host
Host interrupt 4
HIRQ4
PB1
Output
Interrupt output 4 to host
Gate A20
GA20
P81
Output
A20 gate control signal output
HIF shutdown
HIFSD
P82
Input
Host interface shutdown control signal
Note:
*
Selection of CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in
HICR. Host interface channel 2 and the CS2 pin can be used when CS2E = 1. When
CS2E = 1, CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this
manual, both are referred to as CS2.
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Section 18 Host Interface
18.1.4
Register Configuration
Table 18.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,
ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.
Table 18.2 Host Interface Registers
Name
System control register
R/W
Abbreviation
Slave
SYSCR
R/W*
1
Master Address*4
Host
Initial Slave
Value Address*3 CS1
CS2
CS3
CS4
HA0
—
H'09
H'FFC4
—
—
—
—
—
System control register 2 SYSCR2
R/W
—
H'00
H'FF83
—
—
—
—
—
Host interface control
register 1
HICR
R/W
—
H'F8
H'FFF0
—
—
—
—
—
Host interface control
register 2
HICR2
R/W
—
H'F8
H'FE80
—
—
—
—
—
Input data register 1
IDR1
R
W
—
H'FFF4
0
1
1
1
0/1*5
Output data register 1
ODR1
R/W
R
—
H'FFF5
0
1
1
1
0
Status register 1
STR1
R/(W)*2 R
H'00
H'FFF6
0
1
1
1
1
Input data register 2
IDR2
R
W
—
H'FFFC
1
0
1
1
0/1*5
Output data register 2
ODR2
R/W
R
—
H'FFFD
1
0
1
1
0
Status register 2
STR2
R/(W)*
R
H'00
H'FFFE
1
0
1
1
1
Input data register 3
IDR3
R
W
—
H'FE84
1
1
0
1
0/1*5
Output data register 3
ODR3
R/W
R
—
H'FE85
1
1
0
1
0
Status register 3
STR3
R/(W)*2 R
H'00
H'FE86
1
1
0
1
1
Input data register 4
IDR4
R
W
—
H'FE8C
1
1
1
0
0/1*5
Output data register 4
ODR4
R/W
R
—
H'FE8D
1
1
1
0
0
Status register 4
STR4
R/(W)*
R
H'00
H'FE8E
1
1
1
0
1
Module stop control
register
MSTPCRH
R/W
—
H'3F
H'FF86
—
—
—
—
—
MSTPCRL
R/W
—
H'FF
H'FF87
—
—
—
—
—
2
2
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave
processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Pin inputs used in access from the host processor.
5. The HA0 input discriminates between writing of commands and data.
Rev. 4.00 Sep 27, 2006 page 586 of 1130
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Section 18 Host Interface
18.2
Register Descriptions
18.2.1
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
SYSCR is an 8-bit readable/writable register which controls H8S/2148 Group chip operations. Of
the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be
accessed when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can
be accessed regardless of the setting of the HIE bit. The host interface CS2 and ECS2 pins are
controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System
Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information
on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode.
Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin
that performs the CS2 function.
SYSCR
Bit 7
HICR
Bit 0
CS2E
FGA20E
Description
0
0
CS2 pin function halted (CS2 fixed high internally)
(Initial value)
1
1
0
CS2 pin function selected for P81/CS2 pin
1
CS2 pin function selected for P90/ECS2 pin
Rev. 4.00 Sep 27, 2006 page 587 of 1130
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Section 18 Host Interface
Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to the host interface
registers. When enabled, the host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2,
and STR2) can be accessed.
Bit 1
HIE
Description
0
Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is disabled
(Initial value)
1
Host interface register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU
access is enabled
18.2.2
System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
KWUL1
KWUL0
P6PUE
—
SDE
CS4E
CS3E
HI12E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit readable/writable register which controls chip operations. Host interface
functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can
be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2
is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be
set and changed by software. For details see section 8, I/O Ports.
Bit 5—Port 6 Input Pull-Up Extra (P6PUE): Controls and selects the current specification for
the port 6 MOS input pull-up function connected by means of KMPCR settings. For details see
section 8, I/O Ports.
Bit 4—Reserved: Do not write 1 to this bit.
Rev. 4.00 Sep 27, 2006 page 588 of 1130
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Section 18 Host Interface
Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function.
When this function is enabled, host interface pin functions can be halted, and the pins placed in the
high-impedance state, according to the state of the HIFSD pin.
Bit 3
SDE
Description
0
Host interface pin shutdown function disabled
1
Host interface pin shutdown function enabled
(Initial value)
Bit 2—CS4 Enable (CS4E): Enables or disables host interface channel 4 functions in slave mode.
When these functions are enabled, channel 4 pins are enabled and processing can be performed for
data transfer between the slave and the host.
Bit 2
CS4E
Description
0
Host interface pin channel 4 functions disabled
1
Host interface pin channel 4 functions enabled
(Initial value)
Bit 1—CS3 Enable (CS3E): Enables or disables host interface channel 3 functions in slave mode.
When these functions are enabled, channel 3 pins are enabled and processing can be performed for
data transfer between the slave and the host.
Bit 1
CS3E
Description
0
Host interface pin channel 3 functions disabled
1
Host interface pin channel 3 functions enabled
(Initial value)
Bit 0—Host Interface Enable Bit (HI12E): Enables or disables host interface functions in
single-chip mode. When the host interface functions are enabled, slave mode is entered and
processing is performed for data transfer between the slave and host.
Bit 0
HI12E
Description
0
Host interface functions are disabled
1
Host interface functions are enabled
(Initial value)
Rev. 4.00 Sep 27, 2006 page 589 of 1130
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Section 18 Host Interface
18.2.3
Host Interface Control Register (HICR)
• HICR
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
IBFIE2
Initial value
1
1
1
1
1
0
0
0
Slave Read/Write
—
—
—
—
—
R/W
R/W
R/W
Host Read/Write
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
—
—
—
—
—
IBFIE4
IBFIE3
—
IBFIE1 FGA20E
• HICR2
Bit
Initial value
1
1
1
1
1
0
0
0
Slave Read/Write
—
—
—
—
—
R/W
R/W
—
Host Read/Write
—
—
—
—
—
—
—
—
HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts
and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host
interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in
hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1)
HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)
These bits enable or disable the IBF1, IBF2, IBF3, and IBF4 interrupts to the internal CPU.
Rev. 4.00 Sep 27, 2006 page 590 of 1130
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Section 18 Host Interface
HICR2
Bit 2
HICR2
Bit 1
HICR
Bit 2
HICR
Bit 1
IBFIE4
IBFIE3
IBFIE2
IBFIE1
Description
—
—
—
0
Input data register (IDR1) reception completed interrupt
request disabled
(Initial value)
—
—
—
1
Input data register (IDR1) reception completed interrupt
request enabled
—
—
0
—
Input data register (IDR2) reception completed interrupt
request disabled
(Initial value)
—
—
1
—
Input data register (IDR2) reception completed interrupt
request enabled
—
0
—
—
Input data register (IDR3) reception completed interrupt
request disabled
(Initial value)
—
1
—
—
Input data register (IDR3) reception completed interrupt
request enabled
0
—
—
—
Input data register (IDR4) reception completed interrupt
request disabled
(Initial value)
1
—
—
—
Input data register (IDR4) reception completed interrupt
request enabled
HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate
function. When the fast A20 gate is disabled, the normal A20 gate can be implemented byte
firmware operation of the P81 output.
HICR
Bit 0
FGA20E
Description
0
Fast A20 gate function disabled
1
Fast A20 gate function enabled
(Initial value)
HICR2 Bit 0—Reserved: Do not set this bit to 1.
Rev. 4.00 Sep 27, 2006 page 591 of 1130
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Section 18 Host Interface
18.2.4
Input Data Register 1 (IDR1)
Bit
7
6
5
4
3
2
1
0
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0
Initial value
—
—
—
—
—
—
—
—
Slave Read/Write
R
R
R
R
R
R
R
R
Host Read/Write
W
W
W
W
W
W
W
W
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CSn (n = 1 to 4) is low, information on the host data bus is written into
IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STRn to indicate
whether the written information is a command or data.
The initial values of IDR1 after a reset and in standby mode are undetermined.
18.2.5
Output Data Register 1 (ODR)
Bit
7
6
5
4
3
2
1
0
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0
—
—
—
—
—
—
—
—
Slave Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Host Read/Write
R
R
R
R
R
R
R
R
Initial value
ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODRn contents are output on the host data bus when HA0 is low, CSn
(n = 1 to 4) is low, and IOR is low.
The initial values of ODR1 after a reset and in standby mode are undetermined.
Rev. 4.00 Sep 27, 2006 page 592 of 1130
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Section 18 Host Interface
18.2.6
Status Register (STR)
Bit
Initial value
7
6
5
4
3
2
1
0
DBU
DBU
DBU
DBU
C/D
DBU
IBF
OBF
0
0
0
0
0
0
0
0
Slave Read/Write
R/W
R/W
R/W
R/W
R
R/W
R
R/(W)*
Host Read/Write
R
R
R
R
R
R
R
R
Note: * Only 0 can be written, to clear the flag.
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors.
STR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D
D): Receives the HA0 input when the host processor writes to IDR1,
and indicates whether IDR1 contains data or a command.
Bit 3
C/D
D
Description
0
Contents of input data register (IDR1) are data
1
Contents of input data register (IDR1) are a command
(Initial value)
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR1.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18.7.
Bit 1
IBF
Description
0
[Clearing condition]
When the slave processor reads IDR
1
(Initial value)
[Setting condition]
When the host processor writes to IDR
Rev. 4.00 Sep 27, 2006 page 593 of 1130
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Section 18 Host Interface
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR.
Bit 0
OBF
Description
0
[Clearing condition]
When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value)
1
[Setting condition]
When the slave processor writes to ODR
Table 18.3 shows the conditions for setting and clearing the STR flags.
Table 18.3 Set/Clear Timing for STR Flags
Flag
Setting Condition
Clearing Condition
C/D
Rising edge of host’s write signal
(IOW) when HA0 is high
Rising edge of host’s write signal (IOW) when
HA0 is low
IBF*
Rising edge of host’s write signal
(IOW) when writing to IDR1
Falling edge of slave’s internal read signal (RD)
when reading IDR1
OBF
Falling edge of slave’s internal write Rising edge of host’s read signal (IOR) when
signal (WR) when writing to ODR1 reading ODR1
Note:
*
The IBF flag setting and clearing conditions are different when the fast A20 gate is
used. For details see table 18.7.
Rev. 4.00 Sep 27, 2006 page 594 of 1130
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Section 18 Host Interface
18.2.7
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.
MSTPCRL
Bit 2
MSTP2
Description
0
Host interface module stop mode is cleared
1
Host interface module stop mode is set
18.3
Operation
18.3.1
Host Interface Activation
(Initial value)
The HIF (slave mode) is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip
mode. When the HIF (slave mode) is activated, all related I/O ports (data port 3, control ports 8
and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E
bit and CS4E bit to 1 enables the number of HIF channels to be extended to a four, and makes the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Table 18.4 shows HIF host interface channel selection and pin operation.
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Section 18 Host Interface
Table 18.4 Host Interface Channel Selection and Pin Operation
HI12E
CS2E
CS3E
CS4E
Operation
0
—
—
—
Host interface functions halted
1
0
0
0
Host interface channel 1 only operating
Operation of channels 2 to 4 halted
(No operation as CS2 or ECS2, CS3, and CS4 inputs. Pins
P43, P81, P90, and PB0 to PB3 operate as I/O ports.)
1
Host interface channel 1 and 4 functions operating
Operation of channels 2 and 3 halted
(No operation as CS2 or ECS2 and CS3 inputs. Pins P43, P81,
P90, PB0, and PB2 operate as I/O ports.)
1
0
Host interface channel 1 and 3 functions operating
Operation of channels 2 and 4 halted
(No operation as CS2 or ECS2 and CS4 inputs. Pins P43, P81,
P90, PB1, and PB3 operate as I/O ports.)
1
Host interface channel 1, 3, and 4 functions operating
Operation of channel 2 halted
(No operation as CS2 or ECS2 input. Pins P43, P81, and P90
operate as I/O ports.)
1
0
0
Host interface channel 1 and 2 functions operating
Operation of channels 3 and 4 halted
(No operation as CS3 and CS4 inputs. Pins PB0 to PB3
operate as I/O ports.)
1
Host interface channel 1, 2, and 4 functions operating
Operation of channel 3 halted
(No operation as CS3 input. Pins PB0 and PB2 operate as I/O
ports.)
1
0
Host interface channel 1 to 3 functions operating
Operation of channel 4 halted
(No operation as CS4 input. Pins PB1 and PB3 operate as I/O
ports.)
1
Host interface channel 1 to 4 functions operating
For host read/write timing, see section 26.7.5, Timing of On-Chip Supporting Modules.
Rev. 4.00 Sep 27, 2006 page 596 of 1130
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Section 18 Host Interface
18.3.2
Control States
Table 18.5 shows host interface operations from the HIF host, and slave operation.
Table 18.5 Host Interface Operations from HIF Host, and Slave Operation
Other than
CSn
CSn
IOR
IOW
HA0
Operation
1
0
0
0
0
Setting prohibited
1
Setting prohibited
1
1
0
1
0
Data read from output data register n (ODRn)
1
Status read from status register n (STRn)
0
Data written to input data register n (IDRn)
1
Command written to input data register n (IDRn)
0
Idle state
1
Idle state
Note: n = 1 to 4
18.3.3
A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be
output under firmware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0)
to 1 in HICR (H'FFF0).
Note: * Intel microprocessor.
Regular A20 Gate Operation
Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the
slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt
to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs
it at the gate A20 pin.
Fast A20 Gate Operation
When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit
P81DDR must be set to 1 to assign this pin for output. The initial output from this pin will be a
logic 1, which is the initial value. Afterward, the host processor can manipulate the output from
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REJ09B0327-0400
Section 18 Host Interface
this pin by sending commands and data. This function is available only when register IDR1 is
accessed using CS1. Slave logic decodes the commands input from the host processor. When an
H'D1 host command is detected, bit 1 of the data following the host command is output from the
GA20 output pin. This operation does not depend on firmware or interrupts, and is faster than the
regular processing using interrupts. Table 18.6 lists the conditions that set and clear GA20 (P81).
Figure 18.2 shows the GA20 output in flowchart form. Table 18.7 indicates the GA20 output
signal values.
Table 18.6 GA20 (P81) Set/Clear Timing
Pin Name
Setting Condition
Clearing Condition
GA20
(P81)
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 1
and the data follows an H'D1 host
command
Rising edge of the host’s write signal
(IOW) when bit 1 of the written data is 0
and the data follows an H'D1 host
command
Also, when bit FGA20E in HICR is cleared
to 0
Start
Host write
No
H'D1 command
received?
Yes
Wait for next byte
Host write
No
Data byte?
Yes
Write bit 1 of data byte
to DR bit of P81/GA20
Figure 18.2 GA20 Output
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Section 18 Host Interface
Table 18.7 Fast A20 Gate Output Signal
HA0
Data/Command
Internal CPU
Interrupt Flag
GA20
(P81)
1
0
1
H'D1 command
1
1 data*
H'FF command
0
0
0
Q
1
Q (1)
Turn-on sequence
1
0
1
H'D1 command
2
0 data*
H'FF command
0
0
0
Q
0
Q (0)
Turn-off sequence
1
0
1/0
H'D1 command
1
1 data*
Command other than H'FF
and H'D1
0
0
1
Q
1
Q (1)
Turn-on sequence
(abbreviated form)
1
0
1/0
H'D1 command
2
0 data*
Command other than H'FF
and H'D1
0
0
1
Q
0
Q (0)
Turn-off sequence
(abbreviated form)
1
1
H'D1 command
Command other than H'D1
0
1
Q
Q
Cancelled sequence
1
1
H'D1 command
H'D1 command
0
0
Q
Q
Retriggered sequence
1
0
1
H'D1 command
Any data
H'D1 command
0
0
0
Q
1/0
Q(1/0)
Consecutively executed
sequences
Remarks
Notes: 1. Arbitrary data with bit 1 set to 1.
2. Arbitrary data with bit 1 cleared to 0.
18.3.4
Host Interface Pin Shutdown Function
Host interface output can be placed in the high-impedance state according to the state of the
HIFSD pin. Setting the SDE bit to 1 in the SYSCR2 register enables the HIFSD pin is slave mode.
The HIF constantly monitors the HIFSD pin, and when this pin goes low, places the host interface
output pins (HIRQ1, HIRQ11, HIRQ12, HIRQ3, HIRQ4, and GA20) in the high-impedance state.
At the same time, the host interface input pins (CS1, CS2 or ECS2, CS3, CS4, IOW, IOR, and
HA0) are disabled (fixed at the high input state internally) regardless of the pin states, and the
signals of the multiplexed functions of these pins (input block) are similarly fixed internally. As a
result, the host interface I/O pins (HDB7 to HDB0) also go to the high-impedance state.
This state is maintained while the HIFSD pin is low, and when the HIFSD pin returns to the highlevel state, the pins are restored to their normal operation as host interface pins.
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Section 18 Host Interface
Table 18.8 shows the scope of HIF pin shutdown in slave mode.
Table 18.8 Scope of HIF Pin Shutdown in Slave Mode
Abbreviation
Port
Scope of
Shutdown in
Slave Mode I/O
IOR
P93
O
Input
Slave mode
IOW
P94
O
Input
Slave mode
CS1
P95
O
Input
Slave mode
CS2
P81
∆
Input
Slave mode and CS2E = 1 and FGA20E = 0
ECS2
P90
∆
Input
Slave mode and CS2E = 1 and FGA20E = 1
CS3
PB2
∆
Input
Slave mode and CS3E = 1
CS4
PB3
∆
Input
Slave mode and CS4E = 1
HA0
P80
O
Input
Slave mode
HDB7 to
HDB0
P37 to
P30
O
I/O
Slave mode
HIRQ11
P43
∆
Output
Slave mode and CS2E = 1 and P43DDR = 1
HIRQ1
P44
∆
Output
Slave mode and P44DDR = 1
HIRQ12
P45
∆
Output
Slave mode and P45DDR = 1
HIRQ3
PB0
∆
Output
Slave mode and CS3E = 1 and PB0DDR = 1
HIRQ4
PB1
∆
Output
Slave mode and CS4E = 1 and PB1DDR = 1
GA20
P81
∆
Output
Slave mode and FGA20E = 1
HIFSD
P82
—
Input
Slave mode and SDE = 1
Selection Conditions
Legend:
O: Pins shut down by shutdown function
The IRQ2/ADTRG input signal is also fixed in the case of P90 shutdown, the TMCI1/HSYNCI
signal in the case of P43 shutdown, and the TMRI/CSYNCI in the case of P45 shutdown.
∆: Pins shut down only when the HIF function is selected by means of a register setting
—: Pin not shut down
Note: Slave mode: Single-chip mode and HI12E = 1
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Section 18 Host Interface
18.4
Interrupts
18.4.1
IBF1, IBF2, IBF3, IBF4
The host interface can issue two interrupt requests to the slave CPU: IBF1, IBF2, IBF3, and IBF4.
They are input buffer full interrupts for input data registers IDR1, IDR2, IDR3, and IDR4
respectively. Each interrupt is enabled when the corresponding enable bit is set.
Table 18.9 Input Buffer Full Interrupts
Interrupt
Description
IBF1
Requested when IBFIE1 is set to 1 and IDR1 is full
IBF2
Requested when IBFIE2 is set to 1 and IDR2 is full
IBF3
Requested when IBFIE3 is set to 1 and IDR3 is full
IBF4
Requested when IBFIE4 is set to 1 and IDR4 is full
18.4.2
HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4
In slave mode (single-chip mode, with HI12E = 1 in SYSCR2), bits P45DR to P43DR in the port
4 data register (P4DR) and bits PB1ODR and PB0ODR in the port B data register (PBODR) can
be used as host interrupt request latches
The corresponding bits in P4DR are cleared to 0 by the host processor’s read signal (IOR). If CS1
and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared
to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to
0. The corresponding bit in PBODR is cleared to 0 by the host’s read signal (IOR). If CS3 and
HA0 are low, when IOR goes low and the host reads ODR3, HIRQ3 is cleared to 0. If CS4 and
HA0 are low, when IOR goes low and the host reads ODR4, HIRQ4 is cleared to 0. To generate a
host interrupt request, normally on-chip firmware writes 1 in the corresponding bit. In processing
the interrupt, the host’s interrupt handling routine reads the output data register (ODR1, ODR2,
ODR3, or ODR4) and this clears the host interrupt latch to 0.
Table 18.10 indicates how these bits are set and cleared. Figure 18.3 shows the processing in
flowchart form.
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Section 18 Host Interface
Table 18.10 HIRQ Setting/Clearing Conditions
Host Interrupt
Signal
Setting Condition
Clearing Condition
HIRQ11
(P43)
Internal CPU reads 0 from bit P43DR,
then writes 1
Internal CPU writes 0 in bit P43DR, or
host reads output data register 2
HIRQ1
(P44)
Internal CPU reads 0 from bit P44DR,
then writes 1
Internal CPU writes 0 in bit P44DR, or
host reads output data register 1
HIRQ12
(P45)
Internal CPU reads 0 from bit P45DR,
then writes 1
Internal CPU writes 0 in bit P45DR, or
host reads output data register 1
HIRQ3
(PB0)
Internal CPU reads 0 from bit PB0ODR,
then writes 1
Internal CPU writes 0 in bit PB0ODR,
or host reads output data register 3
HIRQ4
(PB1)
Internal CPU reads 0 from bit PB1ODR,
then writes 1
Internal CPU writes 0 in bit PB1ODR,
or host reads output data register 4
Slave CPU
Master CPU
Write to ODR
Write 1 to P4DR
No
HIRQ output high
Interrupt initiation
HIRQ output low
ODR read
P4DR = 0?
Yes
No
All bytes
transferred?
Yes
Hardware operations
Software operations
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)
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Section 18 Host Interface
HIRQ Setting/Clearing Contention
If there is contention between a P4DR or PBODR read/write by the CPU and P4DR (HIRQ11,
HIRQ1, HIRQ12) or PBODR (HIRQ3, HIRQ4) clearing by the host, clearing by the host is held
pending during the P4DR or PBODR read/write by the CPU. P4DR or PBODR clearing is
executed after completion of the read/write.
18.5
Usage Note
The following points require attention when using the host interface.
(1) Host and slave transmission/reception procedures
The host interface provides buffering of asynchronous data from the host and slave processors,
but an interface protocol must be followed to implement necessary functions and avoid data
contention. For example, if the host and slave processors try to access the same input or output
data register simultaneously, the data will be corrupted. Interrupts can be used to design a
simple and effective protocol.
(2) Preventing data contention on the HDB
When the HIF function is used (HI12E = 1 in SYSCR2) and channel 3 or channel 4 has been
set as deselected (CS3E = 0 or CS4E = 0 in SYSCR2), apply either of the following usage
conditions.
1. Ensure that the CS pin for the deselected channel is fixed high.
2. Do not perform port B reads.
(3) Preventing through-current in pins CS1 to CS4
Also, if two or more of pins CS1 to CS4 are driven low simultaneously in attempting IDR or
ODR access, signal contention will occur within the chip, and a through-current may result.
This usage must therefore be avoided.
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Section 18 Host Interface
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Section 19 D/A Converter
Section 19 D/A Converter
19.1
Overview
This LSI have an on-chip D/A converter module with two channels.
19.1.1
Features
Features of the D/A converter module are listed below.
• Eight-bit resolution
• Two-channel output
• Maximum conversion time: 10 µs (with 20-pF load capacitance)
• Output voltage: 0 V to AVref
• D/A output retention in software standby mode
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Section 19 D/A Converter
19.1.2
Block Diagram
Module data bus
Bus interface
Figure 19.1 shows a block diagram of the D/A converter.
AVref
DACR
8-bit D/A
DADR1
DA0
DADR0
AVCC
DA1
AVSS
Control
circuit
Legend:
DACR: D/A control register
DADR0: D/A data register 0
DADR1: D/A data register 1
Figure 19.1 Block Diagram of D/A Converter
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Internal data bus
Section 19 D/A Converter
19.1.3
Input and Output Pins
Table 19.1 lists the input and output pins used by the D/A converter module.
Table 19.1 Input and Output Pins of D/A Converter Module
Name
Abbreviation
I/O
Function
Analog supply voltage
AVCC
Input
Power supply for analog circuits
Analog ground
AVSS
Input
Ground and reference voltage for analog
circuits
Analog output 0
DA0
Output
Analog output channel 0
Analog output 1
DA1
Output
Analog output channel 1
Reference voltage pin
AVref
Input
Reference voltage for analog circuits
19.1.4
Register Configuration
Table 19.2 lists the registers of the D/A converter module.
Table 19.2 D/A Converter Registers
Name
Abbreviation
R/W
Initial Value
Address*
D/A data register 0
DADR0
R/W
H'00
H'FFF8
D/A data register 1
DADR1
R/W
H'00
H'FFF9
D/A control register
DACR
R/W
H'1F
H'FFFA
Module stop control
register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Note:
*
Lower 16 bits of the address.
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Section 19 D/A Converter
19.2
Register Descriptions
19.2.1
D/A Data Registers 0 and 1 (DADR0, DADR1)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable/writable registers that store
data to be converted. When analog output is enabled, the value in the D/A data register is
converted and output continuously at the analog output pin.
The D/A data registers are initialized to H'00 by a reset and in hardware standby mode.
19.2.2
D/A Control Register (DACR)
Bit
7
6
5
4
3
2
1
0
DAOE1
DAOE0
DAE
—
—
—
—
—
Initial value
0
0
0
1
1
1
1
1
Read/Write
R/W
R/W
R/W
—
—
—
—
—
DACR is an 8-bit readable/writable register that controls the operation of the D/A converter
module.
DACR is initialized to H'1F by a reset and in hardware standby mode.
Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.
Bit 7
DAOE1
Description
0
Analog output DA1 is disabled
1
D/A conversion is enabled on channel 1. Analog output DA1 is enabled
Rev. 4.00 Sep 27, 2006 page 608 of 1130
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(Initial value)
Section 19 D/A Converter
Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.
Bit 6
DAOE0
Description
0
Analog output DA0 is disabled
1
D/A conversion is enabled on channel 0. Analog output DA0 is enabled
(Initial value)
Bit 5—D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and
DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0.
Channels 0 and 1 are controlled together when DAE = 1.
Output of the converted results is always controlled independently by DAOE0 and DAOE1.
Bit 7
Bit 6
Bit 5
DAOE1
DAOE0
DAE
D/A conversion
0
0
*
Disabled on channels 0 and 1
1
0
Enabled on channel 0
Disabled on channel 1
1
Enabled on channels 0 and 1
0
Disabled on channel 0
Enabled on channel 1
1
Enabled on channels 0 and 1
*
Enabled on channels 0 and 1
1
0
1
Legend:
*: Don’t care
If the chip enters software standby mode while D/A conversion is enabled, the D/A output is
retained and the analog power supply current is the same as during D/A conversion. If it is
necessary to reduce the analog power supply current in software standby mode, disable D/A
output by clearing the DAOE0, DAOE1, and DAE bits to 0.
Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1.
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Section 19 D/A Converter
19.2.3
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP10 bit is set to 1, the D/A converter halts and enters module stop mode at the end
of the bus cycle. See section 25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 2—Module Stop (MSTP10): Specifies D/A converter module stop mode.
MSTPCRH
Bit 2
MSTP10
Description
0
D/A converter module stop mode is cleared
1
D/A converter module stop mode is set
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(Initial value)
Section 19 D/A Converter
19.3
Operation
The D/A converter module has two built-in D/A converter circuits that can operate independently.
D/A conversion is performed continuously whenever enabled by the D/A control register (DACR).
When a new value is written in DADR0 or DADR1, conversion of the new value begins
immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1.
An example of conversion on channel 0 is given next. Figure 19.2 shows the timing.
• Software writes the data to be converted in DADR0.
• D/A conversion begins when the DAOE0 bit in DACR is set to 1. After the elapse of the
conversion time, analog output appears at the DA0 pin. The output value is AVref × (DADR
value)/256.
This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0.
• If a new value is written in DADR0, conversion begins immediately. Output of the converted
result begins after the conversion time.
• When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
φ
Address
Conversion data (1)
DADR0
Conversion data (2)
DAOE0
Conversion result (2)
Conversion result (1)
DA0
High-impedance state
t DCONV
t DCONV
Legend:
t DCONV: D/A conversion time
Figure 19.2 D/A Conversion (Example)
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Section 19 D/A Converter
Rev. 4.00 Sep 27, 2006 page 612 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Section 20 A/D Converter
20.1
Overview
This LSI incorporate a 10-bit successive-approximations A/D converter that allows up to eight
analog input channels to be selected.
In addition to the eight analog input channels, up to 16 channels of digital input can be selected for
A/D conversion. Since the conversion precision falls when digital input is selected, digital input is
ideal for use by a comparator identifying multi-valued inputs, for example.
20.1.1
Features
A/D converter features are listed below.
• 10-bit resolution
• Eight (analog) or 16 (digital) input channels
• Settable analog conversion voltage range
 The analog conversion voltage range is set using the reference power supply voltage pin
(AVref) as the analog reference voltage
• High-speed conversion
 Minimum conversion time: 6.7 µs per channel (at 20-MHz operation)
• Choice of single mode or scan mode
 Single mode: Single-channel A/D conversion
 Scan mode:
Continuous A/D conversion on 1 to 4 channels
• Four data registers
 Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
 Choice of software or timer conversion start trigger (8-bit timer), or ADTRG pin
• A/D conversion end interrupt generation
 An A/D conversion end interrupt (ADI) request can be generated at the end of A/D
conversion
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Section 20 A/D Converter
20.1.2
Block Diagram
Figure 20.1 shows a block diagram of the A/D converter.
Internal
data bus
AVSS
ADCR
ADCSR
ADDRD
ADDRC
+
–
Multiplexer
AN0
AN1
AN2
AN3
AN4
AN5
AN6/CIN0 to CIN7
AN7/CIN8 to CIN15
ADDRB
10-bit D/A
ADDRA
AVref
Successive approximations
register
AVCC
Bus interface
Module data bus
Comparator
φ/8
Control circuit
Sample-andhold circuit
φ/16
ADI interrupt
signal
ADTRG
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
Conversion start
trigger from 8-bit
timer
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 20.1 Block Diagram of A/D Converter
Rev. 4.00 Sep 27, 2006 page 614 of 1130
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Section 20 A/D Converter
20.1.3
Pin Configuration
Table 20.1 summarizes the input pins used by the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
Table 20.1 A/D Converter Pins
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground and A/D conversion
reference voltage
Reference power supply pin
AVref
Input
A/D conversion reference voltage
Analog input pin 0
AN0
Input
Analog input channel 0
Analog input pin 1
AN1
Input
Analog input channel 1
Analog input pin 2
AN2
Input
Analog input channel 2
Analog input pin 3
AN3
Input
Analog input channel 3
Analog input pin 4
AN4
Input
Analog input channel 4
Analog input pin 5
AN5
Input
Analog input channel 5
Analog input pin 6
AN6
Input
Analog input channel 6
Analog input pin 7
AN7
Input
Analog input channel 7
A/D external trigger input pin
ADTRG
Input
External trigger input for starting A/D
conversion
Expansion A/D input pins
0 to 15
CIN0 to
CIN15
Input
Expansion A/D conversion input (digital
input pin) channels 0 to 15
Rev. 4.00 Sep 27, 2006 page 615 of 1130
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Section 20 A/D Converter
20.1.4
Register Configuration
Table 20.2 summarizes the registers of the A/D converter.
Table 20.2 A/D Converter Registers
Name
Abbreviation
R/W
Initial Value
1
Address*
A/D data register AH
ADDRAH
R
H'00
H'FFE0
A/D data register AL
ADDRAL
R
H'00
H'FFE1
A/D data register BH
ADDRBH
R
H'00
H'FFE2
A/D data register BL
ADDRBL
R
H'00
H'FFE3
A/D data register CH
ADDRCH
R
H'00
H'FFE4
A/D data register CL
ADDRCL
R
H'00
H'FFE5
A/D data register DH
ADDRDH
R
H'00
H'FFE6
A/D data register DL
ADDRDL
R
H'00
H'FFE7
A/D control/status register
ADCSR
2
R/(W)*
H'00
H'FFE8
A/D control register
ADCR
R/W
H'3F
H'FFE9
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
KBCOMP
R/W
H'00
H'FEE4
Keyboard comparator control
register
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written in bit 7, to clear the flag.
20.2
Register Descriptions
20.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
Rev. 4.00 Sep 27, 2006 page 616 of 1130
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Section 20 A/D Converter
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
20.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
20.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode, watch mode,
subactive mode, subsleep mode, and module stop mode.
Table 20.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6 or CIN0 to CIN7
ADDRC
AN3
AN7 or CIN8 to CIN15
ADDRD
20.2.2
A/D Control/Status Register (ADCSR)
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Note: * Only 0 can be written in bit 7, to clear the flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Rev. 4.00 Sep 27, 2006 page 617 of 1130
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Section 20 A/D Converter
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing conditions]
1
•
When 0 is written in the ADF flag after reading ADF = 1
•
When the DTC is activated by an ADI interrupt and ADDR is read
(Initial value)
[Setting conditions]
•
Single mode: When A/D conversion ends
•
Scan mode:
When A/D conversion ends on all specified channels
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE
Description
0
A/D conversion end interrupt (ADI) request is disabled
1
A/D conversion end interrupt (ADI) request is enabled
(Initial value)
Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1
during A/D conversion.
The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external
trigger input pin (ADTRG).
Bit 5
ADST
Description
0
A/D conversion stopped
1
Single mode: A/D conversion is started. Cleared to 0 automatically when conversion
on the specified channel ends
Scan mode:
(Initial value)
A/D conversion is started. Conversion continues sequentially on the
selected channels until ADST is cleared to 0 by software, a reset, or a
transition to standby mode or module stop mode
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating
mode. See section 20.4, Operation, for single mode and scan mode operation. Only set the SCAN
bit while conversion is stopped.
Rev. 4.00 Sep 27, 2006 page 618 of 1130
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Section 20 A/D Converter
Bit 4
SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time
while ADST = 0.
Bit 3
CKS
Description
0
Conversion time = 266 states (max.)
1
Conversion time = 134 states (max.)
(Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select
the analog input channel(s).
One analog input channel can be switched to digital input.
Only set the input channel while conversion is stopped.
Group
Selection
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0
AN0
1
AN1
1
1
0
1
(Initial value)
AN0, AN1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6 or CIN0 to CIN7
AN4, AN5,
AN6 or CIN0 to CIN7
1
AN7 or CIN8 to CIN15
AN4, AN5,
AN6 or CIN0 to CIN7
AN7 or CIN8 to CIN15
Rev. 4.00 Sep 27, 2006 page 619 of 1130
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Section 20 A/D Converter
20.2.3
A/D Control Register (ADCR)
7
6
5
4
3
2
1
0
TRGS1
TRGS0
—
—
—
—
—
—
Bit
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/W
R/W
—
—
—
—
—
—
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or
disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0
while conversion is stopped.
Bit 7
Bit 6
TRGS1
TRGS0
Description
0
0
Start of A/D conversion by external trigger is disabled
1
Start of A/D conversion by external trigger is disabled
0
Start of A/D conversion by external trigger (8-bit timer) is enabled
1
Start of A/D conversion by external trigger pin is enabled
1
(Initial value)
Bits 5 to 0—Reserved: Should always be written with 1.
Note: Some of these bits are readable/writable in products other than the HD64F2148,
HD64F2147N, HD64F2144, HD64F2142R and HD6432142, however, when writing, be
sure to write 1 here for software compatibility.
Rev. 4.00 Sep 27, 2006 page 620 of 1130
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Section 20 A/D Converter
20.2.4
Keyboard Comparator Control Register (KBCOMP)
Bit
7
6
5
4
3
2
1
0
IrE
IrCKS2
IrCKS1
IrCKS0
KBADE
KBCH2
KBCH1
KBCH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
KBCOMP is an 8-bit readable/writable register that controls the SCI2 IrDA function and selects
the CIN input channels for A/D conversion.
KBCOMP is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—IrDA Control: See the description in section 15.2.11, Keyboard Comparator Control
Register (KBCOMP).
Bit 3—Keyboard A/D Enable (KBADE): Selects either analog input pins (AN6, AN7) or digital
input pins (CIN0 to CIN7, CIN8 to CIN15) for A/D converter channel 6 and channel 7 input.
Bits 2 to 0—Keyboard A/D Channel Select 2 to 0 (KBCH2 to KBCH0): These bits select the
channels for A/D conversion from among the digital input pins. Only set the input channel while
A/D conversion is stopped.
Bit 3
Bit 2
Bit 1
Bit 0
KBADE
KBCH2
KBCH1
KBCH0
A/D Converter
Channel 6 Input
A/D Converter
Channel 7 Input
0
—
—
—
AN6
AN7
1
0
0
0
CIN0
CIN8
1
CIN1
CIN9
0
CIN2
CIN10
1
CIN3
CIN11
0
CIN4
CIN12
1
CIN5
CIN13
0
CIN6
CIN14
1
CIN7
CIN15
1
1
0
1
Rev. 4.00 Sep 27, 2006 page 621 of 1130
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Section 20 A/D Converter
20.2.5
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 25.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 1—Module Stop (MSTP9): Specifies the A/D converter module stop mode.
MSTPCRH
Bit 1
MSTP9
Description
0
A/D converter module stop mode is cleared
1
A/D converter module stop mode is set
Rev. 4.00 Sep 27, 2006 page 622 of 1130
REJ09B0327-0400
(Initial value)
Section 20 A/D Converter
20.3
Interface to Bus Master
ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR, always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 20.2 shows the data flow for ADDR access.
Upper byte read
Bus master
(H'AA)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower byte read
Bus master
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 20.2 ADDR Access Operation (Reading H'AA40)
Rev. 4.00 Sep 27, 2006 page 623 of 1130
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Section 20 A/D Converter
20.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
20.4.1
Single Mode (SCAN = 0)
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D
conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends.
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an
ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure
20.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the
A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 to the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
Rev. 4.00 Sep 27, 2006 page 624 of 1130
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Section 20 A/D Converter
Set*
ADIE
ADST
A/D
conversion
starts
Set*
Set*
Clear*
Clear*
ADF
State of channel 0 (AN0)
Idle
State of channel 1 (AN1)
Idle
State of channel 2 (AN2)
Idle
State of channel 3 (AN3)
Idle
A/D conversion 1
Idle
A/D conversion 2
Idle
ADDRA
ADDRB
Read conversion result
A/D conversion result 1
Read conversion result
A/D conversion result 2
ADDRC
ADDRD
Note: * Vertical arrows ( ) indicate instructions executed by software.
Figure 20.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Rev. 4.00 Sep 27, 2006 page 625 of 1130
REJ09B0327-0400
Section 20 A/D Converter
20.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels
are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR
registers corresponding to the channels.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 20.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1)
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set
to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this
time, an ADI interrupt is requested after A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Rev. 4.00 Sep 27, 2006 page 626 of 1130
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Section 20 A/D Converter
Continuous A/D conversion execution
Clear*1
Set*1
ADST
Clear*1
ADF
A/D conversion time
State of channel 0 (AN0)
State of channel 1 (AN1)
State of channel 2 (AN2)
Idle
Idle
A/D conversion 1
Idle
Idle
A/D conversion 2
Idle
Idle
A/D conversion 4
A/D conversion 5 *2
Idle
A/D conversion 3
State of channel 3 (AN3)
Idle
Idle
Transfer
ADDRA
A/D conversion result 4
A/D conversion result 1
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
2. Data currently being converted is ignored.
Figure 20.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Rev. 4.00 Sep 27, 2006 page 627 of 1130
REJ09B0327-0400
Section 20 A/D Converter
20.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D
conversion timing. Table 20.4 indicates the A/D conversion time.
As indicated in figure 20.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 20.4.
In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
Legend:
(1)
: ADCSR write cycle
(2)
: ADCSR address
: A/D conversion start delay time
tD
tSPL : Input sampling time
tCONV : A/D conversion time
Figure 20.5 A/D Conversion Timing
Rev. 4.00 Sep 27, 2006 page 628 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Table 20.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Item
Symbol
Min
Typ
Max
Min
Typ
Max
A/D conversion start delay
tD
10
—
17
6
—
9
Input sampling time
tSPL
—
63
—
—
31
—
A/D conversion time
tCONV
259
—
266
131
—
134
Note: Values in the table are the number of states.
20.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit is set to 1 by software. Figure 20.6 shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 20.6 External Trigger Input Timing
20.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
Rev. 4.00 Sep 27, 2006 page 629 of 1130
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Section 20 A/D Converter
20.6
Usage Notes
The following points should be noted when using the A/D converter.
Setting Range of Analog Power Supply and Other Pins
1. Analog input voltage range
The voltage applied to the ANn analog input pins during A/D conversion should be in the
range AVSS ≤ ANn ≤ AVref (n = 0 to 7).
2. Digital input voltage range
The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVref
and VSS ≤ CINn ≤ VCC (n = 0 to 15).
3. Relation between AVCC, AVSS and VCC, VSS
As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is
not used, the AVCC and AVSS pins must on no account be left open.
4. Setting Range of AVref Pin:
The reference voltage supplied via the AVref pin should be in the range AVref ≤ AVCC.
If conditions 1 to 4 above are not met, the reliability of the device may be adversely affected.
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog
reference power supply (AVref), and analog power supply (AVCC) by the analog ground (AVSS).
Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)
on the board.
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7) or analog reference power supply pin (AVref) should
be connected between AVCC and AVSS as shown in figure 20.7.
Rev. 4.00 Sep 27, 2006 page 630 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0
to AN7 must be connected to AVSS.
If a filter capacitor is connected as shown in figure 20.7, the input currents at the analog input pins
(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required
when deciding the circuit constants.
AVCC
AVref
100 Ω
Rin*2
*1
AN0 to AN7
*1
0.1 µF
AVSS
Notes:
Figures are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 20.7 Example of Analog Input Protection Circuit
Table 20.5 Analog Pin Ratings
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
—
10*
kΩ
Permissible signal source impedance
Note:
*
When VCC = 4.0 to 5.5 V and φ ≤ 12 MHz.
Rev. 4.00 Sep 27, 2006 page 631 of 1130
REJ09B0327-0400
Section 20 A/D Converter
10 kΩ
AN0 to AN7
To A/D converter
20 pF
Note: Numeric values are reference values.
Figure 20.8 Analog Input Pin Equivalent Circuit
A/D Conversion Precision Definitions
The A/D conversion precision in this LSI is defined as follows.
• Resolution
The number of A/D converter digital output codes
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 20.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'111111111 (H'3FF) (see
figure 20.11).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 20.9).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.
• Absolute precision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Rev. 4.00 Sep 27, 2006 page 632 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Digital output
Ideal A/D conversion
characteristic
H'3FF
H'3FE
H'3FD
H'004
H'003
H'002
Quantization error
H'001
H'000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 20.9 A/D Conversion Precision Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog
input voltage
Figure 20.10 A/D Conversion Precision Definitions (2)
Rev. 4.00 Sep 27, 2006 page 633 of 1130
REJ09B0327-0400
Section 20 A/D Converter
Permissible Signal Source Impedance
Analog input in this LSI is designed so that conversion precision is guaranteed for an input signal
for which the signal source impedance is 10 kΩ (AVcc = 4.0 to 5.5 V, when φ ≤ 12 MHz) or less.
This specification is provided to enable the A/D converter’s sample-and-hold circuit input
capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ
(AVcc = 4.0 to 5.5 V, when φ ≤ 12 MHz), charging may be insufficient and it may not be possible
to guarantee the A/D conversion precision.
However, if a large capacitance is provided externally, the input load will essentially comprise
only the internal input resistance of 10 kΩ, and the signal source impedance is ignored.
But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog
signal with a large differential coefficient (e.g., 5 mV/µsec or greater).
When converting a high-speed analog signal, a low-impedance buffer should be inserted.
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVSS.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
This LSI
A/D converter
equivalent circuit
Sensor output
impedance,
up to 10 kΩ
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Note: Values are reference values.
Figure 20.11 Example of Analog Input Circuit
Rev. 4.00 Sep 27, 2006 page 634 of 1130
REJ09B0327-0400
20 pF
Section 21 RAM
Section 21 RAM
21.1
Overview
The H8S/2148, H8S/2144, and H8S/2143 have 4 kbytes of on-chip high-speed static RAM, and
the H8S/2147, H8S/2147N, and H8S/2142 have 2 kbytes. The on-chip RAM is connected to the
CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This
makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
21.1.1
Block Diagram
Figure 21.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFE080
H'FFE081
H'FFE082
H'FFE083
H'FFE084
H'FFE085
H'FFEFFE
H'FFEFFF
H'FFFF00
H'FFFF01
H'FFFF7E
H'FFFF7F
Figure 21.1 Block Diagram of RAM (H8S/2148, H8S/2144, H8S/2143)
Rev. 4.00 Sep 27, 2006 page 635 of 1130
REJ09B0327-0400
Section 21 RAM
21.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration.
Table 21.1 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address*
System control register
SYSCR
R/W
H'09
H'FFC4
Note:
21.2
*
Lower 16 bits of the address.
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Rev. 4.00 Sep 27, 2006 page 636 of 1130
REJ09B0327-0400
(Initial value)
Section 21 RAM
21.3
Operation
21.3.1
Expanded Mode (Modes 1, 2, 3 (EXPE = 1))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, accesses to addresses H'(FF)E080 to
H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to the off-chip address space.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
21.3.2
Single-Chip Mode (Modes 2 and 3 (EXPE = 0))
When the RAME bit is set to 1, accesses to H8S/2148, H8S/2144, and H8S/2143 addresses
H'(FF)E080 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, and H8S/2147, H8S/2147N, and
H8S/2142 addresses H'(FF)E880 to H'(FF)EFFF and H'(FF)FF00 to H'(FF)FF7F, are directed to
the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not accessed.
Undefined values are read from these bits, and writing is invalid.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
Rev. 4.00 Sep 27, 2006 page 637 of 1130
REJ09B0327-0400
Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 638 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Section 22 ROM
(Mask ROM Version, H8S/2148 F-ZTAT,
H8S/2147N F-ZTAT, H8S/2144 F-ZTAT,
and H8S/2142 F-ZTAT)
22.1
Overview
The H8S/2148 and H8S/2144 have 128 kbytes of on-chip ROM (flash memory or mask ROM),
the H8S/2143 has 96 kbytes, the H8S/2147, H8S/2147N, and H8S/2142 have 64 kbytes. The
ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in
one state, enabling faster instruction fetches and higher processing speed.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM.
The flash memory versions of the H8S/2148, H8S/2147N, H8S/2144, and H8S/2142 can be erased
and programmed on-board as well as with a general-purpose PROM programmer.
22.1.1
Block Diagram
Figure 22.1 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000001
H'000002
H'000003
H'01FFFE
H'01FFFF
Figure 22.1 ROM Block Diagram (H8S/2148, H8S/2144)
Rev. 4.00 Sep 27, 2006 page 639 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.1.2
Register Configuration
This group on-chip ROM is controlled by the operating mode and register MDCR. The register
configuration is shown in table 22.1.
Table 22.1 ROM Register
Register Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R/W
Undefined
Depends on the operating mode
H'FFC5
Note:
*
Lower 16 bits of the address.
22.2
Register Descriptions
22.2.1
Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
EXPE
—
—
—
—
—
MDS1
MDS0
Initial value
—*
0
0
0
0
0
—*
—*
Read/Write
R/W*
—
—
—
—
—
R
R
Note: * Determined by the MD1 and MD0 pins.
MDCR is an 8-bit register used to set this group operating mode and monitor the current operating
mode.
The EXPE bit is initialized in accordance with the mode pin states by a reset and in hardware
standby mode.
Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1
and cannot be modified. In modes 2 and 3, EXPE has an initial value of 0 and can be read or
written.
Bit 7
EXPE
Description
0
Single-chip mode selected
1
Expanded mode selected
Rev. 4.00 Sep 27, 2006 page 640 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the
input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0
correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits.
22.3
Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data is
accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the
lower 8 bits. Word data must start at an even address.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM, as shown in table 22.2.
In normal mode, the maximum amount of ROM that can be used is 56 kbytes.
Table 22.2 Operating Modes and ROM
Operating Mode
MCU
Operating
Mode
CPU
Operating
Mode
Mode 1
Mode 2
Mode 3
Note:
*
Mode Pins
MDCR
Description
MD1
MD0
EXPE
On-Chip ROM
Normal
Expanded mode with
on-chip ROM disabled
0
1
1
Disabled
Advanced
Single-chip mode
1
0
0
Enabled*
Advanced
Expanded mode with
on-chip ROM enabled
Normal
Single-chip mode
Normal
Expanded mode with
on-chip ROM enabled
1
1
0
1
Enabled
(max. 56 kbytes)
128 kbytes in the H8S/2148 and H8S/2144, 96 kbytes in the H8S/2143, 64 kbytes in the
H8S/2147, H8S/2147N, and H8S/2142.
Rev. 4.00 Sep 27, 2006 page 641 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.4
Overview of Flash Memory
22.4.1
Features
The features of the flash memory are summarized below.
• Four flash memory operating modes
 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in
single-block units). When erasing multiple blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28kbyte, and 32-kbyte blocks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match
the transfer bit rate of the host.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Rev. 4.00 Sep 27, 2006 page 642 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.4.2
Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1 *
FLMCR2 *
EBR1
EBR2
Bus interface/controller
Operating
mode
Mode pins
*
*
Flash memory
(128 kbytes/64 kbytes)
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
Note: * These registers are used only in the flash memory version. In the mask ROM version,
a read at any of these addresses will return an undefined value, and writes are invalid.
Figure 22.2 Block Diagram of Flash Memory
Rev. 4.00 Sep 27, 2006 page 643 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.4.3
Flash Memory Operating Modes
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of
the operating modes shown in figure 22.3. In user mode, flash memory can be read but not
programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
Reset state
MD1 = 1
RES = 0
User mode with
on-chip ROM
enabled
SWE = 1
RES = 0
*1
SWE = 0
RES = 0
*2
RES = 0
Programmer
mode
User
program mode
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1
2. MD0 = MD1 = 0, P92 = P91 = P90 = 1
Figure 22.3 Flash Memory Mode Transitions
Rev. 4.00 Sep 27, 2006 page 644 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
On-Board Programming Modes
• Boot mode
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
2. SCI communication check
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started, an SCI communication check is carried
out, and the boot program required for flash
memory erasing is automatically transferred to
the RAM boot program area.
Host
Host
Programming control
program
Programming control
program
New application
program
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
RAM
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Host
Host
Programming control
program
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
Flash memory
RAM
Programming
control program
Boot program area
Flash memory
erase
SCI
Boot program
New application
program
Program execution state
Figure 22.4 Boot Mode
Rev. 4.00 Sep 27, 2006 page 645 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
• User program mode
1. Initial state
(1) The program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand.
(2) The programming/erase control program
should be prepared in the host or in the flash
memory.
2. Programming/erase control program transfer
Executes the transfer program in the flash
memory, and transfers the programming/erase
control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
Transfer program
RAM
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
Transfer program
SCI
Boot program
RAM
Flash memory
Transfer program
Programming/
erase control program
Flash memory
erase
Programming/
erase control program
New application
program
Program execution state
Figure 22.5 User Program Mode (Example)
Rev. 4.00 Sep 27, 2006 page 646 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Differences between Boot Mode and User Program Mode
Entire memory erase
Boot Mode
User Program Mode
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify
Program/program-verify
Erase/erase-verify
Note:
*
To be provided by the user, in accordance with the recommended algorithm.
Block Configuration
The flash memory is divided into two 32-kbyte blocks (128-kbyte version only), two 8-kbyte
blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Address H'00000
1 kbyte
1 kbyte
1 kbyte
1 kbyte
Address H'00000
1 kbyte
1 kbyte
1 kbyte
1 kbyte
28 kbytes
128 kbytes
64 kbytes
16 kbytes
28 kbytes
16 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
Address H'0FFFF
32 kbytes
32 kbytes
Address H'1FFFF
(a) 128-kbyte version
(b) 64-kbyte version
Figure 22.6 Flash Memory Block Configuration
Rev. 4.00 Sep 27, 2006 page 647 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.4.4
Pin Configuration
The flash memory is controlled by means of the pins shown in table 22.3.
Table 22.3 Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Mode 1
MD1
Input
Sets MCU operating mode
Mode 0
MD0
Input
Sets MCU operating mode
Port 92
P92
Input
Sets MCU operating mode when MD1 = MD0 = 0
Port 91
P91
Input
Sets MCU operating mode when MD1 = MD0 = 0
Port 90
P90
Input
Sets MCU operating mode when MD1 = MD0 = 0
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
22.4.5
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 22.4.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 22.4 Flash Memory Registers
Initial Value
Address*
R/W*
3
R/W*
3
H'80
4
H'00*
H'FF80*
2
H'FF81*
Erase block register 2
EBR1*
5
EBR2*
R/W*
3
R/W*
H'00*
4
H'00*
H'FF82*
2
H'FF83*
Serial/timer control register
STCR
R/W
H'00
H'FFC3
Register Name
Abbreviation R/W
Flash memory control register 1
FLMCR1*
5
FLMCR2*
Flash memory control register 2
Erase block register 1
5
5
3
4
1
2
2
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the serial/timer control register (STCR).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
4. The SWE bit in FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states. These registers are used only in the
flash memory version. In the mask ROM version, a read at any of these addresses will
return an undefined value, and writes are invalid.
Rev. 4.00 Sep 27, 2006 page 648 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.5
Register Descriptions
22.5.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
FWE
SWE
—
—
EV
PV
E
P
Initial value
1
0
0
0
0
0
0
0
Read/Write
R
R/W
—
—
R/W
R/W
R/W
R/W
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to
1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by
setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is
initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive
mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return
H'00, and writes are invalid.
Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only
when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable (FWE): Controls programming and erasing of the on-chip flash
memory. This bit cannot be modified and is always read as 1.
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be
cleared at the same time as these bits.
Bit 6
SWE
Description
0
Writes disabled
1
Writes enabled
(Initial value)
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3
EV
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
When SWE = 1
Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the
SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2
PV
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
(Initial value)
[Setting condition]
When SWE = 1
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,
PV, or P bit at the same time.
Bit 1
E
Description
0
Erase mode cleared
1
Transition to erase mode
[Setting condition]
When SWE = 1, and ESU = 1
Rev. 4.00 Sep 27, 2006 page 650 of 1130
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(Initial value)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0
P
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
When SWE = 1, and PSU = 1
22.5.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
ESU
PSU
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
R/W
R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.
When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
Rev. 4.00 Sep 27, 2006 page 651 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Bit 7
FLER
Description
0
Flash memory is operating normally
(Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
1
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 22.8.3, Error Protection
Bits 6 to 2—Reserved: Always write 0 when writing to these bits.
Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
When SWE = 1
Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU
Description
0
Program setup cleared
1
Program setup
[Setting condition]
When SWE = 1
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(Initial value)
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.5.3
Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit
7
6
5
4
3
2
1
0
EBR1
—
—
—
—
—
—
EB9/—* EB8/—*
Initial value
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
0
0
1 2
1 2
*
*
R/W
R/W* *
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
1
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2
2
2
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they must not be set to 1.
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and
2 in EBR1 (128 kB versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and
EBR2 are each initialized to H'00 by a reset, in hardware standby mode, software standby mode,
subactive mode, subsleep mode, and watch mode, and the SWE bit in FLMCR1 is not set. When a
bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are eraseprotected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When on-chip
flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 22.5.
Rev. 4.00 Sep 27, 2006 page 653 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.5 Flash Memory Erase Blocks
Block (Size)
128-kbyte Versions
64-kbyte Versions
Address
EB0 (1 kbyte)
EB0 (1 kbyte)
H'(00)0000 to H'(00)03FF
EB1 (1 kbyte)
EB1 (1 kbyte)
H'(00)0400 to H'(00)07FF
EB2 (1 kbyte)
EB2 (1 kbyte)
H'(00)0800 to H'(00)0BFF
EB3 (1 kbyte)
EB3 (1 kbytes)
H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes)
EB4 (28 kbytes)
H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes)
EB5 (16 kbytes)
H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes)
EB6 (8 kbytes)
H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes)
EB7 (8 kbytes)
H'00E000 to H'00FFFF
EB8 (32 kbytes)
—
H'010000 to H'017FFF
EB9 (32 kbytes)
—
H'018000 to H'01FFFF
22.5.4
Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS
IICX1
IICX0
IICE
FLSHE
—
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory control (in F-ZTAT
versions), and also selects the TCNT input clock. For details on functions not related to on-chip
flash memory, see section 3.2.4, Serial Timer Control Register (STCR), and descriptions of
individual modules. If a module controlled by STCR is not used, do not write 1 to the
corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
2
Bits 7 to 4—I C Control (IICS, IICX1, IICX0, IICE): When the on-chip IIC option is included,
2
2
these bits control the operation of the I C bus interface. For details, see section 16, I C Bus
Interface.
Rev. 4.00 Sep 27, 2006 page 654 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE
Description
0
Flash memory control registers deselected
1
Flash memory control registers selected
(Initial value)
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer
operation. See section 12, 8-Bit Timers, for details.
22.6
On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
22.6. For a diagram of the transitions to the various flash memory modes, see figure 22.3.
Only advanced mode setting is possible for boot mode.
In the case of user program mode, established in advanced mode or normal mode, depending on
the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash
memory is possible.
Table 22.6 Setting On-Board Programming Modes
Mode
Mode Name
CPU Operating Mode
MD1
MD0
P92
P91
P90
1*
1*
Boot mode
Advanced mode
0
0
1*
User program mode
Advanced mode
1
0
—
—
—
1
—
—
—
Normal mode
Note:
*
Can be used as I/O ports after boot mode is initiated.
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.6.1
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after this group MCU’s pins have been set to boot mode, the boot
program built into the MCU is started and the programming control program prepared in the host
is serially transmitted to the MCU via the SCI. In the MCU, the programming control program
received via the SCI is written into the programming control program area in on-chip RAM. After
the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory
programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 22.7, and the boot program mode
execution procedure in figure 22.8.
This group chip
Flash memory
Host
Write data reception
Verify data transmission
RxD1
SCI1
TxD1
Figure 22.7 System Configuration in Boot Mode
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On-chip RAM
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Start
Set pins to boot program mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
MCU measures low period
of H'00 data transmitted by host
MCU calculates bit rate and
sets value in bit rate register
After bit rate adjustment, transmits
one H'00 data byte to host to
indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
MCU transfers part of boot
program to RAM
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
MCU transmits one H'AA data
byte to host
Host transmits number
of user program bytes (N),
upper byte followed by lower byte
MCU transmits received
number of bytes to host as verify
data (echo-back)
n=1
Host transmits user program
sequentially in byte units
MCU transmits received user
program to host as verify data
(echo-back)
n+1→n
Transfer received programming
control program to on-chip RAM
No
n = N?
Yes
End of transmission
Transmit one H'AA data byte to host,
and execute programming control
program transferred to on-chip RAM
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Figure 22.8 Boot Mode Execution Procedure
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Automatic SCI Bit Rate Adjustment
Start
bit
D0
D1
D2
D3
D4
D5
D6
Low period (9 bits) measured (H'00 data)
D7
Stop
bit
High period
(1 or more bits)
Figure 22.9 RxD1 Input Signal when Using Automatic SCI Bit Rate Adjustment
When boot mode is initiated, this group MCU measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the MCU’s system clock frequency, there will
be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation,
the host’s transfer bit rate should be set to (2400, 4800, or 9600) bps.
Table 22.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 22.7 System Clock Frequencies for which Automatic Adjustment of This Group Bit
Rate Is Possible
Host Bit Rate
System Clock Frequency for which Automatic Adjustment
of This Group Bit Rate Is Possible
9600 bps
8 MHz to 20 MHz
4800 bps
4 MHz to 20 MHz
2400 bps
2 MHz to 18 MHz
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
On-Chip RAM Area Divisions in Boot Mode
In boot mode, the 128-byte area from H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot
program, as shown in figure 22.10. The area to which the programming control program is
transferred is H'(FF)E080 to H'(FF)EFFF (3968 bytes) in the 128-kbyte versions, or H'(FF)E880 to
H'(FF)EFFF (1920 bytes) in the 64-kbyte versions. The boot program area can be used when the
programming control program transferred into RAM enters the execution state. A stack area
should be set up as required.
H'(FF)E080
Programming
control program
area
(3,968 bytes)
H'(FF)EFFF
H'(FF)FF00
H'(FF)FF7F
H'(FF)E880
Programming
control program
area
(1,920 bytes)
H'(FF)EFFF
Boot program
area*
(128 bytes)
(a) 128-kbyte versions
H'(FF)FF00
H'(FF)FF7F
Boot program
area*
(128 bytes)
(b) 64-kbyte versions
Note: * The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
Figure 22.10 RAM Areas in Boot Mode
Notes on Use of User Mode
• When the chip comes out of reset in boot mode, it measures the low period of the input at the
SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the RxD1 input.
• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'(FF)E080 (128-kbyte
versions) or H'(FF)E880 (64-kbyte versions)), the chip terminates transmit and receive
operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but
the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the
high-level output state (P84DDR = 1, P84DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
• Boot mode can be entered by making the pin settings shown in table 22.6 and executing a
reset-start.
1
When the chip detects the boot mode setting at reset release* , P92, P91, and P90 can be used
as I/O ports.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
1
the mode pins, and executing reset release* . Boot mode can also be cleared by a WDT
overflow reset.
The mode pin input levels must not be changed in boot mode.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output pins (AS, RD, WR)
2
will change according to the change in the microcomputer’s operating mode* .
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Notes: 1. Mode pin input must satisfy the mode programming setup time (tMDS = 4 states) with
respect to the reset release timing.
2. Ports with multiplexed address functions will output a low level as the address signal if
mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedance state. The bus control output signals will output a high level
if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedance state.
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.6.2
User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board supply of programming data, and storing a
program/erase control program in part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3).
In this mode, on-chip supporting modules other than flash memory operate as they normally
would in mode 2 and 3.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Figure 22.11 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Write the transfer program (and the program/
erase control program if necessary) beforehand
MD1, MD0 = 10, 11
Reset-start
Transfer program/erase control
program to RAM
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Branch to flash memory application
program
Note: The watchdog timer should be activated to prevent overprogramming or overerasing
due to program runaway, etc.
Figure 22.11 User Program Mode Execution Procedure
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.7
Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in
FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash
memory.
2. Perform programming in the erased state. Do not perform additional programming on
previously programmed addresses.
22.7.1
Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 21.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a
time.
For the wait times (x, y, z, α, β, γ, ε, η) after setting/clearing individual bits in flash memory
control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N), see
section 26.2.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the reprogram data area written consecutively to the write addresses.
The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0,
or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 32-byte data transfer must be performed even if
writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z + α + β) µs as the WDT overflow period. After this, preparation for
program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
Rev. 4.00 Sep 27, 2006 page 662 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a
program setting so that the time for one programming operation is within the range of (z) µs.
22.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later). The watchdog
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data
is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy
write before performing this read operation. Next, the originally written data is compared with the
verify data, and reprogram data is computed (see figure 22.12) and transferred to the reprogram
data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least (η)
µs, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again,
and repeat the program/program-verify sequence as before. However, ensure that the
program/program-verify sequence is not repeated more than (N) times on the same bits.
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Start
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Set SWE bit in FLMCR1
Wait (x) µs
*5
Store 32-byte program data in program
data area and reprogram data area
*4
n=1
m=0
Write 32-byte data in RAM reprogram data
area consecutively to flash memory
*1
n←n+1
Enable WDT
Set PSU bit in FLMCR2
Wait (y) µs
Set P bit in FLMCR1
Wait (z) µs
Clear P bit in FLMCR1
Wait (α) µs
*5
Start of programming
*5
End of programming
*5
Clear PSU bit in FLMCR2
Wait (β) µs
*5
Disable WDT
Set PV bit in FLMCR1
Wait (γ) µs
*5
Notes: 1. Data transfer is performed by byte transfer. The lower
8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer
must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. If a bit for which programming has been completed in the 32-byte
programming loop fails the following verify phase, additional
programming is performed for that bit.
4. An area for storing program data (32 bytes) and reprogram data
(32 bytes) must be provided in RAM. The contents of the latter
are rewritten as programming progresses.
5. See section 26.2.6, Flash Memory Characteristics, for the values
of x, y, z, α, β, γ, ε, η, and N.
H'FF dummy write to verify address
Wait (ε) µs
*5
Read verify data
*2
Program data =
verify data?
NG
Increment address
OK
Reprogram data computation
Transfer reprogram data to reprogram
data area
NG
m=1
Program
Data
0
Verify
Data
0
Reprogram
Data
1
0
1
0
Programming incomplete;
reprogram
1
0
1
—
1
1
1
Still in erased state;
no action
Comments
Reprogramming is not
performed if program data
and verify data match
*3
RAM
*4
Program data storage
area (32 bytes)
End of 32-byte
data verification?
OK
Clear PV bit in FLMCR1
Wait (η) µs
m = 0?
OK
Reprogram data storage
area (32 bytes)
*5
NG
n ≥ N?
*5
NG
OK
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
End of programming
Programming failure
Figure 22.12 Program/Program-Verify Flowchart
Rev. 4.00 Sep 27, 2006 page 664 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.7.3
Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 22.13.
The wait times (x, y, z, α, β, γ, ε, η) after setting/clearing individual bits in flash memory control
registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N), see section
26.2.6, Flash Memory Characteristics.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
erase block register 1 or 2 (EBR1 or EBR2) at least (x) µs after setting the SWE bit to 1 in flash
memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in
the event of program runaway, etc. Set a value greater than (y + z + α + β) ms as the WDT
overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the
ESU bit in FLMCR2, and after the elapse of (y) µs or more, the operating mode is switched to
erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash
memory erase time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
to 0) is not necessary before starting the erase procedure.
22.7.4
Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least (α) µs later), the watchdog timer is cleared after the elapse
of (β) µs or more, and the operating mode is switched to erase-verify mode by setting the EV bit in
FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of (γ) µs or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has not been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least (η) µs. If erasure has been completed on all the erase blocks,
clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or
EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the
same way.
Rev. 4.00 Sep 27, 2006 page 665 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Start
*1
Set SWE bit in FLMCR1
Wait (x) µs
*5
n=1
Set EBR1, EBR2
*3
Enable WDT
Set ESU bit in FLMCR2
Wait (y) µs
*5
Start of erase
Set E bit in FLMCR1
Wait (z) ms
*5
Clear E bit in FLMCR1
n←n+1
Halt erase
Wait (α) µs
*5
Clear ESU bit in FLMCR2
Wait (β) µs
*5
Disable WDT
Set EV bit in FLMCR1
Wait (γ) µs
*5
Set block start address to verify address
H'FF dummy write to verify address
Increment
address
Wait (ε) µs
*5
Read verify data
*2
Verify data = all 1?
NG
OK
NG
Last address of block?
OK
Clear EV bit in FLMCR1
Wait (η) µs
NG
Notes: 1.
2.
3.
4.
5.
*4
End of
erasing of all erase
blocks?
OK
Clear EV bit in FLMCR1
*5
Wait (η) µs
*5
*5
n ≥ N?
Clear SWE bit in FLMCR1
OK
Clear SWE bit in FLMCR1
End of erasing
Erase failure
NG
Preprogramming (setting erase block data to all 0) is not necessary.
Verify data is read in 16-bit (W) units.
Set only one bit in EBR1or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
See section 26.2.6, Flash Memory Characteristics, for the values of x, y, z, α, β, γ, ε, η, and N.
Figure 22.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
Rev. 4.00 Sep 27, 2006 page 666 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.8
Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
22.8.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1
and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 22.8.)
Table 22.8 Hardware Protection
Functions
Item
Description
Program
Erase
Reset/standby
protection
•
In a reset (including a WDT overflow reset),
software standby mode, subactive mode,
subsleep mode, and watch mode, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
Yes
Yes
•
In a reset via the RES pin, the reset state is
not entered unless the RES pin is held low
until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the
RES pin low for the RES pulse width specified
in the AC Characteristics section.
22.8.2
Software Protection
Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block
registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 22.9.)
Rev. 4.00 Sep 27, 2006 page 667 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.9 Software Protection
Functions
Item
Description
Program
Erase
SWE bit protection
•
Yes
Yes
—
Yes
Clearing the SWE bit to 0 in FLMCR1 sets the
program/erase-protected state for all blocks.
(Execute in on-chip RAM or external memory.)
Block specification
protection
22.8.3
•
Erase protection can be set for individual blocks
by settings in erase block registers 1 and 2
(EBR1, EBR2).
•
Setting EBR1 and EBR2 to H'00 places all blocks
in the erase-protected state.
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (transition to software standby, sleep, subactive, subsleep, or watch
mode) is executed during programming/erasing
• When the bus is released during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 22.14 shows the flash memory state transition diagram.
Rev. 4.00 Sep 27, 2006 page 668 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Program mode
Erase mode
Reset or hardware standby
(hardware protection)
RES = 0 or STBY = 0
RD VF PR ER FLER = 0
RD VF PR ER FLER = 0
Error occurrence*2
RES = 0 or
STBY = 0
RES = 0 or
STBY = 0
Error
occurrence*1
Error protection mode
RD VF*4 PR ER FLER = 1
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
Software standby,
sleep, subsleep, and
watch mode
Error protection
mode (software standby,
sleep, subsleep, and watch )
Software standby,
sleep, subsleep, and
watch mode release
RD:
VF:
PR:
ER:
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
RD VF PR ER FLER = 1
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state*3
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
executed for a transition to subactive mode
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4. VF in subactive mode
Figure 22.14 Flash Memory State Transitions
Rev. 4.00 Sep 27, 2006 page 669 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.9
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input is disabled when flash memory is being programmed or erased
1
(when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* ,
to give priority to the program or erase operation. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. In the interrupt exception handling sequence during programming or erasing, the vector would
2
not be read correctly* , possibly resulting in MCU runaway.
3. If interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupt, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests, including NMI input, must
therefore be disabled inside and outside the MCU when programming or erasing flash memory.
Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming
control program has completed programming.
2. The vector may not be read correctly in this case for the following two reasons:
•
If flash memory is read while being programmed or erased (while the P or E bit is
set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
•
If the interrupt entry in the vector table has not been programmed yet, interrupt
exception handling will not be executed correctly.
Rev. 4.00 Sep 27, 2006 page 670 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.10
Flash Memory Programmer Mode
22.10.1 Programmer Mode Setting
Programs and data can be written and erased in programmer mode as well as in the on-board
programming modes. In programmer mode, the on-chip ROM can be freely programmed using a
PROM programmer that supports Renesas Technology microcomputer device types with 1281 3
2 3
kbyte* * or 64-kbyte* * on-chip flash memory. Flash memory read mode, auto-program mode,
auto-erase mode, and status read mode are supported with these device types. In auto-program
mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read
mode, detailed internal signals are output after execution of an auto-program or auto-erase
operation.
Table 22.10 shows programmer mode pin settings.
Notes: 1. Applies to the H8S/2148 and H8S/2144.
2. Applies to the H8/2147N and H8S/2142.
3. Use products other than the A-mask version of the H8S/2148, H8S/2147N, H8/2144,
and H8S/2142 (in either 5-V or 3-V version) with the writing voltage for the PROM
programmer set to 5.0 V. Do not use the A-mask version with a 5.0-V PROM
programmer setting.
Table 22.10 Programmer Mode Pin Settings
Pin Names
Setting/External Circuit Connection
Mode pins: MD1, MD0
Low-level input to MD1, MD0
STBY pin
High-level input
(Hardware standby mode not set)
RES pin
Power-on reset circuit
XTAL and EXTAL pins
Oscillation circuit
Other setting pins: P97, P92, P91, P90, P67
Low-level input to P92, P67,
high-level input to P97, P91, P90
Rev. 4.00 Sep 27, 2006 page 671 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.10.2 Socket Adapters and Memory Map
In programmer mode, a socket adapter is mounted on the writer programmer to match the package
concerned. Socket adapters are available for each writer manufacturer supporting Renesas
Technology microcomputer device types with 128-kbyte or 64-kbyte on-chip flash memory.
Figure 22.15 shows the memory map in programmer mode. For pin names in programmer mode,
see section 1.3.2, Pin Functions in Each Operating Mode.
MCU mode
H8S/2148
H8S/2144
H'000000
Programmer
mode
H'00000
MCU mode
H8S/2147N
H8S/2142
Programmer
mode
H'00000
H'000000
On-chip
ROM area
On-chip
ROM area
H'01FFFF
H'00FFFF
H'0FFFF
Undefined value
output
H'1FFFF
H'1FFFF
Figure 22.15 Memory Map in Programmer mode
22.10.3 Programmer Mode Operation
Table 22.11 shows how the different operating modes are set when using programmer mode, and
table 22.12 lists the commands used in programmer mode. Details of each mode are given below.
• Memory Read Mode
Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-erasing.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the FO6 signal. In status read mode, error information is output if an
error occurs.
Rev. 4.00 Sep 27, 2006 page 672 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.11 Settings for Each Operating Mode in Programmer Mode
Pin Names
Mode
CE
OE
WE
FO0 to FO7
FA0 to FA17
Read
L
L
H
Data output
Ain
Output disable
L
H
H
Hi-Z
X
Command write
1
Chip disable*
L
H
L
Data input
Ain*
H
X
X
Hi-Z
X
2
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
Table 22.12 Programmer Mode Commands
1st Cycle
2nd Cycle
Command Name
Number
of Cycles
Mode
Address Data
Mode
Address Data
Memory read mode
1+n
Write
X
H'00
Read
RA
Dout
Auto-program mode
129
Write
X
H'40
Write
WA
Din
Auto-erase mode
2
Write
X
H'20
Write
X
H'20
Status read mode
2
Write
X
H'71
Write
X
H'71
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
2. In memory read mode, the number of cycles depends on the number of address write
cycles (n).
22.10.4 Memory Read Mode
• After the end of an auto-program, auto-erase, or status read operation, the command wait state
is entered. To read memory contents, a transition must be made to memory read mode by
means of a command write before the read is executed.
• Command writes can be performed in memory read mode, just as in the command wait state.
• Once memory read mode has been entered, consecutive reads can be performed.
• After power-on, memory read mode is entered.
Rev. 4.00 Sep 27, 2006 page 673 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.13 AC Characteristics in Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
—
µs
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Command write
Memory read mode
FA17 to FA0
Address stable
CE
OE
WE
FO7 to FO0
twep
tceh
tnxtc
tces
tf
tr
Data
Data
tdh
tds
Note: Data is latched on the rising edge of WE.
Figure 22.16 Memory Read Mode Timing Waveforms after Command Write
Rev. 4.00 Sep 27, 2006 page 674 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.14 AC Characteristics when Entering Another Mode from Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
—
µs
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Memory read mode
FA17 to FA0
Other mode command write
Address stable
CE
twep
tnxtc
OE
tces
WE
FO7 to FO0
tceh
tf
Data
tr
H'XX
tdh
Note: Do not enable WE and OE at the same time.
tds
Figure 22.17 Timing Waveforms when Entering Another Mode from Memory Read Mode
Rev. 4.00 Sep 27, 2006 page 675 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.15 AC Characteristics in Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Access time
tacc
—
20
µs
CE output delay time
tce
—
150
ns
OE output delay time
toe
—
150
ns
Output disable delay time
tdf
—
100
ns
Data output hold time
toh
5
—
ns
FA17 to FA0
Address stable
Address stable
CE
VIL
OE
VIL
tacc
WE
VIH
tacc
toh
toh
Data
FO7 to FO0
Data
Figure 22.18 Timing Waveforms for CE/OE
CE OE Enable State Read
FA17 to FA0
Address stable
Address stable
tacc
CE
tce
tce
OE
toe
toe
WE
FO7 to FO0
tdf
tdf
tacc
Data
Data
toh
Figure 22.19 Timing Waveforms for CE/OE
CE OE Clocked Read
Rev. 4.00 Sep 27, 2006 page 676 of 1130
REJ09B0327-0400
toh
VIH
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.10.5 Auto-Program Mode
AC Characteristics
Table 22.16 AC Characteristics in Auto-Program Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
—
µs
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
twsts
1
—
ms
Status polling access time
tspa
—
150
ns
Address setup time
tas
0
—
ns
Address hold time
tah
60
—
ns
Memory write time
twrite
1
3000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Rev. 4.00 Sep 27, 2006 page 677 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Address
stable
FA17 to FA0
tceh
CE
tas
tah
tnxtc
OE
tnxtc
twep
WE
FO7
Data transfer
1 byte to 128 bytes
tces
twsts
tspa
twrite (1 to 3000 ms)
Programming operation
end identification signal
tr
tf
tds
tdh
Programming normal
end identification signal
FO6
Programming wait
FO7 to FO0
H'40
Data
Data
FO0 to FO5 = 0
Figure 22.20 Auto-Program Mode Timing Waveforms
Notes on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers.
• A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this
case, H'FF data must be written to the extra addresses.
• The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective
address is input, processing will switch to a memory write operation but a write error will be
flagged.
• Memory address transfer is performed in the second cycle (figure 22.20). Do not perform
transfer after the second cycle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
• Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode
can also be used for this purpose (FO7 status polling uses the auto-program operation end
identification pin).
• The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling CE and OE.
Rev. 4.00 Sep 27, 2006 page 678 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.10.6 Auto-Erase Mode
AC Characteristics
Table 22.17 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
—
µs
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
tests
1
—
ms
Status polling access time
tspa
—
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
terase (100 to 40000 ms)
tnxtc
FA17 to FA0
tceh
tces
CE
tspa
OE
WE
tnxtc
twep
tf
tests
tr
tds
FO7
Erase end identification
signal
tdh
Erase normal end
confirmation signal
FO6
FO7 to FO0
CLin
DLin
H'20
H'20
FO0 to FO5 = 0
Figure 22.21 Auto-Erase Mode Timing Waveforms
Rev. 4.00 Sep 27, 2006 page 679 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Notes on Use of Erase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also
be used for this purpose (FO7 status polling uses the auto-erase operation end identification
pin).
• The status polling FO6 and FO7 pin information is retained until the next command write.
Until the next command write is performed, reading is possible by enabling CE and OE.
22.10.7 Status Read Mode
• Status read mode is used to identify what type of abnormal end has occurred. Use this mode
when an abnormal end occurs in auto-program mode or auto-erase mode.
• The return code is retained until a command write for other than status read mode is
performed.
Table 22.18 AC Characteristics in Status Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Command write cycle
tnxtc
20
—
µs
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
OE output delay time
toe
—
150
ns
Disable delay time
tdf
—
100
ns
CE output delay time
tce
—
150
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Rev. 4.00 Sep 27, 2006 page 680 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
FA17 to FA0
CE
tnxtc
tce
OE
WE
tnxtc
twep
tf
tf
tr
toe
tdf
tr
tds
tds
FO7 to FO0
tceh
tces
tceh
tces
tnxtc
twep
tdh
tdh
H'71
H'71
Data
Note: FO2 and FO3 are undefined.
Figure 22.22 Status Read Mode Timing Waveforms
Table 22.19 Status Read Mode Return Commands
Pin Name
FO7
FO6
Attribute
Normal
Command
end
error
identification
Initial value 0
0
Indications Normal
end: 0
Command
error: 1
Abnormal
end: 1
FO5
FO4
FO3
FO2
FO1
FO0
Programming error
Erase
error
—
—
Programming or
erase count
exceeded
Effective
address
error
0
0
0
0
0
0
—
Count
Effective
exceeded: 1 address
Otherwise: 0 error: 1
Erase
—
Programerror: 1
ming
Otherwise: 0
Otherwise: 0 error: 1
Otherwise: 0
Otherwise: 0
Note: FO2 and FO3 are undefined.
22.10.8 Status Polling
• The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode.
• The FO6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase
mode.
Rev. 4.00 Sep 27, 2006 page 681 of 1130
REJ09B0327-0400
Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Table 22.20 Status Polling Output Truth Table
Pin Names
Internal Operation
in Progress
Abnormal End
—
Normal End
FO7
0
1
0
1
FO6
0
0
1
1
FO0 to FO5
0
0
0
0
22.10.9 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 22.21 Command Wait State Transition Time Specifications
Item
Symbol
Min
Max
Unit
Standby release (oscillation stabilization time)
tosc1
20
—
ms
Programmer mode setup time
tbmv
10
—
ms
VCC hold time
tdwn
0
—
ms
VCC
RES
tosc1
tbmv
tdwn
Memory read Auto-program mode
mode
Auto-erase mode
Command wait
state
Command
Don't care
wait state
Normal/
abnormal end
identification
Command reception
Figure 22.23 Oscillation Stabilization Time, Programmer Mode Setup Time, and Power
Supply Fall Sequence
Rev. 4.00 Sep 27, 2006 page 682 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
22.10.10 Notes on Memory Programming
• When programming addresses which have previously been programmed, carry out autoerasing before auto-programming.
• When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level.
2. Auto-programming should be performed once only on the same address block.
22.11
Flash Memory Programming and Erasing Precautions
Precautions concerning the use of on-board programming mode and programmer mode are
summarized below.
Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. For a PROM
programmer, use Renesas Technology microcomputer device types with 128-kbyte or 64-kbyte
on-chip flash memory that support a 5.0-V programming voltage.
Do not select the HN28F101 or use a programming voltage of 3.3 V for the PROM programmer,
and only use the specified socket adapter. Incorrect use will result in damaging the device.
Powering on and off
When applying or disconnecting VCC, fix the RES pin low and place the flash memory in the
hardware protection state.
The power-on and power-off timing requirements should also be satisfied in the event of a power
failure and subsequent recovery.
Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or
E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program
runaway, etc.
Do not set or clear the SWE bit during program execution in flash memory.
Clear the SWE bit before executing a program or reading data in flash memory. When the SWE
bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for
verify operations (verification during programming/erasing).
Rev. 4.00 Sep 27, 2006 page 683 of 1130
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Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled to give priority to program/erase
operations.
Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 32-byte programming
unit block. In programmer mode, too, perform only one programming operation on a 128-byte
programming unit block. Programming should be carried out with the entire programming unit
block erased.
Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer socket,
socket adapter, and chip are not correctly aligned.
Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
22.12
Note on Switching from F-ZTAT Version to Mask ROM Version
The mask ROM version does not have the internal registers for flash memory control that are
provided in the F-ZTAT version. Table 22.22 lists the registers that are present in the F-ZTAT
version but not in the mask ROM version. If a register listed in table 22.22 is read in the mask
ROM version, an undefined value will be returned, Therefore, if application software developed
on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure
that the registers in table 22.22 have no effect.
Table 22.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Version
Register
Abbreviation
Address
Flash memory control register 1
FLMCR1
H'FF80
Flash memory control register 2
FLMCR2
H'FF81
Erase block register 1
EBR1
H'FF82
Erase block register 2
EBR2
H'FF83
Rev. 4.00 Sep 27, 2006 page 684 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Section 23 ROM
(H8S/2148 F-ZTAT A-Mask Version,
H8S/2147 F-ZTAT A-Mask Version,
H8S/2144 F-ZTAT A-Mask Version)
23.1
Overview
H8S/2148 F-ZTAT A-mask version and H8S/2144 F-ZTAT A-mask version have 128 kbytes, and
H8S/2147 F-ZTAT A-mask version has 64 kbytes of on-chip flash memory. The flash memory is
connected to the bus master by a 16-bit data bus. The bus master accesses both byte and word data
in one state, enabling faster instruction fetches and higher processing speed.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM.
The flash memory versions of this group can be erased and programmed on-board as well as with
a general-purpose PROM programmer.
23.1.1
Block Diagram
Figure 23.1 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000001
H'000002
H'000003
H'01FFFE
H'01FFFF
Figure 23.1 ROM Block Diagram
(A-mask versions of the H8S/2148 F-ZTAT and H8S/2144 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 685 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.1.2
Register Configuration
This group on-chip ROM is controlled by the operating mode and register MDCR. The register
configuration is shown in table 23.1.
Table 23.1 ROM Register
Register Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R/W
Undefined
Depends on the operating mode
H'FFC5
Note:
*
Lower 16 bits of the address.
23.2
Register Descriptions
23.2.1
Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
EXPE
—
—
—
—
—
MDS1
MDS0
Initial value
—*
0
0
0
0
0
—*
—*
Read/Write
R/W*
—
—
—
—
—
R
R
Note: * Determined by the MD1 and MD0 pins.
MDCR is an 8-bit read-only register used to set this group operating mode and monitor the current
operating mode.
The EXPE bit is initialized in accordance with the mode pin states by a reset and in hardware
standby mode.
Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1
and cannot be modified. In modes 2 and 3, EXPE has an initial value of 0 and can be read or
written.
Bit 7
EXPE
Description
0
Single-chip mode selected
1
Expanded mode selected
Rev. 4.00 Sep 27, 2006 page 686 of 1130
REJ09B0327-0400
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate values that reflects the
input levels of mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0
correspond to pins MD1 and MD0, respectively. These are read-only bits, and cannot be modified.
When MDCR is read, the input levels of mode pins MD1 and MD0 are latched in these bits.
23.3
Operation
The on-chip flash memory is connected to the CPU by a 16-bit data bus, and both byte and word
data is accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses
to the lower 8 bits. Word data must start at an even address.
The mode pins (MD1 and MD0) and the EXPE bit in MDCR can be set to enable or disable the
on-chip ROM, as shown in table 23.2.
In normal mode, the maximum amount of ROM that can be used is 56 kbytes.
Table 23.2 Operating Modes and ROM
Operating Mode
MCU
Operating
Mode
CPU
Operating
Mode
Mode 1
Mode 2
Mode 3
Note:
*
Mode Pins
MDCR
Description
MD1
MD0
EXPE
On-Chip ROM
Normal
Expanded mode with
on-chip ROM disabled
0
1
1
Disabled
Advanced
Single-chip mode
1
0
0
Enabled*
Advanced
Expanded mode with
on-chip ROM enabled
Normal
Single-chip mode
Normal
Expanded mode with
on-chip ROM enabled
1
1
0
1
Enabled
(56 kbytes)
H8S/2148 F-ZTAT A-mask version and H8S/2144 F-ZTAT A-mask version have
128 kbytes, and H8S/2147 F-ZTAT A-mask version has 64 kbytes of on-chip ROM.
Rev. 4.00 Sep 27, 2006 page 687 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.4
Overview of Flash Memory
23.4.1
Features
The features of the flash memory are summarized below.
• Four flash memory operating modes
 Program mode
 Erase mode
 Program-verify mode
 Erase-verify mode
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in
single-block units). When erasing multiple blocks, the individual blocks must be erased
sequentially. Block erasing can be performed as required on 1-kbyte, 28-kbyte, 16-kbyte, 8kbyte, and 32-kbyte blocks.
• Programming/erase times
The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,
equivalent to approximately 80 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
 Boot mode
 User program mode
• Automatic bit rate adjustment
With data transfer in boot mode, the bit rate of the chip can be automatically adjusted to match
the transfer bit rate of the host.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
Rev. 4.00 Sep 27, 2006 page 688 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.4.2
Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1 *
FLMCR2 *
EBR1
EBR2
Bus interface/controller
Operating
mode
Mode pins
*
*
Flash memory
(128 kbytes/64 kbytes)
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
Note: * These registers are used only in the flash memory version. In the mask ROM version,
a read at any of these addresses will return an undefined value, and writes are invalid.
Figure 23.2 Block Diagram of Flash Memory
Rev. 4.00 Sep 27, 2006 page 689 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.4.3
Flash Memory Operating Modes
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, the MCU enters one of
the operating modes shown in figure 23.3. In user mode, flash memory can be read but not
programmed or erased.
Flash memory can be programmed and erased in boot mode, user program mode, and programmer
mode.
Reset state
MD1 = 1
RES = 0
User mode with
on-chip ROM
enabled
SWE = 1
RES = 0
*2
SWE = 0
RES = 0
*1
RES = 0
Programmer
mode
User
program mode
Boot mode
On-board programming mode
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. MD0 = MD1 = 0, P92 = P91 = P90 = 1
2. MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1
Figure 23.3 Flash Memory Mode Transitions
Rev. 4.00 Sep 27, 2006 page 690 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
On-Board Programming Modes
• Boot mode
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started, an SCI communication check is carried
out, and the boot program required for flash
memory erasing is automatically transferred to
the RAM boot program area.
Host
Host
Programming control
program
Programming control
program
New application
program
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
RAM
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Host
Host
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
Flash memory
Programming control
program
RAM
Boot program
area
Boot program area
Flash memory
erase
SCI
Boot program
New application
program
Programming
control program
Program execution state
Figure 23.4 Boot Mode
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
• User program mode
1. Initial state
(1) the program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
The transfer program in the flash memory is
executed, and the programming/erase control
program is transferred to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
RAM
Transfer program
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
The chip
The chip
SCI
Boot program
Flash memory
RAM
Transfer program
SCI
Boot program
Flash memory
RAM
Transfer program
Programming/
erase control program
Flash memory
erase
Programming/
erase control program
New application
program
Program execution state
Figure 23.5 User Program Mode (Example)
Rev. 4.00 Sep 27, 2006 page 692 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Differences between Boot Mode and User Program Mode
Entire memory erase
Boot Mode
User Program Mode
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify
Program/program-verify
Erase/erase-verify
Notes *
To be provided by the user, in accordance with the recommended algorithm.
Block Configuration
The flash memory is divided into two 32-kbyte blocks (128-kbyte version only), two 8-kbyte
blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Address H'00000
1 kbyte
1 kbyte
1 kbyte
1 kbyte
Address H'00000
1 kbyte
1 kbyte
1 kbyte
1 kbyte
28 kbytes
16 kbytes
64 kbytes
28 kbytes
16 kbytes
128 kbytes
8 kbytes
8 kbytes
8 kbytes
8 kbytes
Address H'0FFFF
(b) 64-kbyte version
32 kbytes
32 kbytes
Address H'1FFFF
(a) 128-kbyte version
Figure 23.6 Flash Memory Block Configuration
Rev. 4.00 Sep 27, 2006 page 693 of 1130
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.4.4
Pin Configuration
The flash memory is controlled by means of the pins shown in table 23.3.
Table 23.3 Flash Memory Pins
Pin Name
Abbreviation
I/O
Function
Reset
RES
Input
Reset
Mode 1
MD1
Input
Sets MCU operating mode
Mode 0
MD0
Input
Sets MCU operating mode
Port 92
P92
Input
Sets MCU operating mode when MD1 = MD0 = 0
Port 91
P91
Input
Sets MCU operating mode when MD1 = MD0 = 0
Port 90
P90
Input
Sets MCU operating mode when MD1 = MD0 = 0
Transmit data
TxD1
Output
Serial transmit data output
Receive data
RxD1
Input
Serial receive data input
23.4.5
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 23.4.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 23.4 Flash Memory Registers
Initial Value
Address*
R/W*
3
R/W*
3
H'80
4
H'00*
H'FF80*
2
H'FF81*
Erase block register 2
EBR1*
5
EBR2*
R/W*
3
R/W*
H'00*
4
H'00*
H'FF82*
2
H'FF83*
Serial/timer control register
STCR
R/W
H'00
H'FFC3
Register Name
Abbreviation
R/W
Flash memory control register 1
FLMCR1*
5
FLMCR2*
Flash memory control register 2
Erase block register 1
5
5
3
4
1
2
2
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the serial/timer control register (STCR).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
4. When the SWE bit in FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.5
Register Descriptions
23.5.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
FWE
SWE
—
—
EV
PV
E
P
Initial value
1
0
0
0
0
0
0
0
Read/Write
R
R/W
—
—
R/W
R/W
R/W
R/W
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to
1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by
setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is
initialized to H'80 by a reset, and in hardware standby mode, software standby mode, subactive
mode, subsleep mode, and watch mode. When on-chip flash memory is disabled, a read will return
H'00, and writes are invalid.
Writes to the EV and PV bits in FLMCR1 are enabled only when SWE=1; writes to the E bit only
when SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1, and PSU = 1.
Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory
programming/erasing. This bit cannot be modified and is always read as 1.
Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming. SWE
should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be
cleared at the same time as these bits.
Bit 6
SWE
Description
0
Writes disabled
1
Writes enabled
(Initial value)
Bit 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
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Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3
EV
Description
0
Erase-verify mode cleared
1
Transition to erase-verify mode
(Initial value)
[Setting condition]
When SWE = 1
Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the
SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2
PV
Description
0
Program-verify mode cleared
1
Transition to program-verify mode
(Initial value)
[Setting condition]
When SWE = 1
Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV,
PV, or P bit at the same time.
Bit 1
E
Description
0
Erase mode cleared
1
Transition to erase mode
[Setting condition]
When SWE = 1, and ESU = 1
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(Initial value)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0
P
Description
0
Program mode cleared
1
Transition to program mode
(Initial value)
[Setting condition]
When SWE = 1, and PSU = 1
23.5.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
ESU
PSU
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
R/W
R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.
When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state.
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Bit 7
FLER
Description
0
Flash memory is operating normally
(Initial value)
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
1
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 23.8.3, Error Protection
Bits 6 to 2—Reserved: Always write 0 when writing to these bits.
Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU
Description
0
Erase setup cleared
1
Erase setup
(Initial value)
[Setting condition]
When SWE = 1
Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 0
PSU
Description
0
Program setup cleared
1
Program setup
[Setting condition]
When SWE = 1
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(Initial value)
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.5.3
Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit
7
6
5
4
3
2
1
0
EBR1
—
—
—
—
—
—
EB9/—* EB8/—*
Initial value
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
0
0
1 2
1 2
*
*
R/W
R/W* *
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
1
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR2
2
2
Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.
2. Bits EB8 and EB9 are not present in the 64-kbyte versions; they must not be set to 1.
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and
0 in EBR1 and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized
to H'00 by a reset, in hardware standby mode, software standby mode, subactive mode, subsleep
mode, and watch mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR1 and
EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one
bit in EBR1 and EBR2 (more than one bit cannot be set). When on-chip flash memory is disabled,
a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 23.5.
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Table 23.5 Flash Memory Erase Blocks
Block (Size)
128-kbyte Version
64-kbyte Version
Address
EB0 (1 kbyte)
EB0 (1 kbyte)
H'(00)0000 to H'(00)03FF
EB1 (1 kbyte)
EB1 (1 kbyte)
H'(00)0400 to H'(00)07FF
EB2 (1 kbyte)
EB2 (1 kbyte)
H'(00)0800 to H'(00)0BFF
EB3 (1 kbytes)
EB3 (1 kbytes)
H'(00)0C00 to H'(00)0FFF
EB4 (28 kbytes)
EB4 (28 kbytes)
H'(00)1000 to H'(00)7FFF
EB5 (16 kbytes)
EB5 (16 kbytes)
H'(00)8000 to H'(00)BFFF
EB6 (8 kbytes)
EB6 (8 kbytes)
H'(00)C000 to H'(00)DFFF
EB7 (8 kbytes)
EB7 (8 kbytes)
H'00E000 to H'00FFFF
EB8 (32 kbytes)
—
H'010000 to H'017FFF
EB9 (32 kbytes)
—
H'018000 to H'01FFFF
23.5.4
Serial/Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
IICS
IICX1
IICX0
IICE
FLSHE
—
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory, and also selects the TCNT
input clock. For details on functions not related to on-chip flash memory, see section 3.2.4,
Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module
controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
2
2
Bits 7 to 4—I C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I C
2
2
bus interface for the I C on-chip option. For details, see section 16, I C Bus Interface.
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Bit 3—Flash Memory Control Register Enable (FLSHE): Setting the FLSHE bit to 1 enables
read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash
memory control registers are deselected. In this case, the flash memory control register contents
are retained.
Bit 3
FLSHE
Description
0
Flash memory control registers deselected
1
Flash memory control registers selected
(Initial value)
Bit 2—Reserved: Do not write 1 to this bit.
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits control 8-bit timer
operation. See section 12, 8-Bit Timers, for details.
23.6
On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
23.6. For a diagram of the transitions to the various flash memory modes, see figure 23.3.
Only advanced mode setting is possible for boot mode.
In the case of user program mode, established in advanced mode or normal mode, depending on
the setting of the MD0 pin. In normal mode, only programming of a 56-kbyte area of flash
memory is possible.
Table 23.6 Setting On-Board Programming Modes
Mode
Mode Name
CPU Operating Mode
MD1
MD0
P92
P91
P90
1*
1*
Boot mode
Advanced mode
0
0
1*
User program mode
Advanced mode
1
0
—
—
—
1
—
—
—
Normal mode
Note:
*
Can be used as I/O ports after boot mode is initiated.
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Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
23.6.1
Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the chip pins have been set to boot mode, the boot program
built into the chip is started and the programming control program prepared in the host is serially
transmitted to the chip via the SCI. In the chip, the programming control program received via the
SCI is written into the programming control program area in on-chip RAM. After the transfer is
completed, control branches to the start address of the programming control program area and the
programming control program execution state is entered (flash memory programming is
performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 23.7, and the boot program mode
execution procedure in figure 23.8.
The chip
Flash memory
Host
Write data reception
Verify data transmission
RxD1
SCI1
TxD1
Figure 23.7 System Configuration in Boot Mode
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On-chip RAM
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Start
Set pins to boot mode and execute reset-start
Host transfers data (H'00) continuously at prescribed
bit rate
The chip measures low period of H'00 data transmitted
by host
The chip calculates bit rate and sets value in bit rate
register
After bit rate adjustment, transmits one H'00 data byte
to host to indicate end of adjustment
Host confirms normal reception of bit rate adjustment
end indication (H'00), and transmits one H'55 data byte
After receiving H'55, trransmit one H'AA data byte
to host
Host transmits number of user program bytes (N),
upper byte followed by lower byte
The chip transmits received number of bytes to host as
verify data (echo-back)
n=1
Host transmits programming control program
sequentially in byte units
The chip transmits received programming control
program to host as verify data (echo-back)
n+1→n
Transfer received programming control program
to on-chip RAM
No
n = N?
Yes
End of transmission
Check flash memory data, and if data has already
been written, erase all blocks
Check that all flash memory data has been erased
Check the starting ID code of the area to which the
programming control program is to be transferred
No
ID code match?
Yes
The chip transmits one H'AA data byte to the host
Execute programming control program transffered
to on-chip RAM
The chip transmits one H'FF
data byte as an ID code error
and stops the subsequent
operations
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and
the erase operation and subsequent operations are halted.
Figure 23.8 Boot Mode Execution Procedure
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Automatic SCI Bit Rate Adjustment
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Low period (9 bits) measured (H'00 data)
Stop
bit
High period
(1 or more bits)
Figure 23.9 Automatic SCI Bit Rate Adjustment
When boot mode is initiated, the chip measures the low period of the asynchronous SCI
communication data (H'00) transmitted continuously from the host. The SCI transmit/receive
format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of
the transmission from the host from the measured low period, and transmits one H'00 byte to the
host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end
indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception
cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the chips system clock frequency, there will be a
discrepancy between the bit rates of the host and the chip. To ensure correct SCI operation, the
host’s transfer bit rate should be set to (4800, 9600, or 19200) bps.
Table 23.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the chips bit rate is possible. The boot program should be executed within this
system clock range.
Table 23.7 System Clock Frequencies for Which Automatic Adjustment of the Chips Bit
Rate Is Possible
Host Bit Rate
System Clock Frequency for Which Automatic Adjustment
of Bit Rate Is Possible
19200 bps
8 MHz to 20 MHz
9600 bps
4 MHz to 20 MHz
4800 bps
2 MHz to 18 MHz
On-Chip RAM Area Divisions in Boot Mode
In boot mode, the 1920-byte area from H'(FF)E880 to H'(FF) EFFF and the 128-byte area from
H'(FF)FF00 to H'(FF)FF7F is reserved for use by the boot program, as shown in figure 23.10. The
area to which the programming control program is transferred is H'(FF)E080 to H'(FF)E87F (2048
bytes). In the 64-kbyte version, this is a reserved area that is used only during the boot mode.
However, the 8-byte area from H'(FF)E080 to H'(FF)E087 is reserved for ID codes as shown in
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Figure 23.10. The boot program area can be used when the programming control program
transferred into the RAM enters the execution state. A stack area should be set up as required.
H'(FF)E080
ID code area*1
H'(FF)E088
Programming
control program
area*1
(2040 bytes)
H'(FF)E880
Boot program
area*2
(1920 bytes)
H'(FF)EFFF
H'(FF)FF00
H'(FF)FF7F
Boot program
area*2
(128 bytes)
Notes: 1. In the 64-kbyte version, this is a reserved area that is used only during the boot mode.
Do not use this area for other purposes.
2. The boot program area cannot be used until a transition is made to the execution state
for the programming control program transferred to the RAM. Note that the boot program
remains stored in this area after a branch is made to the programming control program.
Figure 23.10 RAM Areas in Boot Mode
In the boot mode of this chip, the content in the 8-byte ID code area shown below is confirmed so
that whether or not there is a programming control program that corresponds to the chip can be
checked.
H'(FF)E080
40
FE
64
66
32
31
34
39
↑ (product identification ID)
H'(FF)E088 and above
Instruction code for write control program
When a new programming control program for use in boot mode is created, add the 8-byte ID
code described above to the head of the program.
Notes on Use of Boot Mode
• When the chip comes out of reset in boot mode, it measures the low period of the input at the
SCI’s RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the RxD1 input.
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• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
• Interrupts cannot be used while the flash memory is being programmed or erased.
• The RxD1 and TxD1 pins should be pulled up on the board.
• Before branching to the programming control program (RAM area H'(FF)E088), the chip
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE
and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data
output pin, TxD1, goes to the high-level output state (P84DDR = 1, P84DR = 1).
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
• Boot mode can be entered by making the pin settings shown in table 23.6 and executing a
reset-start.
1
When the chip detects the boot mode setting at reset release* , P92, P91, and P90 can be used
as I/O ports.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
1
the mode pins, and executing reset release* . Boot mode can also be cleared by a WDT
overflow reset. The mode pin input levels must not be changed in boot mode.
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
2
will change according to the change in the microcomputer’s operating mode* .
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Notes: 1. Mode pins input must satisfy the mode programming setup time (tMDS = 4 states) with
respect to the reset release timing.
2. Ports with multiplexed address functions will output a low level as the address signal if
mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedance state. The bus control output signals will output a high level
if mode pin setting is for mode 1 is entered during a reset. In other modes, the port pins
go to the high-impedance state.
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23.6.2
User Program Mode
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing an on-board means of supplying programming data, and
storing a program/erase control program in part of the program area as necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 2 or 3).
In this mode, on-chip supporting modules other than flash memory operate as they normally
would in mode 2 and 3.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
RAM or external memory.
Figure 23.11 shows the procedure for executing the program/erase control program when
transferred to on-chip RAM.
Write the transfer program
(and the program/erase control program
if necessary) beforehand
MD1, MD0 = 10, 11
Reset-start
Transfer program/erase control
program to RAM
Branch to program/erase control
program in RAM area
Execute program/erase control
program (flash memory rewriting)
Branch to flash memory application
program
Note: The watchdog timer should be activated to prevent overprogramming or overerasing
due to program runaway, etc.
Figure 23.11 User Program Mode Execution Procedure
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23.7
Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in
FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash
memory.
2. Perform programming in the erased state. Do not perform additional programming on
previously programmed addresses.
23.7.1
Program Mode
Follow the procedure shown in the program/program-verify flowchart in figure 23.12 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a
time.
The wait times (x, y, z1, z2, z3, α, ß, γ, ε, η, θ) after setting/clearing individual bits in flash
memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N),
see section 26.2.6, Flash Memory Characteristics.
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 128-byte program data is stored in the program data area and reprogram
data area, and the 128-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive
byte data transfers are performed. The program address and program data are latched in the flash
memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this
case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation
for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the
elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in
FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a
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program setting so that the time for one programming operation is within the range of (z1), (z2) or
(z3) µs.
23.7.2
Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least (α) µs later). The watchdog
timer is cleared after the elapse of (β) µs or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy
write of H'FF data should be made to the addresses to be read. The dummy write should be
executed after the elapse of (γ) µs or more. When the flash memory is read in this state (verify data
is read in 16-bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy
write before performing this read operation. Next, the originally written data is compared with the
verify data, and reprogram data is computed (see figure 23.12) and transferred to the reprogram
data area. After 128 bytes of data have been verified, exit program-verify mode, wait for at least
(η) µs. If the programming count is less than 6, the 128-byte data in the additional program data
area should be written consecutively to the write addresses, and additional programming
performed. Next clear the SWE bit in FLMCR1, and wait at least (θ) µs. If reprogramming is
necessary, set program mode again, and repeat the program/program-verify sequence as before.
However, ensure that the program/program-verify sequence is not repeated more than (N) times on
the same bits.
Rev. 4.00 Sep 27, 2006 page 709 of 1130
REJ09B0327-0400
Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Write pulse application subroutine
Sub-routine write pulse
Start of programming
Start
Enable WDT
Set SWE bit in FLMCR1
Set PSU bit in FLMCR1
Wait (y) µs
Wait (x) µs
*6
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
*5
m=0
Clear P bit in FLMCR1
Wait (α) µs
*6
Clear PSU bit in FLMCR2
Wait (β) µs
*6
Write 128-byte data in RAM reprogram data
*1
area consecutively to flash memory
Sub-routine-call
Write pulse
See Note 7 for pulse width
(z1) µs or (z2) µs
*6
Disable WDT
Set PV bit in FLMCR1
End sub
Wait (γ) µs
*6
H'FF dummy write to verify address
Wait (ε) µs
Increment address
*6
Read verify data
Note 7: Write Pulse Width
Number of Writes n Write Time (z*6) µsec
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
13
z2
..
..
.
.
998
z2
999
z2
1000
z2
Note: Use a (z3) µs write pulse for additional
programming.
Program data =
verify data?
*2
m=1
OK
6 ≥ n?
NG
OK
Additional program data computation
Transfer additional program data
to additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
End of 128-byte
data verification?
NG
OK
Clear PV bit in FLMCR1
Wait (η) µs
6 ≥ n?
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional program data
storage area (128 kbytes)
n←n+1
NG
*6
NG
OK
Write 128-byte data in additional program data
area in RAM consecutively to flash memory
*1
Additional write pulse (z3) µs
*6
m = 0?
NG
n ≥ 1000?
OK
Clear SWE bit in FLMCR1
Wait