ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 1 Hermetically Sealed Analog Isolation Amplifier Data Sheet Description Features The HCPL-7850, HCPL-7851, and ACPL-785E are isolation amplifiers that provide accurate, electrically isolated and amplified representations of voltage and current. When used with a shunt resistor to monitor the motor phase current in a high-speed motor drive, the device offers superior reliability compared with the traditional solutions such as current transformers and Hall-effect sensors. These devices consist of a sigma-delta analog-to-digital converter optically coupled to a digital-to-analog converter in a hermetically sealed package. The products are capable of operation and storage over the full military temperature range and can be purchased as a commercial product (HCPL-7850), with full MIL-PRF-38534 Class H testing (HCPL-7851), with MIL-PRF-38534 Class E testing (ACPL-785E) (Class K with exceptions) or from the DLA Standard Microcircuit Drawing (SMD) 5962-97557. Details of the Class E program exceptions are listed here: 1. Nondestructive Bond Pull, Test method 2023 of MIL-STD-883 in screening is not required. 2. Particle Impact Noise Detection (PIND), Test method 2020 of MIL-STD-883 in device screening and group C testing is not required. Performance guaranteed over full military temperature range: –55°C to +125°C Manufactured and tested on a MIL-PRF-38534 certified line Hermetically sealed packages Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD) QML-38534, Class H and Class E HCPL-7840 function compatibility High common-mode rejection (CMR): 8 kV/μs at VCM = 1000V 5% gain tolerance 0.1% nonlinearity Low offset voltage and offset temperature coefficient 100 kHz bandwidth Applications 3. Die Shear Strength, Test method 2019 of MIL-STD-883 in group B testing is not required. 4. Internal Water Vapor Content, Test method 1018 of MIL-STD-883 in group C is not required. 5. Scanning Electron Microscope (SEM) inspection, Test method 2018 of MIL-STD-883 in element evaluation is not required. Industrial, military, and space systems High reliability systems Harsh industrial environments Transportation, medical, and life critical systems General-purpose analog signal isolation CAUTION 1. See Selection Guide – Lead Configuration Options for available extensions. Broadcom -1- It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Schematic Diagram Schematic Diagram IDD1 IDD2 VDD1 1 VIN+ 2 + + 7 VOUT+ VIN– 3 – – 6 VOUT– GND1 4 8 VDD2 With common-mode rejection of 8 kV/μs, these devices are suitable for noisy electrical environments such as those generated by the high switching rates of power IGBTs. 5 GND2 SHIELD NOTE Superior performance in design-critical specifications, such as common-mode rejection, offset voltage, nonlinearity, and operating temperature, makes the HCPL-7850, HCPL-7851 and ACPL-785E excellent choices for designing reliable products such as motor controllers and inverters. Low offset voltage together with a low offset voltage temperature coefficient permits accurate use of auto-calibration techniques. A 0.1-μF bypass capacitor must be connected between pins 1 and 4 and between pins 5 and 8. Gain tolerance of 5% with 0.1% nonlinearity further provide the performance necessary for accurate feedback and control. Selection Guide – Lead Configuration Options Part Number and Options Commercial HCPL-7850 MIL-PRF-38534, Class H HCPL-7851 MIL-PRF-38534, Class E ACPL-785E Standard Lead Finish Gold Plate Gold Platea Solder Dippedb Option #200 Option -200 Butt Cut/Gold Platea Option #100 Option -100 Gull Wing/Solderedb Option #300 Option -300 Prescript for all below 5962- 5962- Gold Platea 9755701HPC 9755701EPC Solder Dippedb 9755701HPA 9755701EPA Butt Cut/Gold Platea 9755701HYC 9755701EYC Butt Cut/Solderedb 9755701HYA 9755701EYA Gull Wing/Solderedb 9755701HXA 9755701EXA a SMD Part Number a. Gold Plate lead finish: Maximum gold thickness of leads is <100 micro inches. Typical is 60 to 90 micro inches. b. Solder lead finish: Sn63/Pb37. Device Marking Avago DESIGNATOR Avago P/N DLA SMD[1] DLA SMD[1] PIN ONE/ ESD IDENT A QYYWWZ XXXXXXXX XXXXXXXXX XXX XXX 50434 COMPLIANCE INDICATOR,[1] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE[1] [1] QML PARTS ONLY Broadcom -2- ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Outline Drawing Outline Drawing 8-Pin DIP Through Hole 1.02 (0.040) 1.52 (0.060) 10.03 (0.395) 10.29 (0.405) 8.13 (0.320) MAX. 7.16 (0.282) 7.57 (0.298) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 2.29 (0.090) 2.79 (0.110) 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Hermetic Optocoupler Options Option 100 Description Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial, Class H and Class E product in 8-pin DIP. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 4.32 (0.170) MAX. 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 200 Lead finish is solder dipped rather than gold plated. This option is available on Commercial, Class H and Class E product in 8-pin DIP. DLA Drawing (SMD) part numbers contain provisions for lead finish. 300 Surface-mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercial, Class H and Class E product in 8-pin DIP. This option has solder-dipped leads. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 4.57 (0.180) MAX. 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 4.57 (0.180) MAX. 5° MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Broadcom -3- 1.07 (0.042) 1.32 (0.052) ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min Max Unit Storage Temperature TS –65 +150 °C Operating Temperature TA –55 +125 °C VDD1, VDD2 0.0 +5.5 V VIN+, VIN– –2.0 –6.0 VDD1 + 0.5 VDD1 + 0.5 V V –0.5 VDD2 + 0.5 V — 260 for 10 sec °C Supply Voltages Steady-State Input Voltage 2 Second Transient Input Voltage Output Voltages VOUT+, VOUT– Lead Solder Temperature a. Notes a a If VIN– is brought above VDD1 – 2V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use. ESD Classification (MIL-STD-883, Method 3015) HCPL-7850, HCPL-7851, and ACPL-785E , Class 1 Recommended Operating Conditions Parameter Supply Voltages Input Voltagea a. Symbol Min Max Unit VDD1, VDD2 4.5 5.5 V VIN+, VIN– –200 +200 mV If VIN– is brought above VDD1 – 2V with respect to GND1 an internal test mode may be activated. This test mode is not intended for customer use. Broadcom -4- ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet DC Electrical Specifications DC Electrical Specifications Over recommended operating conditions (TA = –55°C to +125°C, VIN+ = 0V, VIN– = 0V, VDD1 = 5V and VDD2 = 5V, unless otherwise specified). Parameter Input Offset Voltage Gain 20-mV Nonlinearity 10-mV Nonlinearity Symbol Group Aa Subgroups Min Typb Max Unit Test Conditions Fig Notes VOS 1, 2 ,3 –1.0 0.6 5.0 mV 4.5V ≤ (VDD1, VDD2) ≤ 5.5V 1, 2, 3 c G 2, 3 7.36 8.00 8.64 V/V 7.60 8.00 8.4 –200 mV ≤ VIN+ ≤ 200 mV, 4.5V ≤ (VDD1, VDD2) ≤ 5.5V 5, 6, 7 1 2, 3 — 0.05 0.8 % 1 — 0.05 0.2 –200 mV ≤ VIN+ ≤ 200 mV, 4.5V ≤ (VDD1, VDD2) ≤ 5.5V 5, 8, 9, 10, 12 2, 3 — 0.01 0.2 –100 mV ≤ VIN+ ≤ 100 mV, 1 — 0.01 0.1 4.5V ≤ (VDD1, VDD2) ≤ 5.5V 5, 8, 9, 11, 12 NL200 NL100 Output Common-Mode Voltage VOCM 1, 2, 3 2.20 2.56 2.80 V Input Supply Current IDD1 1, 2, 3 — 10.7 15.5 mA Output Supply Current IDD2 1, 2, 3 — 9.4 17 mA Input-Output Insulation Leakage Current II–O 1 — — 1.0 μA — 320 — mV 4, 12 13 Maximum Input Voltage Before Output Clipping |VIN+| –400 mV ≤ VIN+ ≤ 400 mV, 4.5V ≤ (VDD1, VDD2) ≤ 5.5V d 14, 16 15, 16 RH ≤ 65%, t = 5 sec. VI–O = 1500 Vdc, TA = 25°C e MAX Average Input Bias Current IIN — –0.57 — μA Average Input Resistance RIN — 480 — kΩ Input DC Common-Mode Rejection Ratio CMRRIN — 69 — dB Output Resistance RO — 1 — Ω Output Low Voltage VOL — 1.28 — V VIN+ = 400 mV Output High Voltage VOH — 3.84 — V VIN+ = –400 mV Output Short-Circuit Current |IOSC| — 11 — mA VOUT = 0V or VDD2 i Resistance (Input-Output) RI–O — 1012 — Ω VI–O = 500 Vdc e Capacitance (Input–Output) CI–O — 2.7 — pF f = 1 MHz, VI–O = 0 Vdc f g 4 h a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class E receive 100% testing at 25, 125, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typicals are at the nominal operating conditions of VIN+ = 0V, VIN– = 0V, TA = 25°C, VDD1 = 5V and VDD2 = 5V. c. Exact offset value is dependent on layout of external bypass capacitors. The offset value in the data sheet corresponds to Broadcom’s recommended layout (see Figure 26 and Figure 27). d. Nonlinearity is defined as half of the peak-to-peak output deviation from the best-fit gain line, expressed as a percentage of the full-scale differential output voltage. e. Device considered a two-terminal device: Pins 1, 2, 3, and 4 are shorted together, and pins 5, 6, 7, and 8 are shorted together. f. Because of the switched capacitor nature of the sigma-delta A/D converter, time averaged values are shown. g. CMRRIN is defined as the ratio of the gain for differential inputs applied between pins 2 and 3 to the gain for both common-mode inputs applied to both pins 2 and 3 with respect to pin 4. h. When the differential input signal exceeds approximately 320 mV, the outputs will limit at the typical values shown. i. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or ground. Broadcom does not recommend operations under these conditions. Broadcom -5- ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications AC Electrical Specifications Over recommended operating conditions (TA = –55°C to +125°C, VIN+ = 0V, VIN– = 0V, VDD1 = 5V and VDD2 = 5V, unless otherwise specified). Symbol Group Aa Subgroups Min Typb Max Unit Test Conditions Fig Notes Common-Mode Rejection CMR 9 5 8 5.0 kV/μs VCM = 1 kV 4.5V ≤ (VDD1, VDD2) ≤ 5.5V, TA = 25° C 17 c, d Propagation Delay to 50% tPD50 9, 10, 11 — 3.7 7.5 μs 18, 19 Propagation Delay to 90% tPD90 9, 10, 11 — 5.7 11.0 VIN+ = 0 to 100 mV step 4.5V ≤ (VDD1, VDD2) ≤ 5.5V Rise/Fall Time (10% to 90%) tR/F 9, 10, 11 — 3.4 7.5 Small-Signal Bandwidth (–3 dB) f–3 dB 9, 10, 11 45 100 — kHz 4.5V ≤ (VDD1, VDD2) ≤ 5.5V VIN+ = 200 mVpk-pk 18, 20, 21 e Small-Signal Bandwidth (–45°) f–45° — 31 — RMS Input-Referred Noise VN — 0.6 — mVrms In recommended application circuit 22, 24 f Power Supply Rejection PSR — 570 — mVP-P Parameter g a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class E receive 100% testing at 25, 125, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typicals are at the nominal operating conditions of VIN+ = 0V, VIN– = 0V, TA = 25°C, VDD1 = 5V and VDD2 = 5V. c. CMR (also known as IMR or Isolation Mode Rejection) specifies the minimum rate of rise of a common-mode signal applied across the isolation boundary at which small output perturbations begin to occur. These output perturbations can occur with both the rising and falling edges of the common-mode waveform and may be of either polarity. A CMR failure is defined as a perturbation exceeding 200 mV at the output of the recommended application circuit (Figure 24). See Applications for more information on CMR. d. Parameters are tested as part of device initial characterization and after design and process changes only. Parameters are guaranteed to limits specified for all lots not specifically tested. e. The f–3dB test is guaranteed by the TRISE test. f. Output noise comes from two primary sources: chopper noise and sigma-delta quantization noise. Chopper noise results from chopper stabilization of the output op-amps. It occurs at a specific frequency (typically 500 kHz) and is not attenuated by the on-chip output filter. The on-chip filter does eliminate most, but not all, of the sigma-delta quantization noise. An external filter circuit may be easily added to the external post-amplifier to reduce the total RMS output noise. See Applications for more information. g. Data sheet value is the amplitude of the transient at the differential output of the device when a 1 VP-P, 1 MHz square wave with 100 ns rise and fall times (measured at pins 1 and 8) is applied to both VDD1 and VDD2. Broadcom -6- ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 1 Input Offset Voltage Test Circuit VDD2 VDD1 +15 V 0.1 PF 1 8 0.1 PF 7 2 10 K + 0.1 PF HCPL-785x 3 6 4 5 VOUT 10 K – 0.47 PF AD624CD GAIN = 100 0.47 PF 0.1 PF -15 V Figure 2 Gain Change vs. Temperature Figure 3 Input Off set Change vs. VDD1 and VDD2 1.5 0.9 VDD1 = 5 V VDD2 = 5 V 'VOS – INPUT OFFSET CHANGE – mV 'VOS – INPUT OFFSET CHANGE – mV 2.0 1.0 0.5 0 -0.5 -60 -20 20 60 TA – TEMPERATURE – °C 100 VO – OUTPUT VOLTAGE – V 4.0 3.5 POSITIVE OUTPUT NEGATIVE OUTPUT 2.5 2.0 VDD1 = 5 V VDD2 = 5 V TA = 25° C 1.5 1.0 -0.6 -0.4 -0.2 0 0.2 VIN – INPUT VOLTAGE – V 0.4 0.6 TA = 25° C 0.3 0 -0.3 4.4 140 Figure 4 Output Voltages vs. Input Voltage 3.0 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) 0.6 Broadcom -7- 4.6 4.8 5.0 5.2 VDD – SUPPLY VOLTAGE – V 5.4 5.6 ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 5 Gain and Nonlinearity Test Circuit VDD1 0.1 PF VIN 404 13.2 VDD2 1 8 2 7 0.1 PF 10 K 6 10 K 3 0.01 PF HCPL-785x 4 5 +15 V 0.1 PF +15 V 0.1 PF + + – AD624CD GAIN = 4 0.1 PF 0.47 PF -15 V 0.47 PF – AD624CD GAIN = 10 0.1 PF VOUT -15 V 10 K 0.47 PF Figure 6 Gain Change vs. Temperature Figure 7 Gain Change vs. VDD1 and VDD2 0.05 0.10 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) 0.08 'G– GAIN CHANGE – % 'G– GAIN CHANGE – % 0 -0.05 -0.10 -0.15 -0.20 -60 VDD1 = 5 V VDD2 = 5 V -20 20 60 TA – TEMPERATURE – °C 100 NL ERROR – % OF FULL SCALE 200 mV ERROR 100 mV ERROR VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25° C 0 -0.05 -0.10 -0.2 -0.1 0 0.1 VIN+ – INPUT VOLTAGE – V 0.02 0 -0.02 -0.06 4.4 140 0.15 0.05 TA = 25° C 0.04 -0.04 Figure 8 Nonlinearity Error Plot vs. Input Voltage 0.10 0.06 0.2 Broadcom -8- 4.6 4.8 5.0 5.2 VDD – SUPPLY VOLTAGE – V 5.4 5.6 ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 9 Nonlinearity vs. Temperature Figure 10 200-mV Nonlinearity vs. VDD1 and VDD2 0.3 0.07 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25° C 200 mV 100 mV TA = 25° C NL – NONLINEARITY – % NL – NONLINEARITY – % 0.4 0.2 0.1 0 -60 -20 20 60 TA – TEMPERATURE – °C 100 0.06 0.05 0.04 0 4.4 140 Figure 11 100-mV Nonlinearity vs. VDD1 and VDD2 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) 4.6 4.8 5.0 5.2 VDD – SUPPLY VOLTAGE – V 5.4 5.6 Figure 12 Nonlinearity vs. Full-Scale Input Voltage 0.025 0.020 0.015 0.010 4.6 4.8 5.0 5.2 VDD – SUPPLY VOLTAGE – V 5.4 VDD1 = 5 V VDD2 = 5 V 0 ±0.40 ±0.10 ±0.20 ±0.30 FS – FULL-SCALE INPUT VOLTAGE – V Figure 14 Input Supply Current vs. Input Voltage 11 IDD1 – INPUT SUPPLY CURRENT – mA 2 IIN – INPUT CURRENT – mA 0.05 5.6 Figure 13 Input Current vs. Input Voltage 0 -2 -4 -6 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V TA = 25° C -8 -10 0.50 0.01 0.005 4.4 TA = 25° C 5.00 vs. VDD1 (VDD2 = 5 V) vs. VDD2 (VDD1 = 5 V) NL – NONLINEARITY – % NL – NONLINEARITY – % TA = 25° C -6 -4 -2 0 2 VIN+ – INPUT VOLTAGE – V 4 TA = 25° C 10 9 8 6 -0.4 6 Broadcom -9- VDD1 = 5 V VDD2 = 5 V VIN– = 0 V 7 -0.2 0 0.2 VIN+ – INPUT VOLTAGE – V 0.4 ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 15 Output Supply Current vs. Input Voltage Figure 16 Input and Output Supply Current vs. Temperature 20 VDD1 = 5 V VDD2 = 5 V VIN– = 0 V 9.5 IDD – POWER SUPPLY CURRENT – mA IDD2 – OUTPUT SUPPLY CURRENT – mA 10.0 9.0 8.5 TA = 25° C 8.0 -0.4 -0.2 0 0.2 VIN+ – INPUT VOLTAGE – V IDD1 IDD2 15 10 10 K VDD2 0.1 PF 1 0.1 PF 150 pF +15 V 0.1 PF 8 0.1 PF 7 2K 3 6 2K 4 5 2 9V – HCPL-785x PULSE GEN. VOUT + MC34081 0.1 PF 10 K 150 pF -15 V – + VCM Figure 18 Propagation Delay, Rise/Fall Time and Bandwidth Test Circuit 10 K VDD1 0.1 PF VIN VDD2 8 2 7 2K 3 6 2K 4 5 0.1 PF HCPL-785x 0.01 PF +15 V 0.1 PF 1 – 10 K 5 0 -60 0.4 Figure 17 Common-Mode Rejection Test Circuit 78L05 IN OUT + MC34081 VOUT 0.1 PF -15 V VIN IMPEDANCE LESS THAN 10 :. Broadcom - 10 - VDD1 = 5 V VDD2 = 5 V VIN+ = 320 mV VIN– = 0 V -20 20 60 TA – TEMPERATURE – °C 100 140 ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 19 Propagation Delays and Rise/Fall Time vs. Temperature Figure 20 Amplitude Response vs. Frequency 0 10 t – TIME – Ps 8 7 RELATIVE AMPLITUDE – dB DELAY TO 90% DELAY TO 50% RISE/FALL TIME 9 VDD1 = 5 V VDD2 = 5 V 6 5 4 VIN– = 0 V VIN+ = 0 TO 100 mV STEP 3 2 -60 -40 -20 0 20 40 60 80 100 120 TA – TEMPERATURE – °C -1 -3 -4 140 Figure 21 3-dB Bandwidth vs. Temperature VDD1 = 5 V VDD2 = 5 V TA = 25° C -2 1 5 10 50 f – FREQUENCY – kHz 100 500 Figure 22 RMS Input-Referred Noise vs. Recommended Application Circuit Bandwidth 2.5 VDD1 = 5 V VDD2 = 5 V 140 VN – RMS INPUT-REFERRED NOISE – mV f (-3 dB) – 3 dB BANDWIDTH – kHz 160 120 100 80 60 40 -60 -40 -20 0 20 40 60 80 100 120 140 TA – TEMPERATURE – °C Broadcom - 11 - VIN+ = 200 mV VIN+ = 100 mV VIN+ = 0 mV 2.0 TA = 25° C VDD1 = 5 V VDD2 = 5 V 1.5 1.0 0.5 0 5 10 50 100 f – FREQUENCY – KHz 500 ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet AC Electrical Specifications Figure 23 HCPL-785x Block Diagram VOLTAGE REGULATOR CLOCK GENERATOR VOLTAGE REGULATOR ISOLATION BOUNDARY ISO-AMP INPUT 6' MODULATOR LED DRIVE CIRCUIT ENCODER DETECTOR CIRCUIT DECODER AND D/A FILTER ISO-AMP OUTPUT Figure 24 Recommended Application Circuit POSITIVE FLOATING SUPPLY C5 150 pF HV+ GATE DRIVE CIRCUIT R3 ••• 10.0 K U1 78L05 IN OUT C1 0.1 PF R5 68 MOTOR ••• + – +5 V +15 V C8 0.1 PF C2 0.1 PF 1 8 2 7 C3 0.01 PF 3 C4 0.1 PF R1 2.00 K U2 6 R2 – U3 + MC34081 2.00 K 4 5 RSENSE HCPL-785x ••• HV– Broadcom - 12 - C7 C6 150 pF R4 10.0 K -15 V 0.1 PF VOUT ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Applications Information Applications Information Supplies and Bypassing Functional Description Figure 23 shows the primary functional blocks of the HCPL-785x. In operation, the sigma-delta modulator converts the analog input signal into a high-speed serial bit stream. The time average of this bit stream is directly proportional to the input signal. This stream of digital data is encoded and optically transmitted to the detector circuit. The detected signal is decoded and converted back into an analog signal, which is filtered to obtain the final output signal. Application Circuit The recommended application circuit is shown in Figure 24. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5V using a simple three-terminal voltage regulator (U1). The voltage from the current sensing resistor, or shunt (Rsense), is applied to the input of the HCPL-785x through an RC anti-aliasing filter (R5, C3). And finally, the differential output of the isolation amplifier is converted to a ground-referenced single-ended output voltage with a simple differential amplifier circuit (U3 and associated components). Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. C5 150 pF R3 10.0 K +5 V +5 V 1 8 2 7 U2 6 3 C4 0.1 PF C4 R1 – U3 + MC34071 2.00 K R2 5 HCPL-785x C2 R5 2.00 K 4 Figure 26 Top Layer of Printed Circuit Board Layout C8 0.1 PF R4A 20.0 K As shown in Figure 24, a 0.1-μF bypass capacitor (C2, C4) should be located as close as possible to the input and output power supply pins of the HCPL-785x. The bypass capacitors are required because of the high-speed digital nature of the signals inside the isolation amplifier. A 0.01-μF bypass capacitor (C3) is also recommended at the input pin(s) due to the switched-capacitor nature of the input circuit. The input bypass capacitor should be at least 1000 pF to maintain gain accuracy of the isolation amplifier. Inductive coupling between the input power-supply capacitor and the input circuit, including the input bypass capacitor and the input leads of the HCPL-785x, can introduce additional DC offset in the circuit. Several steps can be taken to minimize the mutual coupling between the two parts of the circuit, thereby improving the offset performance of the design. Separate the two bypass capacitors C2 and C3 as much as possible (even putting them on opposite sides of the PC board), while keeping the total lead lengths, including traces, of each bypass capacitor less than 20 mm. PC board traces should be made as short as possible and placed close together or over ground plane to minimize loop area and pickup of stray magnetic fields. Avoid using sockets, as they will typically increase both loop area and inductance. And finally, using capacitors with small body size and orienting them perpendicular to each other on the PC board can also help. For more information concerning this effect, see Application Note 1078, Designing with Avago Technologies Isolation Amplifiers. Figure 25 Single-Supply Post-Amplifier Circuit +5 V As mentioned, an inexpensive three-terminal regulator can be used to reduce the gate-drive power supply voltage to 5V. To help attenuate high frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator’s input bypass capacitor. C6 150 pF R4B 20.0 K C3 VOUT Figure 27 Bottom Layer of a Printed Circuit Board Layout TO VDD1 TO RSENSE+ TO RSENSE– Broadcom - 13 - TO VDD2 VOUT+ VOUT– ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Shunt Resistor Selections Shunt Resistor Selections The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes that could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). The value of the shunt should be chosen as a compromise between minimizing power dissipation by making the shunt resistance smaller and improving circuit accuracy by making it larger and utilizing the full input range of the HCPL-785x. Broadcom recommends four different shunts that can be used to sense average currents in motor drives up to 35A and 35 hp. Table 1 shows the maximum current and horsepower range for each of the LVR-series shunts from Dale. Even higher currents can be sensed with lower value shunts available from vendors such as Dale, IRC, and Isotek (Isabellenhuette). When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. Using a heat sink for the shunt or using a shunt with a lower tempco can help minimize this effect. The Application Note 1078, Designing with Avago Technologies Isolation Amplifiers, contains additional information on designing with current shunts. The recommended method for connecting the isolation amplifier to the shunt resistor is shown in Figure 24. Pin 2 (VIN+) is connected to the positive terminal of the shunt resistor, while pin 3 (VIN–) is shorted to pin 4 (GND1), with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of wires or PC board traces to connect the isolation amplifier circuit to the shunt resistor. In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting pin 3 to the negative terminal of the shunt resistor separate from the power supply return path. When connected this way, both input pins should be bypassed. Whether two or three wires are used, it is recommended that twisted-pair wire or very close PC board traces be used to connect the current shunt to the isolation amplifier circuit to minimize electromagnetic interference to the sense signal. The 68Ω resistor in series with the input lead forms a low-pass anti-aliasing filter with the input bypass capacitor with a 200 kHz bandwidth. The resistor performs another important function as well: it dampens any ringing that might be present in the circuit formed by the shunt, the input bypass capacitor, and the wires or traces connecting the two. Undampened ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device. To be effective, the damping resistor should be at least 39Ω. PC Board Layout In addition to affecting offset, the layout of the PC board can also affect the common-mode rejection (CMR) performance of the isolation amplifier, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the printed circuit board (PCB) should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground plane on the PCB does not pass directly below the HCPL-785x. Using surface-mount components can help achieve many of the PCB objectives discussed in the preceding paragraphs. An example through-hole PCB layout illustrating some of the more important layout recommendations is shown in Figure 26 and Figure 27. See Application Note 1078, Designing with Avago Technologies Isolation Amplifiers, for more information on PCB layout consideration. Figure 28 Operating Circuit for Burn-In and Steady State Life Tests 27 : VDD 2 1k VIN+ VIN– 8 1 3 4 GND VDD + – + – 1k 7 VOUT+ 6 1k 0.1 PF (+) VDD (–) 5.5 VDC VOUT– 5 GND CONDITIONS: ICC = 17.5 mA TA = +125° C Broadcom - 14 - ACPL-785E, HCPL-7850, HCPL-7851, 5962-97557 Data Sheet Post-Amplifier Circuit Post-Amplifier Circuit The post-amplifier circuit can be easily modified to allow for single-supply operation. Figure 25 shows a schematic for a post amplifier for use in 5V single supply applications. One additional resistor is needed and the gain is decreased to 1 to allow circuit operation over the full input voltage range. See Application Note 1078, Designing with Avago Technologies Isolation Amplifiers, for more information on the post-amplifier circuit. The recommended application circuit (Figure 24) includes a post-amplifier circuit that serves three functions: to reference the output signal to the desired level (usually ground), to amplify the signal to appropriate levels, and to help filter output noise. The particular op-amp used in the post-amp is not critical; however, it should have low enough offset and high enough bandwidth and slew rate so that it does not adversely affect circuit performance. The offset of the op-amp should be low relative to the output offset of the HCPL-785x, or less than about 5 mV. Other Information As mentioned above, reducing the bandwidth of the post amplifier circuit reduces the amount of output noise. Figure 22 shows how the output noise changes as a function of the post-amplifier bandwidth. The post-amplifier circuit exhibits a first-order low-pass filter characteristic. For the same filter bandwidth, a higher-order filter can achieve even better attenuation of modulation noise due to the second-order noise shaping of the sigma-delta modulator. For more information on the noise characteristics of the HCPL-785x, see Application Note 1078, Designing with Avago Technologies Isolation Amplifiers. To maintain overall circuit bandwidth, the post-amplifier circuit should have a bandwidth at least twice the minimum bandwidth of the isolation amplifier, or about 200 kHz. To obtain a bandwidth of 200 kHz with a gain of 5, the op-amp should have a gain-bandwidth greater than 1 mHz. The post-amplifier circuit includes a pair of capacitors (C5 and C6) that form a single-pole low-pass filter. These capacitors allow the bandwidth of the post-amp to be adjusted independently of the gain and are useful for reducing the output noise from the isolation amplifier (doubling the capacitor values halves the circuit bandwidth). The component values shown in Figure 24 form a differential amplifier with a gain of 5 and a cutoff frequency of approximately 100 kHz, and were chosen as a compromise between low noise and fast response times. The overall recommended application circuit has a bandwidth of 66 kHz, a rise time of 5.2 μs and a delay to 90% of 8.5 μs. The HCPL-785x can also be used to isolate signals with amplitudes larger than its recommended input range through the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 KΩ so that the input resistance (480 KΩ) and input bias current (0.6 μA) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 68Ω series damping resistor is not. (The resistance of the voltage divider provides the same function.) The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. The gain-setting resistors in the post-amp should have a tolerance of 1% or better to ensure adequate CMRR and gain tolerance for the overall circuit. Resistor networks with even better ratio tolerances can be used, which offer better performance, as well as reducing the total component count and board space. Table 1 Current Shunt Summary Shunt Resistor Part Number Shunt Resistance Maximum Power Dissipation Maximum Average Current Maximum Horsepower Range LVR-3.05-1% 50 mΩ 3W 3A 0.8 to 3.0 hp LVR-3.02-1% 20 mΩ 3W 8A 2.2 to 8.0 hp LVR-3.01-1% 10 mΩ 3W 15A 4.1 to 15 hp LVR-5.005-1% 5 mΩ 5W 35A 9.6 to 35 hp Broadcom - 15 - For product information and a complete list of distributors, please go to our web site: www.broadcom.com. Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom in the United States, certain other countries and/or the EU. Copyright © 2005-2017 Broadcom. All Rights Reserved. The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AV02-3479EN – January 6, 2017