MC74HC32A Quad 2-Input OR Gate High−Performance Silicon−Gate CMOS The MC74HC32A is identical in pinout to the LS32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. http://onsemi.com Features • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7 A Requirements Chip Complexity: 48 FETs or 12 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PIN ASSIGNMENT LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 TSSOP−14 DT SUFFIX CASE 948G SOIC−14 NB D SUFFIX CASE 751A VCC B4 A4 Y4 B3 A3 Y3 14 13 12 11 10 9 8 7 1 2 3 4 5 6 A1 B1 Y1 A2 B2 Y2 GND 14−Lead (Top View) 1 3 2 Y1 MARKING DIAGRAMS 14 14 4 6 5 HC 32A ALYWG G HC32AG AWLYWW Y2 Y = A+B 9 8 10 1 Y3 SOIC−14 NB A L, WL Y, YY W, WW G or G 12 11 13 1 Y4 PIN 14 = VCC PIN 7 = GND TSSOP−14 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Output A B Y L L H H L H L H L H H H ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 12 1 Publication Order Number: MC74HC32A/D MC74HC32A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 V DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature –65 to +150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating: SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 _C 0 0 0 1000 500 400 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 2 MC74HC32A DC CHARACTERISTICS (Voltages Referenced to GND) −55 to 25°C ≤85°C ≤125°C Unit Vout = 0.1V or VCC −0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V |Iout| ≤ 20mA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Parameter VIH Minimum High−Level Input Voltage VIL VOH Condition |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin =VIH or VIL VOL Guaranteed Limit VCC V Symbol Maximum Low−Level Output Voltage Vin = VIH or VIL |Iout| ≤ 20mA |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA Vin = VIH or VIL V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0mA 6.0 1.0 10 40 mA AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns) Symbol Parameter Guaranteed Limit VCC V −55 to 25°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 30 15 13 95 40 19 16 110 55 22 19 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns 10 10 10 pF Cin Maximum Input Capacitance Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD 20 Power Dissipation Capacitance (Per Buffer)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . http://onsemi.com 3 pF MC74HC32A tr tf VCC 90% INPUT A OR B 50% 10% GND tPLH tPHL 90% 50% 10% OUTPUT Y tTLH tTHL Figure 1. Switching Waveforms TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 2. Test Circuit A Y B Figure 3. Expanded Logic Diagram (1/4 of the Device) http://onsemi.com 4 MC74HC32A ORDERING INFORMATION Package Shipping† MC74HC32ADG SOIC−14 NB (Pb−Free) 55 Units / Rail MC74HC32ADR2G SOIC−14 NB (Pb−Free) 2500 / Tape & Reel TSSOP−14 (Pb−Free) 2500 / Tape & Reel NLV74HC32ADG* SOIC−14 NB (Pb−Free) 55 Units / Rail NLV74HC32ADR2G* SOIC−14 NB (Pb−Free) 2500 / Tape & Reel TSSOP−14 (Pb−Free) 2500 / Tape & Reel Device MC74HC32ADTR2G NLV74HC32ADTR2G* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable http://onsemi.com 5 MC74HC32A PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC32A PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE K D A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S DETAIL A h A X 45 _ M A1 e DIM A A1 A3 b D E e H h L M C SEATING PLANE MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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