AVAGO HCPL-3180-000E 2.5 amp output current, high speed, gate drive optocoupler Datasheet

HCPL-3180
2.5 Amp Output Current, High Speed, Gate Drive Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
This family of devices consists of a GaAsP LED. The LED
is optically coupled to an integrated circuit with a power
stage. These optocouplers are ideally suited for high
frequency driving of power IGBTs and MOSFETs used in
Plasma Display Panels, high performance DC/DC converters, and motor control inverter applications.
•
•
•
•
Functional Diagram
N/C
1
8 VCC
ANODE
2
7 VO
CATHODE
3
6 VO
N/C
4
SHIELD
•
•
•
•
•
•
5 VEE
A 0.1 µF bypass capacitor must be connected between pins VCC and Ground.
2.5 A maximum peak output current
2.0 A minimum peak output current
250 kHz maximum switching speed
High speed response: 200 ns maximum propagation delay over
temperature range
10 kV/µs minimum Common Mode Rejection (CMR) at VCM =
1500 V
Under Voltage Lock-Out protection (UVLO) with hysteresis
Wide operating temperature range: –40°C to 100°C
Wide VCC operating range: 10 V to 20 V
20 ns typical pulse width distortion
Safety approvals: – UL approval, 3750 Vrms for 1 minute
– CSA approval
– IEC/EN/DIN EN 60747-5-2 approval
Applications
•
•
•
•
•
•
•
Plasma Display Panel (PDP)
Distributed Power Architecture (DPA)
Switch Mode Rectifier (SMR)
High performance DC/DC converter
High performance Switching Power Supply (SPS)
High performance Uninterruptible Power Supply (UPS)
Isolated IGBT/Power MOSFET gate drive
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Ordering Information
HCPL-3180 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
HCPL-3180
RoHS
Compliant
Non RoHS
Compliant
Surface
Mount
-000E
No option
-300E
-300
-500E
-500
-060E
-060
-360E
-360
X
X
-560E
-560
X
X
Package
Gull
Wing
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2
Quantity
50 per tube
300 mil
DIP-8
X
X
X
X
50 per tube
X
1000 per reel
X
50 per tube
X
X
50 per tube
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-3180-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-3180 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE’.
Package Outline Drawings
HCPL-3180 Standard DIP Package
9.65 ± 0.25
(0.380 ± 0.010)
TYPE NUMBER
8
7
6
5
7.62 ± 0.25
(0.300 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
6.35 ± 0.25
(0.250 ± 0.010)
YYWW
1
1.19 (0.047) MAX.
2
3
4
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
2
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-3180 Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
7
8
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Solder Reflow Temperature Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
Note: Non-halide flux should be used.
3
PEAK
TEMP.
230°C
200
250
Recommended Pb-Free IR Profile
Regulatory Information
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
The HCPL-3180 has been approved by the following
organizations:
IEC/EN/DIN EN 60747-5-2
Approved under: IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
(Option 060 only)
UL
Approval under UL 1577, component recognition
program up to VISO = 3750 Vrms. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5,
File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics (HCPL-3180 Option 060)
Description
Symbol
HCPL-3180
Installation classification per DIN EN 0110 1997-04
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I - IV
I - III
I-II
Climatic Classification
55/100/21
Pollution Degree (DIN EN 0110 1997-04)
Maximum Working Insulation Voltage
Unit
2
VIORM
630
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875=VPR, 100% Production Test with
tm=1 sec, Partial Discharge < 5 pC
VPR
1181
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,
Partial Discharge < 5 pC
VPR
945
Vpeak
Highest Allowable Overvoltage
VIOTM
6000
(Transient Overvoltage tini = 10 sec)
Vpeak
Safety-limiting values – maximum values allowed in the
event of a failure.
Case Temperature
Input Current**
Output Power**
TS
IS,INPUT
PS, OUTPUT
175
230
600
°C
mA
mW
RS
>109
Ω
Insulation Resistance at TS, VIO = 500 V
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/
EN/DIN EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.
** Refer to the following figure for dependence of PS and IS on ambient temperature.
4
OUTPUT POWER – PS, INPUT CURRENT – IS
800
PS (mW)
IS (mA)
700
600
500
400
300
200
100
0
0
25
50
75
100 125 150 175 200
TS – CASE TEMPERATURE – °C
Insulation and Safety Related Specifications
Parameter
Symbol
HCPL-3180
Units
Conditions
Minimum External Air Gap
L(101)
7.1
mm
(Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
L(102)
7.4
mm
(Creepage)
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.08
mm
(Internal Clearance)
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Note: Option 300 – surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
5
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
TS
-55
125
°C
Junction Temperature
TJ
-40
125
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current
(<1 µs pulse width, 300 pps)
IF(TRAN)
1.0
A
Reverse Input Voltage
VR
5
V
“High” Peak Output Current
IOH(PEAK)
2.5
A
2
“Low” Peak Output Current
IOL(PEAK)
2.5
A
2
Supply Voltage
VCC-VEE
-0.5
25
V
Output Voltage
VO(PEAK)
0
VCC
V
Output Power Dissipation
PO
250
mW
3
Total Power Dissipation
PT
295
mW
4
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
1
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply
VCC -VEE
10
20
V
Input Current (ON)
IF(ON)
10
16
mA
Input Voltage (OFF)
VF(OFF)
- 3.6
0.8
V
Operating Temperature
TA
-40
100
°C
Note
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Parameter
Symbol
Min.
Typ.
Max.
Units
High Level Output Current
IOH
Low Level Output Current
IOL
Test
Conditions
Fig.
Note
0.5
A
VO = VCC- 4
2, 3, 17
5
2.0
A
VO = VCC-10
2, 3, 17
2
0.5
A
VO = VEE+2.5
5, 6, 18
5
2.0
A
VO = VEE+10
5, 6, 18
2
VCC-4
V
IO = -100 mA
1, 3, 19
6, 7
V
IO = 100 mA
4, 6, 20
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
0.5
High Level Supply Current
ICCH
3.0
6.0
mA
Output Open 7, 8
IF = 10 to 16 mA
Low Level Supply Current
ICCL
3.0
6.0
mA
Output Open 7, 8
VF = 3.0 to 0.8 mA
Threshold Input Current
IFLH
8.0
mA
Low to High
Threshold Input Voltage
VFHL
0.8
High to Low
V
VO > 5 V
Input Forward Voltage
VF
V
IF = 10 mA
Temperature Coefficient of
Input Forward Voltage
DVF/DTA
–1.6
mV/°C
IF = 10 mA
UVLO Threshold
VUVLO+
7.9
V
IF = 10 mA,
VUVLO–
7.4
V
VO > 5 V
UVLOHYST
0.5
V
5
V
UVLO Hysteresis
Input Reverse Breakdown
BVR
Voltage
1.2
1.5
1.8
Input Capacitance
CIN
60
pF
6
IO = 0 mA,
IR = 10 µA
f = 1 MHz,
VF = 0 V
9, 15, 21
16
22, 33
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Test
Conditions
Fig.
Note
Propagation Delay Time to
tPLH
50
150
200
ns
High Output Level
10, 11,
12, 13,
14
IF = 10 mA,
Propagation Delay Time to
tPHL
50
150
200
ns
Low Output Level
Rg = 10 Ω,
f = 250 kHz,
Pulse Width Distortion
Duty Cycle = 50%,
Parameter
Symbol
Min.
Typ.
Max.
Units
PWD
20
65
ns
14, 23
Propagation Delay
PDD
-90
90
ns
Cg = 10 nF
34, 35
Difference Between Any
(tPHL-tPLH)
Two Parts or Channels
10
10
Rise Time
tr
25
ns
CL = 1 nF,
23
Fall Time
tf
25
ns
Rg = 0 Ω
UVLO turn On Delay
tUVLO ON
2.0
µs
22
UVLO turn Off Delay
tUVLO OFF
0.3
µs
22
Output High Level Common |CMH|
10
kV/µs
Mode Transient Immunity
TA = 25°C,
24
IF = 10 to 16 mA,
11, 12
Output Low Level Common |CML|
10
kV/µs
Mode Transient Immunity
VCM = 1.5 kV,
24
VCC = 20 V
11, 13
Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Input-Output Momentary
VISO
3750
Vrms
Withstand Voltage
Test
Conditions
Fig.
Note
TA = 25°C,
RH < 50%
8,9
9
Input-Output Resistance
RI-O
10[11]
Ω
VI-O = 500 V
Input-Output Capacitance
CI-O
1
pF
Freq = 1 MHz
Notes:
1. Derate linearly above +70°C free air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above +70°C, free air temperature at the rate of 4.8 mW/°C.
4. Derate linearly above +70°C, free air temperature at the rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed
+125°C.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a dc load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 4500 Vrms for 1 second (leakage detection current limit II-O < 5 µA).
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PWD is defined as |tPHL - tPLH| for any given device.
11. Pin 1 and 4 need to be connected to LED common.
12. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse VCM to assure that the
output will remain in the high state (i.e. VO > 10.0 V).
13. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. VO < 1.0 V).
14. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the VO
signal. tPLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the
VO signal.
15. The difference between tPHL and tPLH between any two HCPL-3180 parts under same test conditions.
7
-1.5
-2.0
-2.5
-3.0
-40 -20
0
20
40
60
80
1.5
1.0
IF = 10 to 16 mA
VOUT = (VCC - 4 V)
VCC = 10 to 20 V
VEE = 0 V
0.5
0
-40 -20
100
0
0.30
3.0
0.25
2.5
0.20
0.15
0
-40
VF (OFF) = -3.0 TO 0.8 V
IOUT = 100 mA
VCC = 10 TO 20 V
VEE = 0 V
-20
0
20
40
60
80
1.0
0.5
-20
0
20
40
60
80
ICC – SUPPLY CURRENT – mA
3.0
ICCH
ICCL
2.0
1.5
VCC = 20 V
VEE = 0 V
IF = 10 mA for ICCH
IF = 0 mA for ICCL
0
20
40
60
80
TA – TEMPERATURE – °C
Figure 7. ICC vs. temperature.
IF = 10 to 16 mA
VCC = 10 to 20 V
VEE = 0 V
-5
-6
100
3.1
2.9
IF = 10 mA for ICCH
IF = 0 mA for ICCL
TA = 25 °C
VEE = 0 V
12
14
16
18
VCC – SUPPLY VOLTAGE – V
Figure 8. ICC vs. VCC.
4
3
100 °C
0 °C
25 °C
3
2
1
0
VF(OFF) = -3.0 to 0.8 V
VCC = 10 to 20 V
VEE = 0 V
0
0.5
1.0
2.0
1.5
2.5
Figure 6. VOL vs. IOL.
3.3
2.5
10
2
IOL – OUTPUT LOW CURRENT – A
ICCH
ICCL
2.7
1
0
4
100
3.5
0
-40 -20
-4
Figure 3. VOH vs. IOH.
3.5
0.5
-3
IOH – OUTPUT HIGH CURRENT – A
Figure 5. IOL vs. temperature.
2.5
100 °C
25 °C
-40 °C
-2
TA – TEMPERATURE – °C
4.0
1.0
100
1.5
0
-40
100
Figure 4. VOL vs. temperature.
ICC – SUPPLY CURRENT – mA
80
VF (OFF) = -3.0 TO 0.8 V
VOUT = 2.5 V
VCC = 10 TO 20 V
VEE = 0 V
2.0
TA – TEMPERATURE – °C
8
60
Figure 2. IOH vs. temperature.
IOL – OUTPUT LOW CURRENT – A
VOL – OUTPUT LOW VOLTAGE – V
Figure 1. VOH vs. temperature.
0.05
40
-1
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
0.10
20
VOL – OUTPUT LOW VOLTAGE – V
-1.0
2.0
20
IFLH – LOW TO HIGH CURRENT THRESHOLD – mA
-0.5
(VOH – VCC) – OUTPUT HIGH VOLTAGE DROP – V
2.5
IF = 10 to 16 mA
IOUT = -100 mA
VCC = 10 to 20 V
VEE = 0 V
IOH – OUTPUT HIGH CURRENT – A
(VOH – VCC) – HIGH OUTPUT VOLTAGE DROP – V
0
5
4
3
2
VCC = 10 to 20 V
VEE = 0 V
OUTPUT = OPEN
1
0
-40
-20
0
20
40
60
TA – TEMPERATURE – °C
Figure 9. IFLH vs. temperature.
80
100
tPHL
tPLH
150
100
50
10
200
150
100
tPLH
tPHL
50
25
20
15
VCC = 20 V, VEE = 0 V
Rg = 10 Ω, Cg = 10 nF
TA = 25 °C
f = 250 kHz
DUTY CYCLE = 50%
6
VCC – SUPPLY VOLTAGE – V
150
100
tPLH
tPHL
10
30
20
40
50
Figure 13. Propagation delay vs. Rg.
1000
IF
+
VF
–
10
1.0
0.1
0.01
0.001
1.10
1.20
1.30
1.40
1.50
VF – FORWARD VOLTAGE – VOLTS
Figure 16. Input current vs. forward voltage.
150
100
tPHL
tPLH
-40 -20
0
1.60
40
60
80
100
Figure 12. Propagation delay vs. temperature.
20
200
150
100
tPHL
tPLH
50
20
TA – TEMPERATURE – °C
IF = 10 mA
TA = 25°C
Rg = 10 Ω�
f = 250 kHz
Cg = 10 nF
DUTY CYCLE = 50%
5
10
15
20
Cg – LOAD CAPACITANCE – nF
Figure 14. Propagation delay vs. Cg.
TA = 25°C
100
200
50
16
VO – OUTPUT VOLTAGE – V
200
tp – PROPAGATION DELAY – ns
tp – PROPAGATION DELAY – ns
14
250
IF = 10 mA
TA = 25°C
f = 250 kHz
Cg = 10 nF
DUTY CYCLE = 50%
Rg – SERIES LOAD RESISTANCE – Ω
IF – FORWARD CURRENT – mA
12
10
Figure 11. Propagation delay vs. IF.
250
9
8
IF = 10 mA
VCC = 20 V, VEE = 0 V
Rg = 10 Ω, Cg = 10 nF
f = 250 kHz
DUTY CYCLE = 50%
IF – FORWARD LED CURRENT – mA
Figure 10. Propagation delay vs. VCC.
50
tp – PROPAGATION DELAY – ns
200
250
250
IF = 10 mA
TA = 25°C
Rg = 10 Ω
Cg = 10 nF
DUTY CYCLE = 50%
f = 250 kHz
tp – PROPAGATION DELAY – ns
tp – PROPAGATION DELAY – ns
250
25
15
10
5
0
0
1
2
3
4
IF – FORWARD LED CURRENT – mA
Figure 15. Transfer characteristics.
5
1
8
1
8
0.1 µF
2
0.1 µF
+ 4 V/10
–
7
IF = 10 to
16 mA
2
+
–
3
+ VCC = 10
–
to 20 V
VCC = 10
to 20 V
6
IOH
4
IOL
7
5
Figure 17. IOH test circuit.
3
6
4
5
2.5 V/10 V
Figure 18. IOL test circuit.
1
8
1
8
2
7
0.1 µF
0.1 µF
2
7
VOH
IF = 10 to
16 mA
+
–
3
100 mA
+ VCC = 10
–
to 20 V
VCC = 10
to 20 V
6
3
6
4
5
VOL
100 mA
4
5
Figure 19. VOH test circuit.
1
Figure 20. VOL test circuit.
8
1
8
2
7
3
6
4
5
0.1 µF
2
10
0.1 µF
7
IF
3
6
4
5
Figure 21. IFLH test circuit.
+
–
VO > 5 V
+ VCC = 10
–
to 20 V
IF = 10 mA
Figure 22. UVLO test circuit.
VO > 5 V
+
–
VCC
1
8
2
7
+
250 KHz –
500 Ω
50% DUTY
CYCLE
IF
0.1 µF
IF = 10 to 16 mA
+
–
VCC = 20 V
tr
tf
VO
3
90%
10 Ω
6
50%
VOUT
10 nF
4
10%
5
tPLH
tPHL
Figure 23. tPLH, tPHL, tr and tf test circuit and waveform.
VCM
1
IF
δV
8
0.1 µF
A
B
2
VO
3
6
4
5
=
VCM
∆t
0V
7
+
–
5V
δt
+
–
∆t
VCC = 20 V
VOH
VO
SWITCH AT A: IF = 10 mA
VO
VOL
+
–
SWITCH AT B: IF = 0 mA
VCM = 1500 V
Figure 24. CMR test circuit and waveform.
Applications Information Eliminating Negative IGBT Gate
Drive
negative IGBT gate drive in many applications as shown
in Figure 25. Care should be taken with such a PC board
design to avoid routing the IGBT collector or emitter
traces close to the HCPL-3180 input as this can result in
unwanted coupling of transient signals into the input of
HCPL-3180 and degrade performance.
To keep the IGBT firmly off, the HCPL-3180 has a very
low maximum VOL specification of 0.4 V. The HCPL-3180
realizes the very low VOL by using a DMOS transistor with
1 W (typical) on resistance in its pull down circuit. When
the HCPL-3180 is in the low state, the IGBT gate is shorted
to the emitter by Rg + 1 W. Minimizing Rg and the lead
inductance from the HCPL-3180 to the IGBT gate and
emitter (possibly by mounting HCPL-3180 on a small PC
board directly above the IGBT) can eliminate the need for
(If the IGBT drain must be routed near the HCPL-3180
input, then the LED should be reverse biased when in the
off state to prevent the transient signals coupled from the
IGBT drain from turning on the HCPL-3180.)
+5 V
1
8
270 Ω
0.1 µF
2
+
–
VCC = 15 V
+ HVDC
7
Rg
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
3
6
4
5
Figure 25. Recommended LED drive and application circuit for HCPL-3180.
11
Q1
3-PHASE
AC
Q2
- HVDC
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and
Rg in Figure 25 can be analyzed as a simple RC circuit with a voltage supplied
by the HCPL-3180.
VCC – VOL
IOLPEAK
Rg ≥
20 – 3
2
=
= 8.5 Ω
The VOL value of 3 V in the previous equation is the VOL at the peak current of
2 A. (See Figure 6.)
Step 2: Check the HCPL-3180 power dissipation and increase Rg if necessary.
The HCPL-3180 total power dissipation (PT ) is equal to the sum of the emitter
power (PE) and the output power (PO).
PT = PE + PO
PE = IF * VF * Duty Cycle
PO = PO(BIAS) + PO(SWITCHING)
= ICC * VCC + ESW (Rg;Qg) * f
For the circuit in Figure 25 with IF (worst case) = 16 mA, Rg = 10 Ω, Max Duty
Cycle = 80%, Qg = 100 nC, f = 200 kHz and TAMAX = +75°C:
PE = 16 mA * 1.8 V * 0.8 = 23 mW
PO = 4.5 mA * 20 V + 0.85 µ * 200 kHz
= 260 mW ≥ 226 mW (PO(MAX) @ 75°C = 250 mW (5°C * 4.8 mW/°C))
The value of 4.5 mA for ICC in the previous equation was obtained by derating
the ICC max of 6 mA to ICC max at +75°C. Since PO for this case is greater than
the PO(MAX), Rg must be increased to reduce the HCPL-3180 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) – PO(BIAS)
= 226 mW – 90 mW
= 136 mW
ESW(MAX)
= PO(SWITCHING MAX)
f
= 136 mW 200 kHz
= 0.68 µW
For Qg = 100 nC, a value of Esw = 0.68 µW gives a Rg = 15 W.
12
Esw – ENERGY PER SWITCHING CYCLE – µJ
Selecting the Gate Resistor (Rg) for HCPL-3180
2.0
1.8
Qg = 100 nC
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
Rg — GATE RESISTANCE — Ω
Figure 26. Energy dissipated in the HCPL-3180 and for
each IGBT.
Thermal Model
(Discussion applies to HCPL-3180)
The steady state thermal model for the HCPL-3180 is
shown in Figure 27. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through qCA which
raises the case temperature TC accordingly. The value of
qCA depends on the conditions of the board design and
is, therefore, determined by the designer. The value of
TJE = PE * (qLC//qLD + qDC) + qCA) + PD *
TJD = PE *
[
qCA = +83 °C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces
(no ground plane), a single HCPL- 3180 soldered into the
center of the board and still air. The absolute maximum
power dissipation derating specifications assume a qCA
value of +83 °C/W. From the thermal mode in Figure 27,
the LED and detector IC junction temperatures can be
expressed as:
qLC * qDC
+q
+ TA
qLC + qDC + qLD CA
]
* qDC
[ qLCq+LCqDC
+ q ] + PD * (qLC//qLD + qDC) + qCA) + TA
+ qLD CA
θLD = 442 °C/W
TJE
TJD
θLC = 467 °C/W
θDC = 126 °C/W
TC
θCA = 83 °C/W*
TA
TJE = LED JUNCTION TEMPERATURE
TJD = DETECTOR IC JUNCTION TEMPERATURE
TC = CASE TEMPERATURE MEASURED AT THE
CENTER OF THE PACKAGE BOTTOM
θLC = LED-TO-CASE THERMAL RESISTANCE
θLD = LED-TO-DETECTOR THERMAL RESISTANCE
θDC = DETECTOR-TO-CASE THERMAL RESISTANCE
θCA = CASE-TO-AMBIENT THERMAL RESISTANCE
*θCA WILL DEPEND ON THE BOARD DESIGN AND
THE PLACEMENT OF THE PART.
Figure 27. Thermal model.
TJE = PE * (256°C/W + qCA) + PD * (57°C/W + qCA) + TA
TJD = PE * (57°C/W + qCA) + PD * (111°C/W + qCA) + TA
For example, given PE = 45 mW,
PO = 250 mW, TA = +70 °C and qCA = +83 °C/W:
TJE = PE * 339°C/W + PD * 140°C/W + TA
= 45 mW * 339°C/W + 250 mW * 140°C/W + 70°C
= 120°C
TJD = PE * 140°C/W + PD * 194°C/W + TA
= 45 mW * 140°C/W + 250 mW * 194°C/W + 70°C
= 125°C
TJE and TJD should be limited to +125 °C based on the board layout and part
placement (qCA) specific to the application.
13
LED Drive Circuit Considerations for Ultra High CMR Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 28. The HCPL-3180
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 29. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode transients. For example, the recommended application circuit
(Figure 25), can achieve 10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are discussed in the next two sections.
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on
during common mode transients. This is achieved by
over-driving the LED current beyond the input threshold
so that it is not pulled below the threshold during a
transient. A minimum LED current of 10 mA provides
adequate margin over the maximum IFLH of 8 mA to achieve 10 kV/µs CMR.
+5 V
1
+
VSAT
–
2
8
0.1
µF
CLEDP
7
+
–
VCC = 20 V
ILEDP
3
4
6
CLEDN
SHIELD
5
•••
Rg
•••
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
+ –
VCM
Figure 30. Equivalent circuit for Figure 25 during common mode transient.
1
2
3
8
CLEDP
7
6
CLEDN
4
5
Figure 28. Optocoupler input to output capacitance model for
unshielded optocouplers.
1
2
8
CLEDO1
CLEDP
7
CLEDO2
3
4
CLEDN
SHIELD
6
5
Figure 29. Optocoupler input to output capacitance model for
shielded optocouplers.
14
CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off (VF
≤ VF(OFF)) during common mode transients. For example,
during a -dVCM/dt transient in Figure 30, the current
flowing through CLEDP also flows through the RSAT and
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than VF(OFF), the
LED will remain off and no common mode failure will
occur.
The open collector drive circuit, shown in Figure 31,
cannot keep the LED off during a +dVCM/dt transient,
since all the current flowing through CLEDN must be
supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure
32 is an alternative drive circuit, which like the recommended application circuit (Figure 25), does achieve
ultra high CMR performance by shunting the LED in the
off state.
1
8
+5 V
CLEDP
2
3
Q1
1
8
+5 V
CLEDN
7
2
6
3
5
4
CLEDP
7
6
CLEDN
ILEDN
4
SHIELD
5
SHIELD
Figure 31. Not recommended open collector drive circuit.
Figure 32. Recommended LED drive circuit for ultra-high CMR.
Under Voltage Lockout Feature
IPM Dead Time and Propagation Delay Specifications
The HCPL-3180 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3180 supply voltage
(equivalent to the fully charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the HCPL-3180 output is in the
high state and the supply voltage drops below the HCPL3180 VUVLO- threshold (typ 7.5 V) the optocoupler output
will go into the low state. When the HCPL-3180 output is
in the low state and the supply voltage rises above the
HCPL-3180 VUVLO+ threshold (typ 8.5 V) the optocoupler
output will go into the high state (assume LED is “ON”).
The HCPL-3180 includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time is
the time during which the high and low side power transistors are off. Any overlap in Q1 and Q2 conduction will
result in large currents flowing through the power devices
from the high voltage to the low-voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 34. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is
specified to be 90 ns over the operating temperature
range of -40 °C to +100 °C.
ILED1
VOUT1
20
Q1 ON
Q1 OFF
VO – OUTPUT VOLTAGE – V
18
16
Q2 ON
14
VOUT2
12
10
ILED2
8
6
Q2 OFF
tPHL MAX
tPLH MIN
4
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
2
0
0
5
10
15
(VCC - VEE) – SUPPLY VOLTAGE – V
Figure 33. Under voltage lock out.
20
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS, THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 34. Minimum LED skew for zero dead time.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specification as shown in
Figure 35. The maximum dead time for the HCPL-3180 is
180 ns (= 90 ns-(- 90 ns)) over the operating temperature
range of –40 °C to +100 °C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other
and are switching identical IGBTs.
ILED1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
Q2 OFF
ILED2
tPHL MIN
tPHL MAX
tPLH
MIN
tPLH MAX
(tPHL-tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS, ALL PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Figure 35. Waveforms for dead time.
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Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-0165EN - March 10, 2009