ON LC75829PE Lcd display driver Datasheet

Ordering number : ENA1462
LC75829PE
LC75829PW
http://onsemi.com
CMOS IC
1/4 and 1/3-Duty General-Purpose
LCD Display Driver
Overview
The LC75829PE and LC75829PW are 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD drivers
that can be used in applications such as frequency display in products with electronic tuning.
In addition to being able to drive up to 208 segments directly, the LC75829PE and LC75829PW can also control up
to 4 general-purpose output ports. Incorporation of an oscillation circuit helps to reduce the number of external
resistors and capacitors required.
Features
• Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control.
When 1/4-duty: Capable of driving up to 208 segments
When 1/3-duty: Capable of driving up to 159 segments
• Serial data input supports CCB format communication with the system controller. (Support 3.3V and 5V operation)
• Serial data control of the power-saving mode based backup function and the all segments forced off function.
• Serial data control of switching between the segment output port and general-purpose output port function.
(Support for up to 4 general-purpose output ports)
• Support for clock output function of 1ch.
• Serial data control of the frame frequency of the common and segment output waveforms.
• Serial data control of switching between the internal oscillator operating mode and external clock operating mode.
• High generality, since display data is displayed directly without the intervention of a decoder circuit.
• The INH pin allows the display to be forced to the off state.
• Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation)
•
•
CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
52709HKIM 20090421-S00013,20090421-S00010 No.A1462-1/22
LC75829PE, 75829PW
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Symbol
Maximum supply voltage
Conditions
VDD max
Input voltage
Ratings
VDD
Unit
-0.3 to +6.5
V
VIN1
CE, CL, DI, INH
VIN2
OSCI, VDD1, VDD2
-0.3 to VDD+0.3
Output voltage
VOUT
S1 to S53, COM1 to COM4, P1 to P4
-0.3 to VDD+0.3
V
Output current
IOUT1
S1 to S52
300
μA
IOUT2
COM1 to COM4, S53
3
IOUT3
P1 to P4
5
Pd max
Ta=85°C
Allowable power dissipation
-0.3 to +6.5
V
mA
200
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply voltage
VDD
VDD
Input voltage
VDD1
VDD1
2/3VDD
VDD
VDD2
VDD2
1/3VDD
VDD
VIH1
CE, CL, DI, INH
0.4VDD
6.0
VIH2
OSCI: External clock operating mode
0.4VDD
VDD
Input high-level voltage
Input low-level voltage
4.5
6.0
V
V
V
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSCI: External clock operating mode
0
0.2VDD
External clock operating frequency
fCK
OSCI: External clock operating mode [Figure 4]
10
300
600
kHz
External clock duty cycle
DCK
OSCI: External clock operating mode [Figure 4]
30
50
70
%
V
Data setup time
tds
CL, DI
[Figure 2][Figure 3]
160
ns
Data hold time
tdh
CL, DI
[Figure 2][Figure 3]
160
ns
CE wait time
tcp
CE, CL
[Figure 2][Figure 3]
160
ns
CE setup time
tcs
CE, CL
[Figure 2][Figure 3]
160
ns
CE hold time
tch
CE, CL
[Figure 2][Figure 3]
160
ns
High-level clock pulse width
tφH
CL
[Figure 2][Figure 3]
160
ns
Low-level clock pulse width
tφL
CL
[Figure 2][Figure 3]
160
ns
Rise time
tr
CE, CL, DI
[Figure 2][Figure 3]
160
Fall time
tf
CE, CL, DI
[Figure 2][Figure 3]
160
INH switching time
tc
INH, CE
[Figure 5][Figure 6]
10
ns
ns
μs
No.A1462-2/22
LC75829PE, 75829PW
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Ratings
Conditions
min
typ
Unit
max
Hysteresis
VH
CE, CL, DI, INH
Input high-level current
IIH1
CE, CL, DI, INH
VI = 6.0V
5.0
IIH2
OSCI
VI = VDD: External clock operating mode
5.0
IIL1
CE, CL, DI, INH
VI = 0V
-5.0
IIL2
OSCI
VI = 0V: External clock operating mode
-5.0
Input low-level current
Output high-level voltage
0.03VDD
VOH1
S1 to S53
IO = -20μA
VOH2
COM1
IO = -100μA
VOH3
P1 to P4
IO = -1mA
VOL1
S1 to S53
IO = 20μA
VOL2
COM1
IO = 100μA
μA
V
VDD-0.9
VDD-0.9
0.9
0.9
to COM4
Output middle-level
VOL3
P1 to P4
IO =1mA
VMID1
S1 to S53
1/3 bias IO = ±20μA
2/3VDD
-0.9
+0.9
VMID2
S1 to S53
1/3 bias IO = ±20μA
1/3VDD
1/3VDD
-0.9
+0.9
VMID3
COM1
1/3 bias IO = ±100μA
2/3VDD
2/3VDD
-0.9
+0.9
VMID4
COM1
1/3 bias IO = ±100μA
1/3VDD
1/3VDD
-0.9
+0.9
to COM4
to COM4
fosc
Internal
Internal oscillator operating mode
oscillator circuit
Current drain
V
0.9
voltage *1
Oscillator frequency
μA
VDD-0.9
to COM4
Output low-level voltage
V
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD = 6.0V
Output open
240
2/3VDD
300
360
V
kHz
100
800
1600
Internal oscillator operating mode
IDD3
VDD
VDD = 6.0V
Output open
μA
External clock operating mode
fCK = 300kHz
800
1600
VIH2 = 0.5VDD
VIL2 = 0.1VDD
Note: *1 Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.)
VDD
VDD1
To the common and segment drivers
VDD2
Except these resistors.
VSS
[Figure 1]
No.A1462-3/22
LC75829PE, 75829PW
1. When CL is stopped at the low level
≈
VIH1
CE
CL
≈ ≈
tφH
tφL
tf
DI
tcp
≈ ≈
VIH1
VIL1
tds
≈ ≈ ≈
VIH1
50%
VIL1
tr
VIL1
tcs
tch
tdh
[Figure 2]
2. When CL is stopped at the high level
≈
VIH1
CE
≈
VIL1
tφH
≈
tφL
tf
tr
tcp
tcs
≈ ≈
≈ ≈ ≈
VIH1
50%
VIL1
CL
VIH1
DI
VIL1
tds
tch
tdh
[Figure 3]
3. OSCI pin clock timing in external clock operating mode
tCKH
OSCI
VIH2
50%
VIL2
tCKL
fCK=
1
tCKH+ tCKL
[kHz]
tCKH
×100[%]
DCK=
tCKH+ tCKL
[Figure 4]
No.A1462-4/22
LC75829PE, 75829PW
Package Dimensions
Package Dimensions
unit : mm (typ)
3159A
unit : mm (typ)
3190A
[LC75829PE]
17.2
14.0
12.0
48
32
64
17
17.2
14.0
64
49
10.0
32
49
1
17
1
33
12.0
33
0.5
10.0
0.8
48
16
0.5
0.15
0.18
(1.25)
16
0.35
0.15
(1.5)
0.8
[LC75829PW]
3.0max
0.1
(2.7)
1.7max
(1.0)
0.1
SANYO : SQFP64(10X10)
SANYO : QIP64E(14X14)
S34
S33
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
Pin Assignment
48
33
49
32
S49
S32
S50
S31
S51/COM4
S30
COM3
COM2
S29
S28
COM1
S27
LC75829PE
(QIP64E)
LC75829PW
(SQFP64)
S52
VDD
VDD1
VDD2
S26
S25
S24
S23
VSS
S53/OSCI
INH
S22
CE
S19
CL
DI
S18
S17
S21
S20
64
17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
P4/S4
P3/S3
P2/S2
16
P1/S1
1
Top view
No.A1462-5/22
LC75829PE, 75829PW
COMMON
DRIVER
S1/P1
S2/P2
S3/P3
S4/P4
S5
S50
S52
COM3
COM4/S51
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
S53/OSCI
CLOCK
GENERATOR
CONTROL
REGISTER
VDD
SHIFT REGISTER
VDD1
VDD2
CCB INTERFACE
CE
CL
DI
VSS
No.A1462-6/22
LC75829PE, 75829PW
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1/P1 to S4/P4
1 to 4
S5 to S50
5 to 50
S52
55
COM1 to COM3
54 to 52
COM4/S51
51
S53/OSCI
60
CE
62
CL
63
DI
64
Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.
-
O
OPEN
-
O
OPEN
-
I/O
OPEN
Common driver outputs
The frame frequency is fo[Hz].
The COM4/S51 pin can be used as a segment output in 1/3 duty.
Segment output. This pin can also be used as the external clock input pin when the
external clock operating mode is selected by control data.
Serial data transfer inputs. Must be connected to the controller.
H
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
I
I
GND
-
I
L
I
GND
Display off control input
• INH = low (VSS) ...Display forced off
S1/P1 to S4/P4 = low (VSS)
(These pins are forcibly set to the general-purpose output port
function and held at the VSS level.)
S9 to S50, S52=low (VSS)
COM1 to COM3=low (VSS)
COM4/S51=low (VSS)
S53/OSCI=low (VSS)
INH
61
(This pin is forcibly set to the segment output port function and
held at the VSS level.)
Stops the internal oscillator.
Inhibits external clock input.
• INH = high (VDD)...Display on
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
However, serial data transfer is possible when the display is forced off.
VDD1
57
Used to apply the LCD drive 2/3 bias voltage externally.
-
I
OPEN
VDD2
58
Used to apply the LCD drive 1/3 bias voltage externally.
-
I
OPEN
VDD
56
Power supply pin. A power voltage of 4.5 to 6.0V must be applied to this pin.
-
-
-
VSS
59
Ground pin. Must be connected to ground.
-
-
-
No.A1462-7/22
LC75829PE, 75829PW
Serial Data Input
1. 1/4 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
18 bits
Display data
52 bits
CCB address
8 bits
1
0 D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
52 bits
1
0 D105 D106
D151 D152 0
Fixed data
18 bits
0
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
48 bits
1
0 D153 D154
Fixed data
22 bits
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
56 bits
Fixed data
14 bits
DD
2 bits
Note: DD is the direction data.
No.A1462-8/22
LC75829PE, 75829PW
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
18 bits
Display data
52 bits
CCB address
8 bits
1
0
D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
52 bits
1
0
D105 D106
D151 D152 0
Fixed data
18 bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
48 bits
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
D153 D154
Fixed data
22 bits
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
Display data
56 bits
0
0
0
DD
2 bits
0
0
0
0
0
0
0
0
0
0
Fixed data
14 bits
1
1
DD
2 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D208 ............ Display data
• PS10, PS11 ............ General-purpose output port (P1) function setting control data
• EXF ....................... External clock operating frequency setting control data
• P0 to P2 ................. Segment output port/general-purpose output port switching control data
• DT ......................... 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• DN ......................... S52 pin and S53/OSCI pin state setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off control data
• BU ......................... Normal mode/power-saving mode control data
No.A1462-9/22
LC75829PE, 75829PW
2. 1/3 duty
(1) When CL is stopped at the low level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
16 bits
Display data
54 bits
CCB address
8 bits
1
0 D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
54 bits
1
0
D109 D110
D155 D156 D157 D158 D159 0
Fixed data
16 bits
0
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
No.A1462-10/22
LC75829PE, 75829PW
(2) When CL is stopped at the high level
CE
CL
DI
1
0
0
0
0
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
Control data
16 bits
Display data
54 bits
CCB address
8 bits
1
0
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
1
0
0
0
0
0
Display data
54 bits
1
0
D109 D110
D155 D156 D157 D158 D159 0
Fixed data
16 bits
0
0
0
0
0
0
0
0
0
0
0
DD
2 bits
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
51 bits
Fixed data
19 bits
DD
2 bits
Note: DD is the direction data.
• CCB address .......... “41H”
• D1 to D159 ............ Display data
• PS10, PS11 ............ General-purpose output port (P1) function setting control data
• EXF ....................... External clock operating frequency setting control data
• P0 to P2 ................. Segment output port/general-purpose output port switching control data
• DT ......................... 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
• DN ......................... S52 pin and S53/OSCI pin state setting control data
• FC0 to FC2 ............ Common/segment output waveform frame frequency control data
• OC ......................... Internal oscillator operating mode/external clock operating mode switching control data
• SC .......................... Segment on/off control data
• BU ......................... Normal mode/power-saving mode control data
No.A1462-11/22
LC75829PE, 75829PW
Serial Data Transfer Example
1. 1/4 duty
• When 153 or more segments are used
All 288 bits of serial data must be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
D53 D54
D99 D100 D101 D102 D103 D104 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D105 D106
D151 D152 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
D153 D154
D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 153 segments are used
Either 72, 144, or 216 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D52 display data and the control data) must always be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 0
0
0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
2. 1/3 duty
• When 109 or more segments are used
All 216 bits of serial data must be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
D55 D56
D101 D102 D103 D104 D105 D106 D107 D108 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D109 D110
D155 D156 D157 D158 D159 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
1
0
0
0
0
0
1
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 109 segments are used
Either 72, or 144 bits of serial data must be sent, depending on the number of segments to be used.
However, the serial data shown below (the D1 to D54 display data and the control data) must always be sent.
8 bits
1
0
0
0
0
72 bits
0
1
0
D1 D2
D47 D48 D49 D50 D51 D52 D53 D54 0
0 PS10 PS11 EXF P0 P1 P2 DT DN FC0 FC1 FC2 OC SC BU 0
0
B0 B1 B2 B3 A0 A1 A2 A3
No.A1462-12/22
LC75829PE, 75829PW
Control Data Functions
(1) PS10 and PS11 … General-purpose output port (P1) function setting control data
These control data bits set the clock output or general-purpose output function (High or low level output) of the P1
output pin.
PS10
PS11
General-purpose output port (P1) function
0
0
General-purpose output function (High or low level output)
1
0
Clock output function (Clock frequency : fosc/2, fCK/2)
0
1
Clock output function (Clock frequency : fosc/8, fCK/8)
Note: When is setting (PS10, PS11)=(1,1), the P1 output pin selects the general-purpose output function
(High or low level output).
(2) EXF … External clock operating frequency setting control data
This control data sets the operating frequency of the external clock which input into the OSCI pin, when the external
clock operating mode (OC=”1”) is set. However, this data is effective only when external clock operating mode
(OC= "1") is set.
EXF
External clock operating frequency fCK[kHz]
0
fCK1=300[kHz]typ
1
fCK2=38[kHz]typ
(3) P0 to P2 … Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4
output pins.
Control data
Output pin state
P0
P1
P2
S1/P1
S2/P2
S3/P3
S4/P4
0
0
0
S1
S2
S3
S4
0
0
1
P1
S2
S3
S4
0
1
0
P1
P2
S3
S4
0
1
1
P1
P2
P3
S4
1
0
0
P1
P2
P3
P4
Note: Sn (n=1 to 4): Segment output ports
Pn (n=1 to 4): General-purpose output ports
Note: When are setting (P0,P1,P2)=(1,0,1), (1,1,0), and (1,1,1), the all P1/S1 to P4/S4 output pins selects the
segment output port.
The table below lists the correspondence between the display data and the output pins when these pins are selected
to be general-purpose output ports.
Correspondence display data
Output pin
1/4 duty
1/3 duty
S1/P1
D1
D1
S2/P2
D5
D4
S3/P3
D9
D7
S4/P4
D13
D10
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port, the S4/P4 output pin will output a high level (VDD) when the display data D13 is 1, and will output a low level
(VSS) when D13 is 0.
(4) DT … 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data
This control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive.
DT
Drive scheme
The COM4/S51 pin state
0
1/4-duty 1/3-bias drive
COM4
1
1/3-duty 1/3-bias drive
S51
Note: COM4: Common output
S51
: Segment output
No.A1462-13/22
LC75829PE, 75829PW
(5) DN … S52 pin and S53/OSCI pin state setting control data
This control data bit sets state of the S52 pin and the S53/OSCI pin.
Number of display segments
DN
Pin state
1/4 duty
1/3 duty
S52
S53/OSCI
0
Up to 200 segments
Up to 153 segments
“L” (VSS)
“L” (VSS)/OSCI
1
Up to 208 segments
Up to 159 segments
S52
S53/OSCI
Note: “L” (VSS)
: Low (VSS) level output
S52
: Segment output
“L” (VSS)/OSCI : Low (VSS) level output in internal oscillator operating mode (OC=0)
: External clock input in external clock operating mode (OC=1)
S53/OSCI
: Segment output in internal oscillator operating mode (OC=0)
External clock input in external clock operating mode (OC=1)
(6) FC0 to FC2 … Common/segment output waveform fram frequency control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
FC0
FC1
Frame frequency fo[Hz]
FC2
Internal oscillator operating mode
External clock operating mode
(The control data OC is 0,
(The control data OC is 1
(The control data OC is 1
fosc=300[kHz]typ)
and EXF is 0, fCK1=300[kHz]typ)
and EXF is 1, fCK2=38[kHz]typ)
External clock operating mode
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
(7) OC … Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
OC
Fundamental clock operating mode
I/O pin (S53/OSCI) state
0
Internal oscillator operating mode
S53
1
External clock operating mode
OSCI
Note: S53: Segment output
OSCI: External clock input
(8) SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
(9) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
0
Mode
Normal mode
Power saving mode
In this mode, the internal oscillator circuit stops oscillation (the S53/OSCI pin is configured for segment
output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external
1
clock signals (the S53/OSCI pin is configured for external clock input) if the IC is in the external clock
operating mode (OC=1). The common and segment output pins go to the VSS level. However, the S1/P1
to S4/P4 output pins can be used as general-purpose output ports under the control of the data bits P0 to
P2. (The general-purpose output port P1 can not be used as clock output).
No.A1462-14/22
LC75829PE, 75829PW
Display Data and Output Pin Correspondence (1/4 Duty)
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
S1/P1
D1
D2
D3
D4
S27
D105
D106
D107
D108
S2/P2
D5
D6
D7
D8
S28
D109
D110
D111
D112
S3/P3
D9
D10
D11
D12
S29
D113
D114
D115
D116
S4/P4
D13
D14
D15
D16
S30
D117
D118
D119
D120
S5
D17
D18
D19
D20
S31
D121
D122
D123
D124
S6
D21
D22
D23
D24
S32
D125
D126
D127
D128
S7
D25
D26
D27
D28
S33
D129
D130
D131
D132
S8
D29
D30
D31
D32
S34
D133
D134
D135
D136
S9
D33
D34
D35
D36
S35
D137
D138
D139
D140
S10
D37
D38
D39
D40
S36
D141
D142
D143
D144
S11
D41
D42
D43
D44
S37
D145
D146
D147
D148
S12
D45
D46
D47
D48
S38
D149
D150
D151
D152
S13
D49
D50
D51
D52
S39
D153
D154
D155
D156
S14
D53
D54
D55
D56
S40
D157
D158
D159
D160
S15
D57
D58
D59
D60
S41
D161
D162
D163
D164
S16
D61
D62
D63
D64
S42
D165
D166
D167
D168
S17
D65
D66
D67
D68
S43
D169
D170
D171
D172
S18
D69
D70
D71
D72
S44
D173
D174
D175
D176
S19
D73
D74
D75
D76
S45
D177
D178
D179
D180
S20
D77
D78
D79
D80
S46
D181
D182
D183
D184
S21
D81
D82
D83
D84
S47
D185
D186
D187
D188
S22
D85
D86
D87
D88
S48
D189
D190
D191
D192
S23
D89
D90
D91
D92
S49
D193
D194
D195
D196
S24
D93
D94
D95
D96
S50
D197
D198
D199
D200
S25
D97
D98
D99
D100
S52
D201
D202
D203
D204
S26
D101
D102
D103
D104
S53/OSCI
D205
D206
D207
D208
Note: This table assumes that pins S1/P1 to S4/P4 and S53/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D81
D82
D83
D84
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
0
0
0
1
The LCD segment corresponding to COM4 is on.
0
0
1
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
The LCD segments corresponding to COM3 and COM4 are on.
0
1
0
0
The LCD segment corresponding to COM2 is on.
0
1
0
1
The LCD segments corresponding to COM2 and COM4 are on.
0
1
1
0
The LCD segments corresponding to COM2 and COM3 are on.
0
1
1
1
The LCD segments corresponding to COM2, COM3, and COM4 are on.
1
0
0
0
The LCD segment corresponding to COM1 is on.
1
0
0
1
The LCD segments corresponding to COM1 and COM4 are on.
1
0
1
0
The LCD segments corresponding to COM1 and COM3 are on.
1
0
1
1
The LCD segments corresponding to COM1, COM3, and COM4 are on.
1
1
0
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
0
1
The LCD segments corresponding to COM1, COM2, and COM4 are on.
1
1
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
No.A1462-15/22
LC75829PE, 75829PW
Display Data and Output Pin Correspondence (1/3 Duty)
Output pin
COM1
COM2
COM3
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
S28
D82
D83
D84
S2/P2
D4
D5
D6
S29
D85
D86
D87
S3/P3
D7
D8
D9
S30
D88
D89
D90
S4/P4
D10
D11
D12
S31
D91
D92
D93
S5
D13
D14
D15
S32
D94
D95
D96
S6
D16
D17
D18
S33
D97
D98
D99
S7
D19
D20
D21
S34
D100
D101
D102
S8
D22
D23
D24
S35
D103
D104
D105
S9
D25
D26
D27
S36
D106
D107
D108
S10
D28
D29
D30
S37
D109
D110
D111
S11
D31
D32
D33
S38
D112
D113
D114
S12
D34
D35
D36
S39
D115
D116
D117
S13
D37
D38
D39
S40
D118
D119
D120
S14
D40
D41
D42
S41
D121
D122
D123
S15
D43
D44
D45
S42
D124
D125
D126
S16
D46
D47
D48
S43
D127
D128
D129
S17
D49
D50
D51
S44
D130
D131
D132
S18
D52
D53
D54
S45
D133
D134
D135
S19
D55
D56
D57
S46
D136
D137
D138
S20
D58
D59
D60
S47
D139
D140
D141
S21
D61
D62
D63
S48
D142
D143
D144
S22
D64
D65
D66
S49
D145
D146
D147
S23
D67
D68
D69
S50
D148
D149
D150
S24
D70
D71
D72
S51/COM4
D151
D152
D153
S25
D73
D74
D75
S52
D154
D155
D156
S26
D76
D77
D78
S53/OSCI
D157
D158
D159
S27
D79
D80
D81
Note: This table assumes that pins S1/P1 to S4/P4, S51/COM4, and S53/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Output pin (S21) state
D61
D62
D63
0
0
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
0
0
1
The LCD segment corresponding to COM3 is on.
0
1
0
The LCD segment corresponding to COM2 is on.
0
1
1
The LCD segments corresponding to COM2 and COM3 are on.
1
0
0
The LCD segment corresponding to COM1 is on.
1
0
1
The LCD segments corresponding to COM1 and COM3 are on.
1
1
0
The LCD segments corresponding to COM1 and COM2 are on.
1
1
1
The LCD segments corresponding to COM1, COM2, and COM3 are on.
No.A1462-16/22
LC75829PE, 75829PW
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
VDD
VDD1
VDD2
0V
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
Control data
Frame frequency fo[Hz]
FC0
FC1
FC2
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
External clock operating mode
(The control data OC is 1
and EXF is 0, fCK1=300[kHz]typ)
External clock operating mode
(The control data OC is 1
and EXF is 1, fCK2=38[kHz]typ)
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
No.A1462-17/22
LC75829PE, 75829PW
Output waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
VDD
VDD1
VDD2
0V
COM2
VDD
VDD1
VDD2
0V
COM3
VDD
VDD1
VDD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are off.
VDD
VDD1
VDD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VDD
VDD1
VDD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VDD
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VDD
VDD1
VDD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VDD
VDD1
VDD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3
are on.
VDD
VDD1
VDD2
0V
Control data
Frame frequency fo[Hz]
FC0
FC1
FC2
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
0
0
0
fosc/6144
fCK1/6144
fCK2/768
0
0
1
fosc/4608
fCK1/4608
fCK2/576
0
1
0
fosc/3072
fCK1/3072
fCK2/384
0
1
1
fosc/2304
fCK1/2304
fCK2/288
1
0
0
fosc/1536
fCK1/1536
fCK2/192
1
0
1
fosc/1152
fCK1/1152
fCK2/144
1
1
0
fosc/768
fCK1/768
fCK2/96
External clock operating mode
(The control data OC is 1
and EXF is 0, fCK1=300[kHz]typ)
External clock operating mode
(The control data OC is 1
and EXF is 1, fCK2=38[kHz]typ)
Note: When is setting (FC0,FC1,FC2)=(1,1,1), the frame frequency is same as frame frequency at the time of the
(FC0,FC1,FC2)=(0,1,0) setting (fosc/3072, fCK1/3072, fCK2/384).
No.A1462-18/22
LC75829PE, 75829PW
Display Control and the INH Pin
Since the LSI internal data (1/4 duty : the display data D1 to D208 and the control data, 1/3 duty : the display data D1 to
D159 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S4/P4, S5 to S50, COM1 to COM3, COM4/S51,
S52, and S53/OSCI pins to the VSS level.) and during this period send serial data from the controller. The controller
should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at
power on.
(See Figure 5 and Figure 6.)
• 1/4 duty
t2
t1
VDD
INH
VIL1
tc
CE
D1 to D52,PS10,PS11,
EXF,P0 to P2,DT,DN,
FC0 to FC2,OC,SC,BU
VIL1
Display data and control
data transferred
Undefined
Defined
Undefined
Internal data (D53 to D104)
Undefined
Defined
Undefined
Internal data (D105 to D152)
Undefined
Defined
Undefined
Internal data (D153 to D208)
Undefined
Internal data
Defined
Undefined
Notes: t1>1ms
t2>0
tc…10μs min
[Figure 5]
• 1/3 duty
t2
t1
VDD
INH
VIL1
tc
CE
Internal data
D1 to D54,PS10,PS11,
EXF,P0 to P2,DT,DN,
FC0 to FC2,OC,SC,BU
VIL1
Display data and control
data transferred
Undefined
Defined
Undefined
Internal data (D55 to D108)
Undefined
Defined
Undefined
Internal data (D109 to D159)
Undefined
Defined
Undefined
Notes: t1>1ms
t2>0
tc…10μs min
[Figure 6]
No.A1462-19/22
LC75829PE, 75829PW
Notes on Controller Transfer of Display Data
When using the LC75829 in 1/4 duty, applications transfer the display data (D1 to D208) in four operations, and in 1/3
duty, they transfer the display data (D1 to D159) in three operations. In either case, applications should transfer all of
the display data within 30 ms to maintain the quality of displayed image.
S53/OSCI Pin Peripheral Circuit
(1) Internal oscillator operating mode (control data OC=0)
Connect the S53/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.
OSCI/S53
To LCD panel
(2) External clock operating mode (control data OC=1)
When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22kΩ) between
the S53/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according
to the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
External clock output pin
OSCI/S53
Rg
External oscillator
Note: Allowable current value at external clock output pin >
VDD
Rg
(3) Unused pin treatment
When the S53/OSCI pin is not to be used, select the internal oscillator operating mode (setting control
data OC to 0) to keep the pin open.
OSCI/S53
OPEN
No.A1462-20/22
LC75829PE, 75829PW
Sample Applications Circuit1
1/4 Duty, 1/3 Bias
(P1)
(P2)
(P3)
(P4)
VDD
+5V
General-purpose
output ports
Used for functions
such as backlight
control
COM1
COM2
VDD1
LCD panel (up to 208 segments)
COM3
S51/COM4
VDD2
C
P1/S1
C
P2/S2
VSS
P3/S3
P4/S4
S5
C≥0.047μF
INH
From the
controller
CE
S50
S52
*2
CL
DI
*3
OSCI/S53
*2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”).
Sample Application Circuit 2
1/3 Duty, 1/3 Bias
(P1)
(P2)
(P3)
(P4)
VDD
+5V
General-purpose
output ports
Used for functions
such as backlight
control
COM1
COM3
P1/S1
C
VDD2
P2/S2
VSS
P4/S4
C
P3/S3
S5
C≥0.047μF
S50
INH
From the
controller
CE
COM4/S51
*2
S52
CL
DI
LCD panel (up to 159 segments)
COM2
VDD1
*3
OSCI/S53
*2 The pins to be connected to the controller (CE, CL, DI, INH) can handle 3.3V or 5V.
*3 Connect the S53/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg (2.2 to 22kΩ) between the S53/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode (see “S53/OSCI Pin Peripheral Circuit”).
No.A1462-21/22
LC75829PE, 75829PW
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PS No.A1462-22/22