DATASHEET IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Description The IDT74SSTUBF32865A includes a parity checking function. The IDT74SSTUBF32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The IDT74SSTUBF32865A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. • • • To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. and outputs Supports LVCMOS switching levels on CSGateEN and RESET inputs Low voltage operation: VDD = 1.7V to 1.9V Available in 160-ball LFBGA package Applications • DDR2 Memory Modules • Provides complete DDR DIMM solution with In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the IDT74SSTUBF32865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. ICS98ULPA877A or IDTCSPUA877A • Ideal for DDR2 400, 533, 667, and 800 The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high. If either DCS0 and DCS1 input is low, the Qn outputs will function normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 1 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Block Diagram (CS ACTIVE) VREF D PARIN Q R 22 PARITY GENERATOR AND CHECKER PTYERR Q0A D D0 Q Q0B R Q21A D D21 Q Q21B R QCS0A DCS0 D Q QCS0B R CSGateEN QCS1A DCS1 D Q QCS1B R DCKE0, DCKE1 QCKE0A, QCKE1A 2 D 2 Q QCKE0B, QCKE1B R DODT0, DODT1 QODT0A, QODT1A 2 D 2 Q QODT0B, QODT1B R RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 2 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 7 8 9 10 11 12 A VREF NC PARIN NC NC QCKE1A 6 QCKE0A Q21A Q19A Q18A Q17B Q17A B B D1 D2 NC NC NC QCKE1B QCKE0B Q21B Q19B Q18B QODT0B QODT0A C C D3 D4 QODT1B QODT1A D D D6 D5 VDDL GND NC NC GND GND Q20B Q20A E D7 D8 VDDL GND VDDL VDDR GND GND Q16B Q16A F D11 D9 VDDL GND VDDR VDDR Q1B Q1A Q2A A E F G D18 D12 VDDL GND VDDR VDDR Q2B G H CSGate EN D15 VDDL GND GND GND Q5B Q5A H J CLK DCS0 GND GND VDDR VDDR QCS0B QCS0A K CLK DCS1 VDDL VDDL GND GND QCS1B QCS1A L RESET D14 GND GND VDDR VDDR Q6B Q6A J K M D0 D10 GND GND GND GND Q10B Q10A L N D17 D16 VDDL VDDL VDDR VDDR Q9B Q9A M P D19 D21 GND VDDL VDDL VDDR VDDR GND Q11B Q11A R D13 D20 GND VDDL VDDL GND GND GND Q15B Q15A DODT0 Q14B Q14A N T DODT1 P U DCKE0 DCKE1 MCL PTYERR MCH Q3B Q12B Q7B Q4B Q13B Q0B Q8B R V VREF MCL MCL NC MCH Q3A Q12A Q7A Q4A Q13A Q0A Q8A T NOTE: 1. An empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH. U V 160-Ball BGA TOP VIEW 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 160-Ball BGA TOP VIEW 3 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Ball Assignment Signal Group Signal Name Type Description Ungated Inputs DCKE0, DCKE1, DODT0, DODT1 SSTL_18 DRAM function pins not associated with Chip Select. Chip Select Gated Inputs D0 ... D21 SSTL_18 DRAM inputs, re-driven only when Chip Select is LOW. Chip Select Inputs DCS0, DCS1 SSTL_18 DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Re-Driven Q0A...Q21A, Q0B...Q21B, QCSnA,B QCKEnA,B, QODTnA,B SSTL_18 Outputs of the register, valid after the specified clock count outputs and immediately following a rising edge of the clock. Parity Input PARIN SSTL_18 Input parity is received on pin PARIN and should maintain odd parity across the D0...D21 inputs, at the rising edge of the clock. Open Drain When LOW, this output indicates that a parity error was output identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Parity Error PTYERR Program Inputs CSGateEN Clock Inputs CLK, CLK Chip Select Gate Enable. When HIGH, the D0..D21 inputs will be latched only when at least one Chip 1.8V LVCMOS Select input is LOW during the rising edge of the clock. When LOW, the D0...D21 inputs will be latched and redriven on every rising edge of the clock. SSTL_18 MCL, MCH Miscellaneous Inputs Must be connected to a logic LOW or HIGH. RESET SSTL_18 VREF 0.9V nominal 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). 4 Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 Outputs RESET DCS0 DCS1 CSGate EN CLK CLK Dn, DODTn, DCKEn Qn H L L X ↑ ↓ L L L L L H L L X ↑ ↓ H H L L H H L L X L or H L or H X Q0 Q0 Q0 Q0 H L H X ↑ ↓ L L L H L H L H X ↑ ↓ H H L H H H L H X L or H L or H X Q0 Q0 Q0 Q0 H H L X ↑ ↓ L L H L L H H L X ↑ ↓ H H H L H H H L X L or H L or H X Q0 Q0 Q0 Q0 H H H L ↑ ↓ L L H H L H H H L ↑ ↓ H H H H H H H H L L or H L or H X Q0 Q0 Q0 Q0 H H H H ↑ ↓ L Q0 H H L H H H H ↑ ↓ H Q0 H H H H H H H L or H L or H X Q0 Q0 Q0 Q0 L X or Floating X or Floating X or Floating X or Floating L L L L 1 X or X or Floating Floating QCS0x QCS1x QODT, QCKE H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 5 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 Outputs RESET DCS0 DCS1 CLK CLK Σ of Inputs = H (D1 - D21) PARIN2 H L X ↑ ↓ Even L H H L X ↑ ↓ Odd L L H L X ↑ ↓ Even H L H L X ↑ ↓ Odd H H H X L ↑ ↓ Even L H H X L ↑ ↓ Odd L L H X L ↑ ↓ Even H L H X L ↑ ↓ Odd H H H H H ↑ ↓ X X PTYERR0 H X X L or H L or H X X PTYERR0 L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating H PTYERR3 1 H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care ↑ = LOW to HIGH ↓ = HIGH to LOW 2 PARIN arrives one clock cycle after the data to which it applies. 3 This transition assumes PTYERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 6 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Rating Supply Voltage, VDD -0.5V to 2.5V 1 -0.5V to VDD + 2.5V VO1,2 -0.5V to VDDQ + 0.5V Input Voltage Range, VI Output Voltage Range, Input Clamp Current, IIK ±50mA Output Clamp Current, IOK ±50mA Continuous Output Clamp Current, IO ±50mA Continuous Current through each VDD or GND ±100mA Package Thermal Impedance (θja)3 0m/s Airflow 44.3°C/W 1m/s Airflow 38.1°C/W Storage Temperature -65 to +150°C 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 7 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Operating Characteristics The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol Parameter Min. Typ. Max. Units VDD I/O Supply Voltage 1.7 1.8 1.9 V VREF Reference Voltage 0.49 * VDD 0.5 * VDD 0.51 * VDD V VTT Termination Voltage VREF - 0.04 VREF VREF + 0.04 V VDD V VI Input Voltage VIH AC High-Level Input Voltage 0 VIL Dn, PARIN, AC Low-Level Input Voltage DCSn, DCKEn, DC High-Level Input Voltage DODTn DC Low-Level Input Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage VIL VIH RESET, CSGateEN VREF + 0.25 VREF - 0.25 VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ VICR Common Mode Input Range VID Differential Input Voltage IOH High-Level Output Current -8 IOL Low-Level Output Current 8 IERROL TA CLK, CLK 0.675 25 Operating Free-Air Temperature 0 8 1.125 600 PTYERR LOW Level Output Current 28-BIT 1:2 REGISTERED BUFFER WITH PARITY V V V mV mA mA +70 IDT74SSTUBF32865A °C 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, VDD = 1.8V ± 0.1V. Symbol Parameter Test Conditions Min. Typ. Max. VOH Output HIGH Voltage IOH = -6mA, VDDQ = 1.7V VOL Output LOW Voltage IOL = 6mA, VDDQ = 1.7V 0.5 V PTYERR Output LOW Voltage IERROL = 25mA, VDD = 1.7V 0.5 V All Inputs VI = VDD or GND; VDD = 1.9V +5 μA Static Standby IO = 0, VDD = 1.9V, RESET = GND VERROL IIL IDD Static Operating V -5 μA 200 IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) 10 mA IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) 120 Dynamic Operating (clock only) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 300 μA/Clock MHz Dynamic Operating (per each data input) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. 40 μA/Clock MHz/ Data Dn, PARIN VI = VREF ± 350mV CLK and CLK VICR = 1.25V, VIPP = 360mV RESET VI = VDD or GND IDDD CIN 1.2 Units 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 2 3 2.5 3.5 pF 5 9 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V ± 0.1V Symbol fCLOCK tW Min. Parameter Clock Frequency Pulse Duration; CLK, CLK HIGH or LOW tACT tINACT tSU 410 MHz ns Differential Inputs Active Time 2 Differential Inputs Inactive Time Hold Time tH Units 1 1 Setup Time Max. DCS0 before CLK↑, CLK↓, DCS and CSGateEN HIGH; DCS1 before CLK↑, CLK↓, DCS0 and CSGateEN HIGH3 0.6 DCSn, DODT, DCKE, and Dn after CLK↑, CLK↓ 0.5 PARIN after CLK↑, CLK↓ 0.5 DCSn, DODT, DCKE, and Dn after CLK↑, CLK↓ 0.4 PARIN after CLK↑, CLK↓ 0.4 10 ns 15 ns ns ns 1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. 3 tSU = 700ps for DCSx exiting Suspention Mode. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V ± 0.1V Symbol fMAX tPDM 1 tPDQ2 tPDMSS 1 Parameter Min. Max Input Clock Frequency 410 Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn 1.1 1.5 ns Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn 0.4 0.8 ns 1.6 ns Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn Max. Units MHz tLH LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to PTYERR 1.2 3 ns tHL HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to PTYERR 1 3 ns tPHL HIGH to LOW Propagation Delay, RESET↓ to Qn↓ 3 ns tPLH LOW to HIGH Propagation Delay, RESET↓ to PTYERR↑ 3 ns 1 2 Design target as per JEDEC specifications. Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.) 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 10 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V ± 0.1V Parameter dV/dt_r dV/dt_f dV/dt_Δ 1 1 Min. Max. Units 1 4 V/ns 1 4 V/ns 1 V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 11 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Parity Logic Diagram Dn 22 22 Q D QnA QnB D LATCHING AND RESET FUNCTION D PTYERR D PARIN CLOCK Register Timing n-1 n n +1 n+2 n+3 n+4 n+5 CLK CLK tSU tH Dn tSU tH PARIN tPDM, tPDMSS Qn tPDM tPDH PTYERR 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 12 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD/2 VDD DUT RL = 1KΩ TL = 50Ω CLK CLK CLK Inputs ZO = 50Ω Test Point ZO = 50Ω Test Point CLK Inputs Test Point CL = 12 pF Test Point CLK TL = 350ps, 50Ω Out DUT RL = 50Ω ZO = 50Ω Out CLK RL = 1KΩ Test Point RL = 100Ω Test Point Production-Test Load Circuit Simulation Load Circuit CLK tPLH VDD LVCMOS RESET Input VDD/2 V ICR V ICR CLK V ID tPHL V OH Output VDD/2 V TT V TT V OL 0V tACT tINACT Voltage Waveforms - Propagation Delay Times 90% IDD 10% LVCMOS RESET Input Voltage and Current Waveforms Inputs Active and Inactive Times VIH VDD/2 VIL tRPHL VOH Output VTT VOL tW Input VICR VICR Voltage Waveforms - Propagation Delay Times VID NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VID VICR CLK tSU tH VIH Input VREF VREF VIL Voltage Waveforms - Setup and Hold Times 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 13 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V ± 0.1V) VDD DUT VDD DUT RL = 50Ω Out RL = 1KΩ Out Test Point Test Point CL = 10 pF CL = 10 pF Load Circuit: Error Output Measurements Load Circuit: High-to-Low Slew-Rate Adjustment Output LVCMOS RESET Input VOH 80% VCC VCC/2 0V tPLH VOH 20% dv_f 0.15V Output Waveform 2 VOL 0V dt_f Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) Voltage Waveforms: High-to-Low Slew-Rate Adjustment Timing Inputs DUT VICR VICR VI(PP) tHL Out Test Point CL = 10 pF VCC/2 VOL Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) Load Circuit: Low-to-High Slew-Rate Adjustment Timing Inputs dt_r VOH dv_r VCC Output Waveform 1 RL = 50Ω 80% VICR VICR VI(PP) tHL VOH Output Waveform 2 20% Output VOL 0.15V 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) Voltage Waveforms: Low-to-High Slew-Rate Adjustment NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 14 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 0.925 Ref ROW A, COLUMN 1 C 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H D J K L d M N P R T b U 0.975 Ref V h E e TYP T 0.10 C ALL DIMENSIONS IN MILLIMETERS D 13.00 Bsc E 9.00 Bsc T Min/Max 1.10/1.30 BALL GRID e 0.65 Bsc Horiz 12 Vert 18 Total 160 d Min/Max 0.35/0.45 h Min/Max 0.27/0.37 REF. DIMS b 0.975 c 0.925 NOTE: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 15 IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Ordering Information IDT XX SSTUBF XX Family Temp. Range XXX XX Device Type Package X Shipping Carrier 8 28-BIT 1:2 REGISTERED BUFFER WITH PARITY 16 Tape and Reel BKG Thin Profile, Fine Pitch, Ball Grid Array - Green 865A 28-Bit 1:2 Registered Buffer with Parity 32 Double Density 74 0°C to +70°C (Commercial) IDT74SSTUBF32865A 7092/10 IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA