PRELIMINARY ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS873991-147 is a low voltage, low skew, 3.3V ICS LVPECL or ECL Clock Generator and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS873991-147 has two selectable clock inputs. The PCLK, nPCLK pair can accept an LVPECL input and the REF_CLK pin can accept a LVCMOS or LVTTL input. This device has a fully integrated PLL along with frequency configurable outputs. An external feedback input and output regenerates clocks with “zero delay”. • Fourteen differential 3.3V LVPECL/ECL outputs • Selectable differential LVPECL or REF_CLK inputs • PCLK, nPCLK can accept the following input levels: LVPECL, CML, SSTL • REF_CLK accepts the following input levels: LVCMOS, LVTTL • Input clock frequency range: 6.25MHz to 125MHz • Maximum output frequency: 500MHz • VCO range: 200MHz to 1GHz The four independent banks of outputs each have their own output dividers, which allow the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The output frequency range is 25MHz to 500MHz and the input frequency range is 6.25MHz to 125MHz. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers. • Output skew: 70ps (typical) • Cycle-to-cyle jitter: 35ps (typical) • LVPECL mode operating voltage supply range: VCC = 3.135V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -3.135V • 0°C to 70°C ambient operating temperature The ICS873991-147 also has a SYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs for coincident rising edges and signals a pulse per the timing diagrams in this data sheet. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of each other. • Available in lead-free (RoHS 6) package • Industrial temperature available upon request FSEL3 nQC2 QC2 VCCO nQB0 QB0 FSEL2 nQB1 QB1 FSEL1 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 QC1 QB3 41 25 nQC1 VCCO 42 24 QC0 nQA0 43 23 nQC0 QA0 44 nQA1 45 nQB3 ICS873991-147 22 VCCO 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View 21 QD1 20 nQD1 19 QD0 18 nQD0 17 VCCO 47 QA2 48 nQA3 49 QA3 50 16 QFB SYNC_SEL 51 15 nQFB VCO_SEL 52 14 VCCA nEXT_FB EXT_FB VCC nPCLK PCLK REF_CLK 7 8 9 10 11 12 13 FSEL_FB0 FSEL_FB1 4 5 6 FSEL_FB2 2 3 PLL_EN 1 REF_SEL 46 VEE QA1 nQA2 MR 2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies from a reference clock to multiple processing units on an embedded system. nQB2 FSEL0 1. Line Card Multiplier: Multiply 19.44MHz from a back-plane to 77.76MHz on the line card ASIC and Serdes. QB2 PIN ASSIGNMENT Example Applications: The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 1 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY BLOCK DIAGRAM VCO_SEL Pulldown PLL_EN Pulldown QA0 REF_SEL Pulldown nQA0 REF_CLK Pulldown QA1 nPCLK PCLK EXT_FB nQA1 QA2 PHASE DETECTOR VCO nQA2 QA3 LPF nQA3 nEXT_FB QB0 nQB0 MR Pulldown QB1 nQB1 FREQUENCY GENERATOR FSEL_0:3 Pulldown SYNC QB2 nQB2 QB3 nQB3 QC0 FSEL_FB0:2 Pulldown nQC0 QC1 nQC1 QC2 nQC2 QD0 nQD0 SYNC_SEL Pulldown QD1 nQD1 QFB nQFB IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 2 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VEE Power 2 MR Input 3 PLL_EN Input 4 REF_SEL Input 5 6 7 8 FSEL_FB2 FSEL_FB1 FSEL_FB0 REF_CLK 9 PCLK 10 nPCLK Input 11 VCC Power 12 EXT_FB Input 13 nEXT_FB Input 14 15 16 17, 22, 30, 42 VCCA nQFB QFB VCCO Power Output Power Output supply pins. 18, 19 nQD0, QD0 Output Differential output pair. LVPECL interface levels. 20, 21 nQD1, QD1 Output Differential output pair. LVPECL interface levels. 23, 24 nQC0, QC0 Output Differential output pair. LVPECL interface levels. 25, 26 27 33 36 39 28, 29 nQC1, QC1 Output FSEL3 FSEL2 Input FSEL1 FSEL0 nQC2, QC2 Output Differential output pair. LVPECL interface levels. 31, 32 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 34, 35 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 37, 38 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 40, 41 nQB3, QB3 Output Differential output pair. LVPECL interface levels. 43, 44 nQA0, QA0 Output Differential output pair. LVPECL interface levels. 45, 46 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 47, 48 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 49, 50 nQA3, QA3 Output 51 SYNC_SEL Input 52 VCO_SEL Input Negative supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inver ted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH, Pulldown PLL is in bypass mode. LVCMOS/LVTTL interface levels. Selects between the different reference inputs as the PLL reference Pulldown source. When logic LOW, selects PCLK/nPCLK. When logic HIGH, selects REF_CLK. LVCMOS/LVTTL interface levels. Input Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels. Input Pulldown Reference clock input. LVCMOS/LVTTL interface levels. Input Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Core supply pin. Pulldown Non-inver ting external feedback input. Pullup/ Inver ting external feedback input. VCC/2 default when left floating. Pulldown Analog supply pin. Differential feedback output pair. LVPECL Interface levels. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. SYNC output select pin. When LOW, the SYNC otuput follows the Pulldown timing diagram (page 5). When HIGH, QD output follows QC output LVCMOS/LVTTL interface levels.. Pulldown Selects VCO range. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 3 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLup Input Pullup Resistor 51 kΩ TABLE 3A. SELECT PIN FUNCTION TABLE Inputs FSEL3 FSEL2 TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE Inputs Outputs FSEL1 FSEL0 QAx QBx Outputs QCx FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 0 ÷2 ÷2 ÷2 0 0 0 ÷2 0 0 0 1 ÷2 ÷2 ÷4 0 0 1 ÷4 0 0 1 0 ÷2 ÷4 ÷4 0 1 0 ÷6 1 1 ÷8 0 0 1 1 ÷2 ÷2 ÷6 0 0 1 0 0 ÷2 ÷6 ÷6 1 0 0 ÷8 0 1 ÷16 0 1 0 1 ÷2 ÷4 ÷6 1 0 1 1 0 ÷2 ÷4 ÷8 1 1 0 ÷24 0 1 1 1 ÷2 ÷6 ÷8 1 1 1 ÷32 1 0 0 0 ÷2 ÷2 ÷8 1 0 0 1 ÷2 ÷8 ÷8 1 0 1 0 ÷4 ÷4 ÷6 1 0 1 1 ÷4 ÷6 ÷6 1 1 0 0 ÷4 ÷6 ÷8 1 1 0 1 ÷6 ÷6 ÷8 1 1 1 0 ÷6 ÷8 ÷8 1 1 1 1 ÷8 ÷8 ÷8 TABLE 3C. INPUT CONTROL FUNCTION TABLE Control Input Pin Logic 0 Logic 1 PLL_EN Enables PLL Bypasses PLL VCO_SEL fVCO fVCO/2 REF_SEL Selects PCLK/nPCLK Selects REF_CLK MR --- Resets outputs SYNC_SEL Selects outputs Match QC Outputs IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 4 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY 1:1 Mode QA QC SYNC (QD) 2:1 Mode QA QC SYNC (QD) 3:1 Mode QA QC SYNC (QD) 3:2 Mode QA QC SYNC (QD) 4:3 Mode QA QC SYNC (QD) FIGURE 1. TIMING DIAGRAMS IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 5 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat- 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-mum rating conditions for extended pe- Package Thermal Impedance, θJA 63.7°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG riods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCO Output Supply Voltage 3.465 V ICC Power Supply Current 150 mA ICCA Analog Supply Current 15 mA ICCO Output Supply Current 95 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C Symbol VIH Parameter Input High Voltage Test Conditions PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR REF_CLK PLL_EN, VCO_SEL, REF_SEL, SYNC_SEL, FSEL_FB0:FSEL_FB2, FSEL0:FSEL3, MR REF_CLK VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V IIL Input Low Current VIN = 0V, VCC = 3.465V Minimum Typical Maximum Units 2 VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V 150 µA -5 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, VEE = 0V, TA = 0°C TO 70°C Symbol Parameter Maximum Units PCLK VCC = VIN = 3.465V Test Conditions 150 µA nPCLK VCC = VIN = 3.465V 5 µA PCLK VCC = 3.465V, VIN = 0V -5 µA nPCLK VCC = 3.465V, VIN = 0V -150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Minimum Typical 0.3 1 V Common Mode Input Voltage; NOTE 1 VEE + 1.5 VCC V VOH Output High Voltage; NOTE 2 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 2 VCC - 2.0 VCC - 1.7 V 0.6 1 V VSWING Peak-to-Peak Output Voltage Swing NOTE 1: Common mode voltage is defined as VIH. NOTE 2: Outputs terminated with 50Ω to VCCO - 2V. . IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 6 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter t R / tR Input Rise/Fall Time Test Conditions Reference Frequency VCO_SEL = 0 fREF Reference Frequency VCO_SEL = 1 fREFDC Minimum Typical REF_CLK Maximum Units 3 ns Feedback ÷ 6 66.66 166.67 MHz Feedback ÷ 8 50 125 MHz Feedback ÷ 16 25 62.5 MHz Feedback ÷ 24 16.66 41.67 MHz Feedback ÷ 32 12.5 31.25 MHz Feedback ÷ 4 50 100 MHz Feedback ÷ 6 33.33 66.66 MHz Feedback ÷ 8 25 50 MHz Feedback ÷ 16 12.5 25 MHz Feedback ÷ 24 8.33 16.66 MHz Feedback ÷ 32 6.25 12.5 MHz 25 75 % Reference Input Duty Cycle NOTE: These parameters are guaranteed by design, but are not tested in production. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V ± 5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical QA, QB, QC fMAX Output Frequency t(Ø) QD tsk(o) QD; NOTE 1 Static Phase Offset; PCLK, nPCLK NOTE 2, 3 Output Skew; NOTE 4, 5 t sk(w) Multiple Frequency Skew; NOTE 5, 6 tjit(cc) Cycle-to-Cycle Jitter; NOTE 5 f VCO PLL VCO Lock Range; NOTE 7 t LOCK PLL Lock Time tR / tF Output Rise/Fall Time Maximum 500 MHz SYNC_SEL = 1 400 MH z SYNC_SEL = 0 200 MHz 170 ps 70 ps TBD ps 35 ps PLL_SEL = 0 0.4 1. 0 GHz PLL_SEL = 1 200 480 MH z 10 ms 20% to 80% 0.5 odc Output Duty Cycle 50 All parameters measured at fMAX unless noted otherwise. NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at VCCO/2. NOTE 7: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6. When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2. IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR Units 7 ns % ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCA, VCCO VCC SCOPE Qx nPCLK LVPECL V nQx VEE V Cross Points PP CMR PCLK -1.3V ± -0.165V VEE DIFFERENTIAL INPUT LEVELS OUTPUT LOAD AC TEST CIRCUIT nQx nQFB, nQAx:nQDx Qx QFB, QAx:QDx ➤ ➤ tcycle n Qy tcycle n+1 ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles tsk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW nPCLK VOH PCLK VOL nQxx Qxx nQFB, nQAx:nQDx VOH nQyy VOL ➤ t(Ø) ➤ QFB, QAx:QDx ➤ nQy Qyy tsk(ω) MULTIPLE FREQUENCY SKEW STATIC PHASE OFFSET nQFB, nQAx:nQDx 80% 80% QFB, QAx:QDx VSW I N G Clock Outputs tR t PW t 20% 20% tF odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 8 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY APPLICATIONS INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS873991-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a 0.01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 9 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK/nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and V CMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 3.3V 3.3V Zo = 50 Ohm C1 LVDS R3 1K R4 1K PCLK R5 100 C2 nPCLK Zo = 50 Ohm R1 1K HiPerClockS PCL K/n PC LK R2 1K FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 10 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: PCLK/nPCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION 11 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS873991-147. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS873991-147 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 14 * 30mW = 420mW Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 420mW = 939.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 55.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.940W * 55.5°C/W = 122.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 52-PIN LQFP FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 0 1 2.5 63.7°C/W 55.5°C/W 52.4°C/W 12 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) = L L [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) = L L [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 13 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 63.7°C/W 55.5°C/W 52.4°C/W TRANSISTOR COUNT The transistor count for ICS873991-147 is: 5969 IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 14 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BCC MINIMUM NOMINAL MAXIMUM 52 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 D 12.00 BASIC D1 10.00 BASIC D2 7.80 Ref. E 12.00 BASIC E1 10.00 BASIC E2 7.80 Ref. e 0.65 BASIC -- 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 15 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 873991AY-147LF ICS873991A147L 52 Lead "Lead-Free" LQFP tray 0°C to 70°C 873991AY-147LFT ICS873991A147L 52 Lead "Lead-Free" LQFP 500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVPECL/ECL CLOCK GENERATOR 16 ICS873991AY-147 REV. A AUGUST 10, 2007 ICS873991-147 LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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