MOTOROLA MC145074D Stero audio sigma-delta digital-to-analog converter Datasheet

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by MC145074/D
SEMICONDUCTOR TECHNICAL DATA
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16
CMOS
The MC145074 is a high precision, Stereo Audio Digital–to–Analog
Converter that utilizes second order sigma–delta modulators with 2–tap FIR
feedback architecture. The part can be used as a stand alone stereo digital
modulator, or as a companion part to the MC145076 smoothing filter to achieve
high quality, low cost audio performance.
•
•
•
•
•
•
•
•
Peak S/(N+D) > 100 dB
Single 5 V Supply Operation
Accepts 16, 18, or 20–Bit Data Words
Dual/Single Pin Data Input Modes
Programmable WCLK Divider
Operating Temperature Range: – 40 to + 85°C
Low Power Consumption: 40 mW Typical
Companion to MC145076 Stereo Audio FIR Smoothing Filter
VDD
VSS
D SUFFIX
16 PIN SOIC
CASE 751B–05
1
ORDERING INFORMATION
MC145074D
SOIC Package
PIN ASSIGNMENT
VDD
1
16
DOL
STBY
2
15
RES0
DIL/WDLY
3
14
RES1
DIR/DILR
4
13
DMODE
BCLK
5
12
Xin
WCLK
6
11
Xout
MSTR
7
10
DIV2
VSS
8
9
DOR
1
8
STBY
2
DIL/WDLY
3
LEFT CHANNEL
DIR/DILR
BCLK
5
DMODE
13
RES1
RES0
WCLK
MSTR
DIV2
SERIAL/PARALLEL
INTERFACE
4
14
OFFSET SCALER
CONTROL
LOGIC
Σ±∆
MODULATOR
CHOP
16
DOL
RIGHT CHANNEL
SERIAL/PARALLEL
INTERFACE
OFFSET SCALER
Σ±∆
MODULATOR
CHOP
9
DOR
15
6
7
TIMING
12
11
Xin
Xout
10
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/96
 Motorola, Inc. 1996
MOTOROLA
MC145074
1
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Parameter
Symbol
VDD
DC Input Voltage, Any Digital Input
Iin
DC Input Current, per Pin
TL
Unit
6.0
V
VSS – 0.5 to
VDD + 0.5
V
±10
mA
– 55 to 150
°C
260
°C
DC Supply Voltage
Vin
Tstg
Value
Storage Temperature
Lead Temperature, 1 mm from Case for
10 Seconds
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to
this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the
range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges below.
OPERATION RANGES (Applicable to Guaranteed Limits)
Parameter
Symbol
VDD
Vin, Vout
DC Supply Voltage, Referenced to VSS
Digital Input/Output Voltage
Value
Unit
4.5 to 5.5
V
VSS – 0.5 to VDD + 0.5
V
ID
Input Pin Current Drain
1
µA
TA
Operating Temperature
– 40 to + 85
°C
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges table, unless otherwise indicated)
Parameter
Symbol
Idd
Power Supply Current
VIL
VIH
Input Voltage
VOL
VOH
Output Voltage
Ilkg
Input Leakage Current
MC145074
2
Min
Typ
Max
Unit
—
—
10
mA
Low Level Input
High Level Input
—
VDD x 0.7
—
—
VDD x 0.3
—
V
Low Level Output (Load = 0.4 mA)
High Level Output (Load = 0.4 mA)
—
VDD – 0.3
—
—
0.3
—
V
—
—
± 10
µA
MOTOROLA
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table at 50 pf Loads on Outputs)
Parameter
Symbol
Figure
Guaranteed
Limit
Unit
Operating Frequency Xin (DIV2 = 0)
(DIV2 = 1)
18.5
37.0
MHz
Bit Clock Frequency
18.5
MHz
tr, tf
Maximum Rise and Fall Times (BCKL, WCLK)
2, 5
6
ns
tPLH
tTLH
Xout L–H Propagation Delay
Xout Rise Time
2
30
15
ns
tPHL
tTHL
Xout H–L Propagation Delay
Xout Fall Time
2
30
15
ns
tPLH
tTLH
DOL, DOR L–H Propagation Delays
DOL, DOR Rise Time
3
15
5
ns
tPHL
tTHL
DOL, DOR H–L Propagation Delays
DOL, DOR Fall Time
3
15
5
ns
tPLH
tTLH
WCLK Output L–H Propagation Delay
WCLK Output Rise Time
4
15
5
ns
tPHL
tTHL
WCLK Output H–L Propagation Delay
WCLK Output Fall Time
4
15
5
ns
tsu
th
DIR Master Program Mode Minimum Setup Time
DIR Master Program Mode Minimum Hold Time
5
5
5
ns
tsu
th
DIR, DIL Minimum Setup Time
DIR, DIL Minimum Hold Time
5
5
5
ns
tsu
th
WCLK Minimum Setup Time to BCLK (not DMODE = WDLY = 1)
WCLK Minimum Hold Time to BCLK (not DMODE = WDLY = 1)
6
5
5
ns
tsu
th
WCLK Minimum Setup Time to Xin (not DMODE = WDLY = 1)
WCLK Minimum Hold Time to Xin (not DMODE = WDLY = 1)
6
5
5
ns
tsu
th
WCLK Minimum Setup Time to BCLK (DMODE = WDLY = 1)
WCLK Minimum Hold Time to BCLK (DMODE = WDLY = 1)
7
5
5
ns
BCLK to Xin (1st Edge Only) Lag Time (DMODE = WDLY = 1)
BCLK to Xin (1st Edge Only) Lead Time (DMODE = WDLY = 1)
7
5
5
ns
tLAG
tLEAD
MOTOROLA
MC145074
3
SWITCHING WAVEFORMS
tr
Xin
tf
90%
50%
90%
50%
10%
tPHL
Xout
90%
Xin
10%
50%
50%
tPLH
tPHL
90%
50%
10%
50%
10%
tTHL
90%
DOL/DOR
tPLH
50%
10%
tTLH
50%
10%
tTHL
Figure 1. Xout Propagation Delay Timing
tTLH
Figure 2. DOL/DOR Propagation Delay Timing
tr
DIL/DIR/DILR
Xin
50%
50%
tf
90%
50%
10%
th
tPHL
WCLK
90%
90%
tsu
tPLH
50%
10%
90%
50%
10%
tTHL
tsu
90%
50%
BCLK
10%
tf
tr
tTLH
Figure 3. WCLK Out Propagation Delay Timing
(Master Mode)
Figure 4. DIL/DIR/DILR Setup and Hold Timing
th
tsu
50%
Xin
WCLK
50%
50%
BCLK
th
tsu
Figure 5. WCLK Timing (All Modes Except DMODE = 1, WDLY = 1)
Xin
tLAG
BCLK
tLEAD
50%
th
WCLK
Bits
tsu
50%
Figure 6. WCLK Timing (DMODE = 1, WDLY = 1)
MC145074
4
16
18
20
OSR
S/(N+D) dB
S/(N+D) dB
S/(N+D) dB
128x
90
90
90
192x
94
98
99
256x
95
103
105
384x
96
107
113
50%
NOTE: Values are for 0 dB input signal, 0 – 20 kHz BW, and 44.1 kHz
1x fs Sampling Rate.
Figure 7. Digital S/(N+D) Performance Levels
MOTOROLA
PIN DESCRIPTIONS
VDD
Positive Device Supply (Pin 1)
VDD is the positive supply, nominally + 5 volts.
STBY
Active–Low Standby Input (Pin 2)
A low level on the STBY pin will force the device into a
standby state. If the device is being operated in the master
mode (MSTR = 1), the WCLK internal divider can be
programmed using the DIR/DILR, and BCLK pins while
the STBY pin is active. When the device is in standby, the
DOL and DOR pins will output a 50% duty cycle data stream
that will generate a 1/2 scale analog output, when averaged
through the output filter.
MSTR
Active–High Master Mode Select Input (Pin 7)
A high level on the MSTR pin will select the master mode
of operation. In the master mode, the MC145074 will
generate and output a word clock signal on the WCLK pin. A
low level on the MSTR pin will place the MC145074 in the
slave mode, and the WCLK signal must be provided by an
external source. The default master mode divide rate is
MODCLK/64.
VSS
Device Ground (Pin 8)
VSS is normally connected to ground.
DOR
Right Channel Data Output (Pin 9)
DOR is the right channel modulator data output.
DIL/WDLY
Left Channel Data/Word Clock Delay Input (Pin 3)
DIV2
Master Clock Divide Control Input (Pin 10)
When the DMODE pin is low, this pin is the left channel
(MSB first) 2’s complement serial data input. When the
DMODE pin is high, this pin controls the WCLK delay. A high
level on this pin will delay the WCLK an additional clock cycle
internal to the device.
DIV2 is the Xin divide by two control pin. When cleared, the
Xin pin directly provides the modulator clock (MODCLK), and
the data output bit streams are not chopped. When this pin is
set, the Xin clock is divided by two to provide the modulator
clock and the output data bit stream is chopped at the Xin frequency using an alternating 1,0 chop. The chop is used to
reduce even order distortion for a stand–alone application
without the MC145076. The reconstructed output signal will
drop 6dB due to the chopping.
DIR/DILR
Right Channel Data/Multiplexed Left – Right Data Input
(Pin 4)
When the DMODE pin is low, this pin is the right channel
(MSB first) 2’s complement serial data input. When the
DMODE pin is high, this pin is the multiplexed left then right
channel data input. If the part is being operated in the master
mode (MSTR = 1), the WCLK internal divider can be programmed by clocking control word data onto this pin with the
BCLK pin while the device is in the standby mode (STBY
= 0).
BCLK
Bit Clock Input (Pin 5)
The BCLK pin provides the serial bit shift clock for the left
and right channel data in all modes of operation. A rising
edge on the BCLK pin shifts serial data into the device.
WCLK
Word Clock Output/Input (Pin 6)
The WCLK pin is used to latch the shifted serial data word
into the device. The MC145074 can accept an external word
clock when in the slave mode, or can use an internally
generated word clock when operating in the master mode.
When DMODE is low, left and right channel data is latched
into the device on the falling edge of WCLK. When DMODE
is high, left channel data is latched on the rising edge of
WCLK and right channel data is latched on the falling edge of
WCLK with both channel inputs being input to the modulator
on the next rising edge of WCLK. The internal divide ratio
used to generate WCLK, as well as the rising or falling edge
latching of the input data can be programmed using the DIR/
DILR and BCLK pins while the device is in the standby mode.
MOTOROLA
Xout
Master Clock Output (Pin 11)
Xout is the inverted output signal of Xin and may be used
for a buffered clock output or for a crystal oscillator.
Xin
Master Clock Input (Pin 12)
Xin is the input clock pin for the MC145074, and may be
used with Xout as the inverter for a crystal oscillator.
DMODE
Data Mode Input (Pin 13)
A low level on the DMODE pin will select the dual data pin
mode of operation. In this mode, the serial input data is
entered on the DIR and DIL pins. A high level on the DMODE
pin selects the multiplexed mode of operation. In this mode,
the left and right channel serial input data must be multiplexed on the DIR/DILR pin.
RES0 and RES1
Input Data Resolution Pins (Pins 14, 15)
The RES0 and RES1 pins select the length of the serial
data word input to the MC145074. The serial input data can
be 16, 18, or 20–bits in length with the most significant bits
clocked in first. Figure 9 lists the serial interface formats.
DOL
Left Channel Data Output (Pin 16)
DOL is the left channel modulator data output.
MC145074
5
DMODE
RES1
RES0
Operating Mode
0
0
0
Dual Data Pin 16–Bit Input
0
0
1
Dual Data Pin 18–Bit Input
0
1
0
Dual Data Pin 20–Bit Input
0
1
1
Factory Test Mode
1
0
0
Single Data Pin 16–Bit Input
1
0
1
Single Data Pin 18–Bit Input
1
1
0
Single Data Pin 20–Bit Input
1
1
1
Factory Test Mode
Figure 8. Serial Interface Formats
ratio of the internal frequency divider can be programmed
utilizing a 5–bit control word while the MC145074 is in the
standby mode. The 5–bit control word is defined as the last
5–bits (MSB first) that are clocked into the DIR/DILR pin
using the BCLK signal. When cleared, the most significant bit
of the control word indicates that the WCLK signal is negative edge triggered (just as in the slave mode). If the most
significant bit is set, the WCLK is positive edge triggered.
The next three most significant or middle three bits of the
control word determine the value of the divide ratio of the internal frequency divider. The least significant bit of the 5–bit
control word indicates a prescaler divide by two when
cleared, and divide by three when set. The divider modes are
summarized in Figure 10.
NOTE
The default mode of operation is control word
$06 which provides a WCLK signal (negative
edge triggered) at a frequency of 1/64 the modulator clock frequency. This is the preferred operating mode of 256x OSR and 4x FIR.
FUNCTIONAL DESCRIPTION
The MC145074 is a high precision Stereo Audio Digital–
to–Analog Converter, which utilizes a second–order sigma–
delta modulator with a patented 2–tap architecture that
significantly reduces problems normally associated with
one–bit sigma–delta technology. Normally, a second order
modulator can develop patterns in the digital output representation of small signals and with small DC input offsets. It
is common to add dither to mask these effects, but a reduction of dynamic range can result. The implementation used in
the MC145074 has considerable immunity to these troublesome inputs, and without performance compromise.
With RC filtering, the MC145074 can be used as a stand–
alone stereo digital modulator for applications with modest
requirements. High performance can be realized with the
companion MC145076 Stereo Audio FIR Smoothing Filter,
which reduces the in–band IM products formed by large amplitude spectral components of the out–of–band noise shaping, clock corruption, and power supply noise.
The MC145074 has been designed for maximum flexibility
and is well suited for high fidelity audio and multimedia
applications. If used in conjunction with a differential
MC145076 smoothing filter, a peak S/(N+D) ratio of > 100 dB
can be achieved by utilizing 18 or 20–bit input data and a
256x oversampling ratio. The MC145074 has a maximum
operating frequency of 18.5 MHz, and can be used with any
sampling rate including 32, 44.1, or 48 kHz.
The MC145074 can accept a 1x, or a 2x input clock with
serial data output chop. The device can accept 16, 18, or
20–bit digital data in a dual data pin input format, or single pin
multiplexed format. An offset scaler is included to allow 0 dB
digital inputs while maintaining low distortion. The offset,
scaled data is applied to the D/A modulator before being optionally chopped (2x mode), and sent to an external smoothing filter. When this device is used with the MC145076,
dividing the clock down or using the chop mode is not necessary.
TIMING CIRCUIT
The internal timing circuits of the MC145074 are driven by
the X in clock. When the DIV2 pin is active high, the
MC145074 divides the Xin clock by two to generate the internal modulator clock (MODCLK), and uses the Xin clock
frequency to chop the output data using a 50% chop signal.
When the MC145074 is operated in the master mode, the
WCLK pin is configured as an output. The WCLK output is
generated by dividing down the modulator clock. The divide
MC145074
6
Control
Word
Value
(Hex)
Control
Word
Value
(Hex)
Divide
Ratio
Divide
Ratio
0
1
2
3
8
12
16
24
10
11
12
13
8
12
16
24
4
5
6
7
32
48
64
96
14
15
16
17
32
48
64
96
8
9
A
B
128
192
256
384
18
19
1A
1B
128
192
256
384
C
D
E
F
512
768
1024
1536
1C
1D
1E
1F
512
768
1024
1536
WCLK
Edge
WCLK
Edge
Figure 9. WCLK Divider Modes
OFFSET SCALER
Second order sigma–delta modulators typically give up
about 2 dB of dynamic range and an adjustment to the digital
input words must be made if full scale digital input word
recognition is desired. The offset scaler circuitry of the
MC145074 digitally attenuates the input linearly to 3/4 or
approximately – 2.5 dB. Figure 11 illustrates the function of
the offset scaler block. An ideal DAC would perform as
shown in curve one, but the sigma–delta modulator actually
operates as shown in curve two. The digital input words to
the MC145074 are attenuated to 3/4. This allows the
MC145074 to operate on all 2’s compliment digital inputs
from $80000 to $7FFFF, with the resulting response shown
in curve three. In addition to scaling the digital input word, the
offset scaler adds a digital dc offset of 1/8th to re–center the
digital input word so that the MC145074 output signal is centered around VDD/2.
MOTOROLA
SCALER
OUTPUT
SCALER TRANSFER FUNCTION
1
3
3/4 SCALE = – 2.5 dB
2
1 – IDEAL
2 – ACTUAL
3 – COMPENSATED
$80000
20–BIT DIGITAL INPUT
$7FFFF
Figure 10. Offset Scaler Operation
SERIAL INTERFACE AND CONTROL LOGIC
The serial interface and control logic of the MC145074
may be configured to accept 16, 18, or 20–bit data words by
applying the appropriate logic levels to the RES1 and RES0
pins. The DMODE input pin configures the serial interface to
accept 2’s complement data (MSB first) in a dual data pin or
single pin, multiplexed input format. It should be noted that in
some cases when using the single data pin input mode and a
large OSR, the BCLK rate may be too high for some DSPs,
unless an interface circuit is added. Figure 9 shows the available serial interface formats of the MC145074.
When operating in a dual data pin mode, 2’s complement
data words are serially input from the DIR and DIL pins as
shown in Figure 12. A rising edge on BCLK serially shifts in
the data present on the DIR and DIL inputs. After all data bits
of an input word are shifted in, a falling edge on WCLK
MOTOROLA
latches the data word into the MC145074. The BCLK can be
a continuous clock as long as the serial input data word is
right justified in the word time, or as long as there exists one
and only one BCLK cycle for every data bit input to the
device.
When operating in a single pin multiplexed mode, the DIR
input pin is reconfigured as the DILR pin. Left and right channel serial input data is multiplexed into the MC145074 on the
DILR pin, and is serially shifted into the part using BCLK as
shown in Figure 13. When WDLY is low, left channel data is
latched into the part on the rising edge of WCLK, and right
channel data is latched on the falling edge of WCLK. As in
the dual data pin mode, the BCLK can be either an asynchronous or continuous clock as long as the serial input data
word is right justified in the word time. Forcing WDLY high allows the WCLK cycle to appear one clock cycle early as
shown in Figure 14.
MC145074
7
MC145074
8
MOTOROLA
1
1
DIR
DIL
BCLK
WCLK
0
0
DMODE = 0, 16/18/20-BITS IN :
X
X
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Figure 11. DMODE = 0 Serial Interface Timing Diagram
19 18 17 16 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9
X
X
19 18 17 16 15 14
19 18 17 16 15 14
MOTOROLA
MC145074
9
DILR
BCLK
WCLK
DILR
BCLK
WCLK
7
6
5
4
3
X
2
1
6
5 4
3
2 1
X
7
5 4
3 2
1 0
(LEFT CHANNEL) n + 1
6
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
8
(LEFT CHANNEL) n + 1
0 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(RIGHT CHANNEL) n
7
Figure 12. DMODE = 1, WDLY = 0, Serial Interface Timing Diagram
X
8
(RIGHT CHANNEL) n
0 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(LEFT CHANNEL) n
DMODE = 1, WDLY = 0, 384x CLOCK, 16/18/20 – BITS IN:
15 14 13 12 11 10 9 8
(LEFT CHANNEL) n
DMODE = 1, WDLY = 0, 8x INPUT, 256x CLOCK, 16 – BITS IN:
X
MC145074
10
MOTOROLA
DILR
BCLK
WCLK
DILR
BCLK
WCLK
7
6
5
4
3
X
2
1
6
5 4
3
2 1
X
7
5 4
3 2
1 0
(LEFT CHANNEL) n + 1
6
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
8
(LEFT CHANNEL) n + 1
0 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(RIGHT CHANNEL) n
7
Figure 13. DMODE = 1, WDLY = 1, Serial Interface Timing Diagram
X
8
(RIGHT CHANNEL) n
0 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(LEFT CHANNEL) n
DMODE = 1, WDLY = 1, 384x CLOCK, 16/18/20 – BITS IN:
15 14 13 12 11 10 9 8
(LEFT CHANNEL) n
DMODE = 1, WDLY = 1, 8x INPUT, 256x CLOCK, 16 – BITS IN:
X
MOTOROLA
MC145074
11
6
7
8
11
10
9
6
7
8
WCLK
* ALL RESISTORS 1%
5
12
MC145074
5
BCLK
+
10 µF
4
13
14
15
16
9
10
11
MC145076 13
12
4640
22 pF
200
10 µF
+
+5V
Figure 14. Low Cost + 5 V Stereo Audio System, Typically 88 dB S/(N+D)
4
3
2
DIR
14
15
3
1
2
16
DIL
1
STBY
0.01 µ F
+5V
22 pF
200 k Ω
16.9344 MHz
499
0.1 µ F
499
2000
1000
–
+
+
–
1000
+5V
MC33077
+5V
1000
1000
1000
VR
VL
MC145074
12
7
WCLK
* ALL RESISTORS 1%
10
6
8
11
5
BCLK
12
13
4
DIR
1/6 MC74HC04
+
10 µF
4640
11
10
9
7
8
12
13
14
15
16
9
10
11
12
13
14
15
16
6
5
4
3
2
4640
22 pF
MC145076
10 µF
+
249
0.1
µF
249
249
249
Figure 15. Mid Performance Stereo Audio System, Typically 98 dB S/(N+D)
1/6 MC74HC04
1
8
7
6
3
DIL
14
4
3
2
5
+
10 µF
1
15
16
2
1
MC145074
STBY
0.01 µ F
+5V
+5V
22 pF
200 k Ω
22.5792 MHz
MC145076
MOTOROLA
1000
1000
1000
–
+
+
–
1000
–5V
+5V
MC33077
–5V
+5V
1000
1000
1000
VR
VL
MOTOROLA
10
9
6
7
8
WCLK
* ALL RESISTORS 1%
11
5
BCLK
12
13
4
1/6 MC74HC04
4640
11
10
9
7
8
12
13
14
15
16
9
10
11
12
13
14
15
16
6
5
4
3
4640
22 pF
MC145076
10 µF
+
499
0.1
µF
499
499
2000
1000
499
Figure 16. High Performance Stereo Audio System, Typically 105 dB S/(N+D)
1/6 MC74HC04
+
10 µF
2
1
8
7
6
3
14
4
3
2
5
+
10 µF
1
15
16
DIL
2
1
MC145074
DIR
STBY
0.01 µ F
+5V
+5V
22 pF
200 k Ω
22.5792 MHz
MC145076
MC145074
13
–
+
–
+
+
–
+
–
1000
1000
+5V
+5V
+5V
1000
+5V
1000
1000
1000
1000
1000
–
+
1000
1000
+
–
1000
–5V
+5V
MC33077
–5V
+5V
1000
1000
1000
VR
VL
PACKAGE DIMENSIONS
SOIC PACKAGE
CASE 751B–05
-A-
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
-B1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
-TSEATING
PLANE
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.229 0.244
0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC145074
14
◊
*MC145074/D*
MC145074/D
MOTOROLA