AD ADUM4223CRWZ Isolated precision half-bridge driver Datasheet

Isolated Precision Half-Bridge Driver,
4 A Output
ADuM3223/ADuM4223
Data Sheet
FEATURES
GENERAL DESCRIPTION
4 A peak output current
Working voltage
High-side or low-side relative to input: 565 VDC PEAK
High-side to low-side differential: 700 VDC PEAK
High frequency operation: 1 MHz maximum
3.3 V to 5 V CMOS input logic
4.5 V to 18 V output drive
UVLO at 2.5 V VDD1
ADuM3223A/ADuM4223A UVLO at 4.1 V VDD2
ADuM3223B/ADuM4223B UVLO at 7.0 V VDD2
ADuM3223C/ADuM4223C UVLO at 11.0 V VDD2
Precise timing characteristics
49 ns maximum isolator and driver propagation delay
5 ns maximum channel-to-channel matching
CMOS input logic levels
High common-mode transient immunity: >50 kV/µs
Enhanced system-level ESD performance per IEC 61000-4-x
High junction temperature operation: 125°C
Default low output
Safety and regulatory approvals (pending)
ADuM3223 narrow body, 16-lead SOIC
UL 1577 3000 V rms input-to-output withstand voltage
ADuM4223 wide body, 16-lead SOIC
UL 1577 5000 V rms input-to-output withstand voltage
The ADuM3223/ADuM4223 1 are 4 A isolated, half-bridge
gate drivers that employ the Analog Devices, Inc., iCoupler®
technology to provide independent and isolated high-side
and low-side outputs. The ADuM3223 provides 3000 V rms
isolation in the narrow body, 16-lead SOIC package, and the
ADuM4223 provides 5000 V rms isolation in the wide body,
16-lead SOIC package. Combining high speed CMOS and
monolithic transformer technology, these isolation components
provide outstanding performance characteristics superior to the
alternatives, such as the combination of pulse transformers and
gate drivers.
APPLICATIONS
As a result, the ADuM3223/ADuM4223 provide reliable
control over the switching characteristics of IGBT/MOSFET
configurations over a wide range of positive or negative
switching voltages.
The ADuM3223/ADuM4223 isolators each provide two
independent isolated channels. They operate with an input
supply ranging from 3.0 V to 5.5 V, providing compatibility
with lower voltage systems. In comparison to gate drivers
employing high voltage level translation methodologies, the
ADuM3223/ADuM4223 offer the benefit of true, galvanic
isolation between the input and each output. Each output may
be continuously operated up to 560 VPEAK relative to the input,
thereby supporting low-side switching to negative voltages. The
differential voltage between the high-side and low-side may be
as high as 700 VPEAK.
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
FUNCTIONAL BLOCK DIAGRAM
VIB 2
ADuM3223/
ADuM4223
ENCODE
16 VDDA
DECODE
VDD1 3
15 VOA
14 GNDA
GND1 4
13 NC
DISABLE 5
12 NC
11 VDDB
NC 6
NC 7
ENCODE
DECODE
VDD1 8
10 VOB
9
NC = NO CONNECT
GNDB
10450-001
VIA 1
Figure 1.
1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
ADuM3223/ADuM4223
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................9
Applications ....................................................................................... 1
ESD Caution...................................................................................9
General Description ......................................................................... 1
Pin Configuration and Function Descriptions........................... 11
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 12
Revision History ............................................................................... 2
Applications Information .............................................................. 15
Specifications..................................................................................... 3
PC Board Layout ........................................................................ 15
Electrical Characteristics—5 V Operation ................................ 3
Propagation Delay-Related Parameters................................... 15
Electrical Characteristics—3.3 V Operation ............................. 4
Thermal Limitations and Switch Load Characteristics ......... 15
Package Characteristics ............................................................... 5
Output Load Characteristics ..................................................... 15
Insulation and Safety-Related Specifications ............................ 5
DC Correctness and Magnetic Field Immunity........................... 16
Regulatory Information ............................................................... 6
Power Consumption .................................................................. 17
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 7
Insulation Lifetime ..................................................................... 17
Outline Dimensions ....................................................................... 18
Recommended Operating Conditions ...................................... 8
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/12—Revision 0: Initial Version
Rev. 0| Page 2 of 20
Data Sheet
ADuM3223/ADuM4223
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 12 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Per Channel, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
VDDA/VDDB Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD2 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current 1
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
ADuM3223A/ADuM4223A
Symbol
Typ
Max
Unit
IDDI(Q)
IDDO(Q)
1.4
2.3
2.4
3.2
mA
mA
IDD1(Q)
IDDA/IDDB(Q)
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
1.6
5.6
+0.01
2.5
8.0
+1
mA
mA
µA
V
V
V
V
Up to 1 MHz, no load
Up to 1 MHz, no load
0 ≤ VIA, VIB ≤ VDD1
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC)
ROA, ROB
ROA, ROB
PW
Min
−1
0.7 × VDD1
0.3 × VDD1
VDD2 – 0.1
3.2
5.7
8.9
2.0
VDD2
0.0
0.15
Test Conditions
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
4.1
3.6
0.5
4.4
V
V
V
A-grade
A-grade
A-grade
6.9
6.2
0.7
10.5
9.6
0.9
4.0
1.1
0.6
7.4
V
V
V
V
V
V
A
Ω
Ω
B-grade
B-grade
B-grade
C-grade
C-grade
C-grade
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V; see Figure 20
11.1
tDHL, tDLH
50
1
26
38
49
ns
MHz
ns
tDHL, tDLH
30
42
54
ns
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
12
ns
CL = 2 nF, VDD2 = 12 V; see Figure 20
Propagation Delay Skew 5
tPSK
Channel-to-Channel Matching 6
tPSKCD
1
5
ns
CL = 2 nF, VDD2 = 12 V; see Figure 20
tPSKCD
1
7
ns
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
12
18
ns
CL = 2 nF, VDD2 = 12 V; see Figure 20
VDD2 = 12 V
VDD2 = 12 V
Output Rise/Fall Time (10% to 90%)
tR/tF
Dynamic Input Supply Current Per Channel
Dynamic Output Supply Current Per Channel
Refresh Rate
IDDI(D)
IDDO(D)
fr
6
0.05
1.65
1.2
1
mA/Mbps
mA/Mbps
Mbps
Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay
parameters.
5
tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
6
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.
2
Rev. 0| Page 3 of 20
ADuM3223/ADuM4223
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 12 V. Switching
specifications are tested with CMOS signal levels.
Table 2.
Parameter
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current, Per Channel, Quiescent
Supply Current at 1 MHz
VDD1 Supply Current
VDDA/VDDB Supply Current
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD2 Supply
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Positive Going Threshold
Negative Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current 1
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
ADuM3223A/ADuM4223A
Symbol
Typ
Max
Unit
IDDI(Q)
IDDO(Q)
0.87
2.3
1.4
3.2
mA
mA
IDD1(Q)
IDDA/IDDB(Q)
IIA, IIB
VIH
VIL
VOAH, VOBH
VOAL, VOBL
1.1
5.6
+0.01
1.5
8.0
+10
mA
mA
µA
V
V
V
V
Up to 1 MHz, no load
Up to 1 MHz, no load
0 ≤ VIA, VIB ≤ VDD1
V
V
V
V
V
V
V
V
V
A
Ω
Ω
A-grade
A-grade
A-grade
B-grade
B-grade
B-grade
C-grade
C-grade
C-grade
VDD2 = 12 V
VDD2 = 12 V
VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V
CL = 2 nF, VDD2 = 12 V, see Figure 20
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC)
ROA, ROB
ROA, ROB
PW
Min
−10
0.7 × VDD1
0.3 × VDD1
VDD2 – 0.1
3.2
5.7
8.9
2.0
VDD2
0.0
4.1
3.6
0.5
6.9
6.2
0.7
10.5
9.6
0.9
4.0
1.1
0.6
0.15
4.4
7.4
11.1
Test Conditions
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
tDHL, tDLH
50
1
30
42
54
ns
MHz
ns
tDHL, tDLH
32
46
60
ns
CL = 2 nF, VDD2 = 4.5 V, see Figure 20
12
ns
CL = 2 nF, VDD2 = 12 V, see Figure 20
Propagation Delay Skew 5
tPSK
Channel-to-Channel Matching 6
tPSKCD
1
5
ns
CL = 2 nF, VDD2 = 12 V, see Figure 20
tPSKCD
1
7
ns
CL = 2 nF, VDD2 = 4.5 V, see Figure 20
12
22
ns
CL = 2 nF, VDD2 = 12 V, see Figure 20
VDD2 = 12 V
VDD2 = 12 V
Output Rise/Fall Time (10% to 90%)
tR/tF
Dynamic Input Supply Current Per Channel
Dynamic Output Supply Current Per Channel
Refresh Rate
IDDI(D)
IDDO(D)
fr
6
0.05
1.65
1.1
1
mA/Mbps
mA/Mbps
Mbps
Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings.
The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
4
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay
parameters.
5
tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
6
Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.
2
3
Rev. 0| Page 4 of 20
Data Sheet
ADuM3223/ADuM4223
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input-to-Output)
Capacitance (Input-to-Output)
Input Capacitance
IC Junction-to-Ambient Thermal Resistance
ADuM3223
ADuM4223
IC Junction-to-Case Thermal Resistance
ADuM3223
ADuM4223
Symbol
RI-O
CI-O
CI
Min
Typ
1012
2.0
4.0
Max
Unit
Ω
pF
pF
θJA
θJA
76
45
°C/W
°C/W
θJC
θJC
42
29
°C/W
°C/W
Test Conditions
f = 1 MHz
INSULATION AND SAFETY-RELATED SPECIFICATIONS
ADuM3223
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
3000
4.0 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
4.0 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>400
II
mm
V
Unit
V rms
mm
Conditions
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM4223
Table 5.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
5000
8.0 min
Minimum External Tracking (Creepage)
L(I02)
7.6 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>400
II
mm
V
Rev. 0| Page 5 of 20
Conditions
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM3223/ADuM4223
Data Sheet
REGULATORY INFORMATION
The ADuM3223 approval is pending by the organizations listed in Table 6.
Table 6.
UL
Recognized under UL 1577
Component Recognition
Program 1
Single/Protection 3000 V rms
Isolation Voltage
File E214100
1
2
CSA
Approved under CSA Component Acceptance Notice #5A
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12 2
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
400 V rms (565 V peak) maximum working voltage
File 205078
Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM3223 is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 second (current leakage detection limit = 6 µA).
In accordance with DIN V VDE V 0884-10, each ADuM3223 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
The ADuM4223 approval is pending by the organizations listed in Table 7.
Table 7.
UL
Recognized under UL 1577
Component Recognition
Program 1
Single/Protection 5000 V rms
Isolation Voltage
File E214100
1
2
CSA
Approved under CSA Component Acceptance Notice #5A
VDE
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12 2
Reinforced insulation per CSA 60950-1-07 and IEC 60950-1,
400 V rms (565 V peak) maximum working voltage
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
800 V rms (1131 V peak) maximum working voltage
File 205078
Reinforced insulation, 849 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM4223 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA).
In accordance with DIN V VDE V 0884-10, each ADuM4223 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection
limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval.
Rev. 0| Page 6 of 20
Data Sheet
ADuM3223/ADuM4223
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 8. ADuM3223 VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety-Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Conditions
Symbol
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd(m), tini = 60 sec,
tm = 10 sec, partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec,
tm = 10 sec, partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
VIO = 500 V
Characteristic
Unit
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
Vpd(m)
896
672
V peak
V peak
VIOTM
VIOSM
4000
6000
V peak
V peak
TS
PS
RS
150
1.64
>109
°C
W
Ω
VIORM
Vpd(m)
Vpd(m)
Table 9. ADuM4223 VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage
Safety-Limiting Values
Maximum Junction Temperature
Safety Total Dissipated Power
Insulation Resistance at TS
Conditions
Symbol
VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time
Maximum value allowed in the event of a failure
(see Figure 2)
VIO = 500 V
Rev. 0| Page 7 of 20
Characteristic
Unit
I to IV
I to III
I to II
40/105/21
2
849
1592
V peak
V peak
Vpd(m)
1273
1018
V peak
V peak
VIOTM
VIOSM
6000
6000
V peak
V peak
TS
PS
RS
150
2.77
>109
°C
W
Ω
VIORM
Vpd(m)
Vpd(m)
Data Sheet
RECOMMENDED OPERATING CONDITIONS
1.8
Table 10.
1.6
Parameter
Operating Junction
Temperature
Supply Voltages 1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
10450-102
SAFE OPERATING PVDD1 , PVDDA OR PVDDB POWER (W)
ADuM3223/ADuM4223
1
3.0
2.5
2.0
1.5
1.0
0.5
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
Min
−40
Max
+125
Unit
°C
5.5
18
1
1
V
V
V/µs
ms
−50
+50
kV/µs
−50
+50
kV/µs
VDD1
3.0
VDDA, VDDB 4.5
TVDD1
TVIA, TVIB
All voltages are relative to their respective ground. See the Applications
Information section for information on immunity to external magnetic fields.
10450-103
SAFE OPERATING PVDD1 , PVDDA OR PVDDB POWER (W)
Figure 2. ADuM3223 Thermal Derating Curve, Dependence of SafetyLimiting Values on Case Temperature, per DIN V VDE V 0884-10
VDD1 Rise Time
Maximum Input Signal Rise and
Fall Times
Common-Mode Transient
Immunity, Input to Output
Common-Mode Transient
Between Outputs
Symbol
TJ
Figure 3. ADuM4223 Thermal Derating Curve, Dependence of SafetyLimiting Values on Case Temperature, per DIN V VDE V 0884-10
Rev. 0| Page 8 of 20
Data Sheet
ADuM3223/ADuM4223
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 11.
Parameter
Storage Temperature
Operating Junction
Temperature
Supply Voltages1
Input Voltage1
Output Voltage1
Average Output
Current, per Pin2
Common-Mode
Transients3
Symbol
TST
TJ
Rating
−55 °C to +150 °C
−40 °C to +150 °C
VDD1
VDDA ,VDDB
VIA, VIB,
DISABLE
VOA
VOB
IO
−0.5 V to +7.0 V
−0.5 V to +20 V
−0.5 V to VDD1 + 0.5 V
CMH, CML
−100 kV/µs to +100 kV/µs
ESD CAUTION
−0.5 V to VDDA + 0.5 V
−0.5 V to VDDB + 0.5 V
−35 mA to +35 mA
1
All voltages are relative to their respective ground.
See Figure 2 and Figure 3 for information on maximum allowable current for
various temperatures.
3
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating can cause
latch-up or permanent damage.
2
Rev. 0| Page 9 of 20
ADuM3223/ADuM4223
Data Sheet
Table 12. Maximum Continuous Working Voltage 1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
DC Voltage
1
Max
565
1131
1131
Unit
V peak
V peak
V peak
Constraint
50-year minimum lifetime
50-year minimum lifetime
50-year minimum lifetime
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 13. Truth Table ADuM3223/ADuM4223 (Positive Logic)1
VIA
DISABLE Input
L
L
VIB
Input
L
VDD1 State
Powered
VDDA/VDDB State
Powered
VOA Output
L
VOB Output
L
L
L
H
Powered
Powered
L
H
L
H
L
Powered
Powered
H
L
L
H
H
Powered
Powered
H
H
H
X
X
Powered
Powered
L
L
L
L
L
Unpowered
Powered
L
L
X
X
X
Powered
Unpowered
Indeterminate
Indeterminate
1
X = don’t care, L = low, and H = high.
Rev. 0| Page 10 of 20
Notes
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs return to the input state within
1 µs of DISABLE = L assertion.
Outputs take on default low state
within 3 µs of DISABLE = H assertion.
Outputs return to the input state within
1 µs of VDD1 power restoration.
Outputs return to the input state within
1 µs of VDDA/VDDB power restoration.
Data Sheet
ADuM3223/ADuM4223
VIA 1
16
VDDA
VIB 2
15
VOA
14
GNDA
13
NC
12
NC
NC 6
11
VDDB
NC 7
10
VOB
VDD1 8
9
GNDB
VDD1 3
GND1 4
DISABLE 5
ADuM3223/
ADuM4223
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
DO NOT CONNECT TO THIS PIN.
10450-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 14. ADuM3223/ADuM4223 Pin Function Descriptions
Pin No. 1
1
6, 7, 12, 13
2
3, 8
4
5
Mnemonic
VIA
NC
VIB
VDD1
GND1
DISABLE
9
10
11
14
15
16
GNDB
VOB
VDDB
GNDA
VOA
VDDA
1
Description
Logic Input A.
No Connect.
Logic Input B.
Input Supply Voltage.
Ground Reference for Input Logic Signals.
Input Disable. Disables the isolator inputs and refresh circuits. Outputs take on default low state within 3 µs
of DISABLE = H assertion. Outputs return to the input state within 1 µs of DISABLE = L assertion.
Ground Reference for Output B.
Output B.
Output B Supply Voltage.
Ground Reference for Output A.
Output A.
Output A Supply Voltage.
Pin 3 and Pin 8 are internally connected; connecting both pins to supply VDD1 is recommended.
For specific layout guidelines, refer to the AN-1109 Application Note, Recommendations for Control of Radiated Emissions with iCoupler
Devices.
Rev. 0| Page 11 of 20
ADuM3223/ADuM4223
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1000
CH2 = VO (5V/DIV)
800
GATE CHARGE (nC)
VDD2 = 5V
2
600
VDD2 = 8V
400
CH1 = VI (5V/DIV)
VDD2 = 10V
200
1
CH1 5.00V Ω
M40.0ns
2.50GS/s
100k POINTS
A CH1
2.70V
10450-105
CH1 5.00V
0
b
a
b
–820ps
10.5ns
Δ11.3ns
400
600
800
1000
SWITCHING FREQUENCY (kHz)
Figure 8. Typical ADuM4223 Maximum Load vs. Frequency (RG = 1 Ω)
Figure 5. Output Waveform for 2 nF Load with
12 V Output Supply
a
200
10450-108
VDD2 = 15V
0
3.0
1.40V
11.4V
Δ10.0V
2.5
IDD1 CURRENT (mA)
CH2 = VOB (5V/DIV)
2
CH1 = VOA (5V/DIV)
2.0
VDD1 = 5V
1.5
VDD1 = 3.3V
1.0
0.5
CH2 5.00V Ω
M20.0ns
2.50GS/s
100k POINTS
A CH1
2.70V
0
10450-106
CH1 5.00V
0
50
400
40
IDDA , IDDB CURRENT (mA)
GATE CHARGE (nC)
0.75
1.00
Figure 9. Typical IDD1 Supply Current vs. Frequency
500
VDD2 = 5V
VDD2 = 8V
200
0.50
FREQUENCY (MHz)
Figure 6. Output Matching and Rise Time Waveforms for 2 nF Load
with 12 V Output Supply
300
0.25
10450-109
1
VDD2 = 10V
100
VDD2 = 15V
30
VDD2 = 10V
20
VDD2 = 5V
10
200
400
600
SWITCHING FREQUENCY (kHz)
800
1000
0
10450-107
0
Figure 7. Typical ADuM3223 Maximum Load vs. Frequency (RG = 1 Ω)
0
0.25
0.50
FREQUENCY (MHz)
0.75
1.00
10450-110
VDD2 = 15V
0
Figure 10. Typical IDDA, IDDB Supply Current vs. Frequency with 2 nF Load
Rev. 0| Page 12 of 20
Data Sheet
ADuM3223/ADuM4223
60
30
25
tDHL
40
RISE/FALL TIME (ns)
tDLH
30
20
10
FALL TIME
10
RISE TIME
20
40
60
80
100
120
140
0
Figure 11. Typical Propagation Delay vs. Temperature
5
7
9
11
13
15
10450-114
0
10450-111
–20
JUNCTION TEMPERATURE (°C)
17
OUTPUT SUPPLY VOLTAGE (V)
Figure 14. Typical Rise/Fall Time Variation vs. Output Supply Voltage
5
PROPAGATION DELAY CH-CH MATCHING (ns)
60
tDHL
40
tDLH
30
20
0
3.0
3.5
4.0
4.5
5.0
5.5
INPUT SUPPLY VOLTAGE (V)
Figure 12. Typical Propagation Delay vs. Input Supply Voltage,
VDDA, VDDB = 12 V
3
2
PD MATCH tDHL
PD MATCH tDLH
1
0
10450-112
10
4
5
7
9
11
13
15
10450-115
50
PROPAGATION DELAY (ns)
15
5
0
–40
17
OUTPUT SUPPLY VOLTAGE (V)
Figure 15. Typical Propagation Delay, Channel-to-Channel Matching vs.
Output Supply Voltage
5
PROPAGATION DELAY CH-CH MATCHING (ns)
60
50
tDHL
40
tDLH
30
20
10
0
5
7
9
11
13
15
17
OUTPUT SUPPLY VOLTAGE (V)
Figure 13. Typical Propagation Delay vs. Input Supply Voltage,
VDD1 = 5 V
4
3
2
PD MATCH tDLH
1
0
–40
10450-113
PROPAGATION DELAY (ns)
20
PD MATCH tDHL
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
120
140
10450-116
PROPAGATION DELAY (ns)
50
Figure 16. Typical Propagation Delay, Channel-to-Channel Matching vs.
Temperature, VDDA, VDDB = 12 V
Rev. 0| Page 13 of 20
ADuM3223/ADuM4223
Data Sheet
8
1.4
7
1.2
SOURCE/SINK CURRENT (A)
1.6
VOUT SOURCE RESISTANCE
0.8
VOUT SINK RESISTANCE
0.6
0.4
5
4
SOURCE IOUT
3
2
1
0
4
6
8
10
12
14
16
18
OUTPUT SUPPLY VOLTAGE (V)
Figure 17. Typical Output Resistance vs. Output Supply Voltage
0
4
6
8
10
12
14
16
18
OUTPUT SUPPLY VOLTAGE (V)
Figure 18. Typical Output Current vs. Output Supply Voltage
Rev. 0| Page 14 of 20
10450-118
0.2
10450-117
ROUT (Ω)
1.0
SINK IOUT
6
Data Sheet
ADuM3223/ADuM4223
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM3223/ADuM4223 digital isolators require no external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins, as
shown in Figure 19. Use a small ceramic capacitor with a value
between 0.01 μF and 0.1 μF to provide a good high frequency
bypass. On the output power supply pin, VDDA or VDDB, it is
recommended to also add a 10 μF capacitor to provide the
charge required to drive the gate capacitance at the ADuM3223/
ADuM4223 outputs. On the output supply pin, the bypass
capacitor use of vias should be avoided or multiple vias should
be employed to reduce the inductance in the bypassing. The
total lead length between both ends of the smaller capacitor and
the input or output power supply pin should not exceed 5 mm.
VDDA
VIB
VOA
VDD1
GNDB
GND1
NC
DISABLE
NC
VDDB
NC
VOB
GND1
GNDB
Figure 19. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output. The ADuM3223/ADuM4223 specify tDLH
(see Figure 20) as the time between the rising input high logic
threshold, VIH, to the output rising 10% threshold. Likewise, the
falling propagation delay, tDHL, is defined as the time between
the input falling logic low threshold, VIL, and the output falling
90% threshold. The rise and fall times are dependent on the
loading conditions and are not included in the propagation
delay, which is the industry standard for gate drivers.
90%
OUTPUT
10%
VIH
INPUT
VIL
tR
tF
Figure 20. Propagation Delay Parameters
10450-005
tDHL
tDLH
THERMAL LIMITATIONS AND SWITCH LOAD
CHARACTERISTICS
For isolated gate drivers, the necessary separation between the
input and output circuits prevents the use of a single thermal
pad beneath the part, and heat is, therefore, dissipated mainly
through the package pins.
Package thermal dissipation limits the performance of switching
frequency vs. output load, as illustrated in Figure 7 and Figure 8
for the maximum load capacitance that can be driven with a 1 Ω
series gate resistance for different values of output voltage. For
example, this curve shows that a typical ADuM3223 can drive a
large MOSFET with 140 nC gate charge at 8 V output (which is
equivalent to a 17 nF load) up to a frequency of about 300 kHz.
OUTPUT LOAD CHARACTERISTICS
10450-119
NC
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3223/
ADuM4223 components operating under the same conditions.
The ADuM3223/ADuM4223 output signals depend on the
characteristics of the output load, which is typically an N-channel
MOSFET. The driver output response to an N-channel MOSFET
load can be modeled with a switch output resistance (RSW), an
inductance due to the printed circuit board trace (LTRACE), a series
gate resistor (RGATE), and a gate-to-source capacitance (Cgs), as
shown in Figure 21.
VIA
ADuM3223/
ADuM4223
VOA RSW
RGATE
LTRACE
VO
CGS
10450-006
VIA
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3223/ADuM4223 component.
Figure 21. RLC Model of the Gate of an N-Channel MOSFET
RSW is the switch resistance of the internal ADuM3223/
ADuM4223 driver output, which is about 1.1 Ω. RGATE is the
intrinsic gate resistance of the MOSFET and any external series
resistance. A MOSFET that requires a 4 A gate driver has a
typical intrinsic gate resistance of about 1 Ω and a gate-tosource capacitance, CGS, of between 2 nF and 10 nF. LTRACE is the
inductance of the printed circuit board trace, typically a value of
5 nH or less for a well-designed layout with a very short and wide
connection from the ADuM3223/ADuM4223 output to the gate
of the MOSFET.
The following equation defines the Q factor of the RLC circuit,
which indicates how the ADuM3223/ADuM4223 output
responds to a step change. For a well-damped output, Q is
less than 1. Adding a series gate resistance dampens the output
response.
Rev. 0| Page 15 of 20
ADuM3223/ADuM4223
Output ringing can be reduced by adding a series gate resistance
to dampen the response. For applications of less than 1 nF load,
it is recommended to add a series gate resistor of about 2 Ω
to 5 Ω.
The ADuM3223/ADuM4223 is immune to external magnetic
fields. The limitation on the ADuM3223/ADuM4223 magnetic
field immunity is set by the condition in which induced voltage
in the transformer receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3223/ADuM4223 is examined because
it represents the most susceptible mode of operation. The pulses
at the transformer output have an amplitude greater than 1.0 V.
The decoder has a sensing threshold at about 0.5 V, therefore
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑π rn2, n = 1, 2, ... , N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
0.1
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 22. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.08 kgauss induces a voltage
of 0.25 V at the receiving coil. This is about 50% of the sensing
threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse
(and had the worst-case polarity), the received pulse is reduced
from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM3223/ADuM4223 transformers. Figure 23 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM3223/ADuM4223
are immune and only can be affected by extremely large currents
operated at a high frequency and very close to the component.
For the 1 MHz example, a 0.2 kA current must be placed 5 mm
away from the ADuM3223/ADuM4223 to affect the
component’s operation.
1k
MAXIMUM ALLOWABLE CURRENT (kA)
If the decoder receives no internal pulses for more than about
3 µs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default
low state by the watchdog timer circuit. In addition, the outputs
are in a low default state while the power is coming up before
the UVLO threshold is crossed.
1
0.01
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions of more than 1 µs at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output.
10
10450-122
In Figure 5, the ADuM3223/ADuM4223 output waveforms
for a 12 V output are shown for a CGS of 2 nF. Note the small
amount of ringing of the output in Figure 5 with CGS of 2 nF,
RSW of 1.1 Ω, RGATE of 0 Ω, and a calculated Q factor of 0.75,
where less than 1 is desired for good damping.
Given the geometry of the receiving coil in the ADuM3223/
ADuM4223 and an imposed requirement that the induced
voltage is, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field is calculated, as shown in
Figure 22.
Rev. 0| Page 16 of 20
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 23. Maximum Allowable Current for Various
Current-to-ADuM3223/ADuM4223 Spacings
100M
10450-123
(R SW
100
L
1
× TRACE
+ RGATE )
C GS
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
Q=
Data Sheet
Data Sheet
ADuM3223/ADuM4223
POWER CONSUMPTION
The values shown in Table 11 summarize the peak voltage for
50 years of service life for a bipolar ac operating condition, and
the maximum CSA/VDE approved working voltages. In many
cases, the approved working voltage is higher than 50-year
service life voltage. Operation at these high working voltages
can lead to shortened insulation life in some cases.
For each input channel, the supply current is given by
IDDI = IDDI(Q)
f ≤ 0.5fr
IDDI = IDDI(D) × (2f – fr) + IDDI(Q)
f > 0.5fr
For each output channel, the supply current is given by
f ≤ 0.5fr
IDDO = (IDDO(D) + (0.5) × CLVDDO) × (2f – fr) + IDDO(Q)
f > 0.5fr
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
IDDI(Q), IDDO(Q) are the specified input and output quiescent supply
currents (mA).
To calculate the total supply current, the supply currents for
each input and output channel corresponding to IDD1, IDDA, and
IDDB are calculated and totaled.
Figure 9 provides total input IDD1 supply current as a function
of data rate for both input channels. Figure 10 provides total IDDA
or IDDB supply current as a function of data rate for both outputs
loaded with 2 nF capacitance.
A bipolar ac voltage environment is the worst case for the
iCoupler products and is the 50-year operating lifetime that
Analog Devices recommends for maximum working voltage. In
the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. Any crossinsulation voltage waveform that does not conform to Figure 25
or Figure 26 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 12.
Note that the voltage presented in Figure 25 is shown as sinusoidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.
RATED PEAK VOLTAGE
0V
Figure 24. Bipolar AC Waveform
INSULATION LIFETIME
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined.
These factors allow calculation of the time to failure at the actual
working voltage.
Rev. 0| Page 17 of 20
RATED PEAK VOLTAGE
10450-010
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM3223/
ADuM4223.
0V
Figure 25. Unipolar AC Waveform
RATED PEAK VOLTAGE
10450-011
IDDO = IDDO(Q)
The insulation lifetime of the ADuM3223/ADuM4223 depends
on the voltage waveform type imposed across the isolation
barrier. The iCoupler insulation structure degrades at different
rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 24, Figure 25, and Figure 26 illustrate these
different isolation voltage waveforms.
10450-009
The supply current at a given channel of the ADuM3223/
ADuM4223 isolator is a function of the supply voltage,
channel data rate, and channel output load.
0V
Figure 26. DC Waveform
ADuM3223/ADuM4223
Data Sheet
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
9
16
4.00 (0.1575)
3.80 (0.1496)
1
8
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
060606-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 27. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
Rev. 0| Page 18 of 20
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Data Sheet
ADuM3223/ADuM4223
ORDERING GUIDE
Model 1
ADuM3223ARZ
ADuM3223ARZ-RL7
No. of
Channels
2
2
Output
Peak
Current (A)
4
4
Minimum
Output
Voltage (V)
4.5
4.5
Temperature
Range
−40°C to +125°C
−40°C to +125°C
ADuM3223BRZ
ADuM3223BRZ-RL7
2
2
4
4
7.5
7.5
−40°C to +125°C
−40°C to +125°C
ADuM3223CRZ
ADuM3223CRZ-RL7
2
2
4
4
11.5
11.5
−40°C to +125°C
−40°C to +125°C
ADuM4223ARWZ
ADuM4223ARWZ-RL
2
2
4
4
4.5
4.5
−40°C to +125°C
−40°C to +125°C
ADuM4223BRWZ
ADuM4223BRWZ-RL
2
2
4
4
7.5
7.5
−40°C to +125°C
−40°C to +125°C
ADuM4223CRWZ
ADuM4223CRWZ-RL
2
2
4
4
11.5
11.5
−40°C to +125°C
−40°C to +125°C
EVAL-ADuM3223AEBZ 2
4
4.5
−40°C to +125°C
EVAL-ADuM4223AEBZ 2
4
4.5
−40°C to +125°C
1
Z = RoHS Compliant Part.
Rev. 0| Page 19 of 20
Package Description
16-Lead SOIC_N
16-Lead SOIC_N, 13” Tape
and Reel
16-Lead SOIC_N
16-Lead SOIC_N, 13” Tape
and Reel
16-Lead SOIC_N
16-Lead SOIC_N, 13” Tape
and Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Tape
and Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Tape
and Reel
16-Lead SOIC_W
16-Lead SOIC_W, 13” Tape
and Reel
ADuM3223 evaluation
board
ADuM4223 evaluation
board
Package
Option
R-16
R-16
Ordering
Quantity
1,000
R-16
R-16
1,000
R-16
R-16
1,000
RW-16
RW-16
1,000
RW-16
RW-16
1,000
RW-16
RW-16
1,000
ADuM3223/ADuM4223
Data Sheet
NOTES
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