IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 32-BIT BUFFER/ DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH32244 DESCRIPTION: FEATURES: This 32-bit buffer/driver is built using advanced dual metal CMOS technology. This high-speed, low power device offers bus/backplane interface capability with improved packing density. The device has a flowthrough organization for simplifying board layout. The three-state controls operate this device in a Quad-Nibble, Dual-Byte or single 16-bit word mode. All inputs are designed with hysteresis for improved noise margin. The ALVCH32244 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH32244 has “bus-hold” which retains the inputs’ last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in 96-ball LFBGA package DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for Heavy Loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1OE A3 3OE 1A1 A5 A2 1Y1 1A2 A6 A1 1Y2 B5 B2 1Y3 1A3 1A4 2OE 2A1 2A2 B6 B1 C5 C2 C6 C1 D2 D6 D1 5OE 3A4 2Y1 2Y2 2Y3 2Y4 4A1 4A2 7OE E2 3Y1 5A1 J5 J2 5Y1 E6 E1 3Y2 5A2 J6 J1 5Y2 F5 F2 3Y3 5A3 K5 K2 5Y3 F6 F1 5A4 3Y4 H3 6OE G5 G2 4Y1 G6 G1 H6 H1 4A3 4A4 J3 E5 3A3 4OE 2A3 2A4 3A2 1Y4 A4 D5 3A1 H4 H5 H2 6A1 4Y2 6A2 4Y3 K6 K1 J4 L5 L2 6Y1 L6 L1 6Y2 M5 M2 6Y3 6A4 M6 7A2 M1 6Y4 N5 N2 N6 N1 P5 P2 P6 P1 7A3 7A4 8OE 6A3 4Y4 5Y4 7A1 T4 8A1 8A2 7Y2 7Y3 7Y4 T3 R5 R2 R6 R1 T6 T1 8Y3 T5 T2 8Y4 8A3 8A4 7Y1 8Y1 8Y2 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2000 1 ©2000 Integrated Device Technology, Inc. DSC-4906/1 IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION 6 1A2 1A4 2A2 2A4 3A2 3A4 4A2 4A3 5A2 5A4 6A2 6A4 7A2 7A4 8A2 8A3 5 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A4 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A4 4 2OE GND VCC GND GND VCC GND 3OE 6OE GND VCC GND GND VCC GND 7OE 3 1OE GND VCC GND GND VCC GND 4OE 5OE GND VCC GND GND VCC GND 8OE 2 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y4 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y4 1 1Y2 1Y4 2Y2 2Y4 3Y2 3Y4 4Y2 4Y3 5Y2 5Y4 6Y2 6Y4 7Y2 7Y4 8Y2 8Y3 A B C D E F G H J M N R T L K P LFBGA TOPVIEW 96 BALL LFBGA PACKAGE ATTRIBUTES 1.5mm Max. 1.4mm Nom. 1.3mm Min. 0.8mm 6 5 4 TOP VIEW 3 2 1 A B C D E F G H J K L M N P R T A B C D E F G H J K L M N P R T 1 2 3 5.5mm 4 5 6 13.5mm 2 IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA INDUSTRIAL TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. CIN Input Capacitance VIN = 0V 5 7 pF COUT Output Capacitance VOUT = 0V 7 9 pF CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 1. As applicable to the device type. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. FUNCTION TABLE (EACH 4-BIT BUFFER)(1) PIN DESCRIPTION Pin Names Inputs Description Outputs xOE xAx xYx Data Inputs L H H 3-State Outputs L L L H X Z xOE 3-State Output Enable Inputs (Active LOW) xAx xYx (1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 3 Unit IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 — µA µA IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Driver Outputs enabled CPD Power Dissipation Capacitance per Driver Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 32 38 pF 8 10 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter tPLH Propagation Delay tPHL xAx to xYx tPZH Output Enable Time tPZL xOE to xYx tPHZ Output Disable Time tPLZ xOE to xYx tSK(O) Output Skew(2) VCC = 3.3V ± 0.3V Max. Min. Max. Min. Max. Unit 1 3.7 — 3.6 1 3 ns 1 5.7 — 5.4 1 4.4 ns 1 5.2 — 4.6 1 4.1 ns — — — — — 500 ps NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 5 VCC = 2.7V Min. IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) Pulse Generator VIN tPHL VIH VT 0V ALVC Link DISABLE ENABLE VIH VT 0V CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPLH Propagation Delay VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test Switch TIMING INPUT Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open INPUT OUTPUT 1 tSK (x) VIH VT 0V tREM tSU tH Set-up, Hold, and Release Times VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 tH ALVC Link tPHL1 tPLH1 tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH32244 3.3V CMOS 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX ALVC IDT Temp. Range X Bus-Hold XX Family XX XXXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 BF Low Profile Fine Pitch Ball Grid Array 244 32-Bit Buffer/Driver with 3-State Outputs 32 32-Bit Bus Density, ±24mA H Bus-Hold 74 -40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459