CY62147EV30 MoBL® Automotive 4-Mbit (256K x 16) Static RAM Features also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: Very high speed: 45 ns Temperature ranges ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ Wide voltage range: 2.20 V to 3.60 V ■ Pin compatible with CY62147DV30 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A (Automotive-A) ■ Ultra low active power ❐ Typical active current: 2 mA (Automotive-A) at f = 1 MHz [1] and OE features ■ Easy memory expansion with CE ■ ■ ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 48-ball very fine ball grid array (VFBGA) (single/dual CE option) and 44-pin thin small outline package (TSOP) II packages ■ Byte power-down feature ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) ■ Write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Functional Description The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A17 A15 A16 A13 A14 CIRCUIT A12 BHE BLE A11 CE POWER DOWN BHE WE [1] CE OE BLE Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Cypress Semiconductor Corporation Document Number: 001-66256 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 31, 2011 [+] Feedback CY62147EV30 MoBL® Contents Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance........................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Document Number: 001-66256 Rev. ** Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY62147EV30 MoBL® Product Portfolio Product Range CY62147EV30LL Speed (ns) VCC Range (V) Min 2.2 2.2 Auto-A Auto-E Typ[2] 3.0 3.0 Max 3.6 3.6 45 ns 55 ns Power Dissipation Operating ICC (mA) Standby ISB2 (A) f = 1 MHz f = fmax Typ[2] Max Typ[2] Max Typ[2] Max 2 2.5 15 20 1 7 2 3 15 25 1 20 Pin Configuration Figure 1. 48-Ball VFBGA (Single Chip Enable) [3, 4] 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 A I/O0 B I/O8 BHE A3 A4 CE1 I/O0 B I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 C VCC D VSS I/O11 A17 A7 VCC D I/O4 VSS E VCC NC A16 I/O4 VSS E A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F 1 2 3 4 5 6 BLE OE A0 A1 A2 NC I/O8 BHE A3 A4 CE I/O9 I/O10 A5 A6 I/O1 VSS I/O11 A17 A7 VCC NC A16 I/O14 I/O13 A14 I/O12 Figure 2. 48-Ball VFBGA (Dual Chip Enable)[3, 4] I/O3 I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC H Figure 3. 44-Pin TSOP II [3] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 3. NC pins are not connected on the die. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. Document Number: 001-66256 Rev. ** Page 3 of 15 [+] Feedback CY62147EV30 MoBL® DC input voltage [5, 6] ........... –0.3 V to 3.9 V (VCCmax + 0.3 V) Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential .......................... –0.3 V to + 3.9 V (VCCmax + 0.3 V) DC voltage applied to outputs in High Z state [5, 6] .............. –0.3 V to 3.9 V (VCCmax + 0.3 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... >2001 V (MIL-STD-883, method 3015) Latch up current....................................................... >200 mA Operating Range Device Ambient Temperature Range CY62147EV30LL Auto-A VCC [7] –40 °C to +85 °C 2.2 V to 3.6 V Auto-E –40 °C to +125 °C Electrical Characteristics Over the Operating Range Parameter VOH Description 45 ns (Auto-A) Test Conditions Min Typ [8] 55 ns (Auto-E) Max Min Typ [8] Unit Max Output HIGH voltage IOH = –0.1 mA 2.0 – – 2.0 – – V IOH = –1.0 mA, VCC > 2.70 V 2.4 – – 2.4 – – V VOL Output LOW voltage IOL = 0.1 mA – – 0.4 – – 0.4 V VIH Input HIGH voltage VIL IOL = 2.1 mA, VCC = 2.70 V Input LOW voltage – – 0.4 – – 0.4 V VCC = 2.2 V to 2.7 V 1.8 – VCC + 0.3 1.8 – VCC + 0.3 V VCC= 2.7 V to 3.6 V 2.2 – VCC + 0.3 2.2 – VCC + 0.3 V VCC = 2.2 V to 2.7 V –0.3 – 0.6 –0.3 – 0.6 V VCC= 2.7 V to 3.6 V –0.3 – 0.8 –0.3 0.8 V IIX Input leakage current GND < VI < VCC –1 – +1 –4 – +4 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 –4 – +4 A ICC VCC operating supply current f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA f = 1 MHz CMOS levels – 15 20 – 15 25 mA – 2 2.5 – 2 3 ISB1 Automatic CE power-down current — CMOS inputs CE > VCC – 0.2 V VIN > VCC – 0.2 V, VIN < 0.2 V f = fmax (address and data only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60 V – 1 7 – 1 20 A ISB2 [9] Automatic CE CE > VCC – 0.2 V power-down VIN > VCC – 0.2 V or VIN < 0.2 V, current — CMOS f = 0, VCC = 3.60 V inputs – 1 7 – 1 20 A Capacitance For all packages.[10] Parameter CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Notes 5. VIL(min) = –2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-66256 Rev. ** Page 4 of 15 [+] Feedback CY62147EV30 MoBL® Thermal Resistance[13] Parameter Test Conditions VFBGA Package TSOP II Package Unit Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board 75 77 C / W 10 13 C / W Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Figure 4. AC Test Load and Waveforms R1 VCC OUTPUT VCC 30 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT Parameters RTH V 2.50 V 3.0 V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR[12] Data retention current tCDR Conditions Min Typ [11] Max Unit 1.5 – – V Auto-A – 0.8 7 A Auto-E – – 12 0 – – ns CY62147EV30LL-45 45 – – ns CY62147EV30LL-55 55 – – VCC= 1.5 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Chip deselect to data retention time [13] Operation recovery time tR [14] Figure 5. Data Retention Waveform[15, 16] DATA RETENTION MODE VCC CE or VCC(min) tCDR VDR > 1.5V VCC(min) tR BHE.BLE Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document Number: 001-66256 Rev. ** Page 5 of 15 [+] Feedback CY62147EV30 MoBL® Switching Characteristics Over the Operating Range Parameter[17, 18] Description 45 ns (Auto-A) 55 ns (Auto-E) Min Max Min Max Unit Read Cycle tRC Read cycle time 45 – 55 – ns tAA Address to data valid – 45 – 55 ns tOHA Data hold from address change 10 – 10 – ns tACE CE LOW to data valid – 45 – 55 ns tDOE OE LOW to data valid – 22 – 25 ns tLZOE OE LOW to LOW Z[19] 5 – 5 – ns tHZOE OE HIGH to High Z – 18 – 20 ns tLZCE CE LOW to Low Z 10 – 10 – ns tHZCE CE HIGH to High Z[19, 20] – 18 – 20 ns tPU CE LOW to power-up 0 – 0 – ns tPD CE HIGH to power-down – 45 – 55 ns tDBE BLE/BHE LOW to data valid – 45 – 55 ns tLZBE BLE/BHE LOW to Low Z[19] 10 – 10 – ns tHZBE BLE/BHE HIGH to HIGH Z[19, 20] – 18 – 20 ns tWC Write cycle time 45 – 55 – ns tSCE CE LOW to write end 35 – 40 – ns tAW Address setup to write end 35 – 40 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35 – 40 – ns tBW BLE/BHE LOW to write end 35 – 40 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 tHZWE WE LOW to High Z[19, 20] – 18 – 20 ns tLZWE WE HIGH to Low Z[19] 10 – 10 – ns Write Cycle [19, 20] [19] [21] ns Notes 17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Load and Waveforms on page 5. 18. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document Number: 001-66256 Rev. ** Page 6 of 15 [+] Feedback CY62147EV30 MoBL® Switching Waveforms Figure 6. Read Cycle No. 1 Address Transition Controlled[22, 23] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 7. Read Cycle No. 2: OE Controlled[23, 24, 25] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 22. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 23. WE is HIGH for read cycle. 24. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 25. Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 001-66256 Rev. ** Page 7 of 15 [+] Feedback CY62147EV30 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 1: WE Controlled [26, 27, 28, 29] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD tHD DATAIN NOTE 30 tHZOE Figure 9. Write Cycle No. 2: CE Controlled[26, 27, 28, 29] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 30 tHZOE Notes 26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 27. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 28. Data I/O is high impedance if OE = VIH. 29. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 30. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-66256 Rev. ** Page 8 of 15 [+] Feedback CY62147EV30 MoBL® Switching Waveforms (continued) Figure 10. Write Cycle No. 3: WE Controlled, OE LOW[31, 32] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 33 tHD DATAIN tLZWE tHZWE Figure 11. Write Cycle No. 4: BHE/BLE Controlled, OE LOW[31, 32] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 33 tSD tHD DATAIN tLZWE Notes 31. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 32. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 33. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-66256 Rev. ** Page 9 of 15 [+] Feedback CY62147EV30 MoBL® Truth Table I/Os Mode Power CE[34, 35] WE OE BHE BLE H X X X X High Z Deselect/power-down Standby (ISB) L X X H H High Z Deselect/power-down Standby (ISB) L H L L L Data out (I/O0–I/O15) Read Active (ICC) L H L H L Data out (I/O0–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Notes 34. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 35. For the Dual Chip Enable device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels is not permitted on any of the Chip Enable pins (CE for the Single Chip Enable device; CE1 and CE2 for the Dual Chip Enable device). Document Number: 001-66256 Rev. ** Page 10 of 15 [+] Feedback CY62147EV30 MoBL® Ordering Information Speed (ns) 45 55 Ordering Code Package Diagram Package Type CY62147EV30LL-45BVXA 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [36] CY62147EV30LL-45B2XA 51-85150 48-Ball Very Fine Pitch Ball Grid Array (Pb-free) [37] CY62147EV30LL-45ZSXA 51-85087 44-Pin Thin Small Outline Package II (Pb-free) CY62147EV30LL-55ZSXE 51-85087 44-Pin Thin Small Outline Package II (Pb-free) Operating Range Automotive-A Automotive-E Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 4 7 E V30 LL xx xxx x Temperature Range: A = Automotive-A, E = Automotive-E Package type: ZSX = TSOP II (Pb-free), BVX = VFBGA (Pb-free) etc. xx = Speed Grade 45 /55 ns Low Power Voltage Range (3V Typical) E = Process Technology 90 nm Buswidth = × 16 Density = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Notes 36. This BGA package is offered with single chip enable. 37. This BGA package is offered with dual chip enable. Document Number: 001-66256 Rev. ** Page 11 of 15 [+] Feedback CY62147EV30 MoBL® Package Diagrams Figure 12. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 51-85150 *F 51-85150 *F Document Number: 001-66256 Rev. ** Page 12 of 15 [+] Feedback CY62147EV30 MoBL® Package Diagrams (continued) Figure 13. 44-Pin TSOP II, 51-85087 51-85087 *C Acronyms Document Conventions Description Units of Measure CMOS complementary metal oxide semiconductor Symbol I/O input/output °C degrees Celsius SRAM static random access memory A microamperes VFBGA very fine ball grid array mA milliampere TSOP thin small outline package MHz megahertz Acronym Document Number: 001-66256 Rev. ** Unit of Measure ns nanoseconds pF picofarads V volts ohms W watts Page 13 of 15 [+] Feedback CY62147EV30 MoBL® Document History Page Document Title: CY62147EV30 MoBL® Automotive 4-Mbit (256K x 16) Static RAM Document Number: 001-66256 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3123973 RAME 01/31/2011 Created new datasheet for Automotive parts from document number 38-05440 Rev. *I Document Number: 001-66256 Rev. ** Page 14 of 15 [+] Feedback CY62147EV30 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-66256 Rev. ** Revised January 31, 2011 Page 15 of 15 MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback