www.fairchildsemi.com FSDM0565RB Green Mode Fairchild Power Switch (FPSTM) Features • Internal Avalanche Rugged Sense FET • Advanced Burst-Mode operation consumes under 1 W at 240VAC & 0.5W load • Precision Fixed Operating Frequency (66kHz) • Internal Start-up Circuit • Improved Pulse by Pulse Current Limiting • Over Voltage Protection (OVP) • Over Load Protection (OLP) • Internal Thermal Shutdown Function (TSD) • Auto-Restart Mode • Under Voltage Lock Out (UVLO) with hysteresis • Low Operating Current (2.5mA) • Built-in Soft Start Application OUTPUT POWER TABLE 230VAC ±15%(3) 85-265VAC PRODUCT Adapter(1) Open Frame(2) Adapter(1) Open Frame(2) FSDM0565RB 60W 70W 50W 60W FSDM0565RBI 60W 70W 50W 60W FSDM07652RB 70W 80W 60W 70W Table 1. Maximum Output Power Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. • SMPS for LCD monitor and STB • Adaptor Description The FSDM0565RB is an integrated Pulse Width Modulator (PWM) and Sense FET specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. This device is an integrated high voltage power switching regulator which combine an avalanche rugged Sense FET with a current mode PWM control block. The PWM controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (LEB), optimized gate driver, internal soft start, temperature compensated precise current sources for a loop compensation and self protection circuitry. Compared with discrete MOSFET and PWM controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. This device is a basic platform well suited for cost effective designs of flyback converters. FPSTM is a trademark of Fairchild Semiconductor Corporation. ©2006 Fairchild Semiconductor Corporation Typical Circuit AC IN DC OUT Vstr Drain PWM Vfb Vcc Source Figure 1. Typical Flyback Application Rev.1.0.6 FSDM0565RB Internal Block Diagram Vcc Drain 1 Vstr 6 3 N.C 5 Istart 0.5/0.7V + Vref 8V/12V Vcc Vcc good Internal Bias Vref OSC Idelay IFB 2.5R PWM S Q R Q FB 4 Soft start R Gate driver LEB VSD 2 GND Vcc S Q R Q Vovp TSD Vcc good Figure 2. Functional Block Diagram of FSDM0565RB 2 VCL FSDM0565RB Pin Definitions Pin Number Pin Name Pin Function Description 1 Drain This pin is the high voltage power Sense FET drain. It is designed to drive the transformer directly. 2 GND This pin is the control ground and the Sense FET source. Vcc This pin is the positive supply voltage input. During start up, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 12V, the internal high voltage current source is disabled and the power is supplied from the auxiliary transformer winding. 4 Vfb This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6.0V, the over load protection is activated resulting in shutdown of the FPSTM. 5 N.C - Vstr This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current source is disabled. 3 6 Pin Configuration TO-220F-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain I2-PAK-6L 6.Vstr 5.N.C. 4.Vfb 3.Vcc 2.GND 1.Drain Figure 3. Pin Configuration (Top View) 3 FSDM0565RB Absolute Maximum Ratings (Ta=25°C, unless otherwise specified) Parameter Drain-source voltage Vstr Max Voltage Pulsed Drain current (Tc=25°C) Symbol Value Unit VDSS 650 V VSTR 650 V IDM 11 ADC 2.8 A 1.7 A (1) Continuous Drain Current(Tc=25°C) ID Continuous Drain Current(Tc=100°C) Single pulsed avalanche energy (2) EAS 190 mJ Single pulsed avalanche current (3) IAS - A Supply voltage VCC 20 V Input voltage range VFB -0.3 to VCC V Total power dissipation(Tc=25°C) PD(Watt H/S) 45 (TO-220-6L) 75 (I2-PAK-6L) W Operating junction temperature Tj Internally limited °C Operating ambient temperature TA -25 to +85 °C TSTG -55 to +150 °C ESD Capability, HBM Model (All pins excepts for Vstr and Vfb) - 2.0 (GND-Vstr/Vfb=1.5kV) kV ESD Capability, Machine Model (All pins excepts for Vstr and Vfb) - 300 (GND-Vstr/Vfb=225V) V Unit Storage temperature range Notes: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L=14mH, starting Tj=25°C 3. L=13uH, starting Tj=25°C Thermal Impedance Parameter Symbol Package Value Junction-to-Ambient Thermal θJA(1) TO-220F-6L 49.90 I2-PAK-6L 30 Junction-to-Case Thermal θJC(2) TO-220F-6L 2.78 I2-PAK-6L 1.67 Notes: 1. Free standing with no heat-sink under natural convection. 2. Infinite cooling condition - Refer to the SEMI G30-88. 4 °C/W °C/W FSDM0565RB Electrical Characteristics (Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit BVDSS VGS = 0V, ID = 250μA 650 - - V VDS = 650V, VGS = 0V - - 500 μA IDSS VDS= 520V VGS = 0V, TC = 125°C - - 500 μA RDS(ON) VGS = 10V, ID = 2.5A - 1.76 2.2 Ω Output capacitance COSS VGS = 0V, VDS = 25V, f = 1MHz - 78 - pF Turn on delay time TD(ON) - 22 - - 52 - - 95 - - 50 - VFB = 3V 60 66 72 kHz 13V ≤ Vcc ≤ 18V 0 1 3 % -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 % Sense FET SECTION Drain source breakdown voltage Zero gate voltage drain current Static drain source on resistance (1) Rise time Turn off delay time Fall time TR TD(OFF) VDD= 325V, ID= 5A (MOSFET switching time is essentially independent of operating temperature) TF ns CONTROL SECTION Initial frequency FOSC Voltage stability FSTABLE Temperature stability (2) ΔFOSC Maximum duty cycle DMAX - 77 82 87 % Minimum duty cycle DMIN - - - 0 % Start threshold voltage VSTART VFB=GND 11 12 13 V Stop threshold voltage VSTOP VFB=GND 7 8 9 V Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA Soft-start time TS Vfb=3 - 10 15 ms - 250 - ns Leading Edge Blanking time TLEB - BURST MODE SECTION VBURH Vcc=14V - 0.7 - V VBURL Vcc=14V - 0.5 - V Peak current limit (4) IOVER VFB=5V, VCC=14V 2.0 2.25 2.5 A Over voltage protection VOVP 18 19 20 V 130 145 160 °C VFB ≥ 5.5V 5.5 6.0 6.5 V VFB=5V 2.8 3.5 4.2 μA Burst Mode Voltages (2) PROTECTION SECTION Thermal shutdown temperature (2) TSD Shutdown feedback voltage VSD Shutdown delay current IDELAY - 5 FSDM0565RB TOTAL DEVICE SECTION Operating supply current (5) IOP VFB=GND, VCC=14V IOP(MIN) VFB=GND, VCC=10V IOP(MAX) VFB=GND, VCC=18V Notes: 1. Pulse test : Pulse width ≤ 300μS, duty ≤ 2% 2. These parameters, although guaranteed at the design, are not tested in mass production. 3. These parameters, although guaranteed, are tested in EDS(wafer test) process. 4. These parameters indicate the inductor current. 5. This parameter is the current flowing into the control IC. 6 - 2.5 5 mA FSDM0565RB Comparison Between FS6M07652RTC and FSDM0565RB Function FS6M07652RTC Soft-Start Adjustable soft-start time using an external capacitor Burst Mode Operation FSDM0565RB FSDM0565RB Advantages Internal soft-start with • Gradually increasing current limit typically 10ms (fixed) during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot • Built into controller • Built into controller • Improve light load efficiency • Output voltage fixed • Reduces no-load consumption • Output voltage drops to around half 7 FSDM0565RB Typical Performance Characteristics 1.2 1.2 1.0 1.0 Start Thershold Voltage (Vstart) Operating Current (Iop) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 -25 Ju nc tion Te mpe ratu re (℃) 1.2 1.2 1.0 1.0 Operating Frequency (Fosc) Stop Threshold Voltage (Vstop) 50 75 100 125 150 Start Threshold Voltage vs. Temp 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 150 0 25 50 75 100 125 150 Ju nc tion Te mpe ratu re (℃) Ju nc tion Te mpe ratu re (℃) Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp 1.2 1.2 1.0 1.0 FB Source Current (Ifb) Maximum Duty Cycle (Dmax) 25 Ju nc tion Te mpe ratu re (℃) Operating Current vs. Temp 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Ju nc tion Te mpe ratu re (℃) Maximum Duty vs. Temp 8 0 150 0.0 -25 0 25 50 75 100 125 Ju nction Te mperatu re(℃) Feedback Source Current vs. Temp 150 FSDM0565RB Typical Performance Characteristics (Continued) 1.2 1.2 1.0 1.0 Shutdown Delay Current (Idelay) Shutdown FB Voltage (Vsd) (These Characteristic Graphs are Normalized at Ta= 25°C) 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 -25 Ju n c tion Te mpe ratu re (℃) 50 75 100 125 150 ShutDown Delay Current vs. Temp 1.2 1.2 FB Burst Mode Enable Voltage (Vfbe) Over Voltage Protection (Vovp) 25 Ju n c tion T e mpe ra tu re (℃) ShutDown Feedback Voltage vs. Temp 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 1.0 0.8 0.6 0.4 0.2 0.0 -25 100 125 150 0 25 50 75 100 125 150 Junction Temperature(℃) Junction Temperature(℃) Over Voltage Protection vs. Temp Burst Mode Enable Voltage vs. Temp 1.2 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 150 Junction Temperature(℃) Burst Mode Disable Voltage vs. Temp Peak Current Limit(Self protection) (Iover) FB Burst Mode Disable Voltage (Vfbd) 0 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 125 Ju n c tion Te mpe ratu re (℃) Current Limit vs. Temp 9 FSDM0565RB Typical Performance Characteristics (Continued) (These Characteristic Graphs are Normalized at Ta= 25°C) 1.2 Soft Start Time (Normalized to 25℃) 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 Junction Temperature (℃) Soft Start Time vs. Temp 10 100 125 FSDM0565RB Functional Description 1. Startup : In previous generations of Fairchild Power Switches (FPSTM) the Vcc pin had an external start-up resistor to the DC input voltage line. In this generation the startup resistor is replaced by an internal high voltage current source. At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor (Cvcc) that is connected to the Vcc pin as illustrated in Figure 4. When Vcc reaches 12V, the FSDM0565RB begins switching and the internal high voltage current source is disabled. Then, the FSDM0565RB continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless Vcc goes below the stop voltage of 8V. VDC CVcc Vcc 3 6 2.1 Pulse-by-pulse current limit: Because current mode control is employed, the peak current through the Sense FET is limited by the inverting input of PWM comparator (Vfb*) as shown in Figure 5. Assuming that the 0.9mA current source flows only through the internal resistor (2.5R +R= 2.8 kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (Vfb) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, thus clamping Vfb*. Therefore, the peak value of the current through the Sense FET is limited. 2.2 Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current mode PWM control. To counter this effect, the FSDM0565RB employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (TLEB) after the Sense FET is turned on. Vstr Vcc Istart Vref 8V/12V Vref Idelay Vcc good Vfb Vo 4 H11A817A Figure 4. Internal startup circuit SenseFET OSC D1 CB Internal Bias IFB D2 2.5R + Vfb* KA431 Gate driver R - VSD OLP Rsense Figure 5. Pulse width modulation (PWM) circuit 2. Feedback Control : FSDM0565RB employs current mode control, as shown in Figure 5. An opto-coupler (such as the H11A817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the H11A817A LED current increases, thus pulling down the feedback voltage and reducing the duty cycle. This event typically happens when the input voltage is increased or the output load is decreased. 3. Protection Circuit : The FSDM0565RB has several self protective functions such as over load protection (OLP), over voltage protection (OVP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the FSDM0565RB resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated (see Figure 6). 11 FSDM0565RB Vds Power on Fault occurs V FB Fault removed Over load protection 6.0V 2.5V Vcc T12= Cfb*(6.0-2.5)/Idelay T1 12V T2 t Figure 7. Over load protection 8V t Normal operation Fault situation Normal operation Figure 6. Auto restart operation 3.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the Sense FET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked and the 3.5uA current source starts to charge CB slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is terminated as shown in Figure 7. The delay time for shutdown is the time required to charge CB from 2.5V to 6.0V with 3.5uA. In general, a 10 ~ 50 ms delay time is typical for most applications. 12 3.2 Over voltage Protection (OVP) : If the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, Vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the SMPS until the over load protection is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FSDM0565RB uses Vcc instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. In order to avoid undesired activation of OVP during normal operation, Vcc should be designed to be below 19V. 3.3 Thermal Shutdown (TSD) : The Sense FET and the control IC are built in one package. This makes it easy for the control IC to detect the heat generation from the Sense FET. When the temperature exceeds approximately 150°C, the thermal shutdown is activated. 4. Soft Start : The FSDM0565RB has an internal soft start circuit that increases PWM comparator inverting input voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 10msec, The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. It also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. FSDM0565RB 5. Burst operation : In order to minimize power dissipation in standby mode, the FSDM0565RB enters burst mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 8, the device automatically enters burst mode when the feedback voltage drops below VBURL(500mV). At this point switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH(700mV) switching resumes. The feedback voltage then falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in Standby mode. Vo Voset VFB 0.7V 0.5V Ids Vds time Switching disabled T1 T2 T3 Switching disabled T4 Figure 8. Waveforms of burst operation 13 FSDM0565RB Typical application circuit Application Output power LCD Monitor 40W Input voltage Output voltage (Max current) Universal input 5V (2.0A) (85-265Vac) 12V (2.5A) Features • • • • • • High efficiency (>81% at 85Vac input) Low zero load power consumption (<300mW at 240Vac input) Low standby mode power consumption (<800mW at 240Vac input and 0.3W load) Low component count Enhanced system reliability through various protection functions Internal soft-start (10ms) Key Design Notes • Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these resistors since the startup pin is internally disconnected after startup. • The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is required, C106 can be reduced to 10nF. • Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener diode also increases the immunity against line surge. 1. Schematic D202 T1 EER3016 MBRF10100 1 R102 30kΩ C103 100uF 400V R105 40kΩ BD101 2 2KBP06M3N257 1 2 D101 UF 4007 8 3 Vstr Drain 1 5 D201 MBRF1045 NC 4 C102 220nF 275VAC 4 ZD102 10V C106 47nF 50V 12V, 2.5A C202 1000uF 25V C201 1000uF 25V IC1 FSDM0565RB 6 3 C104 2.2nF 1kV R103 56kΩ 2W L201 10 Vcc 3 Vfb GND 2 ZD101 22V C105 D102 22uF TVR10G 50V R104 5Ω 4 L202 5V, 2A 7 C204 1000uF 10V C203 1000uF 10V 6 5 C301 4.7nF LF101 23mH R201 1kΩ R101 560kΩ 1W RT1 5D-9 14 C101 220nF 275VAC R202 1.2kΩ F1 FUSE 250V 2A IC301 H11A817A IC201 KA431 R204 5.6kΩ R203 12kΩ C205 47nF R205 5.6kΩ FSDM0565RB 2. Transformer Schematic Diagram EER3016 Np/2 1 10 N 12V 2 9 3 8 4 7 Na 5 6 Np/2 N5V 3.Winding Specification No Na Pin (s→f) 4→5 Wire 0.2φ ×1 Turns Winding Method 8 Center Winding 18 Solenoid Winding 7 Center Winding 3 Center Winding 18 Solenoid Winding Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 2→1 0.4φ × 1 Insulation: Polyester Tape t = 0.050mm, 2Layers N12V 10 → 8 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers N5V 7→6 0.3φ × 3 Insulation: Polyester Tape t = 0.050mm, 2Layers Np/2 3→2 0.4φ × 1 Outer Insulation: Polyester Tape t = 0.050mm, 2Layers 4.Electrical Characteristics Pin Specification Remarks Inductance 1-3 520uH ± 10% 100kHz, 1V Leakage Inductance 1-3 10uH Max 2nd all short 5. Core & Bobbin Core : EER 3016 Bobbin : EER3016 Ae(mm2) : 96 15 FSDM0565RB 6.Demo Circuit Part List Part Value Note Fuse F101 Part Value Note C301 4.7nF Polyester Film Cap. 2A/250V NTC RT101 Inductor 5D-9 Resistor R101 L201 5uH Wire 1.2mm L202 5uH Wire 1.2mm 560K 1W R102 30K 1/4W R103 56K 2W R104 5 1/4W R105 40K 1/4W D101 UF4007 R201 1K 1/4W D102 TVR10G R202 1.2K 1/4W D201 MBRF1045 R203 12K 1/4W D202 MBRF10100 R204 5.6K 1/4W ZD101 Zener Diode 22V R205 5.6K 1/4W ZD102 Zener Diode 10V Diode Bridge Diode BD101 2KBP06M 3N257 Bridge Diode Capacitor 16 C101 220nF/275VAC Box Capacitor Line Filter C102 220nF/275VAC Box Capacitor C103 100uF/400V Electrolytic Capacitor C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0565RB FPSTM(5A,650V) C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler C201 1000uF/25V Electrolytic Capacitor C202 1000uF/25V Electrolytic Capacitor C203 1000uF/10V Electrolytic Capacitor C204 1000uF/10V Electrolytic Capacitor C205 47nF/50V Ceramic Capacitor LF101 23mH Wire 0.4mm IC FSDM0565RB 7. Layout Figure 9. Layout Considerations for FSDM0565RB Figure 10. Layout Considerations for FSDM0565RB 17 FSDM0565RB Package Dimensions TO-220F-6L(Forming) 18 FSDM0565RB Package Dimensions (Continued) I2-PAK-6L(Forming) 19 FSDM0565RB Ordering Information Product Number Package Marking Code BVdss Rds(on)Max. FSDM0565RBWDTU TO-220F-6L(Forming) DM0565R 650V 2.2 Ω FSDM0565RBIWDTU I2-PAK-6L (Forming) DM0565R 650V 2.2 Ω WDTU : Forming Type DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/9/06 0.0m 001 © 2006 Fairchild Semiconductor Corporation