[AK4420] AK4420 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output GENERAL DESCRIPTION The AK4420 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output. Using AKM’s multi bit modulator architecture, the AK4420 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4420 integrates a combination of switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio applications, such as DVD, AV receiver system and set-top boxes. The AK4420 is offered in a space saving 16pin TSSOP package. FEATURES Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24-Bit 8 times FIR Digital Filter Switched-Capacitor Filter with High Tolerance to Clock Jitter Single Ended 2Vrms Output Buffer Digital de-emphasis Soft mute I/F format: 24-Bit MSB justified or I2S Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode) 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) THD+N: -92dB Dynamic Range: 105dB Automatic Power-on Reset Circuit Power supply: +4.5 ∼ +5.5V Ta = -20 to 85°C Small Package: 16pin TSSOP (6.4mm x 5.0mm) MCLK SMUTE DIF VDD Clock Divider Control Interface DZF VSS1 LRCK BICK SDTI Audio Data Interface 8X Interpolator ΔΣ Modulator SCF LPF AOUTL 8X Interpolator ΔΣ Modulator SCF LPF AOUTR Charge Pump CP CN 1μ MS0683-E-02 VEE VSS2 CVDD 1μ 2007/12 -1- [AK4420] ■ Ordering Guide -20 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4420 AK4420ET AKD4420 ■ Pin Layout CN 1 16 VEE CP 2 15 VSS2 SMUTE 3 14 CVDD MCLK 4 13 DZF BICK 5 12 VSS1 SDTI 6 11 VDD LRCK 7 10 AOUTL DIF 8 9 AOUTR AK4420 Top View MS0683-E-02 2007/12 -2- [AK4420] PIN/FUNCTION No. Pin Name I/O 1 CN I 2 CP I 3 SMUTE I 4 MCLK I 5 6 7 BICK SDTI LRCK I I I 8 DIF I 9 AOUTR O 10 AOUTL O 11 VDD - 12 VSS1 - 13 14 15 DZF CVDD VSS2 O - Function Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Soft Mute Enable Pin (Internal pull down: 100kΩ) “H”: Enable, “L”: Disable Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin Audio Serial Data Input Pin L/R Clock Pin Audio Data Interface Format Pin “L”: Left Justified, “H”: I2S Rch Analog Output Pin When power down, outputs VSS(0V, typ). Lch Analog Output Pin When power down, outputs VSS(0V, typ). DAC Power Supply Pin: 4.5V∼5.5V Ground Pin1 Zero Input Detect Pin Charge Pump Power Supply Pin: 4.5V∼5.5V Ground Pin2 Negative Voltage Output Pin Connect to VSS2 with a 1.0μF capacitor that should have the low ESR 16 (Equivalent Series Resistance) over all temperature range. When this VEE O capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used. Note: All input pins except for the CN pin should not be left floating. MS0683-E-02 2007/12 -3- [AK4420] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD CVDD IIN VIND Ta Tstg Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 1. All voltages with respect to ground. Note 2. VSS1, VSS2 connect to the same analog grand. min -0.3 -0.3 -0.3 -20 -65 max +6.0 +6.0 ±10 VDD+0.3 85 150 Units V V mA V °C °C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD CVDD min +4.5 typ +5.0 VDD max +5.5 Units V Note 3. CVDD should be equal to VDD *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0683-E-02 2007/12 -4- [AK4420] ANALOG CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Resolution 24 Dynamic Characteristics (Note 4) THD+N (0dBFS) fs=44.1kHz, BW=20kHz -92 -84 fs=96kHz, BW=40kHz -92 fs=192kHz, BW=40kHz -92 Dynamic Range (-60dBFS with A-weighted. (Note 5) 98 105 S/N (A-weighted. (Note 6) 98 105 Interchannel Isolation (1kHz) 90 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy DC Offset (at output pin) -60 0 +60 Gain Drift 100 Output Voltage (Note 7) 1.97 2.12 2.27 Load Capacitance (Note 8) 25 Load Resistance 5 Power Supplies Power Supply Current: (Note 9) 24 36 Normal Operation (fs≤96kHz) 27 40 Normal Operation (fs=192kHz) 10 100 Power-Down Mode (Note 10) Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual. Note 5. 98dB for 16bit input data Note 6. S/N does not depend on input data size. Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD, AOUT (typ.@0dB) = 2.12Vrms × VDD/5. Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load. Note 9. The current into VDD and CVDD. Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD MS0683-E-02 Units Bits dB dB dB dB dB dB dB mV ppm/°C Vrms pF kΩ mA mA μA 2007/12 -5- [AK4420] FILTER CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz) Parameter Symbol min Typ max Digital filter PB 0 20.0 Passband ±0.05dB (Note 11) 22.05 –6.0dB Stopband (Note 11) SB 24.1 Passband Ripple PR ± 0.02 Stopband Attenuation SA 54 Group Delay (Note 12) GD 19.3 Digital Filter + LPF Frequency Response 20.0kHz fs=44.1kHz FR ± 0.05 40.0kHz fs=96kHz FR ± 0.05 80.0kHz fs=192kHz FR ± 0.05 Note 11. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. Units kHz kHz kHz dB dB 1/fs dB dB dB DC CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Voltage (Iout = -80uA) Low-Level Input Voltage (Iout = 80uA) Input Leakage Current Symbol VIH VIL VIH VIL Iin min 2.2 VDD-0.4 - typ - max 0.8 0.4 ± 10 Units V V V V μA Note 13. The SMUTE pin is not included. The SMUTE pin has internal pull-up resistor (typ.100kΩ) . MS0683-E-02 2007/12 -6- [AK4420] SWITCHING CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V) Parameter Symbol min Typ fCLK 4.096 11.2896 Master Clock Frequency dCLK 30 Duty Cycle LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 32 Quad Speed Mode fsq 120 Duty Cycle Duty 45 Audio Interface Timing BICK Period tBCK 1/128fsn Normal Speed Mode tBCK 1/64fsd Double Speed Mode tBCK 1/64fsq Quad Speed Mode tBCKL 30 BICK Pulse Width Low tBCKH 30 Pulse Width High tBLR 20 BICK “↑” to LRCK Edge (Note 14) tLRB 20 LRCK Edge to BICK “↑” (Note 14) tSDH 20 SDTI Hold Time tSDS 20 SDTI Setup Time Note 14. BICK rising edge must not occur at the same time as LRCK edge. MS0683-E-02 max 36.864 70 Units MHz % 48 96 192 55 kHz kHz kHz % ns ns ns ns ns ns ns ns ns 2007/12 -7- [AK4420] ■ Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Serial Interface Timing MS0683-E-02 2007/12 -8- [AK4420] OPERATION OVERVIEW ■ System Clock The external clocks required to operate the AK4420 are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master clock is set to the appropriate frequency (Table 1). The AK4420 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode, and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4420 is powered up. After power-up, the AK4420 is in the power-down mode until MCLK and LRCK are input. LRCK fs 32.0kHz 44.1kHz 48.0kHz 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs - 192fs - 22.5792 24.5760 33.8688 36.8640 256fs 8.192 11.2896 12.288 22.5792 24.5760 - MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 12.288 16.9344 18.432 33.8688 36.8640 - 768fs 24.5760 33.8688 36.8640 1152fs 36.8640 - - - Sampling Speed Normal Double Quad Table 1. system clock example When MCLK= 256fs/384fs, the AK4420 supports sampling rate of 32kHz~96kHz (Table 2). But, when the sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. MCLK 256fs/384fs 512fs/768fs DR,S/N 102dB 105dB Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) ■ Audio Serial Interface Format The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial data modes as shown in Table 3. In all modes the serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin. Mode 0 1 DIF L H SDTI Format 24bit MSB justified 24bit I2S BICK ≥48fs ≥48fs Figure Figure 3 Figure 4 Table 3. Audio Data Formats MS0683-E-02 2007/12 -9- [AK4420] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 0 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 1 Timing ■ Zero detect function When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The DZF pin immediately is set to “L” if the input data for both channels are not zero after going to DZF “H”. MS0683-E-02 2007/12 - 10 - [AK4420] ■ Analog output block The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms amplifier. It allows the AK4420 to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative power generation circuit (Figure 5) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by clocks generated from MCLK. When MCLK stops, the AK4420 is placed in the reset mode automatically and the analog outputs settle to VSS (0V, typ). AK4420 CVDD Charge Pump CP CN Negative Power VSS2 (+) 1uF Ca Cb (+) VEE 1uF Figure 5. Negative power generation circuit AK4420 2.12Vrms 0V AOUTR (AOUTL) Figure 6. Audio signal output MS0683-E-02 2007/12 - 11 - [AK4420] ■ Soft Mute Operation Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to -∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE pin 1024/fs 0dB 1024/fs (1) (3) Attenuation -∞ GD (2) GD AOUT DZF pin (4) 8192/fs Notes: (1) The time for input data be attenuation to -∞, is Normal Speed Mode: 1024 LRCK cycles (1020/fs). Double Speed Mode: 2048 LRCK cycles (2048/fs). Quad Speed Mode : 4096 LRCK cycles (4096/fs). (2) The analog output corresponding to a specific digital input has a group delay, GD. (3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level in the same cycle. (4) When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The DZF pin immediately is set to “L” if the input data are not zero after going to DZF “H”. Figure 7. Soft Mute and Zero detect function MS0683-E-02 2007/12 - 12 - [AK4420] ■ System Reset The AK4420 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up. The AK4420 is in power-down mode until LRCK are input. Power Supply (VDD, CVDD) (6) MCLK Low 20 us Analog Circuit Digital Circuit Charge Pump Circuit (1) Power down Power down (2) Power-up 2, 3 LRCK Power down Power-up Power-up (3) Charge Pump Time A Counter circuit D/A In (Digital) “0” data D/A Out (Analog) DZF MUTE (D/A Out) (4) (5) Notes: (1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up. (2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK. (3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal after Time A. Time A = 1024/ (fs x 16): Normal speed mode Time A = 1024/ (fs x 8) : Double speed mode Time A = 1024/ (fs x 4) : Quadruple speed mode (4) No audible click noise occurs under normal conditions. (5) The DZF pin is “L” in the power-down mode. (6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure. Figure 8. System reset diagram MS0683-E-02 2007/12 - 13 - [AK4420] ■ Reset Function When the MCLK or LRCK stops, the AK4420 is placed in reset mode and its analog outputs are set to VSS (0V, typ). When the MCLK and LRCK are restarted, the AK4420 returns to normal operation mode. The BICK can be stopped when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied. Internal Normal Operation Reset Normal Operation State D/A In (Digital) (1) GD D/A Out (Analog) (3) VSS (2) (3) <Case1:MCLK Stop> Clock In (4) MCLK Stop MCLK, BICK, LRCK (6) DZF <Case2:LRCK Stop> Clock In (4) (5) LRCK Stop MCLK, BICK, LRCK (6) DZF Notes: (1) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting the “0” data during this period. (2) The analog output corresponding to a specific digital input has group delay (GD). (3) No audible click noise occurs under normal conditions. (4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped). (5) The AK4420 detects the stop of LRCK if LRCK stops for more than 2048/fs. When LRCK is stopped, the AK4420 exits reset mode after LRCK is inputted.. (6) The DZF pin is set to “L” in the reset mode. Figure 9. Reset Timing Example MS0683-E-02 2007/12 - 14 - [AK4420] SYSTEM DESIGN Figure 10 shows the system connection diagram. An evaluation board (AKD4420) is available for fast evaluation as well as suggestions for peripheral circuitry. CN VEE 16 2 CP VSS2 15 3 SMUTE Master Clock 4 MCLK 64fs 5 BICK 24bit Audio Data 6 SDTI fs 7 LRCK AOUTL 10 8 DIF AOUTR 1u (1) ModeSetting Digital Ground + CVDD 14 DZF 13 AK4420 VSS1 12 VDD 11 9 Analog 5.0V 1u (1) + 1 0.1u + 10u 10Ω External Mute Circuits 0.1u + 10u Lch Out Rch Out Analog Ground Note: Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin should be connected to the CP and VSS2 pin. VSS1 and VSS2 should be separated from digital system ground. Digital input pins should not be allowed to float. Figure 10. Typical Connection Diagram MS0683-E-02 2007/12 - 15 - [AK4420] 1. Grounding and Power Supply Decoupling VDD, CVDD and VSS are supplied from the analog supply and should be separated from the system digital supply. Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD and CVDD as possible. The differential voltage between VDD and VSS pins set the analog output range. The power-up sequence between VDD and CVDD is not critical. 2. Analog Outputs The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically 2.12Vrms (typ @VDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 11) can reduce noise beyond the audio passband. Figure 12 shows example in the case of 10kΩ, 100kΩ terminus. The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±60mV or less. AK4420 470 Analog Out AOUT 2.2nF 2.12Vrms (typ) (fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz) Figure 11. External 1st order LPF Circuit Example1 AK4420 47μ 820 220 AOUT 47k 1000pF Analog Out 10kÆ1.92Vrms (typ) 100kÆ2.1Vrms (typ) Figure 12. External 1st order LPF Circuit Example2 MS0683-E-02 2007/12 - 16 - [AK4420] PACKAGE 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.65 0.17±0.05 Detail A Seating Plane 0.5±0.2 0.1±0.1 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0683-E-02 2007/12 - 17 - [AK4420] MARKING AKM 4420ET XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4420ET Asahi Kasei Logo REVISION HISTORY Date (YY/MM/DD) 07/11/05 Revision 00 07/12/04 01 Reason First Edition Error Correction Page Contents 13 Figure 8. The description of the click noise was corrected. Figure 9. The description of the click noise was corrected. “The BICK can be stopped when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied.” was deleted. 14 07/12/17 02 Error Correction 14 MS0683-E-02 2007/12 - 18 - [AK4420] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0683-E-02 2007/12 - 19 -