PD - 97772
IRFB4510PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
100V
10.7mΩ
13.5mΩ
62A
D
G
D
S
TO-220AB
IRFB4510PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
Parameter
Max.
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Units
62
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
44
IDM
Pulsed Drain Current
250
PD @TC = 25°C
Maximum Power Dissipation
140
W
Linear Derating Factor
0.95
VGS
Gate-to-Source Voltage
± 20
W/°C
V
dv/dt
TJ
Peak Diode Recovery
3.2
Operating Junction and
TSTG
Storage Temperature Range
c
e
A
V/ns
°C
-55 to + 175
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
x
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
d
f
x
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
130
mJ
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Symbol
Parameter
i
Typ.
Max.
RθJC
Junction-to-Case
–––
1.05
RθCS
Case-to-Sink, Flat Greased Surface
0.50
–––
RθJA
Junction-to-Ambient, TO-220
–––
62
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i
Units
°C/W
1
4/10/12
IRFB4510PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
100
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.11
10.7
–––
–––
–––
–––
–––
0.6
Conditions
–––
V VGS = 0V, ID = 250μA
––– V/°C Reference to 25°C, ID = 5mA
13.5 mΩ VGS = 10V, ID = 37A
4.0
V VDS = VGS, ID = 100μA
20
μA VDS = 100V, VGS = 0V
250
VDS = 80V, VGS = 0V, TJ = 125°C
100
nA VGS = 20V
-100
VGS = -20V
–––
Ω
f
c
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
g
Diode Characteristics
Symbol
IS
Parameter
VSD
trr
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
c
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.192mH
RG = 25Ω, IAS = 37A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 37A, di/dt ≤ 1550A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
h
100
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
58
14
18
40
13
32
28
28
3180
220
120
260
325
–––
87
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
Conditions
VDS = 25V, ID = 37A
ID = 37A
VDS =50V
VGS = 10V
ID = 37A, VDS =0V, VGS = 10V
VDD = 65V
ID = 37A
RG =2.7Ω
VGS = 10V
VGS = 0V
VDS = 50V
ƒ = 1.0MHz, See Fig.5
VGS = 0V, VDS = 0V to 80V , See Fig.1
VGS = 0V, VDS = 0V to 80V
f
ns
pF
f
f
h
g
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
showing the
G
––– ––– 250
A integral reverse
S
p-n junction diode.
––– ––– 1.3
V TJ = 25°C, IS = 37A, VGS = 0V
–––
54
81
ns TJ = 25°C
VR = 85V,
–––
60
90
TJ = 125°C
IF = 37A
di/dt = 100A/μs
–––
95
140
nC TJ = 25°C
––– 130 195
TJ = 125°C
––– 3.3
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
–––
–––
62
A
f
f
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .
Rθ is measured at TJ approximately 90°C.
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IRFB4510PbF
1000
1000
100
BOTTOM
10
1
4.0V
≤ 60μs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
100
BOTTOM
4.0V
10
≤ 60μs PULSE WIDTH
Tj = 175°C
1
100
0.1
VDS , Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
≤ 60μs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
ID = 37A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
0.0
7.0
-60 -40 -20 0
VGS, Gate-to-Source Voltage (V)
100000
Fig 4. Normalized On-Resistance vs. Temperature
14
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
10000
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
6.0V
5.0V
4.8V
4.5V
4.3V
4.0V
Ciss
1000
Coss
Crss
100
ID= 37A
VDS = 80V
VDS = 50V
12
10
VDS = 20V
8
6
4
2
0
10
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
20
40
60
80
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB4510PbF
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
TJ = 175°C
10
TJ = 25°C
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100
1msec
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1
1.6
ID, Drain Current (A)
60
50
40
30
20
10
0
75
100
125
150
175
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
70
50
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
10
VDS, Drain-toSource Voltage (V)
VSD, Source-to-Drain Voltage (V)
125
Id = 5mA
120
115
110
105
100
95
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
600
EAS , Single Pulse Avalanche Energy (mJ)
1.2
1.0
0.8
Energy (μJ)
DC
0.1
0.1
0.6
0.4
0.2
0.0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100μsec
100
ID
4.7A
12A
BOTTOM 37A
500
TOP
400
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFB4510PbF
Thermal Response ( ZthJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
140
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 37A
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
4.5
24
4.0
20
3.5
16
IRRM - (A)
VGS(th), Gate threshold Voltage (V)
IRFB4510PbF
3.0
2.5
2.0
1.5
8
ID = 100μA
ID = 250μA
ID = 1.0mA
ID = 1.0A
IF = 24A
VR = 80V
4
TJ = 125°C
TJ = 25°C
0
1.0
-75 -50 -25 0
100 200 300 400 500 600 700 800 900 1000
25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
dif / dt - (A / μs)
Fig 16. Threshold Voltage vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
24
600
20
500
16
400
QRR - (nC)
IRRM - (A)
12
12
8
4
0
300
200
IF = 37A
VR = 80V
IF = 24A
VR = 80V
100
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
600
500
QRR - (nC)
400
300
200
100
0
IF = 37A
VR = 80V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4510PbF
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
tp
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
tp
A
I AS
0.01Ω
Fig 22a. Unclamped Inductive Test Circuit
Fig 22b. Unclamped Inductive Waveforms
LD
VDS
VDS
90%
+
VDD D.U.T
10%
VGS
VGS
Second Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
20K
1K
VCC
Vgs(th)
S
Qgodr
Fig 24a. Gate Charge Test Circuit
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Qgd
Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
IRFB4510PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in assembly line position
indicates "Lead - Free"
INTERNATIONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DATE CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/pkhexfet.html
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/12
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