Cypress CY7C1339B-133BGC 128k x 32 synchronous pipelined cache ram Datasheet

CY7C1339B
128K x 32 Synchronous Pipelined Cache RAM
Features
The CY7C1339B I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V.
• Supports 100-MHz bus for Pentium and PowerPC
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 128K × 32 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339B supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
— 4.0 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119-ball
BGA packages
• “ZZ” Sleep Mode and Stop Clock options
Byte Write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all Byte Write inputs and writes data to all four bytes. All Writes
are conducted with on-chip synchronous self-timed Write
circuitry.
Functional Description
The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[16:0]
GW
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.
Q
17
15
ADDRESS
CE REGISTER
D
D
BWE
BW 3
15
17
128K × 32
MEMORY
ARRAY
DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
BW2
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
D
Q
DQ[7:0]
BYTEWRITE
REGISTERS
BW1
BW0
CE1
CE2
CE3
32
32
D
ENABLE Q
CE REGISTER
CLK
D
Q
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
Cypress Semiconductor Corporation
Document #: 38-05141 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 27, 2002
CY7C1339B
Selection Guide
7C1339B-166
7C1339B-133
7C1339B-100
Unit
Maximum Access Time
3.5
4.0
5.5
ns
Maximum Operating Current
420
375
325
mA
Maximum CMOS Standby Current
10
10
10
mA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE1
CE2
BW3
BW2
BW1
BW0
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configurations
BYTE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1339B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
BYTE1
BYTE0
MODE
A5
A4
A3
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
DNU
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE3
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
Document #: 38-05141 Rev. *A
Page 2 of 17
CY7C1339B
Pin Configurations (continued)
119-ball BGA
CY7C1339B (128K × 32)
1
2
3
4
5
6
7
VDDQ
A
NC
NC
CE2
A
A
ADSP
A
A
ADSC
VDD
A
A
VDDQ
A
A
NC
A
NC
NC
D
E
DQc
DQc
NC
DQc
VSS
VSS
NC
CE1
VSS
VSS
NC
DQb
DQb
DQb
F
G
H
J
VDDQ
DQc
DQc
VDDQ
DQc
DQc
DQc
VDD
VSS
BWc
VSS
NC
OE
ADV
GW
VDD
VSS
BWb
VSS
NC
DQb
DQb
DQb
VDD
VDDQ
DQb
DQb
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
N
VDDQ
DQd
DQd
DQd
VSS
VSS
BWE
A1
VSS
VSS
DQa
DQa
VDDQ
DQa
P
DQd
NC
VSS
A0
VSS
NC
DQa
R
T
NC
NC
A
NC
MODE
A
VDD
A
VDD
A
A
NC
NC
ZZ
U
VDDQ
DNU
DNU
DNU
DNU
NC
VDDQ
A
B
C
Document #: 38-05141 Rev. *A
Page 3 of 17
CY7C1339B
Pin Definitions
Pin Name
I/O
Pin Description
A[16:0]
InputSynchronous
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
two-bit counter.
BW[3:0]
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW[3:0] and BWE).
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputOutput Enable, Asynchronous Input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected
state.
ADV
InputSynchronous
Advance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deserted HIGH.
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ has an internal pull down.
DQ[31:0]
I/OSynchronous
VDD
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
VSS
Ground
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[16:0] during the previous clock rise of the Read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] are placed
in a three-state condition.
Ground for the core of the device. Should be connected to ground of the system.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
VSSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
MODE
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an
internal pull up.
NC
–
No Connects.
DNU
-
Do Not Use pins. These pins could be left floating or tied to GND.
Document #: 38-05141 Rev. *A
Page 4 of 17
CY7C1339B
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 3.5 ns
(166-MHz device).
The CY7C1339B supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs
(A[16:0]) is stored into the address advancement logic and the
Address Register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.5 ns (166-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented to A[16:0] is loaded into the address register and the
address advancement logic while being delivered to the RAM
core. The Write signals (GW, BWE, and BW[3:0]) and ADV
inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
Document #: 38-05141 Rev. *A
data presented to the DQ[31:0] inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BW[3:0]
signals. The CY7C1339B provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW[3:0]) input will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because the CY7C1339B is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW[3:0]) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ[31:0] is written into the
corresponding address location in the RAM core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1339B is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three-stated whenever a Write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1339B provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Page 5 of 17
CY7C1339B
Sleep Mode
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
3
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Cycle Descriptions[1, 2, 3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
L
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
L
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
L
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “Sleep”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document #: 38-05141 Rev. *A
Page 6 of 17
CY7C1339B
Write Cycle Descriptions[4, 5, 6]
Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 – DQ[7:0]
1
0
1
1
1
0
Write Byte 1 – DQ[15:8]
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 – DQ[23:16]
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 – DQ[31:24]
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Notes:
4. X = “don't care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
Document #: 38-05141 Rev. *A
Page 7 of 17
CY7C1339B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High Z State[7] ....................................... −0.5V to VDD + 0.5V
Commercial
DC Input Voltage[7] .................................... −0.5V to VDD + 0.5V
Industrial
Ambient
Temperature[8]
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V
−5%/+10%
2.5V −5%
3.3V /+10%
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range
Parameter
Description
Min.
Max.
Unit
3.3V −5%/+10%
3.135
3.6
V
I/O Supply Voltage
2.5V −5% to 3.3V +10%
2.375
3.6
V
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
VDDQ = 3.3V
VIL
Input LOW Voltage[7]
IX
Input Load Current
except ZZ and MODE
VDD
Power Supply Voltage
VDDQ
VOH
Test Conditions
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
0.7
V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
−5
5
µA
GND ≤ VI ≤ VDDQ
−30
5
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CS
Max. VDD, Device Deselected,
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
Max. VDD, Device Deselected, or
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
µA
µA
30
µA
5
µA
6-ns cycle, 166 MHz
420
mA
7.5-ns cycle, 133 MHz
375
mA
10-ns cycle, 100 MHz
325
mA
Input = VDDQ
Output Leakage
Current
µA
−5
Input = VSS
IOZ
Automatic CS
Power-Down
Current—TTL Inputs
V
VDD + 0.3V
Input = VDDQ
ISB1
V
0.4
2.0
Input Current of MODE Input = VSS
Input Current of ZZ
V
−5
6-ns cycle, 166 MHz
150
mA
7.5-ns cycle, 133 MHz
125
mA
10-ns cycle, 100 MHz
115
mA
All speeds
10
mA
6-ns cycle, 166 MHz
125
mA
7.5-ns cycle, 133 MHz
95
mA
10-ns cycle, 100 MHz
85
mA
18
mA
Notes:
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
Document #: 38-05141 Rev. *A
Page 8 of 17
CY7C1339B
Capacitance[9]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP Max.
BGA Max.
Unit
4
6
pF
4
6
pF
4
8
pF
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 3.3V
AC Test Loads and Waveforms
3.3/2.5V
OUTPUT
R= 317/1667Ω
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
(a)
INCLUDING
JIG AND
SCOPE
[10]
90%
10%
90%
GND
R= 351/1538Ω
≤ 1V/ns
5 pF
VL = 1.5V for 3.3 VDDQ
1.25V for 2.5V VDDQ
ALL INPUT PULSES
3.0/2.5V
≤ 1V/ ns
(c)
(b)
Thermal Resistance[9]
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Symbol
TQFP Typ.
BGA
Units
Still Air, soldered on a 4 × 4.5 inch,
2-layer printed circuit board
QJA
41.83
47.63
°C/W
QJC
9.99
11.71
°C/W
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Input waveform should have a slew rate of 1 V/ns.
Document #: 38-05141 Rev. *A
Page 9 of 17
CY7C1339B
Switching Characteristics Over the Operating Range[10, 12, 13]
-166
Parameter
Description
Min.
-133
Max.
Min.
-100
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
1.9
3.5
ns
tCL
Clock LOW
1.7
1.9
3.5
ns
tAS
Address Set-Up Before CLK Rise
1.5
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.5
2.0
2.0
ns
tADS
ADSP, ADSC Set-up Before CLK Rise
2.0
2.5
2.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
ns
tWES
BWE, GW, BW[3:0] Set-up Before CLK Rise
2.0
2.5
2.5
ns
tWEH
BWE, GW, BW[3:0] Hold After CLK Rise
0.5
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.0
2.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
ns
tDS
Data Input Set-up Before CLK Rise
1.5
1.5
1.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tCES
Chip Select Set-up
2.0
2.5
2.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
ns
[12]
tCHZ
Clock to High-Z
tCLZ
Clock to Low-Z[12]
[12, 13]
OE HIGH to Output High-Z
tEOLZ
OE LOW to Output Low-Z[12, 13]
OE LOW to Output Valid
4.0
3.5
0
tEOHZ
tEOV
3.5
[12]
3.5
0
3.5
0
3.5
0
3.5
0
3.5
5.5
ns
ns
5.5
0
4.0
ns
ns
ns
5.5
ns
Notes:
11. Unless otherwise noted, test conditions assume signal transition time of 3.0/2.5 ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to
3.0/2.5V for 3.3/2.5V VDDQ respectively, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (c) of AC test loads diagram.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mv from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
Document #: 38-05141 Rev. *A
Page 10 of 17
CY7C1339B
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated Write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[3:0], and GW to define a Write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
Document #: 38-05141 Rev. *A
Page 11 of 17
CY7C1339B
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated Read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tDOE
tCEH
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
= DON’T CARE
tCHZ
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05141 Rev. *A
Page 12 of 17
CY7C1339B
Switching Waveforms (continued)
Read/Write Cycle Timing[14, 15, 16, 17]
Single Read
tCYC
Single Write
Unselected
Burst Read
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
tADVS
tADH
ADV
tAS
ADD
tADVH
RD1
WD2
RD3
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tDOE
OE
tOEHZ
Data In/Out
tOELZ
tCO
1a
1a
Out
2a
In
See Note 17
2a
Out
= DON’T CARE
tDS
tDH
3a
Out
= UNDEFINED
tDOH
3b
Out
3c
Out
3d
Out
tCHZ
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Document #: 38-05141 Rev. *A
Page 13 of 17
CY7C1339B
Switching Waveforms (continued)
ZZ Mode Timing [18, 19]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Notes:
18. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
19. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05141 Rev. *A
Page 14 of 17
CY7C1339B
Ordering Information
Speed
(MHz)
Ordering Code
166
CY7C1339B-166AC
133
CY7C1339B-133AC
CY7C1339B-166BGC
CY7C1339B-133BGC
CY7C1339B-133AI
100
Package
Name
A101
BG119
A101
BG119
A101
CY7C1339B-133BGI
BG119
CY7C1339B-100AC
A101
CY7C1339B-100BGC
CY7C1339B-100AI
CY7C1339B-100BGI
BG119
A101
BG119
Package Type
100-lead Thin Quad Flat Pack
Operating
Range
Commercial
119-ball BGA
100-lead Thin Quad Flat Pack
Commercial
119-ball BGA
100-lead Thin Quad Flat Pack
Industrial
119-ball BGA
100-lead Thin Quad Flat Pack
Commercial
119-ball BGA
100-lead Thin Quad Flat Pack
Industrial
119-ball BGA
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05141 Rev. *A
Page 15 of 17
CY7C1339B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*A
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a registered trademark of
IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05141 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1339B
Document Title: CY7C1339B 128K x 32 Synchronous Pipelined Cache RAM
Document Number: 38-05141
REV.
ECN NO.
Issue
Date
**
109885
09/15/01
SZV
Change from Spec number: 38-00936 to 38-05141
*A
113899
03/29/02
SKX
Changed the JTAG pins on the BGA package to DNU pins.
Added BGA capacitance.
Added thermal resistance table for both TQFP and BGA.
Document #: 38-05141 Rev. *A
Orig. of
Change
Description of Change
Page 17 of 17