ETC HA118144AF Video camera cds/agc ic Datasheet

HA118144AF
Video Camera CDS/AGC IC
Description
Features
The HA118144AF is a bipolar IC that wa s
developed to perform the analog signal processing
between the CCD and the ADC in a CCD camera,
and is optimal for use in CCD camera digital signal
processing systems.
•
Excellent suppression of CCD output lower
frequency noise by using clamp-type correlated
double sampling.
•
A high S/N ration by using dual (pre- and
post-) AGC amplifi e rs and high sensitiv i t y
based on increased coverage.
Functions
•
Provides compensation for IC variations and
imaging device sensitivity variations with an 8
state gain select circuit.
•
Allows the AGC, gain select, and knee control
to be controlled from the system microprocessor over a serial interface.
•
•
•
•
•
•
Correlated double sampling
AGC
Sample and hold
Gain select
Knee processing
Serial interface control
1
HA118144AF
HA118144AF
48
47
46
45
44
43
42
41
40
39
38
37
NC
SCK
SDATA
NC
INJECT
NC
SP1
SP2
GND1
NC
VDC
NC
Pin Arrangement
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
NC
VCC9
SPRE
NC
GND3
NC
OSC
VCC3
BLK
OBP
GND2
NC
13
14
15
16
17
18
19
20
21
22
23
24
NC
KNP
CND4
NC
CP
NC
VCLM
CLM
SO2
SO1
GND9
NC
HA118144AF
(top view)
2
NC
SIN
NC
VFB1
VCC1
VCC2
VAGC
SOA1
SIA2
VFB2
NC
S/N
HA118144AF
HA118144AF
Pin Functions
Pin
No.
Pin
Name
1
NC
2
KNP
Knee pulse
3
GND4
GND for IIL
interface
4
NC
5
CP
6
NC
7
Signal
Standard DC Signal Signal
Voltage Type Level
Pulse
5VPP
Impedance Function Description
30 k
0V
Knee pulse input (unused).
Fix at the low level.
GND = 0 V
Clamp pulse
CP
pulse
Base
Clamp pulse input (unused).
Fix at the low level.
VCLM
Clamp input
DC
Base
Clamp input (unused).
Fix at the low level.
8
CLM
Clamp output
DC
Emitter
Clamp output (unused).
Leave open.
9
SO2
Signal output 2
5.4 V
Video
signal
1.5VPP
Emitter
Signal output 2
10
SO1
Signal output 1
3.3 V
Video
signal
1.5VPP
Emitter
Signal output 1
11
GND9
GND for 9 V
0V
GND = 0 V
12
NC
13
NC
14
VCC9
VCC for 9 V
9V
Power supply +9 V
15
SPRE
Signal preview
1.3 V
16
NC
17
GND3
GND for IIL
0V
18
NC
19
OSC
Oscillator
correction
1.7 V
20
VCC3
VCC for IIL
interface
5V
21
BLK
Blanking pulse
BLK
signal
5VPP
Base
Blanking pulse input. The
output is clipped at the BLK
level when a low level is input.
22
OBP
Optical black
pulse
OBP
signal
5VPP
40 k
Optical black pulse input.
The feedback clamp operates
when a high level is input.
Video
signal
5VPP
385 mVPP Emitter
Signal preview.
For use as an output monitor.
GND = 0 V
DC
5k
Oscillator correction pin for the
AGC DAC bias circuit.
Connect to GND through a
0.1 µF capacitor.
Power supply +5 V
3
HA118144AF
HA118144AF
Pin Functions (cont)
Pin Pin
No. Name
23
GND2
24
NC
25
S/N
26
NC
27
Signal
Standard DC Signal Signal
Voltage Type Level
Impedance Function Description
GND for AGC,
0V
knee, BLK, DAC
3.1 V
DC
Base
AGC 1 bias circuit noise
correction pin. Connect to
GND through a 0.1 µF
capacitor.
VFB2
AGC2 feed back 2.4 V
out
DC
Collector
AGC2 feedback output.
Connect to SIA2.
28
SIA2
AGC2 input
2.4 V
Video
signal
370 mVPP
Base
AGC2 input. Connect to SOA1
through a 0.1 µF capacitor.
29
SOA1
AGC1 output
2V
Video
signal
370 mVPP
Emitter
AGC1 output. Connect to
SIA2 through a 0.1 µF
capacitor.
30
VAGC
AGC1 control
out
2.5 V to DC
3.3 V
Diode
AGC control voltage output.
Connect to GND through a
0.1 µF capacitor.
31
VCC2
VCC for AGC,
5V
knee, BLK, DAC
Power supply +5 V
32
VCC1
VCC for gain
select, CDS
5V
Power supply +5 V
33
VFB1
AGC1 feed
back out
2.3 V
DC
34
NC
35
SIN
Signal input
2.3 V
Video
36
NC
37
NC
38
VDC
Bias for FBC
3.5 V
DC
39
NC
40
GND1
GND for gain
select, CDS
0V
4
S/N correction
GND = 0 V
Base
AGC1 feedback output.
Connect to GND through a
0.1 µF capacitor.
115 mVPP to Base
380 mVPP
Signal input from the CCD
sensor
10 k
Gain select bias voltage
output. Connect to GND
through a 0.1 µF capacitor.
GND = 0 V
HA118144AF
HA118144AF
Pin Functions (cont)
Pin Pin
No. Name
Signal
Standard DC Signal Signal
Voltage Type Level
Impedance Function Description
41
SP2
Sample & hold
pulse 2
S&H
pulse
5 VPP
10 k
Signal period sample and hold
pulse. Duty = 25%, phase
difference = 180° (with respect
to SP1).
42
SP1
Sample & hold
pulse 1
S&H
5 VPP
10 k
Field through period clamp
pulse. Duty = 25%, phase
difference = 180° (with respect
to SP2).
43
NC
44
INJECT IIL injector
DC
2.46 mA
45
NC
46
SDATA
Serial data
input
Pulse
5 VPP
30 k
Serial data input pin
47
SCK
Serial data
clock
Pulse
5 VPP
30 k
Serial clock pin. Period of
2 µs to 20 µs.
48
NC
0.7 V
Bias current pin for internal
logic circuits. Leave open.
5
6
42
30
33
1
SP2
4
6
NC
NC
38
41
Typical level:
115 V PP
35
to 380 VPP
SP1
NC
13
NC
12
NC
3.5 VDC
VDC
SP2
SIN
SP1
VAGC
2.3 VDC
VFB1
32
VCC1
OBP
AGC1
48
NC
3
17
23
SP1
45
NC
43
47
SDATA SCK
46
KNP
2
Data converter
8 state
GAIN select
NC
16
27
OBP
2.4 VDC
VFB2
370 mV PP
NC
18
NC
24
5 bit D/A
AGC
bias
NC
26
Knee
AGC2
0.5 dB to 11.3 dB
28
SIA2
7 bit D/A
SOA1
29
NC 2VDC
1.5 dB step
–0.2 dB to 10.1 dB
GND4 GND3 GND2
0 dB to
10.50 dB
31
VCC2
20
VCC3
VCC5V
11
SP2
44
OBP
22
21
37
NC
OSC supplement
pad
39
NC
40
GND1
11.7 dB
385 mVPP
NC
34
VCLM
CP
CLM
SO2
SO1
1.3 VDC
SPRE
S/N correction pad
BLK
OBP
Knee ref
BLK
GND9
linj
7
5
8
9
10
14
15
36
25
19
CP
3.3 VDC
5.4 VDC
VCC9V
Pre view
NC
HA118144AF
HA118144AF
Block Diagram
NC 43
Iinj 44
NC 45
SP2 GND1 NC
39
7.5 kΩ
SP1
40
38
1 kΩ
37
NC
20.9 kΩ
8
NC
36
28 kΩ
9
SIN
35
9V
32
31
40 kΩ
0.4 mA
30
29
200 Ω
2.5 kΩ
10 kΩ
12 kΩ
200 Ω
9V
14
28
1 kΩ
15
27
40 kΩ
40 kΩ
10 kΩ
15.5 kΩ
16
NC
26
5 kΩ
1 kΩ
2 kΩ
12 kΩ
S/N
25
3 kΩ
1.5 kΩ
1.5 kΩ
1 kΩ
17 kΩ
18
3 kΩ
1 kΩ
1 kΩ
17
VCC9V SPRE NC GND3 NC
VFB1 VCC1 VCC2 VAGC SOA1 SIA2 VFB2
33
1 kΩ
5.6 kΩ
500 Ω
3 kΩ
750 Ω
1 kΩ
4.05 kΩ
18.8 kΩ
10 kΩ
1.6 mA
1.1 mA
13
12
10
11
NC
SO1 GND9 NC
1 kΩ
NC
34
1 kΩ
500 Ω
9V
3 kΩ
200 Ω
500 Ω
1 kΩ
0.2 mA 1 mA
7
VCLM CLM SO2
1 kΩ
0.1 mA
6
NC
14.8 kΩ
VDC
1 kΩ
1.5 kΩ
5
0.1 mA
2 kΩ
41
7.5 kΩ
10 kΩ
3 kΩ
4
42
10 kΩ
1.5 kΩ
3 kΩ
17.5 kΩ
10 kΩ
SDATA 46
20 kΩ
10 kΩ
20 kΩ
3
CP
200 Ω
SCK 47
NC 48
2
KNP GND4 NC
20 kΩ
10 kΩ
1
NC
24 NC
23 GND2
22 OBP
21 BLK
20 VCC3
OSC
19 correction
HA118144AF
HA118144AF
I/O Pin Equivalent Circuits
7
HA118144AF
HA118144AF
Absolute Maximum Ratings
Item
Symbol
Rated Value
Unit
Maximum power supply voltage 1
VCC5
Max
6.0
V
Maximum power supply voltage 2
VCC9
Max
10.0
V
Operating temperature
Topr
–10 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Operating power supply voltage 1
VOP5
4.75 to 5.25
V
Operating power supply voltage 2
VOP9
8.5 to 9.5
V
Power dissipation
PT
440
mW
Notes: 1. These values are for the FQFP package mounted under the following conditions.
Substrate material: Glass epoxy
Wiring density:
40 mm × 1.5 mm
30%
2. This IC is for use in consumer products. It should not be used in industrial products, or in
products that will be used outdoors for extended periods.
8
HA118144AF
HA118144AF
Electrical Characteristics (Ta = 25°C, VCC = 5 V, 9 V)
Test Conditions
Applicable
Pins
Item
Symbol Min
Typ
Max
Unit
Current
ICC 5 V
dissipation
ICC 9 V
ICC5
25
36
47
mA
20, 31, 32
ICC9
3.25
4.2
5.55
mA
14
FBC
voltage
fluctuations
VFB1 voltage
fluctuation
∆VFB1
–100
0
100
mV
FBC on,
VVFB max – VVFB min
33
SIA2 voltage
fluctuation
∆SIA2
–120
0
120
mV
FBC on,
VSIA2 – VSIA2 min
28
Pin inflow
currents
SIN pin current
ISIN
–0.5
0
0.5
µA
42 pin 0 VDC
35
VFB1 pin current 1
IVFB1
–0.5
0
0.5
µA
22 pin 0 VDC
33
VFB1 pin current 2
IVFB2
60
100
140
µA
22, 41, 42 pin 5 VDC
33 pin 2.5 VDC
VFB1 pin current 3
IVFB3
–140
–100
–60
µA
22, 41, 42 pin 5VDC
33 pin 2.5 VDC
SIA2 pin current
ISIA2
–0.5
0
0.5
µA
22 pin 0 VDC
28
VFB2 pin current 1
IVFB21
–0.5
0
0.5
µA
22 pin 0 VDC
27
VFB2 pin current 2
IVFB22
37
50
77
µA
22, 41 pin, 5 VDC
27 pin 3 VDC
VFB2 pin current 3
IVFB23
–75
–50
–35
µA
22, 41 pin, 5 VDC
27 pin 2 VDC
CP pin current
ICP
–3.5
–1
0
µA
7 pin 2 VDC,
5 pin 2 VDC
5
VCLM pin current
IVCLM
–3.5
–1
0
µA
7 pin 2 VDC,
5 pin, 1 VDC
7
CLM pin current 1
ICLM1
–0.5
0
0.5
µA
7 pin 0 V,
5 pin 1 VDC,
8 pin 5 VDC
8
CLM pin current 2
ICLM2
–0.5
0
0.5
µA
7 pin 0 V,
5 pin 1 VDC,
8 pin 0 VDC
CLM pin current 3
ICLM3
150
191
271
µA
7 pin 5 V,
5 pin 1 VDC,
8 pin 5 VDC
CLM pin current 4
ICLM4
–5
–3
–1
µA
7 pin 5 V,
5 pin 2 VDC,
8 pin 0.7 VDC
OBP pin current
IOBP
164
205
285
µA
22 pin 5 VDC
22
BLK pin current
IBLK
–14
–5
–2
µA
21 pin 0 VDC
21
9
HA118144AF
HA118144AF
Electrical Characteristics (Ta = 25°C, VCC = 5 V, 9 V) (cont)
Symbol Min
Typ
Max
Unit
Test Conditions
Applicable
Pins
SDATA pin current
ISDATA
8.2
10.2
12.2
µA
46 pin 0.3 VDC
46
SCK pin current
ISCK
7.9
10.4
12.1
µA
47 pin 0.3 VDC
47
KNP pin current
IKNP
8.3
10.3
12.3
µA
2 pin 0.3 VDC
2
SIN pin voltage
VSIN
2.5
2.8
3.1
V
VFB1 pin voltage
VVFB1
2.5
2.8
3.1
V
SOA1 pin voltage
VSOA1
1.78
2.0
2.22
V
41, 42 pin 5 V,
35
22 pin 5 V, 2 pin 0 VDC
33
gain min
29
SIA2 pin voltage
VSIA2
2.2
2.4
2.6
V
41 pin 5 V, 22 pin 5 V,
28
21 pin 5 V, 2 pin 0 VDC
gain min
SPRE pin voltage
VSPRE
1.2
1.4
1.6
V
15
SO1 pin voltage
VSO1
4.95
5.25
5.65
V
SO2 pin voltage
VSO2
2.9
3.15
3.45
V
41 pin 5 V,
22 pin 5 VDC,
21 pin 5 V, 2 pin 0 V,
gain min
CLM pin voltage
VCLM
1.8
1.9
2.05
V
7 pin 1.9 VDC,
5 pin 5 VDC
8
Serial input VTH
SVTH
2.8
—
—
V
Adjusts the pin 46
and 47 serial data
amplitudes.
46, 47
Gain select 1
GSA1
–0.8
–0.2
1.2
dB
33, 29
Gain select 2
GSA2
0.3
1.3
2.3
dB
22, 41, 42 pin 5 VDC
AGC 1 min
Gain select 3
GSA3
1.7
2.7
3.7
dB
Gain select 4
GSA4
3.1
4.1
5.1
dB
Gain select 5
GSA5
4.6
5.6
6.6
dB
Gain select 6
GSA6
6.2
7.2
8.2
dB
Gain select 7
GSA7
7.7
8.7
9.7
dB
Gain select 8
GSA8
9.1
10.1
11.1
dB
AGC1 G (0)
GA01
–1.2
–0.2
0.8
dB
AGC1 G (60)
GA60
–0.6
0.2
1.0
dB
AGC1 G (70)
GA70
0.4
1.2
2.0
dB
AGC1 G (80)
GA80
2.1
2.9
3.7
dB
AGC1 G (90)
GA90
3.7
4.5
5.3
dB
AGC1 G (100)
GA100
5.4
6.2
7.0
dB
AGC1 G (110)
GA110
7.1
7.9
8.7
dB
AGC1 G (120)
GA120
8.8
9.6
10.4
dB
AGC1 G (127)
GA127
9.7
10.5
11.3
dB
Item
Pin inflow
currents
Pin
voltages
AC items
10
22, 41, 42 pin 5 VDC
gain select min
10
9
HA118144AF
HA118144AF
Electrical Characteristics (Ta = 25°C, VCC = 5 V, 9 V) (cont)
Item
AC items
Symbol
Min
Typ
Max
Units Test Conditions
AGC2 G (0)
GA02
–0.5
0.5
1.5
dB
AGC2 G (10)
GA10
0.7
1.5
2.3
dB
AGC2 G (20)
GA20
2.3
3.1
3.9
dB
AGC2 G (30)
GA30
4.0
4.8
5.6
dB
AGC2 G (40)
GA40
5.9
6.7
7.5
dB
AGC2 G (50)
GA50
7.6
8.4
9.2
dB
AGC2 G (60)
GA60
9.2
10.0
10.8
dB
AGC2 G (70)
GA70
9.9
10.7
11.5
dB
SO1 gain
GS01
10.7
12.2
13.7
dB
SO2 gain
GS02
10.7
12.2
13.7
dB
Gain ref pulse
VGRP
170
210
250
mV
BLK level
VBLK
0.5
0.6
0.7
V
Knee compression
ratio
∆Gknee
2.6
3.8
5.0
dB
41, 42 pin 5 VDC
Gknee max–Gknee min
Knee off
Knee off
0.8
0.9
1.0
V
Knee start point
Kne start 0.15
0.25
0.35
V
41, 42 pin 5 VDC
knee min
Applicable
Pins
Pins 21, 22, 41, 42:
5 VDC, Pins 27, 28:
Short knee max.
28, 15
Pins 21, 22, 41, 42:
5 VDC, Pins 27, 28:
Short knee max.
28, 10
28, 9
2, 29
Pins 41, 42: 5 VDC
Pins 27, 28: Short knee 21, 9
max.
28, 15
11
HA118144AF
HA118144AF
Test Circuits
DC item test circuit
SDATA
SCK
KNP
2
3
5
7
42
41
40
38
47
46
44
0.1 µF
33
32
31
30
29
28
HA118144AF
0.1 µF
17
19
20
21
22
23
25
14
11
10 µF 0.1 µF
+
–
VCC 9 V
AC item test circuit
0.1 µF
VCC 5 V
0.1 µF
SDATA
SCK
KNP
CP pulse
42
41
40
38
47
46
0.1 µF
2
3
5
HA118144AF
8
1000 pF
0.1 µF
0.1 µF
75 Ω
17
19
20
21
22
23
25
14
11
33
32
31
30
29
28
27
0.1 µF
0.1 µF 10 µF
VCC 9 V 0.1 µF
BLK pulse
12
OBP pulse
+
–
VCC 5 V
Pin 46
SDATA input
LO 0 V
HI 5 V
LO 0 V
HI 5 V
SDATA input
MSB
Knee level
SCK input
LSB
Gain
calibration
MSB
SDATA8
SDATA7
SDATA6.5
SDATA6
SDATA5.5
SDATA5
SDATA4
SDATA3
SDATA2
SDATA1
SCK1
2 µs
t
AGC127
AGC120
AGC110
AGC100
AGC90
AGC80
AGC70
AGC60
AGC50
AGC40
AGC30
LSB
AGC gain setting
MSB
t
Pulse selection
t
When observing the KNP pulse response,
input pulses after DATE transmission.
SDATA18
AGC20
SDATA17
AGC0
AGC10
HA118144AF
HA118144AF
Test Patterns
13
HA118144AF
HA118144AF
Main Characteristics
AGC1 gain I/O characteristics (VFB1 → SOA1)
(SOA1) (V)
3.750
60
80
100
120
127
AGC No.
.2500
/div
Quiescent
output
potential,
OBP high
1.250
1.000
3.500
VIN (VFB1 ) .2500/div (V)
Gain select min, AGC No. 60, 80, 100, 120, 127
SP1, SP2: high, OBP: low
AGC2 gain I/O characteristics (SIA2 → SPRE)
(SPRE) (V)
2.500
AGC No.
60
40
20
0
.2500
/div
.0000
1.000
Quiescent
output
potential,
OBP high
VIN (SIA2) .2500/div (V)
Knee SDATA min, AGC No. 0, 20, 40, 60
14
3.500
HA118144AF
HA118144AF
Gain select I/O characteristics (V FB1 → SOA1)
(SOA1) (V)
3.750
1
.2500
/div
2
3 4 5 67 8
Gain select
No. 1
Gain select
No. 8
Quiescent
output
potential,
OBP high
1.250
1.000
1.5
2.0
2.5
2.75
3.0
3.500
VIN (VFB1 ).2500/div (V)
AGC gain min, gain select No. 1, 2, 3, 4, 5, 6, 7, 8
SP1, SP2: high, OBP: low
slope B
slope A
= 0.66
Slope A: 1.084
Knee I/O characteristics
Compression ratio =
(V)
3.000
SPRE output
Slope B: 0.715
Knee max
Knee
point
max
.2500
/div
Knee min
0.94 VPP
Knee
point
min
0.25 VPP
1.3 V
(black level)
.5000
1.500
.2500/div (V)
4.000
SIA2 input
15
HA118144AF
HA118144AF
Gain select characteristics
10
Gain (dB)
8
6
4
2
0
0
1
2
3
4
5
6
7
Gain select number
Gain for SIN (37) → SOA1 (32) (AGC number 0)
AGC1 + AGC2 combined gain control characteristics
Maximum gain control level: 21.3 dB
20
Gain control due to
AGC1 (pre-stage)
Gain control level (dB)
15
10
Gain control due to
AGC2 (post-stage)
5
0 10 20 30 40 50 60 70 80 90 100110 120 127
Gain select number
16
HA118144AF
HA118144AF
Built-In Functions and Timing Charts
Function Overview
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•
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CDS (correlated double sampling) circuit
Gain select
AGC gain setting
Knee level setting
Serial data control functions
Gain
select
(sensor) SIN
AGC
Knee
CDS
SO1, SO2
Serial interface
SP1 SP2
SCK
SDATA
Figure 1 CDS/AGC IC Function Overview
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HA118144AF
HA118144AF
— Clamp circuit (CLAMP)
Operation
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This circuit removes low frequency noise by
clamping the input signal 1 noise segment
(A period) to a fixed voltage using the SP1
sample/hold pulse, and supplies its output
signal to the sample and hold circuit. (See
figures 2 and 3 4 .)
CDS (correlated double sampling) circuit
A CCD image sensor alternately outputs a
noise segment (the A period signal) and a
signal segment (the B period signal) that
includes noise. Since the main noise generated
by the image sensor is low frequency noise,
and that noise is added to the signal, this noise
is a factor in S/N ratio degradation.
The CDS circuit removes the low frequency
noise by first clamping the image sensor output
signal noise segment (the A period signal) to a
fixed voltage, and then replacing the noise
segment with the signal segment by sampling
and holding the signal segment (B period),
which includes noise. Thus the CDS circuit
generates a continuous signal, and consists of a
clamping circuit, and sample and hold circuit,
and inverting amplifier. (See figures 2 and 3.)
SP1
— Sample and hold circuit (S/H)
This is a circuit that samples and holds the
signal segment, and uses the SP2 sample/hold
pulse to sample the signal segment (B period)
and replace the noise segment with the signal
segment to generate a continuous signal. (See
figures 2 and 3 5 .)
— Following the inverting amplifier, the signal is
supplied to the gain select circuit.
SP2
2
1
Input
3
4
CLAMP
5
S/H
Figure 2 CDS Circuit
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AMP
Output
HA118144AF
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HA118144AF
Gain select
stage), which together realize a variable
amplification of up to 21 dB.
The gain select circuit can be set to one of
eight gain levels from –0.2 dB to 10.1 dB in
1.5 dB increments according to 3 bits of
control data. The gain select circuit setting is
used to adjust the input level to the AGC
circuit in the next stage.
•
AGC gain
The application should implement an autoaliasing function by processing the camera
DSPIC iris result in the microprocessor, and
using that to control the AGC gain in this IC
using serial data transfers.
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The AGC gain is set by 7 bits of control data.
The setting range is from 0 dB to 21 dB.
Internally, the circuit is divided into two stages,
AGC1 (pre-stage) and AGC2 (post-
A
Knee level
The amplifier I/O characteristics are shown in
figure 4. The inflection point where the gain
changes is determined by 5 bits of data.
B
Low FREQ noise
1
2
3
4
5
6
Figure 3 CDS Timing Chart
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HA118144AF
HA118144AF
Output
Output
Knee off
(typ 0.9 V)
Gain G2
Inflection point
Gain G1
Knee start
(typ 0.25 V)
G2
G1
=
(1.5 VPP )
2
3
Input
Figure 4 Knee Level Characteristics
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Input
HA118144AF
HA118144AF
Serial Data Control
Timing chart
— Internally, the IC takes the case where SDATA
is high on the falling edge of SCK as the data
latch timing.
— Serial transfers are performed by the SCK
and SDATA pins in the CDS/AGC IC.
— Data is acquired on the falling edge of SCK for
D1 to D10 prior to the latch timing.
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Table 3-1 Serial Control Overview
SDATA
Function
D1
D2
D3
D4
Knee level gain selection setting
0
0
Knee level setting
d1
AGC gain setting
0
1
d2
1
D6
D7
D8
D9
0
D10
Gain select
d3
d4
d5
d1
d2
AGC gain
d1
Pulse selection
D5
d3
—
d2
d3
d4
d5
d6
d7
Correc- —
tion/
knee
2 µs to 20 µs
SCK
SDATA
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
IC internal data latch timing
Figure 5 Serial Data Timing Chart
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HA118144AF
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HA118144AF
Bit weightings in serial settings data
• Gain select
D10 D9 D8
d3 d2 d1
1 1 1 10.1 dB
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0 –0.2 dB
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• Knee level
D7 D6 D5
d5 d4 d3
1 1 1
0 1 1
1 0 1
1
0
1
0
1
1
0
0
0
0
0
0
D4
d2
1
1
1
D3
d1
1 Knee start
1
1
0
0
0
0
0
0
0
0
Pulse selection
Since this function is not guaranteed, it should
not be used.
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Knee off
• AGC gain
D9 D8 D7
d7 d6 d5
1 1 1
0 1 1
1 0 1
1
0
1
0
1
1
0
0
0
0
0
0
D6
d4
1
1
1
D5
d3
1
1
1
D4
d2
1
1
1
D3
d1
1 21 dB
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 dB
The KNP pin (pin 2) should be held low. This bit
can be set to either 0 or 1.
HA118144AF
HA118144AF
Other Items
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Standard waveforms for SIN, SP1, and SP2
— SIN inputs a video signal from a CCD.
— The SP1 signal performs the field through
period clamping, and the SP2 signal
performs the signal period sample and hold.
SO1 and SO2 outputs
The figure below shows the equivalent circuit
for these outputs. As shown in the figure, the
output waveform response speed is increased
by using a capacitor coupled push-pull
structure.
SIN
0.5 V/div
50 ns/div
SOA1
(x)
SP2
0.5 V/div
50 ns/div
SP1
Figure 6 CDS → AGC1 Operating Waveforms
10
9
SO1
SO2
Figure 7 Internal Equivalent Circuit for SO1 and SO2
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