SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE (TOP VIEW) Fully Buffered to Offer Maximum Isolation From External Disturbance Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPE ′ALS112A TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) 50 6 1CLK 1K 1J 1PRE 1Q 1Q 2Q GND description 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1CLR 2CLR 2CLK 2K 2J 2PRE 2Q SN54ALS112A . . . FK PACKAGE (TOP VIEW) 1K 1CLK NC VCC These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. 3 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2CLR 2CLK NC 2K 2J 2Q GND NC 2Q 2PRE 1J 1PRE NC 1Q 1Q 1CLR • NC – No internal connection The SN54ALS112A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L L X X X L H† H H† H H ↓ L L Q0 Q0 H H ↓ H L H L H H ↓ L H L H H ↓ H H H Toggle H H H X X Q0 Q0 † The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 logic symbol† 1PRE 1J 1CLK 1K 1CLR 2PRE 2J 2CLK 2K 2CLR 4 3 S 5 1J 1 2 15 1Q C1 6 1K 1Q R 10 9 11 2Q 13 12 7 2Q 14 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. logic diagram (positive logic) Q Q PRE CLR J K CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS112A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 recommended operating conditions SN54ALS112A SN74ALS112A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current – 0.4 – 0.4 mA IOL fclock Low-level output current 4 8 mA 30 MHz tw High-level input voltage 2 Clock frequency 2 0 Pulse duration tsu Set p time before CLK↓ Setup th TA Hold time after CLK↓ 25 15 10 CLK high 20 16.5 CLK low 20 16.5 Data 25 22 PRE or CLR inactive 22 20 Data Operating free-air temperature 0 V 0 PRE or CLR low 125 V ns ns 0 – 55 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = – 0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA VCC = 5 5.5 5V V, VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5 5.5 5V V, VI = 0 0.4 4V II IIH IIL J, K, or CLK PRE or CLR J, K, or CLK PRE or CLR J, K, or CLK PRE or CLR SN54ALS112A MIN TYP† MAX SN74ALS112A MIN TYP† MAX –1.5 VCC – 2 –1.5 VCC – 2 0.25 0.4 UNIT V V 0.25 0.4 0.35 0.5 0.1 0.1 0.2 0.2 20 20 40 40 – 0.2 – 0.2 – 0.4 – 0.4 V mA µA mA IO‡ VCC = 5.5 V, VO = 2.25 V – 20 –112 – 30 –112 mA ICC VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54ALS112A SN74ALS112A MIN fmax tPLH tPHL tPLH MAX MIN 25 PRE or CLR Q or Q 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 30 MHz 3 26 3 15 4 23 4 18 3 15 5 19 3 23 CLK Q or Q tPHL 5 24 † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. UNIT ns ns SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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