Ordering number : ENA1585 Bi-CMOS IC LV5212VH LED Driver Control IC Overview The LV5212VH is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output 8-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5212VH also contains an n-channel CMOS construction high-withstand-voltage, large-current drive 8-stage parallel output driver. Features • Serial input and serial or parallel output • Enable input for output control • Serial output enables cascade connection • Low supply current (0.0μA typ. during standby) • Serial input/output levels compatible with typical CMOS devices • High-withstand-voltage LED driver with open drain output High withstand voltage (VDS < 50V) High-current drive (IO max = 300mA) • Operating temperature range Ta = -25 to 75°C Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage VCC max SVCC Output voltage VO max LEDO1 to LEDO8 off Output current IO max Allowable power dissipation Pd max Operating temperature Topr -25 to +75 °C Storage temperature Tstg -40 to +125 °C Ta ≤ 25°C * 6 V 50 V 300 mA 1000 mW * Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board. * The device must be used within the ranges warranted for its specifications so as to ensure its specified ratings (such as maximum ratings and operating condition ranges) are not exceeded even momentarily. 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N1109 SY PC 20091002-S00003 No.A1585-1/9 LV5212VH Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended supply voltage VCC SVCC 5.0 Operating supply voltage range VCC op SVCC 3.0 to 5.5 V Output applied voltage VO 50 V Output current IO 300 mA Duty = 45% to 55% V Electrical Characteristics at Ta = 25°C, VCC = 5.0V Parameter Symbol Ratings Conditions min Unit typ max Quiescent current drain ICC1 LEDO driver off (standby) 0 LEDO output on resistance Ron IO = 100mA 3 OFF leak current Ileak VO = 50V 0 H level 1 VINH1 Input H level VCC × 0.8 L level 1 VINL1 Input L level 0 H level 2 VOUTH1 SOUT IO = -1mA L level 2 VOUTL1 SOUT IO = 1mA 5 μA 10 μA Ω Control circuit block V VCC × 0.2 VCC -0.3 V V 0 0.3 V Package Dimensions unit : mm (typ) 3325 Pd max -- Ta 9.75 0.5 7.6 9 5.6 16 1 0.8 8 2.0 0.3 0.15 (1.3) 1.5MAX (0.48) Allowable power dissipation, Pd max -- W 1.5 Specified board : 114.3 × 76.1 × 1.6mm3 glass epoxy 1.0 0.50 0.5 0 --25 0 25 50 75 100 2.7 0.1 Ambient temperature, Ta -- °C SANYO : HSSOP16(275mil) No.A1585-2/9 LV5212VH Pin Assignment PGND2 LEDO7 LEDO8 SCK SGND PGND1 LEDO2 LEDO1 SDATAIN XRESET 9 LEDO6 10 LEDO3 11 LEDO5 12 LEDO4 PGND2 LATCH 13 SOUT 14 XEN 15 SVCC 16 1 2 3 4 PGND1 5 6 7 8 Top view Pin Descriptions Pin No. Pin name I/O Description 1 SVCC Power supply 2 SOUT O shift register output (final-stage shift register) 3 LEDO4 O LEDO4 Latch output (LEDO4 of shift register) 4 LEDO3 O LEDO3 Latch output (LEDO3 of shift register) 5 LEDO2 O LEDO2 Latch output (LEDO2 of shift register) 6 LEDO1 O LEDO1 Latch output (LEDO1 of shift register) 7 SDATAIN I Serial input 8 XRESET I Reset input (shift register and latch) 9 SGND GND 10 SCK I Clock input (for shift register) 11 LEDO8 O LEDO8 Latch output (LEDO8 of shift register) 12 LEDO7 O LEDO7 Latch output (LEDO7 of shift register) 13 LEDO6 O LEDO6 Latch output (LEDO6 of shift register) 14 LEDO5 O LEDO5 Latch output (LEDO5 of shift register) 15 LATCH I Latch input When the latch input is held low, the LED0 output status is retained. When a high-level is input, the LED0 outputs change when the status of the shift register changes. 16 XEN I Enable inputs (LEDO1 to LEDO8) When a high-level is input, all the LED0 outputs are turned off. When a low-level is input, the shift register data is output to LED0. PGND1 PGND1 GND PGND1 PGND2 GND No.A1585-3/9 LV5212VH Block Diagram SCK SDATAIN LATCH XEN SVCC XRESET LEDO1 D Q C Q R D Q C Q R LEDO2 D Q C Q R D Q C Q R LEDO3 D Q C Q R D Q C Q R D Q C Q R D Q C Q R D Q C Q R D Q C Q R LEDO4 LEDO5 LEDO6 D Q C Q R D Q C Q R LEDO7 D Q C Q R D Q C Q R LEDO8 D Q C Q R D Q C Q R D Q C Q R SOUT SGND PGND1PGND2 Function The LV5212VH consists of 1) an 8-stage D-type flip-flop and 2) an 8-stage D-type flip-flop connected to the output of 1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input (SCK), the serial data input signal is input to the internal shift register and the data already in the shift register shifted sequentially when the clock changes from low to high. The serial output (SOUT) is used to connect multiple LV5212VH to expand the number of bits and is connected to the SDATAIN of the next stage. (Cascade connection supported.) For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to high and the clock pulse input changes from low to high, the serial data input signal is output to LED01, and the output is shifted sequentially. For parallel outputs (LED2 to LED8), the signals whose polarities inverted from those of the serial data input (SDATAIN) are output. When the EN input is high, outputs LED01 through LED01 all turn off. When the reset input is low, outputs LED01 through LED8 and SOUT outputs all turn off. The power must be turned on after checking that the reset input is low. No.A1585-4/9 LV5212VH Pin Functions Pin No. Pin Name 7 SDATAIN 10 SCK Pin function Equivalent Circuit Pull-down input SVCC SGND 8 XRESET 15 LATCH 16 XEN Pull-up input SVCC SGND 2 SOUT SOUT output SVCC SOUT SGND 3 LEDO4 4 LEDO3 5 LEDO2 6 LEDO1 11 LEDO8 12 LEDO7 13 LEDO6 14 LEDO5 LEDO outputs LEDO1 to LEDO8 SVCC SGND PGND No.A1585-5/9 LV5212VH Timing conditions Parameter symbol Conditions min typ max SCK Duty = 50% unit Clock frequency fs1 10 Clock pulse width twck SCK 50 ns Latch pulse width twla LATCH 50 ns Data set up time ts1 SDATAIN setup time relative to the rise of SCK 25 ns Data hold time th1 SDATAIN data hold time relative to the rise of SCK 25 ns Clock latch time tla1 Input conditions 1 ton SCK and SDATAIN rise time 100 ns Input conditions 2 toff SCL and SDATAIN fall time 100 ns 100 MHz ns twck SCK 2.5V 90% 2.5V 90% 10% ts1 10% th1 ton 2.5V SDATAIN toff 2.5V twla tla1 2.5V LATCH 2.5V SOUT output timings Parameter symbol Conditions min typ max unit SOUT delay time 1 tdso1 The time from a SCK falling edge to SOUT rising edge 50 MHz SOUT delay time 2 tdso2 The time from a SCK falling edge to SOUT falling edge 50 ns SCK 2.5V 2.5V tdso1 tdso2 2.5V 2.5V SOUT No.A1585-6/9 LV5212VH LEDO output timings Parameter symbol LEDO delay time 1 tdled1 Conditions min The time from an XEN rising edge to LEDO rising edge typ max unit 100 ns 100 ns 200 ns 200 ns 200 ns CL = 30pF, IO = 100mA, VO = 30V LEDO delay time 2 tdled2 The time from an XEN falling edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 30V LEDO rise time trled LEDO rise time CL = 30pF, IO = 100mA, VO = 30V LEDO fall time tfled LEDO fall time CL = 30pF, IO = 100mA, VO = 30V LEDO delay time 3 tdled3 The time from a LATCH rising edge to LEDO falling edge CL = 30pF, IO = 100mA, VO = 30V XEN 2.5V 2.5V tdled2 tdled1 90% LEDO 90% 90% 10% 10% trled tfled tdled3 2.5V LATCH No.A1585-7/9 LV5212VH Application Circuit Example • When parallel output is used max : 50V max : 50V SDATAIN SCK LATCH XEN SDATAIN sub CPU SCK LATCH XEN XRESET PGND2 PGND1 SGND1 XRESET SVCC PGND1 sub CPU LEDO1 LEDO2 LEDO3 LEDO4 LEDO5 LEDO6 LEDO7 LEDO8 SOUT SGND1 SVCC 5V LEDO1 LEDO2 LEDO3 LEDO4 LEDO5 LEDO6 LEDO7 LEDO8 SOUT Max IO : 300mA PGND2 5V • When serial output is used (SOUT cascade connection) max:50V 5V XEN PGND1 XRESET SCK LATCH XEN XRESET LEDO1 LEDO2 LEDO3 LEDO4 LEDO5 LEDO6 LEDO7 LEDO8 SOUT To SDATAIN PGND2 LATCH SDATAIN PGND1 SCK SVCC SGND1 SDATAIN SGND1 sub CPU LEDO1 LEDO2 LEDO3 LEDO4 LEDO5 LEDO6 LEDO7 LEDO8 SOUT PGND2 SVCC No.A1585-8/9 LV5212VH Allowable output current characteristics IO -- LEDO Ta = 250 Output current, IO -- mA IO -- LEDO 300 25° C Output current, IO -- mA 300 50°C 200 75°C 150 100 50 Ta = 25°C 250 50°C 200 75°C 150 100 50 duty cycle 100% 0 0 1 2 duty cycle 80% 0 3 4 5 6 7 8 Number of output ports, LEDO 0 1 2 3 4 5 6 7 8 Number of output ports, LEDO IO -- LEDO 300 Ta = 25°C 50°C 75°C Output current, IO -- mA 250 200 150 100 50 duty cycle 50% 0 0 1 2 3 4 5 6 7 8 Number of output ports, LEDO SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2009. Specifications and information herein are subject to change without notice. PS No.A1585-9/9