IC89LV52(51)A CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8(4)-Kbytes of FLASH FEATURES GENERAL DESCRIPTION • 80C52(51) based architecture • 8(4)-Kbytes Flash memory with fast-pulse programming algorithm and software protection • 256 x 8 RAM (128 x 8 RAM) • Three (Two)16-bit Timer/Counters • Full duplex serial channel • Boolean processor • Four 8-bit I/O ports, 32 I/O lines • Memory addressing capability – 64K ROM and 64K RAM • Program memory lock – Lock bits (3) • Power save modes: – Idle and power-down • Eight interrupt sources • Most instructions execute in 0.5 µs • CMOS and TTL compatible • Maximum speed: 24 MHz @ Vcc = 3.3V • Packages available: – 40-pin DIP – 44-pin PLCC – 44-pin PQFP The ICSI IC89LV52(51)A is a high-performance microcontroller fabricated with high-density CMOS technology. The CMOS IC89LV52A is functionally compatible with the NMOS Intel 8052(51) and Philips ’ 80C52(51) micro controller, but its VCC is 3.05V~3.6V . The IC89LV52(51)A contains a 8K (4K) x 8 Flash; a 256 x 8 RAM (128 x 8 RAM); 32 I/O lines for either multiprocessor communications; I/O expansion or full duplex UART; three (two) 16-bit timers/counters; a six-source (five-source), two-priority-level, nested interrupt structure; and on chip oscillator and clock circuit. The IC89LV52(51)A can be expanded using standard TTL compatible memory. T2/P1.0 1 40 VCC T2EX/P1.1 2 39 P0.0/AD0 P1.2 3 38 P0.1/AD1 P1.3 4 37 P0.2/AD2 P1.4 5 36 P0.3/AD3 P1.5 6 35 P0.4/AD4 P1.6 7 34 P0.5/AD5 P1.7 8 33 P0.6/AD6 RST 9 32 P0.7/AD7 RxD/P3.0 10 31 EA/VPP TxD/P3.1 11 30 ALE/PROG INT0/P3.2 12 29 PSEN INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 GND 20 21 P2.0/A8 Figure 1. IC89LV52(51)A Pin Configuration: 40-pin DIP ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. MC010-0D 11/16/2001 1 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 INDEX P1.4 IC89LV52(51)A 6 5 4 3 2 1 44 43 42 41 40 P1.5 7 39 P0.4/AD4 P1.6 8 38 P0.5/AD5 P1.7 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 RxD/P3.0 11 35 EA/VPP NC 12 34 NC TxD/P3.1 13 33 ALE/PROG INT0/P3.2 14 32 PSEN INT1/P3.3 15 31 P2.7/A15 T0/P3.4 16 30 P2.6/A14 T1/P3.5 17 29 P2.5/A13 18 19 20 21 22 23 24 25 26 27 28 WR/P3.6 RD/P3.7 XTAL2 XTAL1 GND NC A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 TOP VIEW Figure 2. IC89LV52(51)A Pin Configuration: 44-pin PLCC 2 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 NC VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 IC89LV52(51)A 44 43 42 41 40 39 38 37 36 35 34 P0.6/AD6 RST 4 30 P0.7/AD7 RxD/P3.0 5 29 EA/Vpp NC 6 29 NC TxD/P3.1 7 27 ALE/PROG INT0/P3.2 8 26 PSEN INT1/P3.3 9 25 P2.7/A15 T0/P3.4 10 24 P2.6/A14 T1/P3.5 11 23 P2.5/A13 12 13 14 15 16 17 18 19 20 21 22 A12/P2.4 31 A11/P2.3 3 A10/P2.2 P1.7 A9/P2.1 P0.5/AD5 A8/P2.0 32 NC 2 GND P1.6 XTAL1 P0.4/AD4 XTAL2 33 RD/P3.7 1 WR/P3.6 P1.5 Figure 3. IC89LV52(51)A Pin Configuration: 44-pin PQFP Integrated Circuit Solution Inc. MC010-0D 11/16/2001 3 IC89LV52(51)A Vcc P2.0-P2.7 P0.0-P0.7 P2 DRIVERS P0 DRIVERS GND ADDRESS DECODER & 256 BYTES RAM RAM ADDR REGISTER P2 LATCH STACK POINT B REGISTER PCON SCON T2CON TH0 TL1 TH2 RCAP2L SBUF P0 LATCH ADDRESS DECODER & 8K FLASH PROGRAM ADDRESS REGISTER ACC TMOD TCON TL0 TH1 TL2 RCAP2H IE IP 3 LOCK BITS TMP2 INTERRUPT BLOCK SERIAL PORT BLOCK TIMER BLOCK TMP1 PROGRAM COUNTER PC INCREMENTER ALU PSW PSEN ALE/PROG RST TIMING AND CONTROL EA/VPP INSTRUCTION REGISTER BUFFER DPTR P3 LATCH P1 LATCH OSCILLATOR XTAL1 XTAL2 P3 DRIVERS P1 DRIVERS P3.0-P3.7 P1.0-P1.7 Figure 4. IC89LV52(51)A Block Diagram 4 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A Table 1. Detailed Pin Description Symbol PDIP PLCC PQFP I/O Name and Function ALE/PROG 30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the Program Pulse input (PROG) during Flash programming. EA/VPP 31 35 29 I External access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 1FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address grater than 1FFFH. IC89C51A internal Programming memory range is from 0000-0FFFH. This is also receives the 12 V programming enable voltage (Vpp) during Flash programming, when 12 V programming is selected. P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pullups when emitting 1s. Port 0 also receives the command and code bytes during programmable memory programming and outputs the code bytes during program verification. External pullups are required during program verification. P1.0-P1.7 1-8 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). The Port 1 output buffers can sink/source four TTL inputs. Port 1 also receives the low-order address byte during Flash programming and verification. P2.0-P2.7 1 2 2 3 40 41 I I T2(P1.0): Timer/Counter 2 external count input.(IC89LV52A only) T2EX(P1.1): Timer/Counter 2 trigger input.(IC89LV52A only) 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order bits and some control signals during Flash programming and verification. P2.6 is a program command strobe signal. P2.7 is a data output enable signal. Integrated Circuit Solution Inc. MC010-0D 11/16/2001 5 IC89LV52(51)A Table 1. Detailed Pin Description (continued) Symbol PDIP PLCC PQFP I/O Name and Function P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 3 also serves the special features of the IC89LV52(51)A, as listed below: 10 11 12 13 14 15 16 11 13 14 15 16 17 18 5 7 8 9 10 11 12 I O I I I I O 17 19 13 O RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt 0. INT1 (P3.3): External interrupt 1. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. Program control signal while the chip programs and erases. RD (P3.7): External data memory read strobe. Program control signal while the chip programs and erases. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. PSEN is an input control signal while memory program and verification. RST 9 10 4 I Reset: A high on this pin for two machine cycleswhile the oscillator is running resets the device. An internal resistor to GND permits a power-on reset using only an external capacitor. A small internal resistor permits power-on reset using only a capacitor connected to VCC. RST is an input control signal during memory program and verification. XTAL 1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL 2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. GND 20 22 16 I Ground: 0V reference. Vcc 40 44 38 I Power Supply: This is the power supply voltage for operation. 6 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A OPERATING DESCRIPTION The detail description of the IC89LV52(51)A included in this description are: • Memory Map and Registers • Timer/Counters • Serial Interface • Interrupt System • Other Information The detail information desription of the IC89LV52(51)A refer to IS80C52/32 data sheet Programming the IC89LV52(51)A: Programming Interface: The IC89LV52(51)A is normally shipped the on-chip Flash memory array in the erased state (i.e. contents=FFH) and ready to be programmed. The IC89LV52(51)A is programmed byte-by-byte in programming mode. Before the on-chip flash code memory can be re-programmed, the entire memory array must be erased electrically. Some conditions must be satisfied before entering the programming mode. The conditions are listed following. 1. RST is high level 2. PSEN is low level 3. P3.6 and P3.7 is high level The interface-controlled signals are matched these conditions, then the IC89C52(51)A will enter received command mode. The flash command is accepted by the flash command decoder in command received mode. The programming interface is listed in figure 5. VCC RST L PSEN PROG pulse 12V/H ALE/PROG EA/VPP Command Write P2.6 Output Enable P2.7 H P3.6 H P3.7 1-12MHz Clock XTAL1 VCC IS89LV52A/51A H 10K P0 D7-D0 P1 A7-A0 P2.4-2.0 A12-A8 VSS Figure 5. Programming Interface Integrated Circuit Solution Inc. MC010-0D 11/16/2001 7 IC89LV52(51)A Flash Command Definitions Normal Verify(1) Read Signature Byte Bus Cycle (n+1) (2) 4 First Bus Cycle Operation Address Data VPP P2.6 X 00H H P2.6 X 90H H Program Code Memory Program Verify(1) Program Lock Bit 1 Program Lock Bit 2 Program Lock Bit 3 Chip Erase 2 (n+1) (2) 2 2 2 2 P2.6 P2.6 P2.6 P2.6 P2.6 P2.6 X X X X X X 40H C0H 60H 70H 80H 20H H H H H H H Second Bus Cycle Operation Address Data P2.7 Low SA(3) SD(3) P2.7 Low 30H D5H 31H 52H 32H 55H/AAH PROG PA(3) PD(3) P2.7 Low SA PVD(3) PROG X D0H PROG X D0H PROG X D0H PROG X D0H Erase Verify(1) (n+1) (2) P2.6 X A0H H P2.7 Low EA(3) EVD(3) VPP H 12V/H H 12V/H 12V/H 12V/H 12V/H H Note: 1. Normal Verify: Internal flash sense amplifier uses the same threshold as instruction executing threshold. Program Verify: The flash sense amplifier applies an internally generated higher margin voltage to the addressed byte. If a comparison between the programmed byte and the true data is successful, there is a margin exists in the programmed data. Erase Verify: The flash sense amplifier applies an internally generated lower margin voltage to the addressed byte. Reading FFH from the addressed byte indicates that all bits in the bytes are erased. 2. To verify n bytes data. 3. SA = Selected Address of memory location to be read except program or erase verify. SD = Data read from location SA with Normal Verification threshold. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. PVD = Data read from location PA during program verify. EA = Address of memory location to be read during erase verify. EVD - Data read from location EA during erase verify. Programming Core Memory Every code byte in the Flash array can be written and the entire array can be erased using the appropriate command from Port 0 by programmer or application system. The program/erase are two-cycle operations. The first cycle is command write cycle; the command 40H is written by P2.6 falling and rising edges. The command would be held a stable value within P2.6 low state. The command decoder enables programming flag after the first cycle is completion, then the internal programming flag is set. Rising edge of PROG will clear internal programming flag, so the programming command must be presented every programming cycle. The second cycle is real flash programming cycle. The programming address and data are latched at PROG falling edge, the programming time is controlled by low time of PROG. The programming flag is cleared at PROG rising edge in the second cycle. Programming address range is from 0 to 1FFFH. IC89LV52(51)A programming range is from 0 to 1FFFH, but the program counter will jump to external menory while MCU executing the address is excess 0FFFH. The IC89LV52(51)A code memory programming now is described in Figure 6. 8 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A Program Verify If lock bits LB2 and LB3 have not been programmed, the programmed code data can be read back via the address and data lines for verification. ‘C0H’ command is needed for switching to program verify mode. During program verify, the code memory use the internally-generated higher margin voltage to the addressed byte. Normal Verify If lock bits LB2 and LB3 have not been programmed, the programmed code data can be read back via the address and data lines for verification. If flash command decoder receives the ‘00H’ command or IC89C52(51)A power is initialized, the command decoder switches to normal verify mode. During normal verify, the code memory use the same threshold as instruction executing threshold. Erase Verify If lock bits LB2 and LB3 have not been programmed, the programmed code data can be read back via the address and data lines for verification. ‘A0H’ command is needed for switching to erase verify mode. During erase verify, the code memory use the internally-generated lower margin voltage to the addressed byte. Program Lock Bit 1, 2, 3 The lock bit 1, 2, 3 is programmed by using the erase command ‘60H’, ‘70H’ and ‘80H’ in the first cycle. In the second cycle, the ‘D0H’ command is presented on whole PROG strobe time. The PROG strobe time is real lock bits programming time. The PROG rising edge will clear the erasing state to normal verify state. The programming lock bits operations don’t use the smart algorithm but it is programmed 10 times directly. If programming lock bits are needed, it must be programmed after the encryption array and code memory programming. The IC89C52(51)A lock bits programming flow is described in Figure 7. Chip Erase All flash cell must be programmed to ‘00’ before the chip is erased. The programming sequence is encryption array, code memory and lock bit 1, 2, 3. The entire flash array is erased electrically by using the erase command ‘20H’ in the first cycle. In the second cycle, the ‘D0H’ command is presented on whole PROG strobe time. The PROG strobe time is real flash erasing time. The PROG rising edge will clear the erasing state to normal verify state. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. If the any flash cell is not ‘1’ (include encryption array and lock bits) repeat erase condition less than 50 times. The IC89C52(51)A detail erase flow is described in Figure 8. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H and 032H, except that command is ‘90H’. The values returned are: (030H) = D5H indicates manufactured by ICSI (031H) = 52H indicates IC89C52A/IC89C51A (032H) = AAH indicates programming voltage is 12V 55H indicates programming voltage is 5V The signatures can be read by following conditions. It’s easier to recognize by programmer. 1. RST = high level. PSEN = Low level. PROG = High level. VPP = High Level. P2.6 = Low level. P2.7 = Low level. P3.6 = Low level. P3.7 = Low level. 2. Address is switched to (030H), (031H) and (032H). Then the Data bus outputs the D5H, 52H, AAH (55H). Lock bits Features Program Lock bits Protection Type LB1 LB2 LB3 1 U U U No program lock feature enabled. 2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3 P P U Same as 2, also verify is disabled 4 P P P Same as 3, also external execution is disabled Integrated Circuit Solution Inc. MC010-0D 11/16/2001 9 IC89LV52(51)A VPP=Vppl, Address=0 Start Programming Setup ’C0H’ Command PLSCNT=0, Address=0, Setup Received Command Mode (1) P2.6 set low pulse for 100 ns VPP=Vppl, Setup ’40H’ Command Setup Address & P2.7 = 0 P2.6 set low pulse for 100 ns Read Data & Set P2.7=1 INC PLSCNT Setup Address ,Data VPP=Vpph orVppl(2) INC Address INC Address No No PLSCNT=10? PROG set low pulse for 200 us Yes Verify Data? Yes No Last Address? No Yes Last Address ? Yes Programming Error Programming Completed 1. Received Command Mode status: RST=1, PSEN=0, PROG=1, VPP=1, P2.6=1, P2.7=1, P3.6=1, P3.7=1 2. The VPP voltage is decided by Signature Byte address(032H) Figure. 6 10 IC89LV52(51)A Main Memory Programming Flow Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A Start Programming PLSCNT=0, Setup Received Command Mode (1) Setup ’60H’(’70H’ ,’80H’)Command P2.6 set low pulse for 100 ns Setup ’D0H’ Command VPP=Vpph or Vppl(2) PROG set low pulse for 100 ns VPP=Vppl No PLSCNT=10? Yes Programming Completed 1. Received Command Mode status: RST=1, PSEN=0, PROG=1, VPP=1, P2.6=1, P2.7=1, P3.6=1, P3.7=1 2. The VPP voltage is decided by Signature Byte address(032H) Figure. 7 IC89LV52(51)A Lock Bits Programming Flow Integrated Circuit Solution Inc. MC010-0D 11/16/2001 11 IC89LV52(51)A Start Erase Flow Start Erase operation PLSCNT=0, Setup Received Command Mode VPP=Vppl, Setup ’20H’ Command (1) Erase operation (2) * 2 pulse P2.6 set low pulse for 100 ns Programming all data to ’00’ (4) Setup ’D0H’ Command, VPP=Vpph or Vppl (5) PLSCNT=0, Address=00H PROG set low pulse for 200 ns Erase operation (2) VPP=Vppl Setup ’A0H’ Command Erase Completed P2.6 set low pulse for 100 ns Chip Erase Sub-flow 1. Received Command Mode status: RST=1, PSEN=0, PROG=1, VPP=1, P2.6=1, P2.7=1, P3.6=1, P3.7=1 2. The erase operation show in "Erase Operation" Sub-flow 3. To program main memory to '00', then program lock bits. The pre-programming address range are from 0 to 1FFFH either in IS89LV52A or in IS89LV51A 4. The VPP voltage is decided by Signature Byte address(032H) Setup Address & P2.7 = 0 INC PLSCNT Read Data & Set P2.7 = 1 No No PLSCNT=50 ? Data=’FF’ ? Yes Yes No Last Address ? INC Address Erase operationx3 Pulse Yes Erase Error Erase Completed Chip Erase Main flow Figure. 8 12 IC89LV52(51)A Erase Flow Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND(2) Temperature Under Bias(3) Storage Temperature Power Dissipation Value –2.0 to +7.0 0 to +70 –65 to +125 1.5 Unit V °C °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2. 0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 20 ns. 3. Operating temperature is for commercial products only defined by this specification. OPERATING RANGE(1) Range Commercial Ambient Temperature VCC Oscillator Frequency 0°C to +70°C 3.05V to 3.6V ; 5V ± 10% 3.5 to 24 MHz Note: 1. Operating ranges define those limits between which the functionality of the device is guaranteed. Integrated Circuit Solution Inc. MC010-0D 11/16/2001 13 IC89LV52(51)A DC CHARACTERISTICS (Ta=0°C to 70°C; VCC=3.05V-3.6V ; VSS=0V ) Symbol Parameter Test conditions Min Max Unit VIL Input low voltage (All except EA) –0.5 0.2Vcc + 0.1 V VIL1 Input low voltage (XTAL 1,EA) –0.5 0.2Vcc + 0.1 V VIH Input high voltage (All except XTAL 1, RST, EA) 0.2Vcc + 0.9 Vcc + 0.5 V VIH1 Input high voltage (XTAL 1) 0.7Vcc Vcc + 0.5 V VSCH+ RST positive schmitt-trigger threshold voltage 0.7Vcc Vcc + 0.5 V VSCH– RST negative schmitt-trigger threshold voltage 0 0.3Vcc V VOL(1) Output low voltage IOL = 1.6 mA — 0.45 V IOL = 3.2 mA — 0.45 V (Ports 1, 2, 3) (1) VOL1 Output low voltage (Port 0, ALE, PSEN) VOH Output high voltage (Ports 1, 2, 3, ALE, PSEN) IOH = –20 µA Vcc-0.9 — V VOH1 Output high voltage (Port 0, ALE, PSEN) IOH = –800 µA VCC-0.9 — V IIL Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V — –50 µA ILI Input leakage current (Port 0) 0.45V < VIN < Vcc –5 +5 µA ITL Logical 1-to-0 transition current (Ports 1, 2, 3) VIN = 1.5V — –450 µA RST pulldown resister VIN=VCC 150 450 KΩ RRST Note: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions. 14 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A POWER SUPPLY CHARACTERISTICS Symbol Parameter Test conditions (1) Icc Min Max Unit Power supply current Vcc = 3.3V Active mode 12 MHz — 15 mA 24 MHz — 24 mA 12 MHz — 4 mA 24 MHz — 8 mA VCC = 3.3V — 50 µA Idle mode Power-down mode Note: 1. See Figures9,10,11 and 12 for Icc test conditiions. Vcc Vcc Vcc Icc Icc RST RST Vcc Vcc Vcc Vcc NC XTAL2 CLOCK SIGNAL XTAL1 GND P0 EA NC XTAL2 CLOCK SIGNAL XTAL1 GND P0 EA Figure 10. Idle Mode Figure 9. Active Mode Vcc Icc RST Vcc Vcc NC XTAL2 P0 XTAL1 GND EA Figure 11. Power-down Mode (Vcc = 2.0V ~ 3.0V) Integrated Circuit Solution Inc. MC010-0D 11/16/2001 15 IC89LV52(51)A tCLCX Vcc — 0.5V 0.45V tCHCX 0.7Vcc 0.2Vcc — 0.1 tCHCL tCLCH tCLCL Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Mode (tCLCH=tCHCL=5 ns) AC CHARACTERISTICS (Ta=0°C to 70 °C; VCC=3.05V~3.6V ; VSS=0V; C1 for port 0, ALE and PSEN Outputs=100pF; C1 for other outputs=80pF) EXTERNAL MEMORY CHARACTERISTICS Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH 16 Parameter Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instr in ALE low to PSEN low PSEN pulse width PSEN low to valid instr in Input instr hold after PSEN Input instr float after PSEN Address to valid instr in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address to RD or WR low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high 24 MHz Clock Min Max — — 68 — 26 — 31 — — 147 31 — 110 — — 105 0 — — 37 — 188 — 10 230 — 230 — — 157 0 — — 78 — 282 — 323 105 145 146 — 26 — 31 — — 0 26 57 12 MHz Clock Min Max — — 152 — 68 — 73 — — 312 68 — 235 — — 230 0 — — 78 — 397 — 10 480 — 480 — — 323 0 — — 162 — 573 — 656 230 270 313 — 68 — 73 — — 0 68 98 Variable Oscillator (3.5 - 24 MHz) Min Max 3.5 24 2tCLCL–15 — tCLCL–15 — tCLCL–10 — — 4tCLCL–20 tCLCL–10 — 3tCLCL–15 — — 3tCLCL–20 0 — — tCLCL–5 — 5tCLCL–20 — 10 6tCLCL–20 — 6tCLCL–20 — — 4tCLCL–10 0 — — 2tCLCL–5 — 7tCLCL–10 — 8tCLCL–10 3tCLCL–20 3tCLCL+20 4tCLCL–20 — tCLCL–15 — tCLCL–10 — — 0 tCLCL–15 tCLCL+15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A SERIAL PORT TIMING: SHIFT REGISTER MODE Symbol Parameter tXLXL tQVXH Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid tXHQX tXHDX tXHDV 24 MHz Clock Min Max 12 MHz Clock Min Max Variable Oscillator (3.5-24 MHz) Min Max 490 327 — — 990 743 — — 12tCLCL–10 10tCLCL–90 — — ns ns 58 — 142 — 2tCLCL–25 — ns 0 — 0 — 0 — ns — 284 — 700 — 10tCLCL—133 ns Max 24 — — 10 10 Unit MHz ns ns ns ns Unit EXTERNAL CLOCK DRIVE CHARACTERISTICS Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency High time Low time Rise time Fall time Min 3.5 10 10 — — Flash Program/Erase and Verification & Test Mode Characteristics Symbol Vcc Vpp Ipp tDVCL tCLCH tCHDX tAVGL tGHAX tDVGL tGHDX tSHGL tGHSL tGLGH tGLGHE tAVQV tELQV tAXQX tEHQX Parameter Programming and Erase Power Voleage Programming and Erase Enable Voltage Programming and Erase Enable Current Data Valid to Command Setup Low Command Setup Width Data Hold after Command Setup Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG Vpp Setup to PROG Low Vpp Hold after PROG PROG Pulse Width in Programming Cycle PROG Pulse Width in Erase Cycle Address Valid to Data Valid ENABLE Low to Data Valid Data Float after Address Float Data Float after ENABLE Integrated Circuit Solution Inc. MC010-0D 11/16/2001 Min 5.25 11.5 10 100 10 20 20 20 20 10 10 200 200 0 0 Max 5.75 12.5 2.0 50 50 - Unit V V mA ns ns ns ns ns ns ns us us us ms ns ns ns ns 17 IC89LV52(51)A TIMING WAVEFORMS tLHLL ALE tLLPL tPLPH tPLIV tAVLL PSEN tPLAZ tLLAX PORT 0 A7-A0 tPXIX tPXIZ INSTR IN A7-A0 tLLIV tAVIV PORT 2 A15-A8 A15-A8 Figure 13. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD PORT 0 tAVLL tRLAZ tLLAX tRLRH tRLDV A7-A0 FROM RI OR DPL tRHDZ tRHDX DATA IN A7-A0 FROM PCL INSTR IN tAVWL tAVDV PORT 2 A15-A8 FROM DPH A15-A8 FROM PCH Figure 14. External Data Memory Read Cycle 18 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tWHQX tQVWX tLLAX A7-A0 FROM RI OR DPL DATA OUT A7-A0 FROM PCL INSTR IN tAVWL PORT 2 A15-A8 FROM DPH A15-A8 FROM PCH Figure 15. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH 0 DATAOUT 1 tXHDV DATAIN VALID VALID 2 tXHDX VALID 3 4 5 6 7 SET TI VALID VALID VALID VALID VALID SET RI Figure 16. Shift Register Mode Timing Waveform Integrated Circuit Solution Inc. MC010-0D 11/16/2001 19 IC89LV52(51)A PROGRAM SETUP CYCLE P2.3-P2.0 P1.7-P1.0 P0 PROGRAM CYCLE PROGRAM VERIFY PROGRAM SETUP CYCLE VERIFY CYCLE ADDRESS IN tAVGL 40H ADDRESS IN tGHAX tAVQV DATA IN C0H tAXQX DATA OUT tDVCL tCHDX tDVGL tGHDX tDVCL tCHDX P2.6 (Command Setup) tCLCH tCLCH tELQV tEHQX P2.7(OE) tGLGH PROG tSHGL tGHSL VPP Figure 17. Programming Timing Wavform 20 Integrated Circuit Solution Inc. MC010-0D 11/16/2001 IC89LV52(51)A ERASE SETUP CYCLE ERASE CYCLE ERASE VERIFY SETUP CYCLE P2.3-P2.0 P1.7-P1.0 P0 ERASE VERIFY CYCLE ADDRESS IN tAVQV 20H D0H A0H tAXQX DATA OUT tDVCL tCHDX tDVGL tGHDX tDVCL tCHDX P2.6 (Command Setup) tCLCH tCLCH tELQV tEHQX P2.7(OE) tGLGH PROG tSHGL tGHSL VPP Figure 18. Erase Timing Waveform tCLCX Vcc — 0.5V 0.45V tCHCX 0.7Vcc 0.2Vcc — 0.1 tCHCL tCLCH tCLCL Figure 19. External Clock Drive Waveform Vcc - 0.5V 0.45V 0.2Vcc + 0.9V 0.2Vcc - 0.1V Figure 20. AC Test Point Note: 1.AC inputs during testing are driven at Vcc-0.5v for logic “1” and 0.45V for logic “0”. Timing measurements are made at Vih min for logic “1” and max for logic “0”. Integrated Circuit Solution Inc. MC010-0D 11/16/2001 21 IC89LV52(51)A ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed 12 MHz 24 MHz Order Part Number IC89LV52(51)A-12PL IC89LV52(51)A-12W IC89LV52(51)A-12PQ IC89LV52(51)A-24PL IC89LV52(51)A-24W IC89LV52(51)A-24PQ Package PLCC 600mil DIP PQFP PLCC 600mil DIP PQFP Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 22 Integrated Circuit Solution Inc. MC010-0D 11/16/2001