Cypress CY7C1041CV33-10ZSXA 4-mbit (256 k ã 16) static ram ttl-compatible inputs and output Datasheet

CY7C1041CV33 Automotive
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Automotive-A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
The CY7C1041CV33 Automotive is a high performance CMOS
static RAM organized as 262,144 words by 16 bits.
■
Pin and function compatible with CY7C1041BNV33
■
High speed
❐ tAA = 10 ns (Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■
Low active power
❐ 432 mW (max)
■
2.0 V data retention
■
Automatic power down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-ball FBGA packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A16
A17
A14
A15
A12
A13
A9
Cypress Semiconductor Corporation
Document Number: 001-67307 Rev. **
A10
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 11, 2011
[+] Feedback
CY7C1041CV33 Automotive
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 001-67307 Rev. **
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ....................................................................... 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Page 2 of 17
[+] Feedback
CY7C1041CV33 Automotive
Selection Guide
Description
Maximum Access Time
-10
-12
-20
Unit
10
12
20
ns
100
–
85
mA
Automotive-E
–
120
90
mA
Automotive-A
10
–
10
mA
–
15
15
mA
Maximum Operating Current
Automotive-A
Maximum CMOS Standby Current
Automotive-E
Pin Configuration
Figure 1. 44-pin SOJ/TSOP II (Top View) [1]
A0
A1
A2
A3
A4
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A14
A13
A12
A11
A10
Figure 2. 48-ball FBGA Pinout (Top View) [1]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
IO0
BHE
A3
A4
CE
IO8
B
IO1
IO2
A5
A6
IO10
IO9
C
VSS
IO3
A17
A7
IO11 VCC
D
VCC
IO4
NC
A16
IO12
VSS
E
IO6
IO5
A14
A15
IO13
IO14
F
IO7
NC
A12
A13
WE
IO15
G
NC
A8
A9
A10
A11
NC
H
Note
1. NC pins are not connected on the die.
Document Number: 001-67307 Rev. **
Page 3 of 17
[+] Feedback
CY7C1041CV33 Automotive
Pin Definitions
Pin Name
SOJ, TSOP
Pin Number
BGA
Pin Number
I/O Type
A0–A17
1–5, 18–27,
42–44
A3, A4, A5, B3,
B4, C3, C4, D4,
H2, H3, H4, H5,
G3, G4, F3, F4,
E4, D3
Input
I/O0–I/O15
Description
Address Inputs. Used to select one of the address locations.
7–10,13–16, B1, C1, C2, D2, Input or Output Bidirectional Data I/O lines. Used as input or output lines
29–32, 35–38 E2, F2, F1, G1,
depending on operation.
B6, C6, C5, D5,
E5, F5, F6, G6
NC
28
A6, E3, G2, H1,
H6
No Connect
WE
17
G5
Input or
Control
Write Enable Input, Active LOW. When selected LOW, a write is
conducted. When deselected HIGH, a read is conducted.
CE
6
B5
Input or
Control
Chip Enable Input, Active LOW. When LOW, selects the chip.
When HIGH, deselects the chip.
BHE, BLE
40, 39
B2, A1
Input or
Control
Byte Write Select Inputs, Active LOW. BHE controls I/O15 – I/O8,
BLE controls I/O7 – I/O0.
OE
41
A2
Input or
Control
Output Enable, Active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, the I/O pins are tri-stated and act as input data
pins.
VSS
12, 34
D1, E6
Ground
Ground for the Device. Connected to ground of the system.
VCC
11, 33
D6, E1
Document Number: 001-67307 Rev. **
No Connects. Not connected to the die.
Power Supply Power Supply Inputs to the Device.
Page 4 of 17
[+] Feedback
CY7C1041CV33 Automotive
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Static Discharge Voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... > 200 mA
Operating Range
Ambient Temperature with
Power Applied .......................................... –55 C to +125 C
Ambient
Temperature (TA)
VCC
Automotive-A
–40 C to +85 C
3.3 V  10%
Automotive-E
–40 C to +125 C
Range
Supply Voltage on VCC Relative to GND[2] ...–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State[2] .................................. –0.5 V to VCC + 0.5 V
DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage VCC = Min, IOH = –4.0 mA
-10
-12
-20
Unit
Min
Max
Min
Max
Min
Max
2.4
–
2.4
–
2.4
–
V
VOL
Output LOW Voltage VCC = Min, IOL = 8.0 mA
–
0.4
–
0.4
–
0.4
V
VIH
Input HIGH Voltage
2.0
VCC +
0.3
2.0
VCC +
0.3
2.0
VCC +
0.3
V
VIL [2]
Input LOW Voltage
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
A
Output Leakage
Current
GND < VOUT < VCC,
Output disabled
VCC Operating
Supply Current
VCC = Max,
f = fMAX = 1/tRC
IOZ
ICC
ISB1
ISB2
Auto-A
–1
+1
–
–
–1
+1
Auto-E
–
–
–20
+20
–20
+20
Auto-A
–1
+1
–
–
–1
+1
Auto-E
–
–
–20
+20
–20
+20
Auto-A
–
100
–
–
–
85
Auto-E
–
–
–
120
–
90
Automatic CE Power Max VCC, CE > VIH,
Down Current —TTL VIN > VIH, or VIN < VIL,
Inputs
f = fMAX
Auto-A
–
40
–
–
–
40
Auto-E
–
–
–
45
–
45
Automatic CE Power Max VCC,
Down Current —
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V,
CMOS Inputs
or VIN < 0.3 V, f = 0
Auto-A
–
10
–
–
–
10
Auto-E
–
–
–
15
–
15
A
mA
mA
mA
Note
2. VIL (min) = –2.0 V and VIH(max) = VCC + 0.5 V for pulse durations of less than 20 ns.
Document Number: 001-67307 Rev. **
Page 5 of 17
[+] Feedback
CY7C1041CV33 Automotive
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
Max
Unit
8
pF
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
SOJ
TSOP II
FBGA
Unit
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
25.99
42.96
38.15
C/W
18.8
10.75
9.15
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [3]
10-ns devices:
12-, 15-, 20-ns devices:
Z = 50 
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317
3.3 V
OUTPUT
30 pF*
OUTPUT
R2
351
30 pF*
1.5 V
(b)
(a)
High Z characteristics:
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(c)
R 317
3.3 V
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Note
3. AC characteristics (except High Z) for 10 ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown
in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
Document Number: 001-67307 Rev. **
Page 6 of 17
[+] Feedback
CY7C1041CV33 Automotive
Switching Characteristics
Over the Operating Range [4]
Parameter
-10
Description
-12
-20
Min
Max
Min
Max
Min
Max
Unit
Read Cycle
tpower[5]
VCC(Typical) to the First Access
100
–
100
–
100
–
s
tRC
Read Cycle Time
10
–
12
–
20
–
ns
tAA
Address to Data Valid
–
10
–
12
–
20
ns
tOHA
Data Hold from Address Change
3
–
3
–
3
–
ns
tACE
CE LOW to Data Valid
–
10
–
12
–
20
ns
tDOE
OE LOW to Data Valid
Auto-A
–
5
–
6
–
8
ns
Auto-E
–
–
–
7
–
8
tLZOE
OE LOW to Low Z[6]
0
–
0
–
0
–
ns
–
5
–
6
–
8
ns
3
–
3
–
3
–
ns
tHZOE
tLZCE
OE HIGH to High
CE LOW to Low
Z[6, 7]
Z[6]
Z[6, 7]
tHZCE
CE HIGH to High
–
5
–
6
–
8
ns
tPU
CE LOW to Power Up
0
–
0
–
0
–
ns
tPD
CE HIGH to Power Down
–
10
–
12
–
20
ns
tDBE
Byte Enable to Data Valid
Auto-A
–
5
–
6
–
8
ns
Auto-E
–
–
–
7
–
8
tLZBE
Byte Enable to Low Z
0
–
0
–
0
–
ns
Byte Disable to High Z
–
6
–
6
–
8
ns
tHZBE
Write Cycle
[8, 9]
tWC
Write Cycle Time
10
–
12
–
20
–
ns
tSCE
CE LOW to Write End
7
–
8
–
10
–
ns
tAW
Address Setup to Write End
7
–
8
–
10
–
ns
tHA
Address Hold from Write End
0
–
0
–
0
–
ns
tSA
Address Setup to Write Start
0
–
0
–
0
–
ns
tPWE
WE Pulse Width
7
–
8
–
10
–
ns
tSD
Data Setup to Write End
5
–
6
–
8
–
ns
tHD
Data Hold from Write End
0
–
0
–
0
–
ns
Z[6]
tLZWE
WE HIGH to Low
3
–
3
–
3
–
ns
tHZWE
WE LOW to High Z[6, 7]
–
5
–
6
–
8
ns
tBW
Byte Enable to End of Write
7
–
8
–
10
–
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 6. Transition is measured 500 mV from steady state
voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-67307 Rev. **
Page 7 of 17
[+] Feedback
CY7C1041CV33 Automotive
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 001-67307 Rev. **
Page 8 of 17
[+] Feedback
CY7C1041CV33 Automotive
Switching Waveforms
(continued)
Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
DATA IO
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA IO
Notes
13. Data IO is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-67307 Rev. **
Page 9 of 17
[+] Feedback
CY7C1041CV33 Automotive
Switching Waveforms
(continued)
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA IO
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All Bits
Active (ICC)
L
X
L
I/O0 – I/O7
I/O8 – I/O15
Mode
Power
L
H
Data Out
High Z
Read – Lower Bits Only
Active (ICC)
H
L
High Z
Data Out
Read – Upper Bits Only
Active (ICC)
L
L
Data In
Data In
Write – All Bits
Active (ICC)
L
H
Data In
High Z
Write – Lower Bits Only
Active (ICC)
H
L
High Z
Data In
Write – Upper Bits Only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document Number: 001-67307 Rev. **
Page 10 of 17
[+] Feedback
CY7C1041CV33 Automotive
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns)
10
12
20
Ordering Code
CY7C1041CV33-10BAXA
Package
Diagram
Package Type
51-85106 48-ball FBGA (Pb-free)
CY7C1041CV33-10ZSXA
51-85087 44-pin TSOP II (Pb-free)
CY7C1041CV33-12BAXE
51-85106 48-ball FBGA (Pb-free)
CY7C1041CV33-12ZSXE
51-85087 44-pin TSOP II (Pb-free)
CY7C1041CV33-20ZSXA
51-85087 44-pin TSOP II (Pb-free)
CY7C1041CV33-20VXE
44-pin (400-mil) Molded SOJ (Pb-free)
CY7C1041CV33-20ZSXE
44-pin TSOP II (Pb-free)
Operating
Range
Automotive-A
Automotive-E
Automotive-A
Automotive-E
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY 7C
1
04
1
C V33 - XX XX X
X
Temperature Range: X = A or E
A = Automotive; E = Automotive Extended
X = Pb-free; X Absent = Leaded
Package Type: XX = BA or ZS or V
BA = 48-ball FBGA
ZS = 44-pin TSOP II
V = 44-pin (400-mil) Molded SOJ
Speed Grade: XX = 10 ns or 12 ns or 20 ns
V33 = 3.0 V to 3.6 V
Process Technology:C  150 nm
Data width: × 16-bits
4-Mbit density
Fast Asynchronous SRAM
Marketing Code: 7C = SRAMs
Company ID: CY = Cypress
Document Number: 001-67307 Rev. **
Page 11 of 17
[+] Feedback
CY7C1041CV33 Automotive
Package Diagrams
Figure 9. 44-pin (400 Mil) Molded SOJ, 51-85082
51-85082 *C
Document Number: 001-67307 Rev. **
Page 12 of 17
[+] Feedback
CY7C1041CV33 Automotive
Package Diagrams
(continued)
Figure 10. 44-pin Thin Small Outline Package Type II, 51-85087
51-85087 *C
Document Number: 001-67307 Rev. **
Page 13 of 17
[+] Feedback
CY7C1041CV33 Automotive
Package Diagrams
(continued)
Figure 11. 48-ball FBGA (7 × 8.5 × 1.2 mm), 51-85106
51-85106 *F
Document Number: 001-67307 Rev. **
Page 14 of 17
[+] Feedback
CY7C1041CV33 Automotive
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CE
Chip Enable
CMOS
complementary metal oxide semiconductor

ohms
FBGA
fine-pitch ball grid array
ns
nano seconds
I/O
input/output
V
Volts
OE
Output Enable
µs
micro seconds
PLL
phase locked loop
µA
micro Amperes
SOJ
Small Outline J-lead
mA
milli Amperes
SRAM
static random access memory
mm
milli meter
TSOP
thin small outline package
ms
milli seconds
TTL
transistor-transistor logic
MHz
Mega Hertz
WE
Write Enable
pF
pico Farad
%
percent
mW
milli Watts
W
Watts
°C
degree Celcius
Document Number: 001-67307 Rev. **
Symbol
Unit of Measure
Page 15 of 17
[+] Feedback
CY7C1041CV33 Automotive
Document History Page
Document Title: CY7C1041CV33 Automotive, 4-Mbit (256 K × 16) Static RAM
Document Number: 001-67307
REV.
**
ECN NO. Issue Date
3187164
03/03/2011
Orig. of
Change
PRAS
Document Number: 001-67307 Rev. **
Description of Change
Separation of the automotive datasheet from CY7C1041CV33 spec no. 38-05134
Rev. *K. Further rev of 38-05134 would include only industrial / commercial parts.
Page 16 of 17
[+] Feedback
CY7C1041CV33 Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-67307 Rev. **
Revised March 11, 2011
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
Similar pages