MCP3201
2.7V 12-Bit A/D Converter with SPI® Serial Interface
FEATURES
PACKAGE TYPES
•
•
•
•
•
•
•
•
•
•
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3201-B)
±2 LSB max INL (MCP3201-C)
On-chip sample and hold
SPI® serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at VDD = 5V
50ksps max. sampling rate at VDD = 2.7V
Low power CMOS technology
- 500nA typical standby current, 2µA max.
- 400µA max. active current at 5V
• Industrial temp range: -40°C to +85°C
• 8-pin PDIP, SOIC and TSSOP packages
PDIP
1
IN+
2
IN–
3
VSS
4
MCP3201
VREF
8
VDD
7
CLK
6
DOUT
5
CS/SHDN
SOIC, TSSOP
1
IN+
2
IN–
3
4
VSS
MCP3201
VREF
8
VDD
7
6
5
CLK
DOUT
CS/SHDN
APPLICATIONS
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
VSS
DESCRIPTION
The Microchip Technology Inc. MCP3201 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The
device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at ±1 LSB, and
Integral Nonlinearity (INL) is offered in ±1 LSB
(MCP3201-B) and ±2 LSB (MCP3201-C) versions.
Communication with the device is done using a simple
serial interface compatible with the SPI protocol. The
device is capable of sample rates of up to 100ksps at a
clock rate of 1.6MHz. The MCP3201 operates over a
broad voltage range (2.7V - 5.5V). Low current design
permits operation with typical standby and active currents of only 500nA and 300µA, respectively. The
device is offered in 8-pin PDIP, TSSOP and 150mil
SOIC packages.
1999 Microchip Technology Inc.
DAC
Comparator
IN+
IN-
Preliminary
12-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
CLK
Shift
Register
DOUT
DS21290B-page 1
MCP3201
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
PIN FUNCTION TABLE
NAME
FUNCTION
+2.7V to 5.5V Power Supply
Ground
Positive Analog Input
Negative Analog Input
Serial Clock
Serial Data Out
Chip select/Shutdown Input
Reference Voltage Input
VDD
VSS
IN+
INCLK
DOUT
CS/SHDN
VREF
VDD.........................................................................7.0V
All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps
and fCLK = 16*fSAMPLE unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNITS
12
clock
cycles
CONDITIONS
Conversion Rate
Conversion Time
tCONV
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
1.5
clock
cycles
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
INL
±0.75
±1
±1
±2
LSB
LSB
MCP3201-B
MCP3201-C
Differential Nonlinearity
DNL
±0.5
±1
LSB
No missing codes over temperature
Offset Error
±1.25
±3
LSB
Gain Error
±1.25
±5
LSB
Dynamic Performance
Total Harmonic Distortion
-82
dB
VIN = 0.1V to 4.9V@1kHz
Signal to Noise and Distortion
(SINAD)
72
dB
VIN = 0.1V to 4.9V@1kHz
Spurious Free Dynamic Range
86
dB
VIN = 0.1V to 4.9V@1kHz
VDD
V
Note 2
150
3
µA
µA
CS = VDD = 5V
Reference Input
Voltage Range
0.25
Current Drain
100
.001
Analog Inputs
Input Voltage Range (IN+)
IN-
VREF+IN-
V
Input Voltage Range (IN-)
VSS-100
VSS+100
mV
±1
µA
Leakage Current
0.001
Switch Resistance
RSS
1K
Ω
See Figure 4-1
Sample Capacitor
CSAMPLE
20
pF
See Figure 4-1
DS21290B-page 2
Preliminary
1999 Microchip Technology Inc.
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100ksps
and fCLK = 16*fSAMPLE unless otherwise noted.
PARAMETER
SYMBOL
MIN.
TYP.
High Level Input Voltage
VIH
0.7 VDD
Low Level Input Voltage
VIL
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
MAX.
UNITS
CONDITIONS
Digital Input/Output
Data Coding Format
Straight Binary
V
0.3 VDD
4.1
V
V
IOH = -1mA, VDD = 4.5V
0.4
V
IOL = 1mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
µA
VOUT = VSS or VDD
CIN, COUT
10
pF
VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Clock Frequency
fCLK
1.6
0.8
MHz
MHz
Clock High Time
tHI
312
ns
Clock Low Time
tLO
312
ns
tSUCS
100
ns
Pin Capacitance (all
inputs/outputs)
Timing Parameters
CS Fall To First Rising CLK
Edge
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
CLK Fall To Output Data Valid
tDO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
100
ns
See Test Circuits, Figure 1-2
(Note 1)
CS Disable Time
tCSH
625
ns
DOUT Rise Time
tR
100
ns
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
100
ns
See Test Circuits, Figure 1-2
(Note 1)
5.5
V
Power Requirements
2.7
Operating Voltage
VDD
Operating Current
IDD
300
210
400
µA
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
0.5
2
µA
CS = VDD = 5.0V
Note 1: This parameter is guaranteed by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 3
MCP3201
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
tDO
tDIS
tR
HI-Z
DOUT
FIGURE 1-1:
NULL BIT
tF
HI-Z
LSB
MSB OUT
Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3K
Test Point
DOUT
3K
tDIS Waveform 2
VDD/2
tEN Waveform
DOUT
100pF
CL = 100pF
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
Voltage Waveforms for tEN
CS
tF
tR
tDIS Waveform 1
VSS
1
2
3
4
CLK
B11
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
VIH
DOUT
Waveform 1*
90%
TDIS
DOUT
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
DS21290B-page 4
Preliminary
1999 Microchip Technology Inc.
MCP3201
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
1.5
Positive INL
INL (LSB)
INL (LSB)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Negative INL
V DD = V REF = 2.7V
1.0
0.5
Positive INL
0.0
-0.5
-1.0
Negative INL
-1.5
-2.0
0
25
50
75
100
125
0
150
20
40
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
2.0
1.5
1.5
Positive INL
INL (LSB)
INL (LSB)
100
VDD = 2.7V
F SAMPLE = 50ksps
Positive INL
1.0
1.0
0.5
0.0
Negative INL
0.5
0.0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
Negative INL
-2.0
0
1
2
3
4
5
0.0
0.5
VREF (V)
FIGURE 2-2:
1.0
1.5
2.0
2.5
3.0
VREF (V)
FIGURE 2-5:
(VDD = 2.7V).
Integral Nonlinearity (INL) vs. VREF.
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
INL (LSB)
INL (LSB)
80
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample
Rate (VDD = 2.7V).
2.0
-0.5
60
Sample Rate (ksps)
0.2
0.0
-0.2
Integral Nonlinearity (INL) vs. VREF
VDD = VREF = 2.7V
FSAMPLE = 50ksps
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
0
512 1024 1536 2048 2560 3072 3584 4096
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code
(Representative Part).
1999 Microchip Technology Inc.
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code
(Representative Part, VDD = 2.7V).
Preliminary
DS21290B-page 5
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
1.0
1.0
0.6
0.6
0.4
0.4
0.2
0.0
Negative INL
-0.2
VDD = VREF = 2.7V
0.8
Positive INL
INL (LSB)
INL (LSB)
0.8
F SAMPLE = 50ksps
Positive INL
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
0
Temperature (°C)
Integral
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Nonlinearity
(INL)
vs.
50
FIGURE 2-10: Integral
Nonlinearity
Temperature (VDD = 2.7V).
75
100
(INL)
vs.
2.0
V DD = V REF = 2.7V
1.5
1.0
DNL (LSB)
DNL (LSB)
FIGURE 2-7:
Temperature.
25
Temperature (°C)
Positive DNL
Negative DNL
Positive DNL
0.5
0.0
-0.5
Negative DNL
-1.0
-1.5
-2.0
0
25
50
75
100
125
150
0
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs.
Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs.
Sample Rate (VDD = 2.7V).
3.0
3.0
VDD = 2.7V
2.0
1.0
DNL (LSB)
DNL (LSB)
2.0
Positive DNL
0.0
Negative DNL
-1.0
FSAMPLE = 50ksps
Positive DNL
1.0
0.0
Negative DNL
-1.0
-2.0
-3.0
-2.0
0
1
2
3
4
0.0
5
FIGURE 2-9:
VREF.
Differential Nonlinearity (DNL) vs.
DS21290B-page 6
0.5
1.0
1.5
2.0
2.5
3.0
VREF(V)
VREF (V)
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF
(VDD = 2.7V).
Preliminary
1999 Microchip Technology Inc.
MCP3201
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
0.2
0.0
-0.2
VDD = VREF = 2.7V
FSAMPLE = 50ksps
0.2
0.0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024 1536 2048 2560 3072 3584 4096
0
512
1024 1536
Digital Code
1.0
1.0
0.8
0.8
0.6
0.6
Positive DNL
0.2
0.0
-0.2
Negative DNL
-0.4
VDD = VREF = 2.7V
FSAMPLE = 50ksps
Positive DNL
0.4
0.2
0.0
-0.2
Negative DNL
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs.
Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs.
Temperature (VDD = 2.7V).
20
5
18
Offset Error (LSB)
4
Gain Error (LSB)
4096
FIGURE 2-16: Differential Nonlinearity (DNL) vs.
Code (Representative Part, VDD = 2.7V).
DNL (LSB)
DNL (LSB)
FIGURE 2-13: Differential Nonlinearity (DNL) vs.
Code (Representative Part).
0.4
2048 2560 3072 3584
Digital Code
VDD = 2.7V
3
FSAMPLE = 50ksps
2
1
0
VDD = 5V
-1
FSAMPLE = 100ksps
16
VDD = 5V
14
FSAMPLE = 100ksps
12
10
8
VDD = 2.7V
6
F SAMPLE = 50ksps
4
2
-2
0
0
1
2
3
4
5
0
VREF(V)
FIGURE 2-15: Gain Error vs. VREF.
1999 Microchip Technology Inc.
1
2
3
4
5
VREF (V)
FIGURE 2-18: Offset Error vs. VREF.
Preliminary
DS21290B-page 7
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
1.0
1.8
0.6
VDD = VREF = 2.7V
0.4
FSAMPLE = 50ksps
Offset Error (LSB)
Gain Error (LSB)
0.8
0.2
0.0
-0.2
-0.4
-0.6
VDD = VREF = 5V
1.4
FSAMPLE = 100ksps
1.2
1.0
0.8
VDD = VREF = 2.7V
0.6
FSAMPLE = 50ksps
0.4
VDD = VREF = 5V
-0.8
1.6
0.2
FSAMPLE = 100ksps
-1.0
0.0
-50
-25
0
25
50
75
100
-50
-25
0
Temperature (°C)
75
100
FIGURE 2-22: Offset Error vs. Temperature.
100
100
90
VDD = VREF = 5V
80
FSAMPLE = 100ksps
60
VDD = VREF = 2.7V
40
FSAMPLE = 100ksps
80
70
50
VDD = VREF = 5V
90
SINAD (dB)
SNR (dB)
50
Temperature (°C)
FIGURE 2-19: Gain Error vs. Temperature.
FSAMPLE = 50ksps
30
70
60
50
VDD = VREF = 2.7V
40
FSAMPLE = 50ksps
30
20
20
10
10
0
0
1
10
100
1
10
Input Frequency (kHz)
100
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input
Frequency.
FIGURE 2-23:
Signal to Noise and Distortion
(SINAD) vs. Input Frequency.
0
80
-10
VDD = 5V
70
-20
-30
-40
VDD = VREF = 2.7V
-50
FSAMPLE = 50ksps
SINAD (dB)
THD (dB)
25
-60
-70
FSAMPLE = 100ksps
60
50
VDD = 2.7V
40
FSAMPLE = 50ksps
30
20
-80
VDD = VREF = 5V
-90
10
FSAMPLE = 100ksps
0
-100
1
10
-40
100
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
Input Frequency (kHz)
FIGURE 2-21: Total Harmonic Distortion (THD) vs.
Input Frequency.
DS21290B-page 8
-35
FIGURE 2-24:
Signal to Noise and Distortion
(SINAD) vs. Input Signal Level.
Preliminary
1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
VDD = 5V
11.5
ENOB (rms)
ENOB (rms)
12.0
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
9.75
9.50
9.25
9.00
VDD = VREF = 5V
FSAMPLE =100ksps
VDD = VREF = 2.7V
FSAMPLE = 50ksps
F SAMPLE = 100ksps
11.0
10.5
10.0
9.5
9.0
VDD = 2.7V
FSAMPLE = 50ksps
8.5
8.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
VREF (V)
Input Frequency (kHz)
FIGURE 2-25: Effective Number of Bits (ENOB) vs.
VREF.
FIGURE 2-28: Effective Number of Bits (ENOB) vs.
Input Frequency.
0
100
F SAMPLE = 100ksps
80
SFDR (dB)
Power Supply Rejection (dB)
VDD = VREF = 5V
90
70
60
50
VDD = VREF = 2.7V
40
F SAMPLE = 50ksps
30
20
10
0
1
10
-10
-20
-30
-40
-50
-60
-70
-80
100
1
10
Input Frequency (kHz)
FIGURE 2-26: Spurious Free
(SFDR) vs. Input Frequency.
Dynamic
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Range
F SAMPLE = 100ksps
F INPUT = 9.985kHz
4096 points
10000
20000
30000
40000
50000
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10000
VDD = VREF = 2.7V
FSAMPLE = 50ksps
FINPUT = 998.76Hz
4096 points
0
Frequency (Hz)
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input
(Representative Part).
1999 Microchip Technology Inc.
1000
FIGURE 2-29: Power Supply Rejection (PSR) vs.
Ripple Frequency.
VDD = VREF = 5V
0
100
Ripple Frequency (kHz)
Amplitude (dB)
Amplitude (dB)
100
FIGURE 2-30: Frequency Spectrum of 1kHz input
(Representative Part, VDD = 2.7V).
Preliminary
DS21290B-page 9
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
500
100
VREF = VDD
450
All points at FCLK = 1.6MHz except
80
at VREF = VDD = 2.5V, FCLK = 800kHz
350
at VREF = VDD = 2.5V, FCLK = 800kHz
70
IREF (µA)
IDD (µA)
VREF = VDD
90
All points at F CLK = 1.6MHz except
400
300
250
200
60
50
40
150
30
100
20
50
10
0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
5.0
5.5
6.0
FIGURE 2-34: IREF vs. VDD.
FIGURE 2-31: IDD vs. VDD.
100
400
90
350
VDD = VREF = 5V
80
VDD = VREF = 5V
300
70
250
IREF (µA)
IDD (µA)
4.5
VDD (V)
VDD (V)
200
VDD = VREF = 2.7V
150
60
50
40
VDD = VREF = 2.7V
30
100
20
50
10
0
0
10
100
1000
10
10000
100
1000
10000
Clock Frequency (kHz)
Clock Frequency (kHz)
FIGURE 2-35: IREF vs. Clock Frequency.
FIGURE 2-32: IDD vs. Clock Frequency.
100
400
350
VDD = VREF = 5V
90
VDD = VREF = 5V
FCLK = 1.6MHz
80
F CLK = 1.6MHz
300
70
IREF (µA)
IDD (µA)
4.0
250
200
VDD = VREF = 2.7V
150
F CLK = 800kHz
100
60
50
40
30
VDD = VREF = 2.7V
20
FCLK = 800kHz
10
50
0
0
-50
-25
0
25
50
75
-50
100
DS21290B-page 10
0
25
50
75
100
Temperature (°C)
Temperature (°C)
FIGURE 2-33: IDD vs. Temperature.
-25
FIGURE 2-36: IREF vs. Temperature.
Preliminary
1999 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 16*fSAMPLE,TA = 25°C
2.0
Analog Input Leakage (nA)
80
VREF = CS = VDD
70
IDDS (pA)
60
50
40
30
20
10
1.8
1.6
1.4
1.2
VDD = VREF = 5V
1.0
FCLK = 1.6Mhz
0.8
0.6
0.4
0.2
0.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
6.0
-25
0
25
50
75
100
Temperature (°C)
VDD (V)
FIGURE 2-39: Analog Input Leakage Current vs.
Temperature.
FIGURE 2-37: IDDS vs. VDD.
100.00
VDD = VREF = CS = 5V
IDDS (nA)
10.00
1.00
0.10
0.01
-50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38: IDDS vs. Temperature.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 11
MCP3201
3.0
PIN DESCRIPTIONS
3.1
IN+
Positive analog input. This input can vary from IN- to
VREF + IN-.
3.2
IN-
Negative analog input. This input can vary ±100mV
from VSS.
3.3
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a conversion and put the device in low power standby when
pulled high. The CS/SHDN pin must be pulled high
between conversions.
3.4
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 for constraints on clock speed.
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
4.0
DEVICE OPERATION
The MCP3201 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit
digital output code. Conversion rates of 100ksps are
possible on the MCP3201. See Section 6.2 for information on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
4.1
Analog Inputs
The MCP3201 provides a single pseudo-differential
input. The IN+ input can range from IN- to VREF
(VREF +IN-). The IN- input is limited to ±100mV from the
VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the
IN+ and IN- inputs.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to
charge the capacitor (CSAMPLE). Consequently, a larger
source impedance increases the offset, gain, and integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amplifier such as the MCP601, which has a closed loop output impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more
than 1 LSB below VSS, then the voltage level at the IN+
input will have to go below VSS to see the 000h output
code. Conversely, if IN- is more than 1 LSB above Vss,
then the FFFh code will not be seen unless the IN+
input level goes above VREF level.
4.2
Reference Input
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
LSB Size = VREF
4096
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the analog input signal and the reference input as shown
below.
Digital Output Code = 4096 * VIN
VREF
where:
VIN = analog input voltage = V(IN+) - V(IN-)
VREF = reference voltage
When using an external voltage reference device, the
system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a
direct effect on the operation of the A/D Converter.
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough time
to acquire a 12-bit accurate voltage level during the
1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
DS21290B-page 12
Preliminary
1999 Microchip Technology Inc.
MCP3201
VDD
RS
Sampling
Switch
VT = 0.6V
CHx
CPIN
7pF
VA
VT = 0.6V
SS
ILEAKAGE
±1nA
RSS = 1kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
Legend
VA = Signal Source
RS = Source Impedance
CHx = Input Channel Pad
CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin
due to various junctions
SS = Sampling Switch
RSS = Sampling Switch Resistor
CSAMPLE = Sample/Hold Capacitance
FIGURE 4-1:
Analog Input Model.
Clock Frequency (MHz)
1.8
1.6
VDD = VREF = 5V
1.4
1.2
1.0
0.8
0.6
VDD = VREF = 2.7V
0.4
0.2
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input
Resistance (RS) to maintain less than a 0.1 LSB
deviation in INL from nominal conditions.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 13
MCP3201
5.0
SERIAL COMMUNICATIONS
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 12 data bits have been transmitted and the
device continues to receive clocks while the CS is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
Communication with the device is done using a standard SPI-compatible serial interface. Initiating communication with the MCP3201 begins with the CS going
low. If the device was powered up with the CS pin low,
it must be brought high and back low to initiate communication. The device will begin to sample the analog
input on the first rising edge after CS goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 12 clocks will output the result of the convertCYC
tCSH
CS
Power
Down
tSUCS
CLK
HI-Z
DOUT
tDATA**
tCONV
tSAMPLE
NULL
BIT
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
HI-Z
B0*
NULL
BIT
B11 B10 B9
B8
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with MCP3201 using MSB first Format.
tCYC
tCSH
CS
tSUCS
Power Down
CLK
tSAMPLE
DOUT
tDATA**
tCONV
HI-Z
NULL
BIT B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11*
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3201 using LSB first Format.
DS21290B-page 14
Preliminary
1999 Microchip Technology Inc.
MCP3201
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3201 with
Microcontroller SPI Ports
(the output is at high impedance for the first two clocks),
the null bit and the highest order five bits of the conversion. After the second eight clocks have been sent to
the device, the MCU receive register will contain the
lowest order seven bits and the B1 bit repeated as the
A/D Converter has begun to shift out LSB first data with
the extra clock. Typical procedure would then call for
the lower order byte of data to be shifted right by one bit
to remove the extra B1 bit. The B7 bit is then transferred from the high order byte to the lower order byte,
and then the higher order byte is shifted one bit to the
right as well. Easier manipulation of the converted data
can be obtained by using this method.
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3201 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with the
MCP3201. Figure 6-1 depicts the operation shown in
SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the A/D Converter
on the falling edge of the third clock pulse. After the first
eight clocks have been sent to the device, the microcontroller’s receive buffer will contain two unknown bits
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D Converter
on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of
A/D Converter on falling edges
DOUT
HI-Z
NULL
B11
BIT
B10
B9
B8
B6
B7
B5
B4
B3
B2
B1
B0
B1
B2
HI-Z
LSB first data begins
to come out
?
?
0
B11
B10
B9
B8
B7
B6
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-1:
B5
B4
B3
B2
B1
B1
B0
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter
on rising edges of SCLK
CLK
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
Data is clocked out of
A/D Converter on falling edges
DOUT
HI-Z
NULL
BIT B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
HI-Z
LSB first data begins
to come out
?
?
0
B11
B10
B9
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-2:
B6
B5
B4
B3
B2
B1
B0
B1
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 15
MCP3201
6.2
Maintaining Minimum Clock Speed
6.4
When the MCP3201 initiates the sample period,
charge is stored on the sample capacitor. When the
sample period is complete, the device converts one bit
for each clock that is received. It is important for the
user to note that a slow clock rate will allow charge to
bleed off the sample cap while the conversion is taking
place. At 85°C (worst case condition), the part will
maintain proper charge on the sample capacitor for at
least 1.2ms after the sample period has ended. This
means that the time between the end of the sample
period and the time that all 12 data bits have been
clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criteria may
induce linearity errors into the conversion outside the
rated specifications. It should be noted that during the
entire conversion cycle, the A/D Converter does not
require a constant clock speed or duty cycle, as long as
all timing specifications are met.
6.3
Buffering/Filtering the Analog Inputs
Layout Considerations
When laying out a printed circuit board for use with analog components, care should be taken to reduce noise
wherever possible. A bypass capacitor should always
be used with this device and should be placed as close
as possible to the device pin. A bypass capacitor value
of 1µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high
frequency signals (such as clock lines) as far as possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered or inaccurate conversion results may occur. See Figure 4-2. It is
also recommended that a filter be used to eliminate any
signals that may be aliased back into the conversion
results. This is illustrated in Figure 6-3 where an op
amp is used to drive the analog input of the MCP3201.
This amplifier provides a low impedance source for the
converter input and a low pass filter, which eliminates
unwanted high frequency noise.
VDD
Connection
Device 4
Low pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab™ software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
VDD
10µF
4.096V
Reference
0.1µF
ADI
REF198
1µF
Tant. 0.1µF
VREF
Device 1
Device 3
Device 2
FIGURE 6-4: VDD traces arranged in a ‘Star’
configuration in order to reduce errors caused by
current return paths.
1µF
IN+
MCP3201
R1
VIN
C1
MCP601
IN-
+
-
R2
C2
R3
R4
FIGURE 6-3: The MCP601 Operational Amplifier is
used to implement a 2nd order anti-aliasing filter for
the signal being converted by the MCP3201.
DS21290B-page 16
FilterLab is a trademark of Microchip Technology Inc. in
the U.S.A and other countries. All rights reserved.
Preliminary
1999 Microchip Technology Inc.
MCP3201
MCP3201 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
MCP3201 - G
T
/P
Package:
Temperature
Range:
Performance
Grade:
Device:
P = PDIP (8 lead)
SN = SOIC (150 mil Body), 8 lead
ST = TSSOP, 8 lead (C Grade only)
I = –40°C to +85°C
B = ±1 LSB INL (TSSOP not available in this grade)
C = ±2 LSB INL
MCP3201 = 12-Bit Serial A/D Converter
MCP3201T = 12-Bit Serial A/D Converter on tape and reel
(SOIC and TSSOP packages only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999, (480) 786-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 17
MCP3201
NOTES:
DS21290B-page 18
Preliminary
1999 Microchip Technology Inc.
MCP3201
NOTES:
1999 Microchip Technology Inc.
Preliminary
DS21290B-page 19
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design and wafer fabrication facilities in
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Company’s quality system processes and
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All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
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1999 Microchip Technology Inc.