IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16823 DESCRIPTION: FEATURES: This 18-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVCH16823 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16823 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in TSSOP package DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 OE 1 CLR 1 CLKEN 2 2 OE 1 2 CLR 55 CE 2 CLKEN 27 28 30 R 1 CLK 1D 1 56 C1 54 CE R 3 2 CLK 1Q 1 2D 1 D1 TO 8 OTHER CHANNELS 29 42 15 C1 2Q 1 D1 TO 8 OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4237/2 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V 1CLR 1 56 1CLK VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V 1OE 2 55 1CLKEN TSTG Storage Temperature –65 to +150 °C 1Q1 3 54 1D1 IOUT DC Output Current –50 to +50 mA GND IIK Continuous Clamp Current, VI < 0 or VI > VCC ±50 mA IOK Continuous Clamp Current, VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA GND 4 53 1Q2 5 52 1D2 1Q3 6 51 1D3 VCC 7 50 VCC 1Q4 8 49 1D4 1Q5 9 48 1D5 1Q6 10 47 1D6 GND 11 46 GND 1Q7 12 45 1D7 1Q8 13 44 1D8 1Q9 14 43 1D9 2Q1 15 42 2D1 2Q2 16 41 2D2 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) 2Q3 17 40 2D3 GND 18 39 GND 2Q4 19 38 2D4 CIN Input Capacitance VIN = 0V 5 7 pF 2Q5 20 37 2D5 COUT Output Capacitance VOUT = 0V 7 9 pF 2Q6 21 36 2D6 COUT I/O Port Capacitance VIN = 0V 7 9 pF VCC 22 35 VCC 2Q7 23 34 2D7 2Q8 24 33 2D8 GND 25 32 GND 2Q9 26 31 2D9 2OE 27 30 2CLKEN 2CLR 28 29 2CLK Symbol Data Inputs(1) xCLK Clock Input Clock Enable Inputs xQx 3-State Outputs xOE 3-State Output Enable Inputs xCLR Clear Inputs Typ. Inputs Description xDx Conditions Max. Unit FUNCTION TABLE (EACH 9-BIT FLIP-FLOP)(1) PIN DESCRIPTION Pin Names Parameter(1) NOTE: 1. As applicable to the device type. TSSOP TOP VIEW xCLKEN INDUSTRIAL TEMPERATURE RANGE Output xOE xCLR xCLKEN xCLK xDx xQx L L X X X L L H L ↑ H H L H L ↑ L L L H L L X Q0(2) L H H X X Q0(2) H X X X X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance ↑ = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. 2 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3 — µA µA IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Test Conditions(1) Parameter Output HIGH Voltage Min. Max. Unit VCC – 0.2 — V IOH = – 6mA 2 — IOH = – 12mA 1.7 — 2.2 — VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled 4 VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 27 30 pF 16 18 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter Min. fMAX tPLH Propagation Delay tPHL xCLK to xQx tPLH Propagation Delay tPHL xCLR to xQx tPZH Output Enable Time tPZL xOE to xQx tPHZ Output Disable Time tPLZ xOE to xQx tW Pulse Duration, xCLR LOW VCC = 2.7V Max. Min. 150 — 1 5.8 1 VCC = 3.3V ± 0.3V Max. Min. Max. Unit 150 — — 5.2 150 — MHz 1 4.5 ns 5.4 — 5.2 1.2 4.6 ns 1 6 — 5.7 1 4.8 ns 1.1 5.4 — 4.7 1.3 4.5 ns 3.3 — 3.3 — 3.3 — ns tW Pulse Duration, xCLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns tSU Set-up Time, xCLR inactive 0.7 — 0.7 — 0.8 — ns tSU Set-up Time, data LOW before xCLK↑ 1.4 — 1.6 — 1.3 — ns tSU Set-up Time, data HIGH before xCLK↑ 1.1 — 1.1 — 1 — ns tSU Set-up Time, xCLKEN LOW before xCLK↑ 1.8 — 1.9 — 1.5 — ns tH Hold Time, data LOW after xCLK↑ 0.4 — 0.5 — 0.5 — ns tH Hold Time, data HIGH after xCLK↑ 0.7 — 0.1 — 0.8 — ns tH Hold Time, xCLKEN LOW after CLK↑ 0.2 — 0.3 — 0.4 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2 Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. DATA INPUT Test Switch Open Drain Disable Low Enable Low VLOAD ASYNCHRONOUS CONTROL Disable High Enable High GND SYNCHRONOUS CONTROL All Other Tests Open VOH VHZ 0V VT 0V tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V tH tREM tSU tH Set-up, Hold, and Release Times VIH VT 0V VOH VT VOL tSK (x) LOW-HIGH-LOW PULSE OUTPUT 2 VT tW VOH VT VOL tPLH2 tPHZ ALVC Link tPHL1 tSK (x) VLOAD/2 VLZ VOL Enable and Disable Times TIMING INPUT OUTPUT 1 VLOAD/2 VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION tPLH1 tPLZ VIH VT 0V ALVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. INPUT ALVC Link DISABLE tPZL CL Test Circuit for All Outputs VIH VT 0V CONTROL INPUT D.U.T. RT tPHL ENABLE VOUT Pulse Generator tPLH Propagation Delay GND 500Ω tPHL OPPOSITE PHASE INPUT TRANSITION Open VIN tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link Output Skew - tSK(X) NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH16823 3.3V CMOS 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ALVC X IDT XX Bus-Hold Temp. Range XXX Family XX XXX Device Type Package PA Thin Shrink Small Outline Package 823 18-Bit Bus-Interface Flip-Flop with 3-State Outputs 16 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Double-Density, ±24mA H Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459