Altera EVB-EN5394QI 9a powersoc voltage mode synchronous buck pwm dc-dc converter with integrated inductor Datasheet

Enpirion® Power Datasheet
EN5394QI 9A PowerSoC
Voltage Mode Synchronous
Buck PWM DC-DC Converter
With Integrated Inductor
Description
Typical Application Circuit
The EN5394QI is a Power Supply on a Chip
(PwrSoC) DC to DC converter with integrated
inductor, PWM controller, MOSFETS, and
compensation providing the smallest possible
solution size in a 68 pin QFN module. The
switching frequency can be synchronized to an
external clock or other EN5394QIs with the
added capability of phasing multiple EN5394QIs
as desired. Other features include precision
ENABLE threshold, pre-bias monotonic start-up,
margining, and parallel operation.
EN5394QI is specifically designed to meet the
precise voltage and fast transient requirements
of
present
and
future
high-performance
applications such as set-top boxes/HD DVRs,
LAN/SAN adapter cards, audio/video equipment,
optical networking, multi-function printers, test
and
measurement,
embedded
computing,
storage,
and
servers.
Advanced
circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver highquality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
very few external components.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity
by offering greatly simplified board design, layout
and manufacturing requirements.
All Altera Enpirion products are RoHS compliant
and
lead-free
manufacturing
environment
compatible.
VIN
47µF
VOUT
VOUT
AVIN
2x47µF
ENABLE
VFB
PGND
SS
15nF
OCP_ADJ
PGND
AGND
Figure 1: Typical Application Schematic
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated Inductor, MOSFETS, Controller in
a 8 x 11 x 1.85mm package
Wide input voltage range of 2.375V to 6.6V.
> 30W continuous output power.
High efficiency, up to 93%.
Output voltage margining
Monotonic output voltage ramp during startup with pre-biased loads.
Precision Enable pin for accurate sequencing
of power converters and Power OK signal.
Programmable soft-start time.
Soft Shutdown.
4 MHz operating frequency with ability to
synchronize to an external system clock or
other EN5394’s.
Programmable phase delays between
synchronized units to allow reduction of
input ripple.
Master/slave configuration for paralleling
multiple EN5394’s for greater power output.
Under Voltage Lockout, Over-current, Short
Circuit, and Thermal Protection
RoHS compliant, MSL level 3, 260C reflow.
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Applications
•
•
•
•
•
Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V, 6V rails
Computing, broadband, networking,
LAN/WAN, optical, test & measurement
A/V, high density cards, storage, DSL, STB,
DVR, DTV, Industrial PC
Beat frequency sensitive applications
•
Applications requiring monotonic start-up with
pre-bias
Ripple voltage sensitive applications
Noise sensitive applications
•
•
Ordering Information
Part Number
EN5394QI
EVB-EN5394QI
Temp Rating
(°C)
Package
-40 to +85
68-pin QFN T&R
QFN Evaluation Board
S_DELAY
SS
OCP_ADJ
EAOUT
VFB
AGND
POK
AVIN
ENABLE
EN_PB
M/S
58
57
56
55
54
53
52
51
50
MAR2
59
VSENSE
62
MAR1
PGND
64
63
61
PGND
60
PGND
65
PGND
67
66
PGND
68
Pin Configuration
49
S_IN
48
S_OUT
47
NC
4
46
NC
VOUT
5
45
NC
VOUT
6
44
NC
VOUT
7
43
PVIN
VOUT
8
42
PVIN
PGND
1
PGND
2
PGND
3
PGND
Thermal Pads
70
PGND
69
PGND
EN5394QI
29
30
31
32
PGND
PGND
PGND
PGND
PGND
34
28
PGND
PVIN
27
NC(SW)
33
26
PGND
25
NC(SW)
PVIN
24
35
NC
15
NC
PVIN
NC
23
36
22
14
NC
PVIN
NC
21
37
NC
PVIN
13
NC
38
VOUT
20
12
19
PVIN
VOUT
NC
39
18
11
NC
PVIN
VOUT
NC
PVIN
40
17
41
10
16
9
VOUT
NC
VOUT
Figure 2: Pinout Diagram (Top View). All perimeter pins must be soldered to PCB.
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Pin Descriptions
PIN
1-4,
27-33,
64-68
5-13
14-24,
44-47
25-26
34-43
48
49
50
51
52
53
54
55
56
57
58
59
60
61-62
63
69, 70
NAME
PGND
FUNCTION
Input/Output power ground. Connect these pins to the ground electrode of the input
and output filter capacitors. See VOUT and PVIN descriptions for more details.
Regulated converter output. Connect to the load, and place output filter capacitor(s)
between these pins and PGND pins 1-4 and 64-68.
NO CONNECT: These pins must be soldered to PCB but not be electrically connected
to each other or to any external signal, voltage, or ground. These pins may be
NC
connected internally. Failure to follow this guideline may result in device damage.
NO CONNECT: These pins are internally connected to the common switching node of
the internal MOSFETs. They must be soldered to PCB but not be electrically
NC(SW)
connected to any external signal, ground, or voltage. Failure to follow this guideline
may result in device damage.
Input power supply. Connect to input power supply, place input filter capacitor(s)
PVIN
between these pins and PGND pins 27-33.
Clock Output. Depending on the mode, either a clock signal or the PWM signal is
S_OUT
output on this pin. These signals are delayed by a time that is related to the resistor
connected between S_DELAY and AGND. Leave this pin floating if not needed.
Clock Input. Depending on the mode, this pin accepts either an input clock to
S_IN
synchronize the internal switching frequency or the S_OUT signal from another
EN5394QI. Leave this pin floating if it is not used.
This is a Ternary Input. Floating the pin disables parallel operation. A low level
M/S
configures the device as Master and a High level configures the device as a slave.
This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support
EN_PB
monotonic start-up under a pre-biased load. There is a 150kΩ pull-down on this pin.
This is the Device Enable pin. A high level enables the device while a low level
ENABLE
disables the device.
AVIN
Input power supply for the controller. Needs to be connected to VIN at a quiet point.
Power OK is an open drain transistor for power system state indication. POK is a
logic high when VOUT is with -10% to +20% of VOUT nominal. Being an open drain
POK
output allows several devices to be wired to logically AND the function. Size pull-up
resistor to limit current to 4mA when POK is low.
AGND
Ground return for the controller. Needs to be connected to a quiet ground.
External Feedback input. The feedback loop is closed through this pin. A voltage
VFB
divider at VOUT is used to set the output voltage. The mid-point of the divider is
connected to VFB. The control loop regulates to make the VFB node voltage 0.6V.
EAOUT
Optional Error Amplifier output. Allows for customization of the control loop.
OCP_ADJ This pin should be pulled to GND for proper operation of the OCP circuit.
A soft-start capacitor is connected between this pin to AGND. The value of the
SS
capacitor controls the soft-start interval and startup time.
A resistor is connected between this pin and AGND. The value of the resistor controls
S_DELAY
the delay in S_OUT. This pin can be left floating if the S_OUT function is not used.
These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float
condition. 7 of the 9 states are used to modulate the output voltage by 0%, ±2.5%,
MAR1,
±5% or ±10%. The 8th state is used to by-pass the delay in S_OUT. See Functional
MAR2
Description section.
VSENSE This pin senses VOUT when the device is placed in the Back-feed (or Pre-bias) mode.
Device thermal pads to be connected to the system gnd plane. See Layout
PGND
Recommendations section.
VOUT
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Voltages on PVIN, AVIN, VOUT
Voltages on VSENSE, ENABLE, EN_PB, POK,
Voltages on VFB, EAOUT, SS, S_IN, S_OUT, OCP_ADJ
Voltages on MAR1, MAR2, M/S
Storage Temperature Range
Maximum Operating Junction Temperature
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
MIN
MAX
UNITS
VIN
-0.5
-0.5
-0.5
-0.5
-65
7.0
VIN + 0.3
2.7
3.6
150
150
260
2000
V
V
V
V
°C
°C
°C
V
TSTG
TJ-ABS MAX
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
VIN
2.375
6.6
V
Output Voltage Range
VOUT
0.60
VIN – VDO†
V
Output Current
ILOAD
0
9
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
†
VDO (drop-out voltage) is defined as (ILOAD x Dropout Resistance). Please see Electrical Characteristics table.
Thermal Characteristics
PARAMETER
SYMBOL
TYP
Thermal Resistance: Junction to Ambient (0 LFM)††
θJA
16
Thermal Resistance: Junction to Case
θJC
1
Thermal Shutdown Trip Point
TSD
+150
Thermal Shutdown Trip Point Hysteresis
TSDH
20
††
Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.
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UNITS
°C/W
°C/W
°C
°C
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Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
Input Voltage
Under Voltage Lock out
threshold
Shut-Down Supply
Current
SYMBOL
VIN
VUVLOR
VUVLOF
IS
Feedback Pin Voltage
VFB
Feedback Pin Input Leakage
Current 1
IFB
Line Regulation
Load Regulation
Temperature Regulation
∆VOUT_LINE
∆VOUT_LOAD
∆VOUT_TEMP
VOUT Rise Time
T RISE
Rise Time Accuracy1
Output Dropout
Voltage1
Resistance1
Maximum Continuous
Output Current2
Current Limit Threshold
ENABLE pin:
Disable Threshold
Enable Threshold
∆T RISE
IOUT_MAX_CONT
ENABLE Lock-out time
tENLO
ENABLE Pin Input
Current
Switching Frequency
External S_IN Clock
Frequency Lock Range
S_IN Threshold – Low
S_IN Threshold – High
S_OUT Threshold – Low
S_OUT Threshold – High
S_IN Duty Cycle for
External Synchronization1
S_IN Duty Cycle for
Parallel Operation1
Phase Delay vs. S_Delay
Resistor value
VDO
RDO
IOCP
VDISABLE
VENABLE
COMMENTS
TYP
2.375
MAX
UNITS
6.6
V
VIN Increasing
VIN Decreasing
2.2
2.1
V
ENABLE=0V
250
µA
2.375V ≤ VIN ≤ 6.6V,
ILOAD = 1A; T A = 25°C
0.588
0.600
-5
2.375V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 6A
-40°C ≤ TEMP ≤ 85°C
Measured from when VIN ≥ VUVLOR
& ENABLE pin crosses logic high
threshold. (4.7nF ≤ CSS ≤ 100nF)
4.7nF ≤ CSS ≤ 100nF
0.612
V
5
nA
0.035
−0.04
0.001
%/V
%/A
%/°C
CSS x
65kΩ
-25
VINMIN – VOUT at Full Load
Input to Output Resistance
360
40
+25
%
720
80
mV
mΩ
9
OCP_ADJ pulled low
2.375V ≤ VIN ≤ 6.6V
ENABLE pin logic low
ENABLE pin logic high
Time for device to re-enable after
a falling edge on ENABLE pin
A
14
A
1.0
1.30
1.00
V
2
ms
IENABLE
VIN = 5.5V
50
µA
F SWITCH
Free Running frequency
Frequency Range of S_IN
Input Clock
S_IN Clock low level
S_IN Clock high level
S_OUT Clock low level
S_OUT Clock high level
4
MHz
F PLL_LOCK
VS_IN_LO
VS_IN_HI
VS_OUT_LO
VS_OUT_HI
3.6
4.4
MHz
1.8
0.8
2.5
0.5
V
V
V
V
1.8
SYDC_SY NC
M/S Pin Float or Low
20
80
%
SYDC_PWM
M/S Pin High
10
90
%
ΦDEL
Delay in ns / kΩ
Delay in phase angle / kΩ @ 4MHz switching frequency
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Phase Delay between
S_IN and S_OUT 1
ΦDEL
Phase Delay between
S_IN and S_OUT 1
Phase Delay Accuracy1
ΦDEL
Pre-Bias Level
VPB
Non-Monotonicity
POK Lower Threshold as
a percent of VOUT3
POK Upper Threshold as
a percent of VOUT3
POK Falling Edge
Deglitch Delay4
POK Output Low Voltage
POK Output High Voltage
Ternary Pin Logic Low5
Ternary Pin Logic High5
Ternary Pin Input Current
(see Figure 5)5
Binary Input Logic Low
Threshold6
Binary Input Logic High
Threshold6
VPB_NM
POKLT
POKUT
Phase delay programmable via
resistor connected from S_Delay
to AGND.
Delay By-Pass Mode
(MAR1 floating, MAR2 high)
Allowable Pre-Bias as a fraction
of programmed output voltage
(subject to a minimum of 300mV)
Allowable non monotonicity
VOUT rising
VOUT falling
VOUT rising
VOUT falling
VPOKL
VPOKH
VT-Low
With 4mA current sink into POK
2.375V ≤ VIN ≤ 6.6V
Tie pin to GND
VT-High
Pull up to VIN through an external
resistor REXT – see Figure 5.
ITERN
VIN = 2.375V, REXT = 3.32kΩ
VIN = 3.3V, REXT = 15kΩ
VIN = 5.0V, REXT = 24.9kΩ
VIN = 6.6V, REXT = 49.9kΩ
20
150
ns
10
ns
-20
20
%
20
85
%
50
92
90
120
115
mV
60
µs
%
%
0.4
VIN
0
see Input
Current
below
50
70
100
85
VB-Low
V
V
V
µA
0.8
VB-High
1.8
NOTES:
1. Parameter guaranteed by design.
2. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
3. POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the
90% level, there is a 256 clock cycle (~50us) delay before POK is de-asserted. The 90%, 92%, 115%, and 120%
levels are nominal values. Expect these thresholds to vary by ±3%.
4. On the falling edge of VOUT below 90% of programmed value, POK response is delayed for the duration of the
deglitch delay time. Any VOUT glitch shorter than the deglitch time is ignored.
5. M/S, MAR1, and MAR2 are ternary. Ternary pins have three logic levels: high, float, and low. These pins are only
meant to be strapped to VIN through an external resistor, strapped to GND, or left floating. Their state cannot be
changed while the device is on.
6. Binary input pins are EN_PB and OCP_ADJ.
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Typical Performance Characteristics
90
90
80
Efficiency (%)
Efficiency (%)
80
70
60
V IN = 3.3V
50
70
60
50
40
30
30
20
0
1
2
3
4
5
6
Load (Am ps)
7
8
0
9
1
2
3
4
5
6
7
8
9
Load (Amps)
Efficiency VIN = 3.3V
VOUT (From top to bottom) = 2.5, 1.8, 1.2, 1.0V
Efficiency VIN = 5.0V
VOUT (From top to bottom) = 3.3, 2.5, 1.8, 1.2, 1.0V
20 MHz BW limit
500 MHz BW
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Iout = 9A
CIN = 2 x 22µF/1206, COUT = 2 x 47µF/1206
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Iout = 9A
CIN = 2 x 22µF/1206, COUT = 2 x 47µF/1206
20 MHz BW limit
500 MHz BW
Output Ripple: VIN = 5.0V, VOUT = 1.2V, Iout = 9A
CIN = 2 x 22µF/1206, COUT = 2 x 47µF/1206
Output Ripple: VIN = 5.0V, VOUT = 1.2V, Iout = 9A
CIN = 2 x 22µF/1206, COUT = 2 x 47µF/1206
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Load Transient: VIN = 5.0V, VOUT = 1.2V
Ch.1: VOUT, Ch.4: ILOAD 0↔ 9A (slew rate ≥ 10A/µS)
CIN ≈ 50µF, COUT ≈ 100µF
RA = 150kΩ , CA = 33pF (see Figure 4)
Load Transient: VIN = 3.3V, VOUT = 1.2V
Ch.1: VOUT, Ch.4: ILOAD 0↔ 9A (slew rate ≥ 10A/µS)
CIN ≈ 50µF, COUT ≈ 100µF
RA = 100kΩ , CA = 56pF (see Figure 4)
Power Up/Down at No Load: VIN/VOUT = 5.0V/1.2V,
15nF soft-start capacitor,
Ch.1: ENABLE, Ch.2: VOUT, Ch.3; POK
Power Up/Down into 0.2Ω load: VIN/VOUT = 5.0V/1.2V,
15nF soft-start capacitor,
Ch.1: ENABLE, Ch.2: VOUT, Ch.3; POK
Delay (ns)
Delay vs. S_Delay Resistance
180
160
140
120
100
80
60
40
20
0
0
20
40
60
80
100
S_Delar R (kohm)
ENABLE Lockout Operation
Ch.1: ENABLE, Ch2: VOUT
Delay vs. S_Delay Resistance
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Block Diagram
S_OUT
M_S
PVIN
S_IN
To PLL
Digital I/O
UVLO
MAR1/2
Thermal Limit
Current Limit
P-Drive
Over Voltage
NC(SW)
VOUT
(-)
PWM
Comp
(+)
N-Drive
EAOUT
PGND
Compensation
Network
PLL / Sawtooth
Generator
(-)
VFB
Error
Amp
(+)
power
Good
Logic
ENABLE
SS
Reference
Voltage
selector
Soft Start
EN_PB
EAOUT
MAR1
POK
Bandgap
Reference
MAR2
Figure 3: System block diagram.
Functional Description
Synchronous Buck Converter
The EN5394QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal
input voltage range is 2.375-6.6V. The output
voltage is programmed using an external resistor
divider network. The feedback control loop is a
type III, voltage-mode, and the device uses a
low-noise PWM topology. Up to 9A of continuous
output current can be drawn from this converter.
The 4MHz operating frequency enables the use
of small-size input and output capacitors.
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The power supply has the following protection
features:
• Over-current protection with hiccup mode.
• Short Circuit protection.
• Thermal shutdown with hysteresis.
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Enable Operation
The ENABLE pin provides a means to start
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted
(high) the device will undergo a normal soft start.
A logic low will disable the converter. A logic low
will power down the device in a controlled
manner and the device is subsequently shut
down. The device will remain shut-down for the
duration of the ENABLE lockout time (see
Electrical Characteristics Table). If the ENABLE
signal is re-asserted during this time, the device
will power up with a normal soft-start at the end
of the ENABLE lockout time.
EMI frequency components.
Master / Slave Parallel Operation
Multiple EN5394QI devices may be connected in
parallel in a Master/Slave configuration to handle
load currents greater than device maximum
rating. The device is set in Master mode by
pulling the ternary M/S pin low or in Slave mode
by pulling M/S pin high to VIN through an external
resistor. When this pin is in Float state, parallel
operation is not possible. In master mode, the
internal PWM signal is output on the S_OUT pin.
This PWM signal from the Master can be fed to
one or more Slave devices at its S_IN input. The
Slave device acts like an extension of the power
FETs in the Master. As a practical matter,
paralleling more than 4 devices may be very
difficult from the view point of maintaining very
low impedance in VIN and VOUT lines.
The table below summarizes the different
configurations for the S_IN and S_OUT pins
depending on the condition of the M/S pin:
The Enable threshold is a precision Analog
voltage rather than a digital logic threshold.
Precision threshold along with choice of soft-start
capacitor helps to accurately sequence multiple
power supplies in a system.
High (Slave)
Low (Master)
S_IN input
should be:
S_OUT from
Master
External Sync input if
needed (NC for internal
clock)
S_OUT is
Same duty
equal to
cycle as
(subject to S_IN
S_DELAY):
Frequency Synchronization
The switching frequency of the DC/DC converter
can be phase-locked to an external clock source
to move unwanted beat frequencies out of band.
To avail this feature, the ternary input M/S pin
should be floating or pulled low. The internal
switching clock of the DC/DC converter can then
be phase locked to a clock signal applied to S_IN
pin. An activity detector recognizes the presence
of an external clock signal and automatically
phase-locks the internal oscillator to this external
clock. Phase-lock will occur as long as the input
clock frequency is within ±10% of the free
running frequency (see Electrical Characteristics
table). When no clock signal is present, the
device reverts to the free running frequency of
the internal oscillator. The external clock input
may be swept between 3.6 MHz and 4.4 MHz at
repetition rates of up to 10 kHz in order to reduce
When M/S
pin is:
S_IN or
internal
clock
Please contact Altera Power Applications support
for more information on Master / Slave operation.
Phase Delay
In all cases, S_OUT can be delayed with respect
to internal switching clock or the clock applied to
S_IN. Multiple EN5394QI devices on a system
board may be daisy chained to reduce or
eliminate input ripple as well as avoiding beat
frequency components. The EN5394QIs can all
be phase locked by feeding S_OUT of one
device into S_IN of the next device in a daisy
chain. All the switchers now run at a common
frequency. The delay is controlled by the value of
a resistor connected between S_DELAY and
AGND pins. The magnitude of this delay as a
function of S_DELAY resistor is shown in the
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Electrical Characteristics table. See Figures 6
and 7 for an example of using phase delay.
be used advantageously for power supply
sequencing using the precision Enable threshold.
Margining
During a soft-start cycle, when the soft-start
capacitor voltage reaches 0.60V, the output has
reached its programmed regulation range. Note
that the soft-start current source will continue to
charge the SS capacitor beyond 0.6V. During
normal operation, the soft-start capacitor will
charge to a final value of ~1.5V.
Using MAR1 and MAR2 pins, the nominal output
voltage can be increased / decreased by 2.5, 5
or 10% for system compliance, reliability or other
tests. The POK threshold voltages scale with the
margined output voltages. The following table
provides the possible combinations:
MAR1
Float
Low
High
Low
High
Low
High
Float
Float
MAR2
Float
Low
Low
High
High
Float
Float
High
Low
Output Modulation
0%
-2.5%
+2.5%
-5%
+5%
-10%
+10%
0%, Delay Bypass
Reserved
Note: Low means tie to GND. High means tie to VIN
as shown in Figure 5.
As shown above, when MAR1 is floating, and
MAR2 is high, the device enters the delay
bypass mode. In this mode, the delay from the
internal clock or S_IN to S_OUT is almost
eliminated (see Electrical Characteristics table).
Soft-Start Operation
The SS pin in conjunction with a small external
capacitor between this pin and AGND provides
the soft start function to limit the in-rush current
during start-up. During start-up of the converter
the reference voltage to the error amplifier is
gradually increased to its final level as an internal
current source of typically 10uA charges the soft
start capacitor. The typical soft-start time for the
output to reach regulation voltage, from when
AVIN > VUVLO and ENABLE crosses its logic high
threshold, is given by:
TSS = (CSS * 65KΩ) ± 25%
where the soft-start time TSS is in seconds and
the soft-start capacitance CSS is in Farads.
Typically, around 15nF is recommended. The
soft-start capacitor should be between 4.7nF and
100nF. A proper choice of SS capacitance can
Soft-Shutdown Operation
When the Enable signal is de-asserted, the softstart capacitor is discharged in a controlled
manner. Thus the output voltage ramps down
gradually. The internal circuits are kept active for
the duration of soft-shutdown, thereafter they are
deactivated.
Pre-Bias Operation
When EN_PB is asserted, the device will support
a monotonic output voltage ramp if the output
capacitor is charged to a pre-bias level.
Proprietary circuit ensures the output voltage
ramps monotonically from pre-bias voltage to the
programmed output voltage. Monotonic start-up
is guaranteed by design for pre-bias voltages
between 20% and 85% of the programmed
output voltage. This feature is not supported
when ENABLE is tied to VIN.
POK Operation
The POK signal indicates if the output voltage is
within a specified range. The POK signal is
asserted when the rising output voltage crosses
92% (nominal) of the programmed output
voltage. POK is de-asserted ~50us (256 clock
cycles) after the falling output voltage crosses
90% (nominal) of the programmed voltage. POK
is also de-asserted if the output voltage exceeds
120% of the programmed output. If the feedback
loop is broken, POK will remain de-asserted
(output < 92% of programmed value), and the
output voltage will equal the input voltage. If
however, there is a short across the PFET, and
the feedback is in place, POK will be de-asserted
as an over voltage condition. The power NFET is
also turned on, resulting in a large input supply
current. This in turn is expected to trip the OCP
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of the EN5394QI input power supply.
POK is an open drain output. It requires an
external pull up. Multiple EN5394QI’s POK pins
may be connected to a single pull up. The open
drain NFET is designed to sink up to 4mA. The
pull-up resistor value should be chosen
accordingly for when POK is logic low.
Input Under-Voltage Lock-Out (UVLO)
When the input voltage is below a required
voltage level (VUVLO) for normal operation, the
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
UVLO is implemented to ensure that operation
does not begin before there is adequate voltage
to properly bias all internal circuitry.
Over-Current Protection (OCP)
The current limit and short-circuit protection is
achieved by sensing the current flowing through
a sense P-FET. When the sensed current
exceeds the current limit, both NFET and PFET
switches are turned off. If the over-current
condition is removed, the over-current protection
circuit will re-enable the PWM operation. If the
over-current condition persists, the circuit will
continue to protect the device.
The OCP trip point is nominally set to 150% of
maximum rated load. In the event the OCP circuit
trips, the device enters a hiccup mode. The
device is disabled for ~10msec and restarted
with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition
persists. During soft-start at power up or fault
recovery, the hiccup mode is disabled and the
device has cycle-by-cycle current limiting. Tie
OCP_ADJ pin to GND for proper OCP operation.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approximately 20ºC, the converter will re-start
with a normal soft-start.
Compensation
The EN5394 uses of a type III compensation
network. Most of this network is integrated.
However a phase lead capacitor is required in
parallel with upper resistor of the external divider
network (see Figure 4). This network results in a
wide loop bandwidth and excellent load transient
performance. It is optimized for approximately
100μF of output filter capacitance at the voltage
sensing point. Additional decoupling capacitance
may be placed beyond the voltage sensing point
outside the control loop. Voltage-mode operation
provides high noise immunity at light load.
Further, voltage-mode control provides superior
impedance matching to ICs processed in sub
90nm technologies.
In exceptional cases modifications to the
compensation may be required. The EN5394QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Altera
Power Applications support.
Application Information
Output Voltage Programming
VOUT
The EN5394 output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB. A phase
lead capacitor CA is also required for stabilizing
the loop. Figure 4 shows the required
components and the equations to calculate their
values. Please note the equations below are
written to optimize the control loop as a function
of input voltage.
R A = 30,000 × Vin (value in Ω)
RA
CA =
5.6 × 10 −6
RA
(C A /R A in F/Ω)
Round C A down to closest
RB
VFB
standard value lower than
calculated value.
RB =
VFB × R A
(VOUT − VFB )
 VFB is 0.6V

 nominal



Figure 4: Output voltage resistor divider and phase-
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lead capacitor calculation. The equations need to be
followed in the order written above.
series inductance, ESL:
Z = ESR + ESL.
Input Capacitor Selection
The EN5394QI requires between 30-40uF of
input capacitance. Low ESR ceramic capacitors
are required with X5R or X7R dielectric
formulation.
Y5V or
equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and
bias voltage.
In some applications, lower value ceramic
capacitors may be needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
1
Z Total
Description
MFG
Typical Output Ripple (mVp-p)
(as measured on EN5394QI
Evaluation Board)†
2x47uF
20mV
2x47uF + 1x10uF
12mV
†
20 MHz bandwidth limit
Output Capacitor
Configuration
P/N
Murata
GRM31CR71A106KA01L
Taiyo Yuden
LMK316B7106KL-T
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK212BJ476ML-T
Output Capacitor Selection
The EN5394 has been optimized for use with
about 100µF of output filter capacitance.
Additional capacitance may be placed beyond
the voltage sensing point outside the control
loop. For the output filter, low ESR X5R or X7R
ceramic capacitors are required. Y5V or
equivalent dielectric formulations must not be
used as these lose capacitance with frequency,
temperature and bias voltage.
Recommended Output Capacitors
Description
47uF, 6.3V, 20%
X5R, 1206
(2 capacitors needed)
10uF, 6.3V, 10%
X5R, 0805
(Optional 1 capacitor in
parallel with 2x47uF)
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK212BJ476ML-T
Murata
GRM21BR60J106KE19L
Taiyo Yuden
JMK212BJ106KG-T
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 4MHz switching frequency, the capacitor
impedance, denoted as Z, is comprised mainly of
effective series resistance, ESR, and effective
Ternary Pin Inputs
The three ternary pins MAR1, MAR2, and M/S
have three possible states. In the Low state, the
pins are to be tied to GND. In the floating state,
nothing is to be connected to the pins. In the
High state, they are to be tied to VIN through an
external resistor REXT in order to limit the input
current to the pin (see Figure 5). The Electrical
Characteristics table lists, as a function of VIN,
some recommended values for REXT , and the
resulting input currents.
Frequency Sync & Phase Delay
The EN5394 can be synchronized to an external
clock source or to another EN5394 in order to
eliminate
unwanted
beat
frequencies.
Furthermore, two or more synchronized
EN5394’s can have a programmable phase
delay with respect to each other to minimize input
voltage ripple and noise. An example of
synchronizing three EN5394’s with approximately
equal phase delay between them is shown in
Figures 6 and 7. The lowest allowable value for
the S_DELAY resistor is 10kΩ.
Power-Up Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
13
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1
1
1
+
+ ... +
Z1 Z 2
Zn
Typical ripple versus capacitor arrangement is
given below:
Recommended Input Capacitors
10uF, 10V, 10%
X7R, 1206
(3-4 capacitors needed)
22uF, 10V, 20%
X5R, 1206
(2 capacitors needed)
47uF, 6.3V, 20%
X5R, 1206
(1 capacitor needed)
=
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be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
2.5V
R1
100k
To Gates
250
Rext
VIN
Figure 5: Equivalent circuit of a ternary pin
(MAR1, MAR2, or M/S) input buffer. To get a
logic High on a ternary input, pull the pin to VIN
through an external resistor REXT. See Electrical
Characteristics table for some recommended
REXT values as a function of VIN and the resulting
input currents.
D1
R2
100k
Vf ~ 2V
R3
3k
AGND
IC Package
VIN
C1
P/AGND
S_DELAY
R4
VOUT
VFB
EN5364
S_IN
OUT2
R6
R5
S_OUT
VOUT
C2
VFB
EN5364
R1
P/AVIN
OUT1
S_OUT
OUT3
R8
C3
P/AGND
S_IN
VOUT
VFB
P/AVIN
S_OUT
P/AGND
S_IN
X1_2
S_DELAY
P/AVIN
EXT_CLK
X1_1
S_DELAY
X1
EN5364
R2
R7
R3
R9
GND
Figure 6: Example of synchronizing multiple EN5394QIs in a daisy chain with phase delay.
VDRAIN- 1
Delay ~ 140°
VDRAIN- 2
VDRAIN- 3
Delay ~ 120°
Figure 7: Example of a possible way to synchronize and use delays advantageously to minimize input ripple.
R1 ~ 39kΩ , R2 ~ 33kΩ. (Refer to Figure 6 for R1 and R2.) R3 does not matter in this case.
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Layout Recommendations
− RA and RB are voltage
programming resistors.
− CA is used for loop
compensation.
− CSS is the soft-start
capacitor.
− AGND via is also a test point.
− Test point added for EAOUT.
− CIN can also be 2x22µF for
improved noise/EMI.
Figure 8: Critical Components and Layer 1 Copper for Minimum Footprint
thermal pads underneath the component must
be connected to the system ground plane
through as many vias as possible. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. This connection provides the
path for heat dissipation from the converter.
Please see figures: 8, 11, and 12.
Figure 8 above shows critical components and
layer 1 traces of the recommended EN5394
layout for minimum footprint with ENABLE tied
to VIN. Alternate ENABLE configurations, and
other small signal pins need to be connected
and routed according to specific customer
application. Please see the Gerber files at
www.altera.com/enpirion for exact dimensions
and other layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EN5394QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EN5394QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 4: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 3) should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias along the edge
of the GND copper closest to the +V copper.
These vias connect the input/output filter
capacitors to the GND plane, and help reduce
parasitic inductances in the input and output
current loops.
Recommendation 2: The system ground
plane referred to in recommendations 2 and 3
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output capacitors.
Recommendation 5: AVIN is the power supply
for the small-signal control circuits. It should be
connected to the input voltage at a quiet point.
In Figure 8 this connection is made at the input
capacitor.
Recommendation 6: The layer 1 metal under
Recommendation 3: The large and small
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the device must not be more than shown in
Figure 8. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
capacitor. Keep the sense trace short in order
to avoid noise coupling into the node.
Recommendation 8: Keep RA, CA, and RB
close to the VFB pin (see Figures 4 and 8).
The VFB pin is a high-impedance, sensitive
node. Keep the trace to this pin as short as
possible. Whenever possible, connect RB
directly to the AGND pin instead of going
through
the
GND
plane.
Recommendation 7: The VOUT sense point
should be just after the last output filter
Thermal Considerations
follows:
The Altera Enpirion EN5394QI DC-DC
converter is packaged in an 11 x 8 x 1.85mm
68-pin QFN package. The QFN package is
constructed with copper lead frames that have
exposed thermal pads. The recommended
maximum junction temperature for continuous
operation is 125°C. Continuous operation
above 125°C will reduce long-term reliability.
The device has a thermal overload protection
circuit designed to shut it off at an approximate
junction temperature value of 150°C.
TJ = TC + (PD)(θJC)
The device case temperature, TC, is the
temperature at the center of the larger exposed
thermal pad at the bottom of the package.
The device junction-to-ambient and junction-tocase thermal resistances, θJA and θJC, are
shown in the Thermal Characteristics table.
The θJC is a function of the device and the 68pin QFN package design. The θJA is a function
of θJC and the user’s system design
parameters
that
include
the
thermal
effectiveness of the customer PCB and airflow.
The silicon is mounted on a copper thermal
pad that is exposed at the bottom of the
package. There is an additional thermal pad in
the corner of the package which provides
another path for heat flow out from the
package. The thermal resistance from the
silicon to the exposed thermal pads is very low.
In order to take advantage of this low
resistance, the exposed thermal pads on the
package should be soldered directly on to a
copper ground pad on layer 1 of the PCB. The
PCB then acts as a heat sink. In order for the
PCB to be an effective heat sink, the device
thermal pads should be coupled to copper
ground planes using multiple vias (refer to
Layout Recommendations section).
The θJA value shown in the Thermal
Characteristics table is for free convection with
the device heat sunk (through the thermal
pads) to a copper plated four-layer PC board
with a full ground and a full power plane
following JEDEC EIJ/JESD 51 Standards. The
θJA can be reduced with the use of forced air
convection. Because of the strong dependence
on the thermal effectiveness of the PCB and
the system design, the actual θJA value will be
a function of the specific application.
When operating on a board with the θJA of the
thermal characteristics table, some thermal
derating is needed to operate all the way up to
maximum output current.
The junction temperature, TJ, is calculated from
the ambient temperature, TA, the device power
dissipation, PD, and the device junction-toambient thermal resistance, θJA in °C/W:
Figures 9 and 10 show, for a given input
voltage, the maximum output current curves as
a function of ambient temperature and output
voltage. These curves in figures have been
plotted assuming a maximum 125 °C limitation
on the junction temperature at a specific θJA for
the PCB.
TJ = TA + (PD)(θJA)
The junction temperature,
expressed in terms of
temperature, TC, and the
case thermal resistance,
TJ, can also be
the device case
device junction-toθJC in °C/W, as
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Current Derating Curves, EN5394QI, Vin = 5V
8x11mm QFN, Tjmax = 125°C, Θ-ja = 16°C/W, No Airflow
Current Derating Curves, EN5394QI, Vin = 3.3V
8x11mm QFN, Tjmax = 125°C, Θ-ja = 16°C/W, No Airflow
9
Max Output Current, A
Max Output Current, A
9
8
7
6
5
55.0
65.0
75.0
8
7
6
5
55.0
85.0
Vout = 1.8V
75.0
85.0
Ambient Temp, °C
Ambient Temp, °C
Vout = 1.0V
65.0
Vout = 1.0V
Vout = 2.5V
Figure 9: Maximum IOUT Curves at VIN = 3.3V
Vout = 1.8V
Vout = 2.5V
Vout=3.3V
Figure 10: Maximum IOUT Curves at VIN = 5.0V
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance,
and in overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This results in several small pads being exposed on the package bottom, as shown in Figure 11.
Only the two thermal pads and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EN5394QI should be clear of any metal (copper pours,
traces, or vias) except for the two thermal pads. The “grayed-out” area in Figure 11 represents the
area that should be clear of any metal on the top layer of the PCB. Any layer 1 metal under the
grayed-out area runs the risk of undesirable shorted connections even if it is covered by soldermask.
One exposed pad in the grayed-out area can have VIN metal under it as noted in Figure 11.
Figure 12 demonstrates the recommended PCB footprint for the EN5394QI. Figure 13 shows the
package dimensions.
VIN copper covered by
soldermask acceptable
under this exposed pad.
Figure 11: Lead-Frame exposed metal. Grey
area highlights exposed metal that is not to
be mechanically or electrically connected to
the PCB.
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Recommended PCB Footprint
Figure 12: EN5394QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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Package Dimensions
Figure 13. Package dimensions.
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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