EMIF02-AV01F3 Dual audio and video line IPAD™, EMI filter and ESD protection Features ■ High-density capacitor ■ EMI low-pass filter and ESD protection ■ High-efficiency in EMI filtering ■ Lead-free package ■ 400 µm pitch ■ Very small PCB footprint: 0.91 mm x 1.31 mm ■ Very thin package: 0.605 mm ■ High reliability offered by monolithic integration ■ Reduction of parasitic elements thanks to CSP integration Flip Chip 5 bumps Figure 1. Pin configuration (bump side view) 1 Complies with the following standards ■ ■ A IEC 61000-4-2 level 4 on external pin (A2, C2) – 15 kV (air discharge) – 8 kV (contact discharge) B IEC 61000-4-2 level 1 on internal pin (A1, C1) – 2 kV (air discharge) – 2 kV (contact discharge) C Figure 2. Schematic Application ■ 2 R A2 A1 Dual audio and video line interface protection and filtering in mobile phones C 2 kV Description 15 kV B2 Gnd The EMIF02-AV01F3 is a highly integrated array designed to suppress EMI / RFI noise and provide impedance matching for mobile phones and portable applications. 2 kV The EMIF02-AV01F3 is in Flip Chip package to offer space saving and high RF performance. 15 kV C C2 C1 R Additionally, this low-pass filter includes an ESD protection circuitry to prevent damage to the application when subjected to ESD surges up to 15 kV. TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 3 1/7 www.st.com 7 Characteristics 1 EMIF02-AV01F3 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Vpp Tj PTOT Parameter Unit Internal pins (A1, C1) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge External pins (A2, C2) ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge 15 8 Maximum junction temperature 125 °C Total Power Dissipation 200 mW 2 2 kV Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameters VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current RI/O Series resistance between input and output Cline Input capacitance per line Symbol Test conditions VBR IR = 1 mA IRM VRM = 3 V per line RI/O Cline 2/7 Value Vline = 0 V, VOSC = 30 mV, F = 100 kHz I IPP VCL VBR VRM IR IRM IRM IR V VRM VBR VCL IPP Min Typ 14 Max Unit 18 V 0.5 µA 12 15 18 Ω 2.56 3.2 3.84 nF EMIF02-AV01F3 Figure 3. 0.00 Characteristics S21 (dB) attenuation Figure 4. Analog crosstalk dB dB 0.00 -10.00 -10.00 -20.00 -30.00 -20.00 -40.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 -90.00 F (Hz) 10.0M 30.0M 100.0M 300.0M Line 1 Figure 5. F (Hz) -100.00 -50.00 1.0G 1.0M 3.0G 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G Xtalk 1/2 Line 2 Digital crosstalk Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (VIN) and one output (VOUT) INPUT : 10 V/Div 100 ns/Div Vin = 1 V/d OUTPUT : 10 V/Div 100 ns/Div Vout = 5 mV/d Figure 7. ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (VIN) and one output (VOUT) Figure 8. CLINE(nF) INPUT : 10 V/Div 100 ns/Div Line capacitance versus applied voltage 3.5 F=100 kHz VOSC=30 mVRMS Tj=25 °C 3.0 2.5 2.0 OUTPUT : 10 V/Div 100 ns/Div 1.5 1.0 0.5 VLINE (V) 0.0 0 1 2 3 4 5 6 3/7 Ordering information scheme 2 EMIF02-AV01F3 Ordering information scheme Figure 9. Ordering information scheme EMIF yy - xx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10 (pF) or 2 letters = application 2 digits = version Package F = Flip Chip x = 3: lead free, pitch = 400 µm, bump = 255 µm 3 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 10. Package dimensions 400 µm ± 40 400 µm ± 50 605 µm ± 55 1310 µm ± 30 µm 255 µm ± 40 910 µm ± 30 µm 4/7 255 µm 255 µm EMIF02-AV01F3 Ordering information Figure 11. Footprint Figure 12. Marking Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum E x x z y ww Solder stencil opening: 220 µm recommended Figure 13. Flip Chip tape and reel specification Dot identifying Pin A1 location 3.5 ± 0.1 xxz yww ST E 1.41 xxz yww 4 ± 0.1 User direction of unreeling All dimensions in mm Note: ST E xxz yww ST E 8 ± 0.3 1.01 0.71 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 Note: More information is available in the application note: AN2348:"Flip Chip: Package description and recommendations for use" AN1751: “EMI filters: Recommendations and measurements” 4 Ordering information Table 3. Ordering information Order code Marking Package Weight Base qty Delivery mode EIMF02-AV01F3 HH Flip Chip 1.4 mg 5000 Tape and reel 7” 5/7 Revision history 5 EMIF02-AV01F3 Revision history Table 4. 6/7 Document revision history Date Revision Changes 06-Oct-2006 1 Initial release. 11-Oct-2006 2 Corrected test conditions for Cline in Table 2. 17-Apr-2008 3 Updated ECOPACK statement. Updated Figure 9, Figure 10 and Figure 13. Reformatted to current standards. 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