ON MC74HCT373AFELG Octal 3-state noninverting transparent latch with lsttl-compatible input Datasheet

MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent D−type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high−impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Chip Complexity: 196 FETs or 49 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
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MARKING
DIAGRAMS
20
PDIP−20
N SUFFIX
CASE 738
1
20
MC74HCT373AN
AWLYYWWG
1
20
SOIC−20
DW SUFFIX
CASE 751D
20
1
HCT373A
AWLYYWWG
1
20
HCT
373A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
F SUFFIX
CASE 967
1
20
1
A
WL, L
YY, Y
WW, W
G or G
74HCT373A
AWLYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
MC74HCT373ANG
Package
Shipping†
PDIP−20
18 / Box
MC74HCT373ADWG
SOIC−20
38 / Rail
MC74HCT373ADWR2G
SOIC−20
1000 / Reel
MC74HCT373AFELG
SOEIAJ−20 2000 / Reel
MC74HCT373ADTR2G
TSSOP−20 2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 12
1
Publication Order Number:
MC74HCT373A/D
MC74HCT373A
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
11
VCC
2
19
Q7
D0
3
18
D7
D6
4
17
Q1
5
16
Q6
Q1
Q2
6
15
Q5
Q2
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
LATCH
ENABLE
Q3
NONINVERTING
OUTPUTS
Q4
GND
Q5
Q6
FUNCTION TABLE
Q7
Inputs
Value
Units
Internal Gate Count*
49
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
mW
0.0075
pJ
Speed Power Product
20
D1
*Equivalent to a two−input NAND gate.
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2
Output
Output
Enable
Latch
Enable
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Design Criteria
1
Q0
PIN 20 = VCC
PIN 10 = GND
1
OUTPUT
ENABLE
Q0
MC74HCT373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
°C
Plastic DIP†
SOIC Package†
TSSOP Package†
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
(Plastic DIP, SOIC, SSOP or TSSOP Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/°C from 65° to 125°C
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
°C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25°C
v 85°C
v 125°C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| v 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum Low−Level Output
Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
5.5
4.0
40
160
mA
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3
MC74HCT373A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 mA
5.5
≥ −55°C
25°C to 125°C
2.9
2.4
mA
NOTE: 1. Total Supply Current = ICC + SDICC.
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to
25°C
v 85°C
v 125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
35
42
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
32
40
48
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
35
44
53
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
12
15
18
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
15
15
15
pF
Symbol
Parameter
Typical @ 25°C, VCC = 5.0 V
CPD
65
Power Dissipation Capacitance (Per Latch)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
2f
pF
+ ICC VCC .
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to
25°C
v 85°C
v 125°C
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
10
13
15
ns
th
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
10
13
15
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 2)
12
15
18
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
ns
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4
MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D
Q
D2
7
D
LE
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
LATCH 11
ENABLE
OUTPUT 1
ENABLE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SWITCHING WAVEFORMS
tr
tf
INPUT D
tw
3V
2.7 V
1.3 V
0.3 V
LATCH ENABLE
GND
tPHL
Q
Figure 2.
3V
1.3 V
GND
tPZL
tPLZ
VALID
3V
HIGH
IMPEDANCE
1.3 V
tPZH
Q
1.3 V
tTHL
Figure 1.
Q
tPHL
tPLH
90%
1.3 V
10%
tTLH
OUTPUT
ENABLE
1.3 V
GND
tPLH
Q
3V
1.3 V
10%
VOL
90%
VOH
INPUT D
GND
tsu
tPHZ
1.3 V
1.3 V
LATCH ENABLE
th
3V
1.3 V
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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5
MC74HCT373A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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6
MC74HCT373A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
20 PL
0.25 (0.010)
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
11
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT373A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
−U−
PIN 1
IDENT
1
SECTION N−N
0.25 (0.010)
N
10
M
0.15 (0.006) T U
S
N
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HCT373A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
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