Cirrus CS4385-CQZ 114 db, 192khz 8-channel d/a converter Datasheet

CS4385
114 dB, 192 kHz 8-Channel D/A Converter
Features
Description
z Advanced
The CS4385 is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mixing,
selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma
modulator which includes mismatch shaping technology
that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog outputs.
Multi-bit Delta Sigma Architecture
z 24-Bit Conversion
z Automatic Detection of Sample Rates up to
192 kHz
z 114 dB Dynamic Range
z -100 dB THD+N
z Direct Stream Digital Mode
– Non-decimating volume control
– On-chip 50 kHz filter
– Matched PCM and DSD analog output levels
z Compatible
with Industry-standard Time
Division Multiplexed (TDM) Serial Interface
z Selectable Digital Filters
z Volume Control with 1/2-dB Step Size and
Soft Ramp
z Low Clock Jitter Sensitivity
z +5 V Analog Supply, +2.5 V Digital Supply
z Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
The CS4385 also has a proprietary DSD processor
which allows for volume control and 50 kHz on-chip filtering without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by directly using the multi-element switched capacitor array.
The CS4385 accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These features are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio systems.
ORDERING INFORMATION
CS4385-CQZ -10 to 70 °C 48-pin LQFP, Lead-Free
CS4385-DQZ -40 to 85 °C 48-pin LQFP, Lead-Free
CDB4385
Evaluation Board
I
Hardw are Mode or
I2C /SP I S oftw are Mode
C ontrol Data
Reset
Le ve l T ra nsla tor
C ontrol Port Supply = 1.8 V to 5 V
Digital S upply = 2.5 V
A nalog S upply = 5 V
Inte rnal Voltage
Reference
Re giste r/Hardwa re
C onfigura tion
Serial A udio Port
Supply = 1.8 V to 5 V
DSD A udio
Input
S e ria l Inte rfa ce
TDM Serial
A udio Input
8
Le ve l T ra nsla tor
P C M S erial
A udio Input
Advance Product Information
http://www.cirrus.com
Volume
C ontrols
Digita l
F ilte rs
Multi-bit ∆Σ
Modula tors
DSD Processor
-Volume control
-50 kHz filter
Switch-C a p
DAC and
A na log F ilte rs
E xterna l Mute
C ontrol
8
8
2
E ight C hannels
of Differential
O utputs
Mute Signals
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
OCT ‘04
DS671A1
CS4385
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................... 4
2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6
SPECIFIED OPERATING CONDITIONS ................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6
DAC ANALOG CHARACTERISTICS ....................................................................................... 7
POWER AND THERMAL CHARACTERISTICS....................................................................... 8
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................... 9
DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE.......................... 10
DIGITAL CHARACTERISTICS ............................................................................................... 11
SWITCHING CHARACTERISTICS - PCM ............................................................................. 12
SWITCHING CHARACTERISTICS - DSD.............................................................................. 13
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT ................................ 14
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 15
3. APPLICATIONS ...................................................................................................................... 18
3.1 Master Clock .................................................................................................................... 18
3.2 Mode Select ..................................................................................................................... 19
3.3 Digital Interface Formats ................................................................................................. 20
3.3.1 OLM #1 ............................................................................................................... 21
3.3.2 OLM #2 ............................................................................................................... 22
3.3.3 OLM #3 ............................................................................................................... 22
3.3.4 OLM #4 ............................................................................................................... 22
3.3.5 TDM .................................................................................................................... 23
3.4 Oversampling Modes ....................................................................................................... 23
3.5 Interpolation Filter ............................................................................................................ 23
3.6 De-Emphasis ................................................................................................................... 24
3.7 ATAPI Specification ......................................................................................................... 25
3.8 Direct Stream Digital (DSD) Mode ................................................................................... 25
3.9 Grounding and Power Supply Arrangements .................................................................. 26
3.9.1 Capacitor Placement ........................................................................................... 27
3.10 Analog Output and Filtering ........................................................................................... 27
3.11 The MUTEC Outputs ..................................................................................................... 29
3.12 Recommended Power-up Sequence ............................................................................. 30
3.12.1 Hardware Mode ................................................................................................. 30
3.12.2 Software Mode .................................................................................................. 30
3.13 Control Port Interface ..................................................................................................... 31
3.13.1 MAP Auto Increment ......................................................................................... 31
3.13.2 I2C Mode ........................................................................................................... 31
3.13.3 SPI Mode .......................................................................................................... 33
3.14 Memory Address Pointer (MAP)
.............................................................................. 34
4. REGISTER QUICK REFERENCE ......................................................................................... 35
5. REGISTER DESCRIPTION .................................................................................................... 37
6. PARAMETER DEFINITIONS .................................................................................................. 49
7. REFERENCES ........................................................................................................................ 49
8. PACKAGE DIMENSIONS ....................................................................................................... 50
9. APPENDIX
......................................................................................................................... 51
2
DS671A1
CS4385
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing......................................................................................... 12
Figure 2. TDM Serial Audio Interface Timing ................................................................................ 12
Figure 3. Direct Stream Digital - Serial Audio Input Timing........................................................... 13
Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation mode.............. 13
Figure 5. Control Port Timing - I2C Format ................................................................................... 14
Figure 6. Control Port Timing - SPI Format................................................................................... 15
Figure 7. Typical Connection Diagram, Software Mode................................................................ 16
Figure 8. Typical Connection Diagram, Hardware ........................................................................ 17
Figure 9. Format 0 - Left Justified up to 24-bit Data...................................................................... 20
Figure 10. Format 1 - I2S up to 24-bit Data................................................................................... 20
Figure 11. Format 2 - Right Justified 16-bit Data .......................................................................... 20
Figure 12. Format 3 - Right Justified 24-bit Data .......................................................................... 20
Figure 13. Format 4 - Right Justified 20-bit Data .......................................................................... 21
Figure 14. Format 5 - Right Justified 18-bit Data .......................................................................... 21
Figure 15. Format 8 - One Line Mode 1........................................................................................ 21
Figure 16. Format 9 - One Line Mode 2........................................................................................ 22
Figure 17. Format 10 - One Line Mode 3...................................................................................... 22
Figure 18. Format 11 - One Line Mode 4...................................................................................... 22
Figure 19. Format 12 - TDM Mode................................................................................................ 23
Figure 20. De-Emphasis Curve..................................................................................................... 24
Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) .................................................. 25
Figure 22. DSD phase modulation mode diagram ........................................................................ 26
Figure 23. Full-Scale Output ......................................................................................................... 27
Figure 24. Recommended Output Filter........................................................................................ 28
Figure 25. Recommended Mute Circuitry ..................................................................................... 29
Figure 26. Control Port Timing, I2C Mode..................................................................................... 32
Figure 27. Control Port Timing, SPI mode .................................................................................... 33
Figure 28. Single Speed (fast) Stopband Rejection ...................................................................... 51
Figure 29. Single Speed (fast) Transition Band ............................................................................ 51
Figure 30. Single Speed (fast) Transition Band (detail) ................................................................ 51
Figure 31. Single Speed (fast) Passband Ripple .......................................................................... 51
Figure 32. Single Speed (slow) Stopband Rejection..................................................................... 51
Figure 33. Single Speed (slow) Transition Band........................................................................... 51
Figure 34. Single Speed (slow) Transition Band (detail)............................................................... 52
Figure 35. Single Speed (slow) Passband Ripple......................................................................... 52
Figure 36. Double Speed (fast) Stopband Rejection..................................................................... 52
Figure 37. Double Speed (fast) Transition Band........................................................................... 52
Figure 38. Double Speed (fast) Transition Band (detail)............................................................... 52
Figure 39. Double Speed (fast) Passband Ripple......................................................................... 52
Figure 40. Double Speed (slow) Stopband Rejection ................................................................... 53
Figure 41. Double Speed (slow) Transition Band ......................................................................... 53
Figure 42. Double Speed (slow) Transition Band (detail) ............................................................. 53
Figure 43. Double Speed (slow) Passband Ripple ....................................................................... 53
Figure 44. Quad Speed (fast) Stopband Rejection ....................................................................... 53
Figure 45. Quad Speed (fast) Transition Band ............................................................................. 53
Figure 46. Quad Speed (fast) Transition Band (detail) ................................................................. 54
Figure 47. Quad Speed (fast) Passband Ripple ........................................................................... 54
Figure 48. Quad Speed (slow) Stopband Rejection...................................................................... 54
Figure 49. Quad Speed (slow) Transition Band ............................................................................ 54
Figure 50. Quad Speed (slow) Transition Band (detail) ................................................................ 54
Figure 51. Quad Speed (slow) Passband Ripple .......................................................................... 54
DS671A1
3
CS4385
AOUTB1-
MUTEC1
AOUTA1AOUTA1+
AOUTB1+
DSDA4
DSDB4
VLS
DSD_SCLK
PIN DESCRIPTION
DSDB2
DSDA3
DSDB3
1.
48 47 46 45 44 43 42 41 40 39 38 37
DSDA2
1
36
AOUTA2-
DSDB1
2
35
AOUTA2+
DSDA1
3
4
34
33
AOUTB2+
VD
GND
5
32
AOUTB2-
MCLK
6
31
VA
GND
LRCK
7
30
AOUTA3-
SDIN1
8
29
SCLK
9
28
AOUTA3+
AOUTB3+
AOUTB3-
CS4385
M4(TST)
10
27
SDIN2
M3(TST)
11
26
AOUTA4-
12
25
AOUTA4+
Pin Name
AOUTB4+
VQ
MUTEC234
AOUTB4-
VLC
RST
FILT+
SDIN3
SDIN4
M2(SCL/CCLK)
M1(SDA/CDIN)
M0(AD0/CS)
13 14 15 16 17 18 19 20 21 22 23 24
#
Pin Description
VD
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.
GND
5
31
Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Tables 1-3 illustrate
several standard audio sample rates and the required master clock frequency.
LRCK
7
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4
8
11
13
14
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK
9
Serial Clock (Input) - Serial clock for the serial audio interface.
VLC
18
Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Recommended Operating Conditions for appropriate voltages.
RST
19
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
FILT+
20
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
4
DS671A1
CS4385
Pin Name
#
Pin Description
VQ
21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be
used to bias the analog circuitry assuming there is no AC signal component and the DC current is less
than the maximum specified in the Analog Characteristics and Specifications section.
MUTEC1
MUTEC234
41
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended
to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,AOUTA4 +,AOUTB4 +,-
39, 40 Differential Analog Output (Output) - The full scale differential analog output level is specified in the
38, 37 Analog Characteristics specification table.
35, 36
34, 33
29, 30
28, 27
25, 26
24, 23
VA
32
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Operating Conditions for appropriate voltages.
VLS
43
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
Software Mode Definitions
SCL/CCLK
15
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I2C mode as shown in the Typical Connection Diagram.
SDA/CDIN
16
Serial Control Data (Input/Output) - SDA is a data I/O line in I2C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input
data line for the control port interface in SPI mode.
AD0/CS
17
Address Bit 0 (I2C) / Chip Select (SPI) (Input) - AD0 is a chip address pin in I2C mode; CS is the chip
select signal for SPI format.
TST
10
12
Test (Input) - These pins are not used in software mode and should not be left floating (connect to
ground).
Hardware Mode Definitions
M0
M1
M2
M3
M4
17
16
15
12
10
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 4 and 5.
DSD Definitions
DSD_SCLK
42
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
3
2
1
48
47
46
45
44
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DS671A1
5
CS4385
2.
CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Specified Temperature Range
-CQZ
-DQZ
Symbol
Min
Typ
Max
Units
VA
VD
VLS
VLC
TA
4.75
2.37
1.71
1.71
-10
-40
5.0
2.5
5.0
5.0
-
5.25
2.63
5.25
5.25
+70
+85
V
V
V
V
°C
°C
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Input Current, Any Pin Except Supplies
Digital Input Voltage
Serial data port interface
Control port interface
Ambient Operating Temperature (power applied)
Storage Temperature
VA
VD
VLS
VLC
Iin
VIND-S
VIND-C
Top
Tstg
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-65
6.0
3.2
6.0
6.0
±10
VLS+ 0.4
VLC+ 0.4
125
150
V
V
V
V
mA
V
V
°C
°C
DC Power Supply
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
6
DS671A1
CS4385
DAC ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 100 pF; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
Parameters
Symbol
Min
Typ
Max
Unit
CS4385-CQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range
TA
24-bit
A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
Total Harmonic Distortion + Noise
-10
-
70
°C
108
105
-
114
111
97
94
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-94
-45
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
-40
-
85
°C
105
102
-
114
111
97
94
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-91
-42
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
THD+N
24-bit
16-bit
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
CS4385-DQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range (Note 1)
TA
24-bit
A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
(Note 1)
Total Harmonic Distortion + Noise
24-bit
16-bit
(Note 2)
THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
Notes: 1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
DS671A1
7
CS4385
DAC ANALOG CHARACTERISTICS - ALL MODES (Continued)
Interchannel Isolation
Parameters
(1 kHz)
Symbol
Min
Typ
Max
Units
-
90
-
dB
-
0.1
100
-
dB
ppm/°C
VFS
132%•VA
94%•VA
134%•VA
96%•VA
136%•VA
98%•VA
Vpp
Vpp
ZOUT
IOUTmax
RL
CL
VQ
IQMAX
-
100
1.0
3
100
50% VA
10
-
Ω
mA
kΩ
pF
VDC
µA
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Analog Output
Full Scale Differential Output Voltage PCM, DSD processor
Direct DSD mode
Output Impedance
Max DC Current draw from an AOUT pin
Min AC-Load Resistance
Max Load Capacitance
Quiescent Voltage
Max Current draw from VQ
(Note 3)
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
normal operation, VA= 5 V
VD= 2.5 V
Interface current, VLC=5 V (Note 5)
VLS=5 V
power-down state (all supplies) (Note 6)
Power Dissipation
(Note 4)
VA = 5 V, VD = 2.5 V
normal operation
power-down (Note 6)
Package Thermal Resistance
IA
ID
ILC
ILS
Ipd
-
75
20
2
84
200
83
26
-
mA
mA
µA
µA
µA
-
426
1
48
15
60
40
482
-
mW
mW
°C/Watt
°C/Watt
dB
dB
Power Supplies
Power Supply Current
(Note 4)
Power Supply Rejection Ratio (Note 7)
(1 kHz)
(60 Hz)
θJA
θJC
PSRR
Notes: 3. VFS is tested under load RL and includes attenuation due to ZOUT
4. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
5. ILC measured with no external loading on the SDA pin.
6. Power down mode is defined as RST pin = Low with all clock and data lines held static.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 7 and 8.
8
DS671A1
CS4385
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The
filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate
by multiplying the given characteristic by Fs.) (See note 12.)
Fast Roll-Off
Parameter
Min
Typ
Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
0.547
StopBand Attenuation
(Note 10)
102
Group Delay
10.3/Fs
De-emphasis Error (Note 11)
Fs = 32 kHz
(Relative to 1 kHz)
Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
.583
StopBand Attenuation
(Note 10)
80
Group Delay
5.9/Fs
Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
.635
StopBand Attenuation
(Note 10)
90
Group Delay
7.0/Fs
Max
Unit
.454
.499
+0.01
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
.430
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
.105
.490
+0.01
-
Fs
Fs
dB
Fs
dB
s
Notes: 8. Slow Roll-off interpolation filter is only available in software mode.
9. Response is clock dependent and will scale with Fs.
10. For Single Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in
hardware mode.
12. Amplitude vs. Frequency plots of this data are available starting on page 51.
DS671A1
9
CS4385
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont.)
Parameter
Single Speed Mode - 48 kHz
Passband (Note 9)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
De-emphasis Error (Note 11)
(Relative to 1 kHz)
Double Speed Mode - 96 kHz
Passband (Note 9)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Quad Speed Mode - 192 kHz
Passband (Note 9)
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Slow Roll-Off (Note 8)
Min
Typ
Max
to -0.01 dB corner
to -3 dB corner
(Note 10)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
to -0.01 dB corner
to -3 dB corner
(Note 10)
to -0.01 dB corner
to -3 dB corner
(Note 10)
Unit
0
0
-0.01
.583
64
-
4.5/Fs
-
0.417
0.499
+0.01
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
0
0
-0.01
.792
70
-
5.3/Fs
.296
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
0
0
-0.01
.868
75
-
6.4/Fs
.104
.481
+0.01
-
Fs
Fs
dB
Fs
dB
s
DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE
Parameter
DSD Processor mode
Passband (Note 9)
Frequency Response 10 Hz to 20 kHz
Roll-off
Direct DSD mode
Passband (Note 9)
Frequency Response 10 Hz to 20 kHz
10
Min
Typ
Max
Unit
to -3 dB corner
0
-0.05
27
-
50
+0.05
-
kHz
dB
dB/Oct
to -0.1 dB corner
to -3 dB corner
0
0
-0.1
-
26.9
176.4
0
kHz
kHz
dB
DS671A1
CS4385
DIGITAL CHARACTERISTICS
Parameters
High-Level Input Voltage
Serial I/O
Control I/O
VIH
VIH
Min
70%
70%
Low-Level Input Voltage
Serial I/O
Control I/O
VIL
VIL
-
-
30%
30%
VLS
VLC
High-Level Output Voltage (IOH = -1.2 mA)
Control I/O
VOH
80%
-
-
VLC
Low-Level Output Voltage (IOL = 1.2 mA)
Control I/O
VOL
-
-
20%
VLC
VIH
VIL
Imax
VOH
VOL
70%
-
3
VA
0
30%
-
VA
VA
mA
V
V
Input Leakage Current
Input Capacitance
MUTEC auto detect input high voltage
MUTEC auto detect input low voltage
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
Symbol
(Note 13)
Iin
Typ
8
-
Max
±10
-
Units
µA
pF
VLS
VLC
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latchup
DS671A1
11
CS4385
SWITCHING CHARACTERISTICS - PCM ( Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30pF)
Parameters
Symbol
RST pin Low Pulse Width
(Note 14)
MCLK Frequency
MCLK Duty Cycle
(Note 15)
Min
Max
Units
1
-
ms
1.024
55.2
MHz
45
55
%
Input Sample Rate - LRCK (Manual selection)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
54
108
216
kHz
kHz
kHz
Input Sample Rate - LRCK (Auto detect)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
84
170
54
108
216
kHz
kHz
kHz
LRCK Duty Cycle
45
55
%
SCLK Duty Cycle
45
55
%
tsckh
8
-
ns
SCLK Low Time
tsckl
8
-
ns
LRCK Edge to SCLK Rising Edge
tlcks
5
-
ns
SCLK Rising Edge to LRCK Falling Edge
tlckd
5
-
ns
SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
SDIN Hold Time After SCLK Rising Edge
tdh
5
-
ns
SCLK High Time
Notes: 14. After powering up, RST should be held low until after the power supplies and clocks are settled.
15. See Tables 1 - 3 on page 18 for suggested MCLK frequencies.
LRCK
LRCK
tlcks
tsckh
tsckl
t lcks
tds
tdh
MSB
t ds
MSB-1
Figure 1. Serial Audio Interface Timing
12
t lcks
t sckh
t sckl
SCLK
SCLK
SDINx
t lckd
SDIN1
t dh
MSB
M SB-1
Figure 2. TDM Serial Audio Interface Timing
DS671A1
CS4385
SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS Volts;
CL = 20 pF)
Parameter
MCLK Duty Cycle
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
Symbol
tsclkl
tsclkh
(64x Oversampled)
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
DSD clock to data transition (Phase Modulation mode)
tsdlrs
tsdh
tdpm
Min
40
160
160
1.024
2.048
20
20
-20
Typ
-
Max
60
3.2
6.4
20
Unit
%
ns
ns
MHz
MHz
ns
ns
ns
t sclkh
t sclkl
DSD_SCLK
t sdlrs
t sdh
DSDxx
Figure 3. Direct Stream Digital - Serial Audio Input Timing
t dpm
t dpm
DSD_SCLK
(128Fs)
DSD_SCLK
(64Fs)
DSDxx
Figure 4. Direct Stream Digital - Serial Audio Input Timing for
Phase Modulation mode
DS671A1
13
CS4385
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
SDA Hold Time from SCL Falling
(Note 16)
SDA Setup time to SCL Rising
Notes: 16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
R e p e a te d
S ta rt
S ta rt
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t sust
tr
Figure 5. Control Port Timing - I2C Format
14
DS671A1
CS4385
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Edge to CS Falling
(Note 17)
CCLK Rising to DATA Hold Time
(Note 18)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 19)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 19)
tf2
-
100
ns
Notes: 17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
C D IN
t dsu t
dh
Figure 6. Control Port Timing - SPI Format
DS671A1
15
CS4385
+2.5 V
+5 V
+
1 µF
0.1 µF
4
VD
AOUTA1AOUTB1+
7
9
PCM
Digital
Audio
Source
8
11
13
14
AOUTB1-
MCLK
LRCK
AOUTA2+
SCLK
AOUTA2-
+1.8 V to +5 V
AOUTB2+
SDIN3
AOUTB2-
SDIN4
AOUTA3-
VLS
CS4385
0.1 µF
AOUTB3+
AOUTB33
2
1
48
DSD
Audio
Source
47
46
AOUTA4+
DSDB1
AOUTA4-
DSDB2
AOUTB4+
DSDA3
AOUTB4-
DSDB4
MUTEC234
42
DSD_SCLK
37
Analog Conditioning
and Muting
35
36
Analog Conditioning
and Muting
34
33
Analog Conditioning
and Muting
29
30
Analog Conditioning
and Muting
28
27
Analog Conditioning
and Muting
25
26
Analog Conditioning
and Muting
24
23
Analog Conditioning
and Muting
41
Mute
Drive
22
RST
SCL/CCLK
SDA/CDIN
ADO/CS
2 KΩ
2 KΩ
17
38
Analog Conditioning
and Muting
DSDB3
MUTEC1
16
40
DSDA2
DSDA4
15
MicroController
DSDA1
45
44
19
39
SDIN1
SDIN2
AOUTA3+
43
1 µF
32
VA
AOUTA1+
6
+
0.1 µF
Note*
FILT+ 20
18
+1.8 V to +5 V
VQ
VLC
0.1 µ F + 1 µF
0.1 µF
2
Note: Necessary for I C
control port operation
+
21
GND
5
GND
31
0.1 µ F
47 µF
TST*
NoteTST: Pins 10, 12
Figure 7. Typical Connection Diagram, Software Mode
16
DS671A1
CS4385
+2.5 V
+5 V
1 µF
+
0.1 µF
0.1 µF
4
VD
AOUTA1AOUTB1+
7
9
PCM
Digital
Audio
Source
8
11
13
14
43
+1.8 V to +5 V
AOUTB1-
MCLK
SCLK
MUTEC1
SDIN3
AOUTA2+
SDIN4
AOUTA2AOUTB2+
VLS
AOUTB2-
AOUTA3-
48
DSD
Audio
Source
47
46
45
44
42
47 KΩ
10
12
15
Stand-Alone
Mode
Configuration
16
17
19
37
Analog Conditioning
and Muting
41
Mute
Drive
35
36
34
33
29
30
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
DSDA1
DSDB1
AOUTB3+
DSDA2
AOUTB3-
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
DSD_SCLK
AOUTA4+
AOUTA4AOUTB4+
AOUTB4-
M4
MUTEC234
M3
28
27
Analog Conditioning
and Muting
25
26
Analog Conditioning
and Muting
24
23
22
Analog Conditioning
and Muting
Mute
Drive
M2
M1
M0
RST
Optional
FILT+ 20
VQ
+1.8 V to +5 V
Analog Conditioning
and Muting
38
SDIN1
AOUTA3+
1
40
SDIN2
0.1 µF
2
39
LRCK
CS4385
3
1 µF
32
VA
AOUTA1+
6
+
18
+
21
0.1 µ F + 1 µF
VLC
0.1 µF
47 µF
0.1 µF
GND
5
GND
31
Figure 8. Typical Connection Diagram, Hardware
DS671A1
17
CS4385
3. APPLICATIONS
The CS4385 serially accepts twos complement formatted PCM data at standard audio sample
rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and
128 kHz in QSM. Audio data is input via the serial data input pins (SDINx). The Left/Right Clock
(LRCK) determines which channel is currently being input on SDINx, and the Serial Clock
(SCLK) clocks audio data into the input data buffer.
The CS4385 can be configured in hardware mode by the M0, M1, M2 , M3 and M4 pins and in
software mode through I2C or SPI.
3.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Tables 1 - 3. The LRCK frequency is equal to
Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK
frequency ratio and speed mode is detected automatically during the initialization sequence by
counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are then set to generate the proper internal clocks. Tables 1 - 3 illustrate several standard audio sample rates and the required MCLK and LRCK
frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK
must be synchronous.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
768x
16.3840
24.5760
22.5792
33.8688
24.5760
36.8640
1024x
32.7680
45.1584
49.1520
1152x
36.8640
Table 1. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64
88.2
96
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
MCLK (MHz)
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
512x
32.7680
45.1584
49.1520
Table 2. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
176.4
192
64x
11.2896
12.2880
96x
16.9344
18.4320
MCLK (MHz)
128x
22.5792
24.5760
192x
33.8688
36.8640
256x
45.1584
49.1520
Table 3. Quad-Speed Mode Standard Frequencies
= Denotes clock ratio and sample rate combinations which are NOT supported under auto
speed-mode detection. Please see “Switching Characteristics - PCM” on page 12.
18
DS671A1
CS4385
3.2
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are
continually scanned for any changes. These pins require connection to supply or ground as outlined in figure 8. For M0, M1, M2 supply is VLC and for M3 and M4 supply is VLS. Tables 4 - 6
show the decode of these pins.
In software mode the operational mode and data format are set in the FM and DIF registers.
See “Register Description” on page 37.
M1
(DIF1)
0
0
M0
(DIF0)
0
1
1
1
0
1
DESCRIPTION
FORMAT
FIGURE
0
1
9
10
2
3
11
12
Left Justified, up to 24-bit data
I2S,
up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Table 4. PCM Digital Interface Format, Hardware Mode Options
M4
M3
0
0
0
0
1
1
1
0
0
1
1
0
0
1
M2
(DEM)
0
1
0
1
0
1
X
DESCRIPTION
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1kHz De-Emphasis; see Figure 20
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Auto Speed-Mode Detect (32kHz to 200kHz sample rates)
Auto Speed-Mode Detect with 44.1kHz De-Emphasis; see Figure 20
DSD Processor Mode (see Table 6 for details)
Table 5. Mode Selection, Hardware Mode Options
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Direct Stream Digital (DSD), Hardware Mode Options
DS671A1
19
CS4385
3.3
Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-Justified, Right-Justified, One-Line
Mode (OLM) and TDM digital interface formats with varying bit depths from 16 to 32 as shown in
Figures 9-19. Data is clocked into the DAC on the rising edge. OLM and TDM configurations are
only supported in software mode.
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 9. Format 0 - Left Justified up to 24-bit Data
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 10. Format 1 - I2S up to 24-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
15 14 13 12 11 10 9 8
7
6
5
4
3
2 1
0
15 14 13 12 11 10 9
8
7
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
32 clocks
Figure 11. Format 2 - Right Justified 16-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
0
23 22 21 20 19 18
7
6
5
4
3
2 1
0
23 22 21 20 19 18
32 clocks
Figure 12. Format 3 - Right Justified 24-bit Data
20
DS671A1
CS4385
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4 3
2
1
0
19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
2
1
0
32 clocks
Figure 13. Format 4 - Right Justified 20-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
17 16 15 14 13 12 11 10 9
8
7 6
5
4 3
2
1
0
17 16 15 14 13 12 11 10 9 8
7
6
5
4 3
32 clocks
Figure 14. Format 5 - Right Justified 18-bit Data
3.3.1
OLM #1
OLM #1 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on
SDIN1. The last two channels are input on SDIN4.
LRCK
64 clks
64 clks
Left Channel
Right Channel
SCLK
SDIN1
MSB
LSB MSB
DAC_A1
20 clks
SDIN4
DAC_A4
20 clks
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
DAC_A2
DAC_A3
DAC_B1
DAC_B2
DAC_B3
20 clks
20 clks
20 clks
20 clks
20 clks
MSB
DAC_B4
20 clks
Figure 15. Format 8 - One Line Mode 1
DS671A1
21
CS4385
3.3.2
OLM #2
OLM #2 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on
SDIN1. The last two channels are input on SDIN4.
LRCK
128 clks
128 clks
Left Channel
Right Channel
SCLK
SDIN1
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB
DAC_A1
DAC_A2
DAC_A3
DAC_B1
DAC_B2
DAC_B3
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
DAC_A4
SDIN4
LSB MSB
MSB
DAC_B4
24 clks
24 clks
Figure 16. Format 9 - One Line Mode 2
3.3.3
OLM #3
OLM #3 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 256 Fs. Eight channels of MSB first 20-bit PCM data are input on
SDIN1.
LRCK
128 clks
128 clks
Left Channel
Right Channel
SCLK
SDIN1
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
DAC_A1
DAC_A2
DAC_A3
DAC_A4
DAC_B1
DAC_B2
DAC_B3
DAC_B4
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
MSB
Figure 17. Format 10 - One Line Mode 3
3.3.4
OLM #4
OLM #4 serial audio interface format operates in single, double, or quad-speed mode and
will slave to SCLK at 256 Fs. Eight channels of MSB first 24-bit PCM data are input on
SDIN1.
LRCK
128 clks
128 clks
Left Channel
Right Channel
SCLK
SDIN1
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB MSB
LSB
DAC_A1
DAC_A2
DAC_A3
DAC_A4
DAC_B1
DAC_B2
DAC_B3
DAC_B4
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
MSB
Figure 18. Format 11 - One Line Mode 4
22
DS671A1
CS4385
3.3.5
TDM
The TDM serial audio interface format operates in single, double, or quad-speed mode
and will slave to SCLK at 256 Fs. Data is received most significant bit first on the first
SCLK after an LRCK transition and is valid on the rising edge of SCLK. LRCK identifies
the start of a new frame and is equal to the sample rate, Fs. LRCK is sampled as valid on
the rising SCLK edge preceding the most significant bit of the first data sample and must
be held valid for one SCLK period. Each time slot is 32 bits wide, with the valid data sample left justified within the time slot with the remaining bits being zero padded.
256 clks
LRCK
SCLK
SDIN1
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
DAC_A1
DAC_A2
DAC_A3
DAC_A4
DAC_B1
DAC_B2
DAC_B3
DAC_B4
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Data
MSB
LSB
zero
Figure 19. Format 12 - TDM Mode
3.4
Oversampling Modes
The CS4385 operates in one of three oversampling modes based on the input sample rate. Mode
selection is determined by the M4, M3 and M2 pins in hardware mode or the FM bits in software
mode. Single-Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode supports input sample rates up to 200 kHz and uses
an oversampling ratio of 32x.
The auto-speed mode detect feature allows for the automatic selection of speed mode based off
of the incoming sample rate. This allows the CS4385 to accept a wide range of sample rates
with no external intervention necessary. The auto-speed mode detect feature is available in both
hardware and software mode.
3.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4385
incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” rolloff filter is available in each of Single, Double, and Quad Speed modes. These filters have been
designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit is used to
select which filter is used (see the Register Description section for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures
28 to 51.
DS671A1
23
CS4385
3.6
De-Emphasis
The CS4385 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to
accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise
reduction. Figure 20 shows the de-emphasis curve. The frequency response of the de-emphasis
curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not
match the coefficient which has been selected.
In software mode the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are
selected via the de-emphasis control bits.
In hardware mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the
input sample rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 20. De-Emphasis Curve
24
DS671A1
CS4385
3.7
ATAPI Specification
The CS4385 implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 9 on page 46 and Figure 21 for additional information.
A Channel
Volume
Control
Left Channel
Audio Data
Σ
SDINx
Right Channel
Audio Data
MUTE
Aout Ax
MUTE
AoutBx
Σ
B Channel
Volume
Control
Figure 21. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
3.8
Direct Stream Digital (DSD) Mode
In software mode the DSD/PCM bits (Reg. 02h) are used to configure the device for DSD mode.
The DSD_DIF bits (Reg 04h) then control the expected DSD rate and MCLK ratio.
The DIR_DSD bit (Reg 04h) selects between two proprietary methods for DSD to analog conversion. The first method uses a decimation free DSD processing technique which allows for features such as matched PCM level output, DSD volume control, and 50kHz on chip filter. The
second method sends the DSD data directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).
The DSD_PM_EN bit (Reg. 04h) selects Phase Modulation (data plus data inverted) as the style
of data input. In this mode the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used
for phase modulated 64x data (see Figure 22). Use of phase modulation mode may not directly
effect the performance of the CS4385, but may lower the sensitivity to board level routing of the
DSD data signals.
The CS4385 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4385 to alter the incoming invalid DSD data. Depending on the error, the data may either be attenuated or replaced with
a muted DSD signal (the MUTEC pins would be set according to the DAMUTE bit (Reg. 08h)).
DS671A1
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CS4385
More information for any of these register bits can be found in the Register Description section.
The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50%
modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at these levels is not guaranteed. If sustained +3 dB-SACD
levels are required, the digital volume control should be set to -3.0 dB. This same volume control
register affects PCM output levels. There is no need to change the volume control setting between PCM and DSD in order to have the 0dB output levels match (both 0 dBFS and 0 dB-SACD
will output at -3 dB in this case).
DSD Phase
Modulation Mode
DSD Normal Mode
BCKA
(64Fs)
Not Used
DSD_SCLK
BCKA
(128Fs)
DSD_SCLK
DSD_SCLK
BCKD
(64Fs)
Not Used
DSDAx,
DSDBx
D0
D0
D1
D1
D1
D2
D2
DSDAx,
DSDBx
Not Used
Figure 22. DSD phase modulation mode diagram
3.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4385 requires careful attention to power supply and
grounding arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to
clean supplies. If the ground planes are split between digital ground and analog ground, the GND
pins of the CS4385 should be connected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid
unwanted coupling into the DAC.
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3.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors
should be located on the same layer as the DAC. If desired, all supply pins with similar
voltage ratings may be connected to the same supply, but a decoupling capacitor should
still be placed on each supply pin.
Note: All decoupling capacitors should be referenced to analog ground.
The CDB4385 evaluation board demonstrates the optimum layout and power supply arrangements.
3.10 Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order Butterworth filter and differential to single-ended converter which was implemented on
the CS4385 evaluation board, CDB4385 Evaluation Board, as seen in Figure 24. The CS4385
does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. The offchip filter has been designed to attenuate the typical full-scale output level to below 2 Vrms.
Figure 23 shows how the full-scale differential analog output level specification is derived.
3.85 V
2.5 V
AOUT+
1.15 V
3.85 V
AOUT-
2.5 V
1.15 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 23. Full-Scale Output
DS671A1
27
CS4385
Figure 24. Recommended Output Filter
28
DS671A1
CS4385
3.11 The MUTEC Outputs
The MUTEC1 and MUTEC234 pins have an auto-polarity detect feature. The MUTEC output pins
are high impedance at the time of reset. The external mute circuitry needs to be self biased into
an active state in order to be muted during reset. Upon release of reset, the CS4385 will detect
the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive
when the mutes become active. The external-bias voltage level that the MUTEC pins see at the
time of release of reset must meet the “MUTEC auto detect input high/low voltage” specs as outlined in the Digital Characteristics section.
Figure 25 shows a single example of both an active high and an active low mute drive circuit. In
these designs, the pull-up and pull-down resistors have been especially chosen to meet the input
high/low threshold when used with the MMUN2111 and MMUN2211 internal bias resistances of
10 kΩ.
Use of the Mute Control function is not mandatory but recommended for designs requiring the
absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Figure 25. Recommended Mute Circuitry
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CS4385
3.12 Recommended Power-up Sequence
3.12.1 Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master
and left/right clocks are locked to the appropriate frequencies, as discussed in section 3.1.
In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ
will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all
other clocks are stable, and if possible the RST should be toggled low again once the system is stable.
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the Hardware power-up sequence after approximately 512 LRCK cycles in SingleSpeed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode).
3.12.2 Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are
locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to
VA/2.
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512
LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048
LRCK cycles in Quad-Speed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior
to the completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK
cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the
chip will enter Hardware mode and begin to operate with the M0-M4 as the mode settings.
CPEN bit may be written at anytime, even after the Hardware sequence has begun. It is
advised that if the CPEN bit can not be set in time then the SDINx pins should remain static low (this way no audio data can be converted incorrectly by the hardware mode settings).
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately
50 µs.
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3.13 Control Port Interface
The control port is used to load all the internal register settings in order to operate in software
mode (see section 5). The operation of the control port may be completely asynchronous with
the audio sample rate. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port operates in one of two modes: I2C or SPI.
3.13.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the
INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment
after each byte is written, allowing block reads or writes of successive registers.
3.13.2 I2C Mode
In the I2C mode, data is clocked into and out of the bi-directional serial control data line,
SDA, by the serial control port clock, SCL (see Figure 26 for the clock to data relationship).
There is no CS pin. Pin AD0 enables the user to alter the chip address
(001100[AD0][R/W]) and should be tied to VLC or GND as required, before powering up
the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected.
3.13.2.1 I2C Write
To write to the device, follow the procedure below while adhering to the control port
Switching Specifications in section 2.
1) Initiate a START condition to the I2C bus followed by the address byte. The upper
6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the
eighth must be 0. The eighth bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address
pointer, MAP. This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP.
4) If the INCR bit (see section 3.13.1) is set to 1, repeat the previous step until all the
desired registers are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is
necessary to initiate a repeated START condition and follow the procedure detailed
from step 1. If no further writes to other registers are desired, initiate a STOP condition
to the bus.
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CS4385
3.13.2.2 I2C Read
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I2C bus followed by the address byte. The upper
6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the
eighth must be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents
of the register pointed to by the MAP. The MAP register will contain the address of the
last register written to the MAP, or the default address (see section 3.13.1) if an I2C
read is the first operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP,
issue an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock and issue an ACK after each byte until all the
desired registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is
necessary to initiate a repeated START condition and follow the procedure detailed
from steps 1 and 2 from the I2C Write instructions followed by step 1 of the I2C Read
section. If no further reads from other registers are desired, initiate a STOP condition
to the bus.
N o te 1
SDA
0 01 1 00
ADDR
AD 0
R /W
ACK
D AT A
1-8
ACK
D A TA
1-8
ACK
SCL
S ta rt
S top
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
Figure 26. Control Port Timing, I2C Mode
32
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CS4385
3.13.3 SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control
port clock, CCLK (see Figure 27 for the clock to data relationship). There is no AD0 pin.
Pin CS is the chip select signal and is used to control SPI writes to the control port. When
the device detects a high to low transition on the AD0/CS pin after power-up, SPI mode
will be selected. All signals are inputs and data is clocked in on the rising edge of CCLK.
3.13.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port
Switching Specifications in Section 2.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 00110000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 3.13.1) is set to 1, repeat the previous step until all the
desired registers are written, then bring CS high.
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is
necessary to bring CS high, and follow the procedure detailed from step 1. If no further
writes to other registers are desired, bring CS high.
CS
C C LK
C H IP
ADDRESS
C DIN
0011000
MAP
R /W
D A TA
LSB
MSB
byte 1
byte n
M A P = M em ory A d dress P oin te r
Figure 27. Control Port Timing, SPI mode
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CS4385
3.14
Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.14.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
3.14.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
34
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CS4385
4.
REGISTER QUICK REFERENCE
Addr
Function
01h
Chip Revision
02h
Mode Control
default
default
03h
PCM Control
default
04h
DSD Control
default
05h
Filter Control
default
06h
Invert Control
07h
Group Control
default
default
08h
Ramp and Mute
default
09h
Mute Control
default
0Ah Mixing Control
Pair 1 (AOUTx1)
default
0Bh Vol. Control A1
default
0Ch Vol. Control B1
default
0Dh Mixing Control
Pair 2 (AOUTx1)
default
0Eh Vol. Control A2
default
0Fh Vol. Control B2
default
10h
Mixing Control
Pair 3 (AOUTx1)
default
11h
Vol. Control A3
12h
Vol. Control B3
default
default
13h
Mixing Control
Pair 4 (AOUTx1)
default
DS671A1
7
6
5
4
3
2
1
0
PART4
PART3
PART2
PART1
PART0
REV
REV
REV
0
0
1
x
x
0
0
CPEN
FREEZE
0
0
0
0
0
0
0
1
DIF3
DIF2
DIF1
DIF0
Reserved
Reserved
FM1
FM0
0
0
0
0
0
0
1
1
DSD/PCM DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS
DSD_DIF2 DSD_DIF1 DSD_DIF0 DIR_DSD
x
PDN
STATIC_D INVALID_D DSD_PM_ DSD_PM_
SD
SD
MD
EN
0
0
0
0
1
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FILT_SEL
0
0
0
0
0
0
0
0
INV_B4
INV_A4
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
0
0
0
0
0
0
0
0
Reserved
MUTEC
Reserved
P1_A=B
P2_A=B
P3_A=B
P4_A=B
SNGLVOL
0
0
1
0
0
1
0
0
SZC1
SZC0
RMP_UP
RMP_DN
PAMUTE
DAMUTE
MUTE_P1
MUTE_P0
1
0
0
0
0
0
0
0
MUTE_B4 MUTE_A4 MUTE_B3 MUTE_A3 MUTE_B2
MUTE_A2
MUTE_B1
MUTE_A1
0
0
0
0
0
0
0
0
Reserved
P1_DEM1
P1_DEM0
P1ATAPI4
P1ATAPI3
P1ATAPI2
P1ATAPI1
P1ATAPI0
0
0
1
0
1
0
0
1
A1_VOL7
A1_VOL6
A1_VOL5
A1_VOL4
A1_VOL3
A1_VOL2
A1_VOL1
A1_VOL0
0
0
0
0
0
0
0
0
B1_VOL7
B1_VOL6
B1_VOL5
B1_VOL4
B1_VOL3
B1_VOL2
B1_VOL1
B1_VOL0
0
0
0
0
0
0
0
0
Reserved
P2_DEM1
P2_DEM0
P2ATAPI4
P2ATAPI3
P2ATAPI2
P2ATAPI1
P2ATAPI0
0
0
1
0
1
0
0
1
A2_VOL7
A2_VOL6
A2_VOL5
A2_VOL4
A2_VOL3
A2_VOL2
A2_VOL1
A2_VOL0
0
0
0
0
0
0
0
0
B2_VOL7
B2_VOL6
B2_VOL5
B2_VOL4
B2_VOL3
B2_VOL2
B2_VOL1
B2_VOL0
0
0
0
0
0
0
0
0
Reserved
P3_DEM1
P3_DEM0
P3ATAPI4
P3ATAPI3
P3ATAPI2
P3ATAPI1
P3ATAPI0
0
0
1
0
1
0
0
1
A3_VOL7
A3_VOL6
A3_VOL5
A3_VOL4
A3_VOL3
A3_VOL2
A3_VOL1
A3_VOL0
0
0
0
0
0
0
0
0
B3_VOL7
B3_VOL6
B3_VOL5
B3_VOL4
B3_VOL3
B3_VOL2
B3_VOL1
B3_VOL0
0
0
0
0
0
0
0
0
Reserved
P4_DEM1
P4_DEM0
P4ATAPI4
P4ATAPI3
P4ATAPI2
P4ATAPI1
P4ATAPI0
0
0
1
0
1
0
0
1
35
CS4385
Addr
14h
Function
Vol. Control A4
default
15h
Vol. Control B4
default
16h
6
5
4
3
2
1
0
A4_VOL7
A4_VOL6
A4_VOL5
A4_VOL4
A4_VOL3
A4_VOL2
A4_VOL1
A4_VOL0
0
0
0
0
0
0
0
0
B4_VOL7
B4_VOL6
B4_VOL5
B4_VOL4
B4_VOL3
B4_VOL2
B4_VOL1
B4_VOL0
0
0
0
0
0
0
0
0
Reserved
MCLKDIV
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
PCM clock mode Reserved
default
36
7
0
DS671A1
CS4385
5.
REGISTER DESCRIPTION
Note:
All registers are read/write in I2C mode and write only in SPI, unless otherwise noted.
5.1
Chip Revision (address 01h)
7
PART4
0
5.1.1
6
PART3
0
5
PART2
0
4
PART1
0
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
PART NUMBER ID (PART) [READ ONLY]
00001- CS4385
REVISION ID (REV) [READ ONLY]
000 - Revision A
Function:
This read-only register can be used to identify the model and revision number of the device.
5.2
Mode Control 1 (address 02h)
7
CPEN
0
5.2.1
6
FREEZE
0
5
DSD/PCM
0
4
DAC4_DIS
0
3
DAC3_DIS
0
2
DAC2_DIS
0
1
DAC1_DIS
0
0
PDN
1
CONTROL PORT ENABLE (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean powerup, the user should write this bit within 10 ms following the release of Reset.
DS671A1
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CS4385
5.2.2
FREEZE CONTROLS (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
5.2.3
PCM/DSD SELECTION (DSD/PCM)
Default = 0
0 - PCM
1 - DSD
Function:
This function selects DSD or PCM Mode. The appropriate data and clocks should be present before
changing modes, or else MUTE should be selected.
5.2.4
DAC PAIR DISABLE (DACX_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power down bit is enabled to eliminate the
possibility of audible artifacts.
5.2.5
POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.
38
DS671A1
CS4385
5.3
PCM Control (address 03h)
7
DIF3
0
5.3.1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
Reserved
0
2
Reserved
0
1
FM1
1
0
FM0
1
DIGITAL INTERFACE FORMAT (DIF)
Default = 0000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The DSD/PCM bit determines whether
PCM or DSD mode is selected.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 9-19.
DIF3
DIF2
DIF1
DIF0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
0
0
0
0
1
X
0
0
1
1
0
0
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
X
DESCRIPTION
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
One-line Mode 1, 24-bit Data +SDIN4
One-line Mode 2, 20-bit Data +SDIN4
One-line Mode 3, 24-bit 6-channel
One-line Mode 4, 20-bit 6-channel
TDM
All other combinations are Reserved
Format
FIGURE
0
1
2
3
4
5
8
9
10
11
12
9
10
11
12
13
14
15
16
17
18
19
Table 7. Digital Interface Formats - PCM Mode
5.3.2
FUNCTIONAL MODE (FM)
Default = 11
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Auto Speed Mode detect (32 kHz to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or Auto Speed Mode.
DS671A1
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CS4385
5.4
DSD Control (address 04h)
7
DSD_DIF2
0
5.4.1
6
DSD_DIF1
0
5
DSD_DIF0
0
4
DIR_DSD
0
3
2
1
0
STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN
1
1
0
0
DSD MODE DIGITAL INTERFACE FORMAT (DSD_DIF)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD mode is selected.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIFO
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 8. Digital Interface Formats - DSD Mode
5.4.2
DIRECT DSD CONVERSION (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode the full scale DSD and PCM levels will not be matched (see Section 2), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available
(see section 2 for filter specifications).
5.4.3
STATIC DSD DETECT (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
40
DS671A1
CS4385
5.4.4
INVALID DSD DETECT (INVALID_DSD)
Function:
When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if detected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE
register.
When set to 0 (default), this function is disabled.
5.4.5
DSD PHASE MODULATION MODE SELECT (DSD_PM_MODE)
Function:
When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation
mode. (See Figure 22 on page 26)
When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
5.4.6
DSD PHASE MODULATION MODE ENABLE (DSD_PM_EN)
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
5.5
Filter Control (address 05h)
7
Reserved
0
5.5.1
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
FILT_SEL
0
INTERPOLATION FILTER SELECT (FILT_SEL)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in figures 28 to 51 found on the page 26.
DS671A1
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CS4385
5.6
Invert Control (address 06h)
7
INV_B4
0
5.6.1
6
INV_A4
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
2
P3_A=B
1
1
P4_A=B
0
0
SNGLVOL
0
INVERT SIGNAL POLARITY (INV_XX)
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
5.7
Group Control (address 07h)
7
Reserved
0
5.7.1
6
MUTEC
0
5
Reserved
1
4
P1_A=B
0
3
P2_A=B
0
MUTEC PIN CONTROL(MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to
‘0’, a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the
mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND
of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For
more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in
section 3.11.
5.7.2
CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes
are ignored when this function is enabled.
5.7.3
SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
42
DS671A1
CS4385
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel
Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
5.8
Ramp and Mute (address 08h)
7
SZC1
1
5.8.1
6
SZC0
0
5
RMP_UP
0
4
RMP_DN
0
3
PAMUTE
0
2
DAMUTE
0
1
MUTE_P1
0
0
MUTE_P0
0
SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
5.8.2
SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Function:
DS671A1
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CS4385
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a
LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
5.8.3
SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
5.8.4
PCM AUTO-MUTE (PAMUTE)
Function:
When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be
retained and the Mute Control pin will go active during the mute period.
When set to 0 this function is disabled.
5.8.5
DSD AUTO-MUTE (DAMUTE)
Function:
When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification).
A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained and
the Mute Control pin will go active during the mute period.
44
DS671A1
CS4385
5.8.6
MUTE POLARITY AND DETECT (MUTEP1:0)
Default = 00
00 - Auto polarity detect, selected from MUTEC1 pin
01 - Reserved
10 - Active low mute polarity
11 - Active high mute polarity
Function:
Auto mute polarity detect (00)
See section 3.11 on page 29 for description.
Active low mute polarity (10)
When RST is low the outputs are high impedance and will need to be biased active. Once reset has been
released and after this bit is set, the MUTEC output pins will be active low polarity.
Active high mute polarity (11)
At reset time the outputs are high impedance and will need to be biased active. Once reset has been
released and after this bit is set, the MUTEC output pins will be active high polarity.
5.9
Mute Control (address 09h)
7
MUTE_B4
0
5.9.1
6
MUTE_A4
0
5
MUTE_B3
0
4
MUTE_A3
0
3
MUTE_B2
0
2
MUTE_A2
0
1
MUTE_B1
0
0
MUTE_A1
0
MUTE (MUTE_XX)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will
be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross
bits. The MUTE pins will go active during the mute period according to the MUTEC bit.
DS671A1
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CS4385
5.10
Mixing Control (address 0Ah, 0Dh, 10h, 13h)
7
Reserved
0
6
Px_DEM1
0
5
Px_DEM0
1
4
PxATAPI4
0
3
PxATAPI3
1
2
PxATAPI2
0
1
PxATAPI1
0
0
PxATAPI0
1
5.10.1 DE-EMPHASIS CONTROL (PX_DEM1:0)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 20)
De-emphasis is only available in Single Speed Mode.
5.10.2 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions
are applied per A-B pair. Refer to Table 14 and Figure 21 for additional information.
ATAPI4
0
0
0
0
0
0
0
0
0
0
0
0
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
AOUTBx
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
Table 9. ATAPI Decode
46
DS671A1
CS4385
ATAPI4
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ATAPI3
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTAx
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
AOUTBx
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 9. ATAPI Decode
DS671A1
47
CS4385
5.11
Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h)
7
xx_VOL7
0
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
xx_VOL1
0
0
xx_VOL0
0
These eight registers provide individual volume and mute control for each of the eight channels.
The values for “xx” in the bit fields above are as follows:
Register address 0Bh - xx = A1
Register address 0Ch - xx = B1
Register address 0Eh - xx = A2
Register address 0Fh - xx = B2
Register address 11h - xx = A3
Register address 12h - xx = B3
Register address 14h - xx = A4
Register address 15h - xx = B4
5.11.1 DIGITAL VOLUME CONTROL (XX_VOL7:0)
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 15. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that
the values in the volume setting column in Table 15 are approximate. The actual attenuation is determined
by taking the decimal value of the volume register and multiplying by 6.02/12.
Table 10. Example Digital Volume Settings
Binary Code
00000000
00000001
00000110
11111111
5.12
Decimal Value
0
1
6
255
Volume Setting
0 dB
-0.5 dB
-3.0 dB
-127.5 dB
PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
5.12.1 MASTER CLOCK DIVIDE BY 2 ENABLE (MCLKDIV)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
48
DS671A1
CS4385
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4385 Evaluation Board Datasheet
3. “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note
AN48
4. “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
DS671A1
49
CS4385
8. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
4°
MAX
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
MIN
--0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.22
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS022
50
DS671A1
CS4385
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
9. APPENDIX
−60
−60
−80
−80
−100
−100
−120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
−120
0.4
1
Figure 28. Single Speed (fast) Stopband Rejection
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 29. Single Speed (fast) Transition Band
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
0
0
−20
−20
−40
−40
−60
−80
−100
−100
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 32. Single Speed (slow) Stopband Rejection
DS671A1
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
−60
−80
−120
0.4
0.05
Figure 31. Single Speed (fast) Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 30. Single Speed (fast) Transition Band (detail)
0
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 33. Single Speed (slow) Transition Band
51
CS4385
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
Figure 34. Single Speed (slow) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 35. Single Speed (slow) Passband Ripple
0
60
60
80
80
100
100
120
0
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 36. Double Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 37. Double Speed (fast) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 38. Double Speed (fast) Transition Band (detail)
52
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 39. Double Speed (fast) Passband Ripple
DS671A1
CS4385
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 40. Double Speed (slow) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 41. Double Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 42. Double Speed (slow) Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
Frequency(normalized to Fs)
0.25
0.3
0.35
60
80
80
100
100
120
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 44. Quad Speed (fast) Stopband Rejection
DS671A1
0.1
0
20
0.2
0.05
Figure 43. Double Speed (slow) Passband Ripple
0
120
0
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 45. Quad Speed (fast) Transition Band
53
CS4385
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 46. Quad Speed (fast) Transition Band (detail)
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 47. Quad Speed (fast) Passband Ripple
0
0
20
40
40
Amplitude (dB)
Amplitude (dB)
20
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 48. Quad Speed (slow) Stopband Rejection
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 49. Quad Speed (slow) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 50. Quad Speed (slow) Transition Band (detail)
54
0.02
0
0.02
0.04
0.06
0.08
Frequency(normalized to Fs)
0.1
0.12
Figure 51. Quad Speed (slow) Passband Ripple
DS671A1
CS4385
Table 11. Revision History
Release
A1
Date
OCT 2004
Changes
Initial Release
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes.Cirrus Logic, Inc. and its subsidiaries ("Cirrus")
believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS
IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
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those components in a standard I2C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
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DS671A1