Freescale MPC8306SEC Powerquicc ii pro integrated communications processor family hardware specification Datasheet

Document Number: MPC8306SEC
Rev. 1, 09/2011
Freescale Semiconductor
Technical Data
MPC8306S
PowerQUICC II Pro Integrated
Communications Processor
Family Hardware Specifications
This document provides an overview of the MPC8306S
PowerQUICC II Pro processor features. The MPC8306S is
a cost-effective, highly integrated communications
processor that addresses the requirements of several
networking applications, including residential gateways,
modem/routers, industrial control, and test and measurement
applications. The MPC8306S extends current PowerQUICC
offerings, adding higher CPU performance, additional
functionality, and faster interfaces, while addressing the
requirements related to time-to-market, price, power
consumption, and board real estate. This document describes
the electrical characteristics of MPC8306S.
To locate published errata or updates for this document, refer
to the MPC8306S product summary page on our website
listed on the back cover of this document or contact your
local Freescale sales office.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 12
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ethernet and MII Management . . . . . . . . . . . . . . . . . 21
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 44
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
System Design Information . . . . . . . . . . . . . . . . . . . 64
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 67
Document Revision History . . . . . . . . . . . . . . . . . . . 69
Overview
1
Overview
The MPC8306S incorporates the e300c3 (MPC603e-based) core built on Power Architecture®
technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and
on-chip memory management units (MMUs). The MPC8306S also includes two DMA engines and a
16-bit DDR2 memory controller.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8306S. The QUICC Engine block contains several peripheral controllers and a
32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). A block diagram of the MPC8306S is shown in the following figure.
2 x DUART
I2C
Timers
GPIO
SPI
RTC
e300c3 Core with Power
Management
16-KB
I-Cache
Interrupt
Controller
16-KB
D-Cache
FPU
DDR2
Controller
16 KB Multi-User RAM
48 KB Instruction RAM
UCC7
UCC5
UCC3
UCC2
Single 32-bit RISC CP Serial DMA
UCC1
Baud Rate
Generators
Enhanced Local
USB 2.0 HS
Host/Device/OTG Bus Controller
DMA
Engine
QUICC Engine™ Block
Accelerators
ULPI
Time Slot Assigner
Serial Interface
2x TDM Ports
3 RMII/MII
2x HDLC
Figure 1. MPC8306S Block Diagram
Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII
Ethernet, HDLC and TDM.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
2
Freescale Semiconductor
Overview
In summary, the MPC8306S provides users with a highly integrated, fully programmable communications
processor. This helps to ensure that a low-cost system solution can be quickly developed and offers
flexibility to accommodate new standards and evolving system requirements.
1.1
Features
The major features of the device are as follows:
• e300c3 Power Architecture processor core
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
• QUICC Engine block
— 32-bit RISC controller for flexible support of the communications peripherals with the
following features:
– One clock per instruction
– Separate PLL for operating frequency that is independent of system’s bus and e300 core
frequency for power and performance optimization
– 32-bit instruction object code
– Executes code from internal IRAM
– 32-bit arithmetic logic unit (ALU) data path
– Modular architecture allowing for easy functional enhancements
– Slave bus for CPU access of registers and multiuser RAM space
– 48 Kbytes of instruction RAM
– 16 Kbytes of multiuser data RAM
– Serial DMA channel for receive and transmit on all serial channels
— Five unified communication controllers (UCCs) supporting the following protocols and
interfaces:
– 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces.
– HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8)
– HDLC Bus (bit rate up to 10 Mbps)
– Asynchronous HDLC (bit rate up to 2 Mbps)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
3
Overview
•
•
•
– Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each
running at 64 kbps
For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference
Manual with Protocol Interworking.
DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— 16-bit data interface, up to 266-MHz data rate
— 14 address lines
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), 256-Mbyte per chip select for 16 bit data interface.
– 64-Mbit to 2-Gbit devices with x8/x16 data ports (no direct x4 support)
– One 16-bit device or two 8-bit devices on a 16-bit bus,
— Support for up to 16 simultaneous open pages for DDR2
— One clock pair to support up to 4 DRAM devices
— Supports auto refresh
— On-the-fly power management using CKE
Enhanced local bus controller (eLBC)
— Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz
— Eight chip selects supporting eight external slaves
– Four chip selects dedicated
– Four chip selects offered as multiplexed option
— Supports boot from parallel NOR Flash and parallel NAND Flash
— Supports programmable clock ratio dividers
— Up to eight-beat burst transfers
— 16- and 8-bit ports, separate LWE for each 8 bit
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
— Variable memory block sizes for FCM, GPCM, and UPM mode
— Default boot ROM chip select with configurable bus width (8 or 16)
— Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC
slave devices
Integrated programmable interrupt controller (IPIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for external and internal discrete interrupt sources
— Programmable highest priority request
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
4
Freescale Semiconductor
Overview
•
•
•
•
•
•
— Six groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Unique vector number for each interrupt source
Universal serial bus (USB) dual-role controller
— Designed to comply with Universal Serial Bus Revision 2.0 Specification
— Supports operation as a stand-alone USB host controller
— Supports operation as a stand-alone USB device
— Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.
Low speed is only supported in host mode.
Dual I2C interfaces
— Two-wire interface
— Multiple-master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— I2C1 can be used as the boot sequencer
DMA Engine
— Support for the DMA engine with the following features:
– Sixteen DMA channels
– All data movement via dual-address transfers: read from source, write to destination
– Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
– Channel activation via one of two methods (for both the methods, one activation per
execution of the minor loop is required):
– Explicit software initiation
– Initiation via a channel-to-channel linking mechanism for continuous transfers
(independent channel linking at end of minor loop and/or major loop)
– Support for fixed-priority and round-robin channel arbitration
– Channel completion reported via optional interrupt requests
— Support for scatter/gather DMA processing
DUART
— Two 2-wire interfaces (RxD, TxD)
– The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Serial peripheral interface (SPI)
— Master or slave support
Power managemnt controller (PMC)
— Supports core doze/nap/sleep/ power management
— Exits low power state and returns to full-on mode when
– The core internal time base unit invokes a request to exit low power state
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
5
Electrical Characteristics
•
•
•
•
2
– The power management controller detects that the system is not idle and there are
outstanding transactions on the internal bus or an external interrupt.
Parallel I/O
— General-purpose I/O (GPIO)
– 56 parallel I/O pins multiplexed on various chip interfaces
– Interrupt capability
System timers
— Periodic interrupt timer
— Software watchdog timer
— Eight general-purpose timers
Real time clock (RTC) module
— Maintains a one-second count, unique over a period of thousands of years
— Two possible clock sources:
– External RTC clock (RTC_PIT_CLK)
– CSB bus clock
IEEE Std. 1149.1™ compliant JTAG boundary scan
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8306S. The MPC8306S is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
The following table provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.26
V
—
PLL supply voltage
AVDD1
AVDD2
AVDD3
–0.3 to 1.26
V
—
GVDD
–0.3 to 1.98
V
—
OVDD
–0.3 to 3.6
V
2
DDR2 DRAM I/O voltage
Local bus, DUART, system control and power management,
SPI, MII, RMII, MII management, USB and JTAG I/O voltage
I2C,
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
6
Freescale Semiconductor
Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic
Input voltage
DDR2 DRAM signals
DDR2 DRAM reference
Local bus, DUART, SYS_CLK_IN,
system control and power
management, I2C, SPI, and JTAG
signals
Storage temperature range
Symbol
Max Value
Unit
Notes
MVIN
–0.3 to (GVDD + 0.3)
V
3
MVREF
–0.3 to (GVDD + 0.3)
V
3
OVIN
–0.3 to (OVDD + 0.3)
V
4
TSTG
–55 to 150
C
—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
7
Electrical Characteristics
2.1.2
Power Supply Voltage Specification
The following table provides the recommended operating conditions for the MPC8306S. Note that these
values are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Symbol
Recommended
Value
Unit
Note
Core supply voltage
VDD
1.0 V ± 50 mV
V
1
PLL supply voltage
AVDD1
AVDD2
AVDD3
1.0 V ± 50 mV
V
1
GVDD
1.8 V ± 100 mV
V
1
OVDD
3.3 V ± 300 mV
V
1, 3
TA/TJ
0 to 105
C
2
Characteristic
DDR2 DRAM I/O voltage
Local bus, DUART, system control and power management, I
SPI, MII, RMII, MII management, USB and JTAG I/O voltage
Junction temperature
2C,
Notes:
1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
direction.
2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction
Temperature).
3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map.
The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306S
G/OVDD + 20%
G/OVDD + 5%
VIH
G/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
8
Freescale Semiconductor
Electrical Characteristics
2.1.3
Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths.
Table 3. Output Drive Capability
Output Impedance
()
Supply Voltage (V)
Local bus interface utilities signals
42
OVDD = 3.3
DDR2 signal
18
GVDD = 1.8
DUART, system control, I2C, SPI, JTAG
42
OVDD = 3.3
GPIO signals
42
OVDD = 3.3
Driver Type
2.1.4
Input Capacitance Specification
The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306S.
Table 4. Input Capacitance Specification
Parameter/Condition
Input capacitance for all pins except SYS_CLK_IN and
QE_CLK_IN
Input capacitance for SYS_CLK_IN and QE_CLK_IN
Symbol
Min
Max
Unit
Note
CI
6
8
pF
—
CICLK_IN
10
—
pF
1
Note:
1. The external clock generator should be able to drive 10 pF.
2.2
Power Sequencing
The device does not require the core supply voltage (VDD) and I/O supply voltages (GVDD and OVDD) to
be applied in any particular order. Note that during power ramp-up, before the power supplies are stable
and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input
and output pins are actively driven and cause contention and excessive current. In order to avoid actively
driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O
voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case
where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before
the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are
stable, wait for a minimum of 32 clock cycles before negating PORESET.
NOTE
There is no specific power down sequence requirement for the device. I/O
voltage supplies (GVDD and OVDD) do not have any ordering requirements
with respect to one another.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
9
Power Characteristics
I/O Voltage (GVDD and OVDD)
V
Core Voltage (VDD)
0.7 V
90%
0
t
PORESET
>= 32  tSYS_CLK_IN
Figure 3. MPC8306S Power-Up Sequencing Example
3
Power Characteristics
The typical power dissipation for this family of MPC8306S devices is shown in the following table.
Table 5.
MPC8306S Power Dissipation
Core
Frequency (MHz)
QUICC Engine
Frequency (MHz)
CSB
Frequency (MHz)
Typical
Maximum
Unit
Note
133
133
133
0.272
0.618
W
1, 2, 3
200
233
133
0.291
0.631
W
1, 2, 3
266
233
133
0.451
0.925
W
1, 2, 3
333
233
133
0.471
0.950
W
1, 2, 3
Notes:
1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power. For I/O power
values, see Table 6.
2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and a smoke test code.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
10
Freescale Semiconductor
Clock Input Timing
The following table shows the estimated typical I/O power dissipation for the device.
Table 6. Typical I/O Power Dissipation
Interface
Parameter
DDR I/O
65% utilization
1.8 V
Rs = 20 
Rt = 50 
1 pair of clocks
266 MHz, 1  16 bits
Local bus I/O load = 25 pF
1 pair of clocks
66 MHz, 26 bits
QUICC Engine block and other I/Os
TDM serial, HDLC/TRAN serial,
DUART, MII, RMII, Ethernet
management, USB, SPI, Timer
output,
GVDD
(1.8 V)
OVDD
(3.3 V)
Unit
Comments
0.141
—
W
—
—
0.150
W
1
Note:
1. Typical I/O power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone
benchmark application. The measurements were taken on the evaluation board using WC process silicon.
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8306S.
NOTE
The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This
should be enforced especially on clock signals. Rise time refers to signal
transitions from 10% to 90% of OVDD; fall time refers to transitions from
90% to 10% of OVDD.
4.1
DC Electrical Characteristics
The following table provides the clock input (SYS_CLK_IN) DC specifications for the MPC8306S. These
specifications are also applicable for QE_CLK_IN.
Table 7. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.4
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
SYS_CLK_IN input current
0 V  VIN  OVDD
IIN
—
±5
A
SYS_CLK_IN input current
0 V  VIN  0.5 V or
OVDD – 0.5 V  VIN OVDD
IIN
—
±5
A
SYS_CLK_IN input current
0.5 V  VIN  OVDD – 0.5 V
IIN
—
±50
A
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
11
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the MPC8306S is SYS_CLK_IN. The following table provides the clock
input (SYS_CLK_IN) AC timing specifications for the MPC8306S. These specifications are also
applicable for QE_CLK_IN.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
SYS_CLK_IN frequency
fSYS_CLK_IN
24
—
66.67
MHz
1
SYS_CLK_IN cycle time
tSYS_CLK_IN
15
—
41.6
ns
—
tKH, tKL
1.1
—
2.8
ns
2
tKHK/tSYS_CLK_
40
—
60
%
3
—
—
±150
ps
4, 5
SYS_CLK_IN rise and fall time
SYS_CLK_IN duty cycle
IN
SYS_CLK_IN jitter
—
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).
5
RESET Initialization
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8306S. The following table provides the reset initialization AC timing specifications for the reset
component(s).
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
—
tSYS_CLK_IN
1
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN
32
—
tSYS_CLK_IN
1
HRESET assertion (output)
512
—
tSYS_CLK_IN
1
Input setup time for POR configuration signals
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET
4
—
tSYS_CLK_IN
1, 2
Input hold time for POR config signals with respect to negation of
HRESET
0
—
ns
1, 2
Notes:
1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306S PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual.
2. POR configuration signals consist of CFG_RESET_SOURCE[0:3].
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
12
Freescale Semiconductor
DDR2 SDRAM
The following table provides the PLL lock times.
Table 10. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Note
—
100
s
—
PLL lock times
5.1
Reset Signals DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S reset signals mentioned
in Table 9.
Table 11. Reset Signals DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Note
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
1
Input low voltage
VIL
—
–0.3
0.8
V
—
Input current
IIN
0 V  VIN  OVDD
—
±5
A
—
Note:
1. This specification applies when operating from 3.3 V supply.
6
DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the
MPC8306S. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V.
6.1
DDR2 SDRAM DC Electrical Characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM component(s)
of the MPC8306S when GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
GVDD
1.7
1.9
V
1
MVREF
0.49  GVDD
0.51  GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF+ 0.125
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
–9.9
9.9
A
4
I/O supply voltage
I/O reference voltage
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
13
DDR2 SDRAM
Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)
Parameter/Condition
Symbol
Min
Max
Unit
Note
Output high current (VOUT = 1.35 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5  GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V  VOUT GVDD.
The following table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA = 25 °C, VOUT = GVDD  2,
VOUT (peak-to-peak) = 0.2 V.
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V).
Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with GVDD of 1.8 V± 100mV.
Parameter
Symbol
Min
Max
Unit
Note
AC input low voltage
VIL
—
MVREF – 0.25
V
—
AC input high voltage
VIH
MVREF + 0.25
—
V
—
The following table provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 15. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Controller skew for MDQS—MDQ/MDM
Symbol
tCISKEW
Min
Max
Unit
Note
ps
1, 2
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
14
Freescale Semiconductor
DDR2 SDRAM
Table 15. DDR2 SDRAM Input AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
Symbol
266 MHz
Min
Max
–750
750
Unit
Note
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute
value of tCISKEW.
The following figure shows the input timing diagram for the DDR controller.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 4. DDR Input Timing Diagram
6.2.2
DDR2 SDRAM Output AC Timing Specifications
The following table provides the output AC timing specifications for the DDR2 SDRAM interfaces.
Table 16. DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Parameter
MCK cycle time, (MCK/MCK crossing)
ADDR/CMD output setup with respect to MCK
Symbol1
Min
Max
Unit
Note
tMCK
5.988
8
ns
2
ns
3
2.5
—
ns
3
2.5
—
ns
3
tDDKHAS
266 MHz
ADDR/CMD output hold with respect to MCK
tDDKHAX
266 MHz
MCS output setup with respect to MCK
tDDKHCS
266 MHz
2.5
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
15
DDR2 SDRAM
Table 16. DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of 1.8V ± 100mV.
Symbol1
Parameter
MCS output hold with respect to MCK
Min
Max
2.5
—
–0.6
0.6
tDDKHCX
266 MHz
MCK to MDQS Skew
tDDKHMH
MDQ/MDM output setup with respect to MDQS
tDDKHDS,
tDDKLDS
266 MHz
MDQ/MDM output hold with respect to MDQS
0.9
Note
ns
3
ns
4
ns
5
ps
5
—
tDDKHDX,
tDDKLDX
266 MHz
Unit
1100
—
MDQS preamble start
tDDKHMP
0.75 x tMCK
—
ns
6
MDQS epilogue end
tDDKHME
0.4 x tMCK
0.6 x tMCK
ns
6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD
setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied
cycle.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjusts in the
CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference
Manual for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data
mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. tDDKHMP follows the symbol conventions described in note 1.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
16
Freescale Semiconductor
DDR2 SDRAM
The following figure shows the DDR SDRAM output timing for the MCK to MDQS skew measurement
(tDDKHMH).
MCK
MCK
tMCK
tDDKHMH(max) = 0.6 ns
MDQS
tDDKHMH(min) = –0.6 ns
MDQS
Figure 5. Timing Diagram for tDDKHMH
The following figure shows the DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]/
MECC[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 6. DDR2 SDRAM Output Timing Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
17
Local Bus
7
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8306S.
7.1
Local Bus DC Electrical Characteristics
The following table provides the DC electrical characteristics for the local bus interface.
Table 17. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 A
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 A
VOL
—
0.2
V
IIN
—
±5
A
Input current
7.2
Local Bus AC Electrical Specifications
The following table describes the general timing parameters of the local bus interface of the MPC8306S.
Table 18. Local Bus General Timing Parameters
Symbol1
Min
Max
Unit
Note
tLBK
15
—
ns
2
Input setup to local bus clock (LCLKn)
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock (LCLKn)
tLBIXKH
1.0
—
ns
3, 4
Local bus clock (LCLKn) to output valid
tLBKHOV
—
3
ns
3
Local bus clock (LCLKn) to output high impedance for LAD/LDP
tLBKHOZ
—
4
ns
5
Parameter
Local bus cycle time
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4  OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
18
Freescale Semiconductor
Local Bus
The following figure provides the AC test load for the local bus.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 7. Local Bus AC Test Load
The following figures show the local bus signals. These figures has been given indicate timing parameters
only and do not reflect actual functional operation of interface.
LCLK[n]
tLBIVKH
Input Signals:
LAD[0:15]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
tLBIXKH
tLBIXKH
tLBKHOV
Output Signals:
LBCTL/LBCKE/LOE
tLBKHOV
tLBKHOZ
Output Signals:
LAD[0:15]
tLBOTOT
LALE
Figure 8. Local Bus Signals
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
19
Local Bus
LCLK
T1
T3
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:15]/LDP[0:3]
tLBKHOV
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
20
Freescale Semiconductor
Ethernet and MII Management
LCLK
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
tLBIXKH
Input Signals:
LAD[0:15]
tLBKHOV
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:1]/LGPL[0:5]
Figure 10. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4
8
Ethernet and MII Management
This section provides the AC and DC electrical characteristics for Ethernet interfaces.
8.1
Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all MII (media independent interface) and RMII
(reduced media independent interface), except MDIO (management data input/output) and MDC
(management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO
and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
DC Electrical Characteristics
All MII and RMII drivers and receivers comply with the DC parametric attributes specified in The
following table.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
21
Ethernet and MII Management
Table 19. MII and RMII DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage 3.3 V
OVDD
—
3
3.6
V
Output high voltage
VOH
IOH = –4.0 mA
OVDD = Min
2.40
OVDD + 0.3
V
Output low voltage
VOL
IOL = 4.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
—
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
—
–0.3
0.90
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
8.2
MII and RMII AC Timing Specifications
The AC timing specifications for MII and RMII are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
The following table provides the MII transmit AC timing specifications.
Table 20. MII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
1
5
15
ns
TX_CLK data clock rise VIL(min) to VIH(max)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall VIH(max) to VIL(min)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
22
Freescale Semiconductor
Ethernet and MII Management
The following figure provides the AC test load.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 11. AC Test Load
The following figure shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 12. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
The following table provides the MII receive AC timing specifications.
Table 21. MII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input
signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
23
Ethernet and MII Management
The following figure shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXF
tMRXH
RXD[3:0]
RX_DV
RX_ER
Valid Data
tMRDVKH
tMRDXKH
Figure 13. MII Receive AC Timing Diagram
8.2.2
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.2.1
RMII Transmit AC Timing Specifications
The following table provides the RMII transmit AC timing specifications.
Table 22. RMII Transmit AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
REF_CLK to RMII data TXD[1:0], TX_EN delay
tRMTKHDX
2
—
13
ns
REF_CLK data clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock
REF_CLK duty cycle
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII
transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
The following figure provides the AC test load.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 14. AC Test Load
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
24
Freescale Semiconductor
Ethernet and MII Management
The following figure shows the RMII transmit AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXH
tRMXF
TXD[1:0]
TX_EN
tRMTKHDX
Figure 15. RMII Transmit AC Timing Diagram
8.2.2.2
RMII Receive AC Timing Specifications
The following table provides the RMII receive AC timing specifications.
Table 23. RMII Receive AC Timing Specifications
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
—
ns
REF_CLK clock rise VIL(min) to VIH(max)
tRMXR
1.0
—
4.0
ns
REF_CLK clock fall time VIH(max) to VIL(min)
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock period
REF_CLK duty cycle
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock
reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect
to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
25
Ethernet and MII Management
The following figure shows the RMII receive AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXF
tRMXH
RXD[1:0]
CRS_DV
RX_ER
Valid Data
tRMRDVKH
tRMRDXKH
Figure 16. RMII Receive AC Timing Diagram
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for
MDIO and MDC are provided in the following table.
Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Supply voltage (3.3 V)
Symbol
Conditions
Min
Max
Unit
OVDD
—
3
3.6
V
Output high voltage
VOH
IOH = –1.0 mA
OVDD = Min
2.40
OVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
—
2.00
—
V
Input low voltage
VIL
—
—
0.80
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
8.3.2
MII Management AC Electrical Specifications
The following table provides the MII management AC timing specifications.
Table 25. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
Note
MDC frequency
fMDC
—
2.5
—
MHz
—
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
Parameter/Condition
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
26
Freescale Semiconductor
Ethernet and MII Management
Table 25. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 300mV.
Symbol1
Min
Typical
Max
Unit
Note
MDC to MDIO delay
tMDKHDX
10
—
70
ns
—
MDIO to MDC setup time
tMDDVKH
8.5
—
—
ns
—
MDIO to MDC hold time
tMDDXKH
0
—
—
ns
—
MDC rise time
tMDCR
—
—
10
ns
—
MDC fall time
tMDHF
—
—
10
ns
—
Parameter/Condition
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
The following figure shows the MII management AC timing diagram.
tMDC
tMDCR
MDC
tMDCH
tMDCF
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 17. MII Management Interface Timing Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
27
TDM/SI
9
TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial
interface of the MPC8306S.
9.1
TDM/SI DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S TDM/SI.
Table 26. TDM/SI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
9.2
TDM/SI AC Timing Specifications
The following table provides the TDM/SI input and output AC timing specifications.
Table 27. TDM/SI AC Timing Specifications1
Symbol2
Min
Max
Unit
TDM/SI outputs—External clock delay
tSEKHOV
2
14
ns
TDM/SI outputs—External clock High Impedance
tSEKHOX
2
10
ns
TDM/SI inputs—External clock input setup time
tSEIVKH
5
—
ns
TDM/SI inputs—External clock input hold time
tSEIXKH
2
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI
outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
The following figure provides the AC test load for the TDM/SI.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 18. TDM/SI AC Test Load
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
28
Freescale Semiconductor
HDLC
The following figure represents the AC timing from Table 27. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
TDM/SICLK (Input)
tSEIXKH
tSEIVKH
Input Signals:
TDM/SI
(See Note)
tSEKHOV
Output Signals:
TDM/SI
(See Note)
tSEKHOX
Note: The clock edge is selectable on TDM/SI.
Figure 19. TDM/SI AC Timing (External Clock) Diagram
10 HDLC
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
of the MPC8306S.
10.1
HDLC DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S HDLC protocol.
Table 28. HDLC DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V  VIN OVDD
—
±5
A
10.2
HDLC AC Timing Specifications
The following table provides the input and output AC timing specifications for HDLC protocol.
Table 29. HDLC AC Timing Specifications1
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tHIKHOV
0
9
ns
Outputs—External clock delay
tHEKHOV
1
12
ns
Outputs—Internal clock high impedance
tHIKHOX
0
5.5
ns
Characteristic
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
29
HDLC
Table 29. HDLC AC Timing Specifications1 (continued)
Symbol2
Min
Max
Unit
tHEKHOX
1
8
ns
Inputs—Internal clock input setup time
tHIIVKH
9
—
ns
Inputs—External clock input setup time
tHEIVKH
4
—
ns
Inputs—Internal clock input hold time
tHIIXKH
0
—
ns
Inputs—External clock input hold time
tHEIXKH
1
—
ns
Characteristic
Outputs—External clock high impedance
Notes:
1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
The following figure provides the AC test load.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 20. AC Test Load
Figure 21 and Figure 22 represent the AC timing from Table 29. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
The following figure shows the timing with external clock.
Serial CLK (Input)
tHEIVKH
tHEIXKH
Input Signals:
(See Note)
tHEKHOV
Output Signals:
(See Note)
tHEKHOX
Note: The clock edge is selectable.
Figure 21. AC Timing (External Clock) Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
30
Freescale Semiconductor
USB
The following figure shows the timing with internal clock.
Serial CLK (Output)
tHIIVKH
tHIIXKH
Input Signals:
(See Note)
tHIKHOV
Output Signals:
(See Note)
Note: The clock edge is selectable.
tHIKHOX
Figure 22. AC Timing (Internal Clock) Diagram
11 USB
11.1
USB Controller
This section provides the AC and DC electrical specifications for the USB (ULPI) interface.
11.1.1
USB DC Electrical Characteristics
The following table provides the DC electrical characteristics for the USB interface.
Table 30. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—
±5
A
High-level output voltage, IOH = –100 A
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 A
VOL
—
0.2
V
11.1.2
USB AC Electrical Specifications
The following table describes the general timing parameters of the USB interface.
Table 31. USB General Timing Parameters
Symbol1
Min
Max
Unit
Note
tUSCK
15
—
ns
—
Input setup to USB clock—all inputs
tUSIVKH
4
—
ns
—
input hold to USB clock—all inputs
tUSIXKH
1
—
ns
—
USB clock to output valid—all outputs (except
USBDR_STP_USBDR_STP)
tUSKHOV
—
7
ns
—
Parameter
USB clock cycle time
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
31
USB
Table 31. USB General Timing Parameters (continued)
Symbol1
Min
Max
Unit
Note
USB clock to output valid—USBDR_STP
tUSKHOV
—
7.5
ns
—
Output hold from USB clock—all outputs
tUSKHOX
2
—
ns
—
Parameter
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing
(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX
symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or
output hold time.
The following figures provide the AC test load and signals for the USB, respectively.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 23. USB AC Test Load
USBDR_CLK
tUSIVKH
tUSIXKH
Input Signals
tUSKHOV
tUSKHOX
Output Signals
Figure 24. USB Signals
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
32
Freescale Semiconductor
DUART
12 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306S.
12.1
DUART DC Electrical Characteristics
The following table provides the DC electrical characteristics for the DUART interface of the MPC8306S.
Table 32. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage OVDD
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 A
VOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 A
VOL
—
0.2
V
IIN
—
±5
A
Input current (0 V VIN OVDD
)1
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
12.2
DUART AC Electrical Specifications
The following table provides the AC timing parameters for the DUART interface of the MPC8306S.
Table 33. DUART AC Timing Specifications
Parameter
Value
Unit
Note
Minimum baud rate
256
baud
—
Maximum baud rate
>1,000,000
baud
1
16
—
2
Oversample rate
Notes:
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
33
I2 C
13 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8306S.
13.1
I2C DC Electrical Characteristics
The following table provides the DC electrical characteristics for the I2C interface of the MPC8306S.
Table 34. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 300mV.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7  OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3  OVDD
V
—
Low level output voltage
VOL
0
0.4
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1  CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
0
50
ns
3
Capacitance for each I/O pin
CI
—
10
pF
—
Input current (0 V VIN OVDD)
IIN
—
±5
A
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for information
on the digital filter used.
4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off.
13.2
I2C AC Electrical Specifications
The following table provides the AC timing parameters for the I2C interface of the MPC8306S.
Table 35. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 34).
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
s
High period of the SCL clock
tI2CH
0.6
—
s
Setup time for a repeated START condition
tI2SVKH
0.6
—
s
Hold time (repeated) START condition (after this period, the first clock
pulse is generated)
tI2SXKL
0.6
—
s
Data setup time
tI2DVKH
100
—
ns
Parameter
2
Data hold time: I C bus devices
Rise time of both SDA and SCL signals
3
tI2DXKL
300
0.9
s
tI2CR
20 + 0.1 CB4
300
ns
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
34
Freescale Semiconductor
I2 C
Table 35. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 34).
Symbol1
Min
Max
Unit
tI2CF
20 + 0.1 CB4
300
ns
Setup time for STOP condition
tI2PVKH
0.6
—
s
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
s
Noise margin at the LOW level for each connected device (including
hysteresis)
VNL
0.1  OVDD
—
V
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2  OVDD
—
V
Parameter
Fall time of both SDA and SCL signals
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. MPC8306S provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
The following figure provides the AC test load for the I2C.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 25. I2C AC Test Load
The following figure shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2SXKL
tI2CF
tI2CR
SCL
tI2SXKL
S
tI2DXKL
tI2CH
tI2SVKH
Sr
tI2PVKH
P
S
Figure 26. I2C Bus AC Timing Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
35
Timers
14 Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8306S.
14.1
Timer DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S timer pins, including
TIN, TOUT, TGATE, and RTC_PIT_CLK.
Table 36. Timer DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
14.2
Timer AC Timing Specifications
The following table provides the timer input and output AC timing specifications.
Table 37. Timer Input AC Timing Specifications1
Characteristic
Timers inputs—minimum pulse width
Symbol2
Min
Unit
tTIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any
external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
The following figure provides the AC test load for the timers.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 27. Timers AC Test Load
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
36
Freescale Semiconductor
GPIO
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8306S.
15.1
GPIO DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S GPIO.
Table 38. GPIO DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
1
Input low voltage
VIL
—
–0.3
0.8
V
—
Input current
IIN
0 V VIN OVDD
—
±5
A
—
Note:
1. This specification applies when operating from 3.3-V supply.
15.2
GPIO AC Timing Specifications
The following table provides the GPIO input and output AC timing specifications.
Table 39. GPIO Input AC Timing Specifications1
Characteristic
GPIO inputs—minimum pulse width
Symbol2
Min
Unit
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
The following figure provides the AC test load for the GPIO.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 28. GPIO AC Test Load
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
37
IPIC
16 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the
MPC8306S.
16.1
IPIC DC Electrical Characteristics
The following table provides the DC electrical characteristics for the external interrupt pins of the
MPC8306S.
Table 40. IPIC DC Electrical Characteristics1,2
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±5
A
Output High Voltage
VOH
IOL = -8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
1. This table applies for pins IRQ, MCP_OUT, and QE ports Interrupts.
2. MCP_OUT is open drain pins, thus VOH is not relevant for those pins.
16.2
IPIC AC Timing Specifications
The following table provides the IPIC input and output AC timing specifications.
Table 41. IPIC Input AC Timing Specifications1
Characteristic
IPIC inputs—minimum pulse width
Symbol2
Min
Unit
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN.
Timings are measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
17 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8306S.
17.1
SPI DC Electrical Characteristics
The following table provides the DC electrical characteristics for the MPC8306S SPI.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
38
Freescale Semiconductor
SPI
Table 42. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
17.2
SPI AC Timing Specifications
The following table and provide the SPI input and output AC timing specifications.
Table 43. SPI AC Timing Specifications1
Symbol2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOV
2
8
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
6
—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0
—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4
—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
3. All units of output delay must be enabled for 8306S output port spimosi (SPI Master Mode)
4. delay units must not be enabled for Slave Mode.
The following figure provides the AC test load for the SPI.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 29. SPI AC Test Load
Figure 30 and Figure 31 represent the AC timing from Table 43. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
39
JTAG
The following figure shows the SPI timing in slave mode (external clock).
SPICLK (Input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
tNEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 30. SPI AC Timing in Slave Mode (External Clock) Diagram
The following figure shows the SPI timing in master mode (internal clock).
SPICLK (Output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 31. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG)
interface of the MPC8306S.
18.1
JTAG DC Electrical Characteristics
The following table provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface
of the MPC8306S.
Table 44. JTAG Interface DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
40
Freescale Semiconductor
JTAG
Table 44. JTAG Interface DC Electrical Characteristics (continued)
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V  VIN  OVDD
—
±5
A
18.2
JTAG AC Electrical Characteristics
This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8306S. The following table provides the JTAG AC timing specifications as defined in Figure 33
through Figure 36.
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1
At recommended operating conditions (see Table 2).
Symbol2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
t JTG
30
—
ns
—
tJTKHKL
11
—
ns
—
tJTGR, tJTGF
0
2
ns
—
tTRST
25
—
ns
3
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
15
15
Parameter
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
ns
Input setup times:
Input hold times:
4
ns
4
ns
Valid times:
5
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
41
JTAG
Table 45. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 (continued)
At recommended operating conditions (see Table 2).
Symbol2
Min
Max
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
Parameter
Output hold times:
Unit
Notes
ns
5
ns
5, 6
6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 32).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
The following figure provides the AC test load for TDO and the boundary-scan outputs of the MPC8306S.
Output
Z0 = 50 
RL = 50 
OVDD/2
Figure 32. AC Test Load for the JTAG Interface
The following figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 33. JTAG Clock Input Timing Diagram
The following figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 34. TRST Timing Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
42
Freescale Semiconductor
JTAG
The following figure provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Input
Data Valid
Boundary
Data Inputs
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 35. Boundary-Scan Timing Diagram
The following figure provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOX
tJTKLOV
TDO
Output Data Valid
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 36. Test Access Port Timing Diagram
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
43
Package and Pin Listings
19 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8306S is available in
a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 19.1, “Package
Parameters for the MPC8306S,” and Section 19.2, “Mechanical Dimensions of the MPC8306S
MAPBGA,” for information on the MAPBGA.
19.1
Package Parameters for the MPC8306S
The package parameters are as provided in the following list.
Package outline
19 mm 19 mm
Package Type
MAPBGA
Interconnects
369
Pitch
0.80 mm
Module height (typical)
1.48 mm; Min = 1.31mm and Max 1.61mm
Solder Balls
96 Sn / 3.5 Ag / 0.5 Cu (VM package)
Ball diameter (typical)
0.40 mm
19.2
Mechanical Dimensions of the MPC8306S MAPBGA
The following figure shows the mechanical dimensions and bottom surface nomenclature of the
MPC8306S, 369-MAPBGA package.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
44
Freescale Semiconductor
Package and Pin Listings
Figure 37. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8306S MAPBGA
Notes:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
45
Package and Pin Listings
19.3
Pinout Listings
Following table shows the pin list of the MPC8306S.
Table 46. MPC8306S
Signal
Pinout Listing
Package Pin Number
Pin Type
Power Supply
Notes
DDR Memory Controller Interface
MEMC_MDQ[0]
W5
IO
GVDD
—
MEMC_MDQ[1]
V4
IO
GVDD
—
MEMC_MDQ[2]
Y4
IO
GVDD
—
MEMC_MDQ[3]
AB1
IO
GVDD
—
MEMC_MDQ[4]
AA1
IO
GVDD
—
MEMC_MDQ[5]
Y2
IO
GVDD
—
MEMC_MDQ[6]
Y1
IO
GVDD
—
MEMC_MDQ[7]
W2
IO
GVDD
—
MEMC_MDQ[8]
G2
IO
GVDD
—
MEMC_MDQ[9]
G1
IO
GVDD
—
MEMC_MDQ[10]
F1
IO
GVDD
—
MEMC_MDQ[11]
E2
IO
GVDD
—
MEMC_MDQ[12]
E1
IO
GVDD
—
MEMC_MDQ[13]
E4
IO
GVDD
—
MEMC_MDQ[14]
F4
IO
GVDD
—
MEMC_MDQ[15]
D1
IO
GVDD
—
MEMC_MDM[0]
AB2
O
GVDD
—
MEMC_MDM[1]
G4
O
GVDD
—
MEMC_MDQS[0]
V5
IO
GVDD
—
MEMC_MDQS[1]
F5
IO
GVDD
—
MEMC_MBA[0]
L2
O
GVDD
—
MEMC_MBA[1]
L1
O
GVDD
—
MEMC_MBA[2]
R4
O
GVDD
—
MEMC_MA[0]
M1
O
GVDD
—
MEMC_MA[1]
M4
O
GVDD
—
MEMC_MA[2]
N1
O
GVDD
—
MEMC_MA[3]
N2
O
GVDD
—
MEMC_MA[4]
P1
O
GVDD
—
MEMC_MA[5]
N4
O
GVDD
—
MEMC_MA[6]
P2
O
GVDD
—
MEMC_MA[7]
R1
O
GVDD
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
46
Freescale Semiconductor
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
MEMC_MA[8]
T1
O
GVDD
—
MEMC_MA[9]
P4
O
GVDD
—
MEMC_MA[10]
L4
O
GVDD
—
MEMC_MA[11]
T2
O
GVDD
—
MEMC_MA[12]
U1
O
GVDD
—
MEMC_MA[13]
U2
O
GVDD
—
MEMC_MWE_B
K1
O
GVDD
—
MEMC_MRAS_B
K2
O
GVDD
—
MEMC_MCAS_B
J1
O
GVDD
—
MEMC_MCS_B[0]
J4
O
GVDD
—
MEMC_MCS_B[1]
H1
O
GVDD
—
MEMC_MCKE[0]
U4
O
GVDD
—
MEMC_MCK[0]
V1
O
GVDD
—
MEMC_MCK_B[0]
W1
O
GVDD
—
MEMC_MODT[0]
H2
O
GVDD
—
MEMC_MODT[1]
H4
O
GVDD
—
MEMC_MVREF
L8
GVDD
—
Local Bus Controller Interface
LAD[0]
B7
IO
OVDD
—
LAD[1]
D9
IO
OVDD
—
LAD[2]
A6
IO
OVDD
—
LAD[3]
B8
IO
OVDD
—
LAD[4]
A7
IO
OVDD
—
LAD[5]
A8
IO
OVDD
—
LAD[6]
A9
IO
OVDD
—
LAD[7]
D10
IO
OVDD
—
LAD[8]
B10
IO
OVDD
—
LAD[9]
A10
IO
OVDD
—
LAD[10]
B11
IO
OVDD
—
LAD[11]
D12
IO
OVDD
—
LAD[12]
D11
IO
OVDD
—
LAD[13]
A11
IO
OVDD
—
LAD[14]
A12
IO
OVDD
—
LAD[15]
B13
IO
OVDD
—
LA[16]
A13
IO
OVDD
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
47
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
LA[17]
B14
O
OVDD
—
LA[18]
A14
O
OVDD
—
LA[19]
A15
O
OVDD
—
LA[20]
A16
O
OVDD
—
LA[21]
B16
O
OVDD
—
LA[22]
A17
O
OVDD
—
LA[23]
B17
O
OVDD
—
LA[24]
A18
O
OVDD
—
LA[25]
B19
O
OVDD
—
LCS_B[0]
A19
O
OVDD
3
LCS_B[1]
B20
O
OVDD
3
LCS_B[2]
A20
O
OVDD
3
LCS_B[3]
A21
O
OVDD
3
LCLK[0]
D13
O
OVDD
—
LGPL[0]
B22
O
OVDD
—
LGPL[1]
D16
O
OVDD
—
LGPL[2]
D19
O
OVDD
—
LGPL[3]
D17
O
OVDD
—
LGPL[4]
E18
IO
OVDD
—
LGPL[5]
E19
O
OVDD
—
LWE_B[0]
D15
O
OVDD
—
LWE_B[1]
D14
O
OVDD
—
LBCTL
A22
O
OVDD
—
LALE
B23
O
OVDD
—
JTAG
TCK
A3
I
OVDD
—
TDI
B5
I
OVDD
3
TDO
D7
O
OVDD
—
TMS
A4
I
OVDD
3
TRST_B
D8
I
OVDD
3
I
OVDD
—
Test Interface
TEST_MODE
A5
System Control Signals
HRESET_B
U20
IO
OVDD
1
PORESET_B
V20
I
OVDD
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
48
Freescale Semiconductor
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
Clock Interface
QE_CLK_IN
P23
I
OVDD
—
SYS_CLK_IN
R23
I
OVDD
—
RTC_PIT_CLOCK
V23
I
OVDD
—
Miscellaneous Signals
QUIESCE_B
A2
O
OVDD
—
THERM0
D6
I
OVDD
—
GPIO
GPIO[0]/MSRCID0 (DDR ID)
E5
IO
OVDD
—
GPIO[1]/MSRCID1 (DDR ID)
E6
IO
OVDD
—
GPIO[2]/MSRCID2 (DDR ID)
D4
IO
OVDD
—
GPIO[3]/MSRCID3 (DDR ID)
C2
IO
OVDD
—
GPIO[4]/MSRCID4 (DDR ID)
C1
IO
OVDD
—
GPIO[5]/MDVAL (DDR ID)
B1
IO
OVDD
—
GPIO[6]/QE_EXT_REQ_3
B3
IO
OVDD
—
GPIO[7]/QE_EXT_REQ_1
B2
IO
OVDD
—
AC4
IO
OVDD
2
Y9
I
OVDD
USBDR_DIR/IIC_SCL2
AC3
IO
OVDD
2
USBDR_NXT/UART2_SIN[1]/QE_EXT_REQ_4
AC2
IO
OVDD
—
USBDR_PCTL[0]/UART2_SOUT[1]/
LB_POR_CFG_BOOT_ECC
AB3
IO
OVDD
—
USBDR_PCTL[1]/UART2_SOUT[2]/
UART2_RTS_B1/LB_POR_BOOT_ERR
Y8
O
OVDD
—
USBDR_STP/QE_EXT_REQ_2
W6
IO
OVDD
—
USBDR_TXDRXD[0]/UART1_SOUT[1]/
GPIO[32]/QE_TRB_O
AB7
IO
OVDD
—
USBDR_TXDRXD[1]/UART1_SIN[1]/GPIO[33]/
QE_TRB_I
AB8
IO
OVDD
—
USBDR_TXDRXD[2]/UART1_SOUT[2]/
UART1_RTS_B1/QE_BRG[1]
AC6
IO
OVDD
—
USBDR_TXDRXD[3]/UART1_SIN[2]/
UART1_CTS_B1/QE_BRG[2]
AC5
IO
OVDD
—
USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3]
AB5
IO
OVDD
—
USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4]
Y7
IO
OVDD
—
USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9]
Y6
IO
OVDD
—
USB
USBDR_PWRFAULT/IIC_SDA2/CE_PIO_1
USBDR_CLK/UART2_SIN[2]/UART2_CTS_B[1]
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
49
Package and Pin Listings
Table 46. MPC8306S
Signal
USBDR_TXDRXD[7]/GPIO[37]/QE_BRG[11]
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
Y5
IO
OVDD
—
DUART
UART1_SOUT[1]/LSRCID4/LCS_B[4]
C23
O
OVDD
—
UART1_SIN[1]/LDVAL/LCS_B[5]
F19
IO
OVDD
—
UART1_SOUT[2]/UART1_RTS_B1/LCS_B[6]
D23
O
OVDD
—
UART1_SIN[2]/UART1_CTS_B[1]/LCS_B[7]
D22
IO
OVDD
—
Interrupts
IRQ_B0_MCP_IN_B/CE_PI_0
E20
IO
OVDD
—
IRQ_B1/MCP_OUT_B
E23
IO
OVDD
—
IRQ_B2/CKSTOP_OUT_B
E22
IO
OVDD
—
IRQ_B3/CKSTOP_IN_B
F20
I
OVDD
—
I2C / SPI
IIC_SDA1
G20
IO
OVDD
2
IIC_SCL1
J20
IO
OVDD
2
LCLK1/IIC_SCL2/CKSTOP_IN_B
H20
IO
OVDD
2
SPISEL_BOOT/IIC_SDA2/CKSTOP_OUT_B
F23
O
OVDD
2
SPIMOSI/LSRCID[2]
G22
IO
OVDD
—
SPIMISO/LSRCID[3]
K20
IO
OVDD
—
SPICLK/LSRCID[0]
G23
IO
OVDD
—
SPISEL/LSRCID[1]
H22
I
OVDD
—
FEC Management
FEC_MDC
H23
O
OVDD
—
FEC_MDIO
L20
IO
OVDD
—
FEC1/GTM/GPIO
FEC1_COL/GTM1_TIN[1]/GPIO[16]
AB20
IO
OVDD
—
FEC1_CRS/GTM1_TGATE1_B/GPIO[17]
AC21
IO
OVDD
—
FEC1_RX_CLK/GPIO[18]
Y17
IO
OVDD
—
FEC1_RX_DV/GTM1_TIN[2]/GPIO[19]
Y18
IO
OVDD
—
FEC1_RX_ER/GTM1_TGATE[2]_B/GPIO[20]
AB19
IO
OVDD
—
FEC1_RXD0/GPIO[21]
AC20
IO
OVDD
—
FEC1_RXD1/GTM1_TIN[3]/GPIO[22]
AC19
IO
OVDD
—
FEC1_RXD2/GTM1_TGATE[3]_B/GPIO[23]
AC18
IO
OVDD
—
FEC1_RXD3/GPIO[24]
AB17
IO
OVDD
—
FEC1_TX_CLK/GTM1_TIN4/GPIO[25]
Y15
IO
OVDD
—
FEC1_TX_EN/GTM1_TGATE[4]_B/GPIO[26]
Y16
IO
OVDD
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
50
Freescale Semiconductor
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
FEC1_TX_ER/GTM1_TOUT[4]_B/GPIO[27]
AC17
IO
OVDD
—
FEC1_TXD0/GTM1_TOUT[1]_B/GPIO[28]
AB16
IO
OVDD
—
FEC1_TXD1/GTM1_TOUT[2]_B/GPIO[29]
AC16
IO
OVDD
—
FEC1_TXD2/GTM1_TOUT[3]_B/GPIO[30]
AC15
IO
OVDD
—
FEC1_TXD3/GPIO[31]
AB14
IO
OVDD
—
FEC2/GPIO
FEC2_COL/GPIO[32]
AC14
IO
OVDD
—
FEC2_CRS/GPIO[33]
AB13
IO
OVDD
—
FEC2_RX_CLK/GPIO[34]
Y14
IO
OVDD
—
FEC2_RX_DV/GPIO[35]
AC13
IO
OVDD
—
FEC2_RX_ER/GPIO[36]
Y13
IO
OVDD
—
FEC2_RXD0/GPIO[37]
AC12
IO
OVDD
—
FEC2_RXD1/GPIO[38]
AB11
IO
OVDD
—
FEC2_RXD2/GPIO[39]
AC11
IO
OVDD
—
FEC2_RXD3/GPIO[40]
AB10
IO
OVDD
—
FEC2_TX_CLK/GPIO[41]
Y12
IO
OVDD
—
FEC2_TX_EN/GPIO[42]
AC10
IO
OVDD
—
FEC2_TX_ER/GPIO[43]
AC9
IO
OVDD
—
FEC2_TXD0/GPIO[44]
AC8
IO
OVDD
—
FEC2_TXD1/GPIO[45]
Y11
IO
OVDD
—
FEC2_TXD2/GPIO[46]
AC7
IO
OVDD
—
FEC2_TXD3/GPIO[47]
Y10
IO
OVDD
—
FEC3/GPIO
FEC3_COL/GPIO[48]
J23
IO
OVDD
—
FEC3_CRS/GPIO[49]
K23
IO
OVDD
—
FEC3_RX_CLK/GPIO[50]
M20
IO
OVDD
—
FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO[51]
K22
IO
OVDD
—
FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO[52]
L22
IO
OVDD
—
FEC3_RXD0/FEC2_TMR_TX_ESFD/GPIO[53]
L23
IO
OVDD
—
FEC3_RXD1/FEC2_TMR_RX_ESFD/GPIO[54]
M23
IO
OVDD
—
FEC3_RXD2/TSEC_TMR_TRIG1/GPIO[55]
N22
IO
OVDD
—
FEC3_RXD3/TSEC_TMR_TRIG2/GPIO[56]
N23
IO
OVDD
—
FEC3_TX_CLK/TSEC_TMR_CLK/GPIO[57]
N20
IO
OVDD
—
FEC3_TX_EN/TSEC_TMR_GCLK/GPIO[58]
P20
IO
OVDD
—
FEC3_TX_ER/TSEC_TMR_PP1/GPIO[59]
P22
IO
OVDD
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
51
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
FEC3_TXD0/TSEC_TMR_PP2/GPIO[60]
R20
IO
OVDD
—
FEC3_TXD1/TSEC_TMR_PP3/GPIO[61]
T22
IO
OVDD
—
FEC3_TXD2/TSEC_TMR_ALARM1/GPIO[62]
T23
IO
OVDD
—
FEC3_TXD3/TSEC_TMR_ALARM2/GPIO[63]
T20
IO
OVDD
—
HDLC/GPIO/TDM
HDLC1_RXCLK/TDM1_RCK/GPIO[1]
U23
IO
OVDD
—
HDLC1_RXD/TDM1_RD/GPIO[3]
U22
IO
OVDD
—
HDLC1_TXCLK/GPIO[0]/TDM1_TCK/
QE_BRG[5]
AC22
IO
OVDD
—
HDLC1_TXD/GPIO[2]/TDM1_TD/
CFG_RESET_SOURCE[0]
W18
IO
OVDD
—
HDLC1_CD_B/GPIO[4]/TDM1_TFS
W19
IO
OVDD
—
HDLC1_CTS_B/GPIO[5]/TDM1_RFS
Y20
IO
OVDD
—
HDLC1_RTS_B/GPIO[6]/TDM1_STROBE_B/
CFG_RESET_SOURCE[1]
AB22
IO
OVDD
—
HDLC2_TXCLK/GPIO[16]/TDM2_TCK/
QE_BRG[7]
AB23
IO
OVDD
—
HDLC2_RXCLK/GPIO[17]/TDM2_RCK/
QE_BRG[8]
AA23
IO
OVDD
—
HDLC2_TXD/GPIO[18]/TDM2_TD/
CFG_RESET_SOURCE[2]
W20
IO
OVDD
—
HDLC2_RXD/GPIO[19]/TDM2_RD
Y23
IO
OVDD
—
HDLC2_CD_B/GPIO[20]/TDM2_TFS
Y22
IO
OVDD
—
HDLC2_CTS_B/GPIO[21]/TDM2_RFS
W23
IO
OVDD
—
HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/
CFG_RESET_SOURCE[3]
W22
IO
OVDD
—
Power
AVDD1
L16
—
—
—
AVDD2
M16
—
—
—
AVDD3
N8
—
—
—
GVDD
G5, H5, J5, K5, L5, M5,
N5, P5, R5, T5, U5
—
—
—
OVDD
E7,E8,E9,E10,E11,E12,
E13,E14, E15,
E16,E17,G19,H19,J19,K
19,L19,M19,
N19,P19,R19,T19,U19,
W7,W8,W9, W10,W11,
W12,W13, W14,W15,
W16, W17
—
—
—
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
52
Freescale Semiconductor
Package and Pin Listings
Table 46. MPC8306S
Signal
Pinout Listing (continued)
Package Pin Number
Pin Type
Power Supply
Notes
VDD
H8,H9,H10,H11,H12,H1
3,H14,H15,H16,J8,J16,K
8,K16,M8,N16,P8,P16,R
8,R16,T8,T9,T10,T11,T1
2,T13,T14,T15,T16
—
—
—
VSS
A1,B4,B6,B9,B12,B15,B
18,B21,C22,D2,D5,D18,
D20,F2,F22,J2,J9,J10,J
11,J12,J13,J14,J15,J22,
K4,K9,K10,K11,K12,K13
,K14,K15,L9,L10,L11,L1
2,L13,L14,L15,M2,M9,M
10,M11,M12,M13,M14,M
15,M22,N9,N10,N11,N1
2,N13,N14,N15,P9,P10,
P11,P12,P13,P14,P15,R
2,R9,R10,R11,R12,R13,
R14,R15,R22,T4,V2,V19
,V22,W4,Y19,AA2,AA22,
AB4,AB6,AB9,AB12,AB1
5,AB18,AB21,AC1,AC23
—
—
—
NC
A23
—
—
—
Notes
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD
2. This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin to OVDD
3. This pin has weak pull-up that is always enabled.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
53
Clocking
20 Clocking
The following figure Figure 39 shows the internal distribution of clocks within the MPC8306S.
Figure 38. MPC8306S Clock Subsystem
e300c3 core
MPC8306S
Core PLL
core_clk
to DDR
memory
controller
csb_clk
DDR
Clock
Divider
/2
MEMC_MCK
MEMC_MCK
DDR
Memory
Device
ddr_clk
Clock
Unit
SYS_CLK_IN
System
PLL
lbc_clk
/n
to local bus
LBC
Clock
Divider
LCLK[0:1]
Local Bus
Memory
Device
csb_clk to rest
of the device
QE_CLK_IN
QE PLL
CLK Gen
qe_clk
QE Block
Figure 39. MPC8306S Clock Subsystem
The primary clock source for MPC8306S is SYS_CLK_IN.
Figure 40.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
54
Freescale Semiconductor
Clocking
20.1
System Clock Domains
As shown in Figure 38, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create four major clock domains:
• The coherent system bus clock (csb_clk)
• The QUICC Engine clock (qe_clk)
• The internal clock for the DDR controller (ddr_clk)
• The internal clock for the local bus controller (lbc_clk)
The csb_clk frequency is derived from the following equation:
csb_clk = SYS_CLK_IN × SPMF
Eqn. 1
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is
loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset
Configuration chapter in the MPC8306S PowerQUICC II Pro Integrated Communications Processor
Family Reference Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF)
Eqn. 2
qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF)
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8306S PowerQUICC II Pro Integrated Communications
Processor Family Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306S PowerQUICC
II Pro Integrated Communications Processor Family Reference Manual.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
55
Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8306S PowerQUICC II Pro
Integrated Communications Processor Family Reference Manual.
Table 47. Configurable Clock Units
Unit
Default Frequency
I2C,SDHC, USB, DMA Complex
csb_clk
Options
Off, csb_clk, csb_clk/2, csb_clk/3
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
The following table provides the maximum operating frequencies for the MPC8306S MAPBGA under
recommended operating conditions (see Table 2).
Table 48. Operating Frequencies for MAPBGA
Characteristic1
Max Operating Frequency
Unit
e300 core frequency (core_clk)
266
MHz
Coherent system bus frequency (csb_clk)
133
MHz
QUICC Engine frequency (qe_clk)
233
MHz
167
MHz
66
MHz
DDR2 memory bus frequency
(MCLK)2
Local bus frequency (LCLKn)3
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating
frequencies.
2. The DDR2 data rate is 2× the DDR2 memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWL[LBCM]).
20.2
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 49 shows the multiplication factor
encodings for the system PLL.
NOTE
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
As described in Section 20, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
56
Freescale Semiconductor
Clocking
Table 49. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
×2
0011
×3
0100
×4
0101
×5
0110
×6
0111–1111
Reserved
coherent system bus clock (csb_clk). The following table shows the expected frequency values for the CSB
frequency for selected csb_clk to SYS_CLK_IN ratios.
Table 50. CSB Frequency Options
SYS_CLK_IN(MHz)
SPMF
csb_clk : sys_clk_in Ratio
25
33.33
66.67
csb_clk Frequency (MHz)
20.3
0010
2:1
0011
3:1
0100
4:1
0101
5:1
0110
6:1
133
133
125
167
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). The following table shows the encodings for RCWL[COREPLL]. COREPLL
values not listed, and should be considered reserved.
Table 51. e300 Core PLL Configuration
RCWL[COREPLL]
0-1
2-5
core_clk : csb_clk Ratio
VCO Divider
6
nn
0000
n
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
00
0001
0
1:1
2
01
0001
0
1:1
4
10
0001
0
1:1
8
11
0001
0
1:1
8
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
57
Clocking
Table 51. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
0-1
2-5
core_clk : csb_clk Ratio
VCO Divider
6
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
11
0001
1
1.5:1
8
00
0010
0
2:1
2
01
0010
0
2:1
4
10
0010
0
2:1
8
11
0010
0
2:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
11
0010
1
2.5:1
8
00
0011
0
3:1
2
01
0011
0
3:1
4
10
0011
0
3:1
8
11
0011
0
3:1
8
NOTE
Core VCO frequency = core frequency  VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO
frequency is in the range of 400–800 MHz.
20.4
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. The
following table shows the multiplication factor encodings for the QUICC Engine PLL.
Table 52. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00000–00001
0
Reserved
00010
0
2
00011
0
3
00100
0
4
00101
0
5
00110
0
6
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
58
Freescale Semiconductor
Clocking
Table 52. QUICC Engine PLL Multiplication Factors (continued)
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00111
0
7
01000
0
8
01001–11111
0
Reserved
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in the
following table.
Table 53. QUICC Engine PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
2
01
4
10
8
11
Reserved
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
qe_clk = (primary clock input × CEPMF)  (1 + CEPDF)
QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF)
20.5
Suggested PLL Configurations
To simplify the PLL configurations, the MPC8306S might be separated into two clock domains. The first
domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs is configured separately.
The following table shows suggested PLL configurations for 33 and 66 MHz input clocks.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
59
Clocking
Table 54. Suggested PLL Configurations
CEDF
Input Clock
Frequency
(MHz)
CSB
Frequency
(MHz)
Core
Frequency
(MHz)
QUICC
Engine
Frequency
(MHz)
Conf No.
SPMF
Core
PLL
1
0100
0000100
0111
0
33.33
133.33
266.66
233
2
0010
0000100
0111
1
66.67
133.33
266.66
233
3
0100
0000101
0111
0
33.33
133.33
333.33
233
4
0101
0000101
1001
0
25
125
312.5
225
5
0010
0000101
0111
1
66.67
133.33
333.33
233
CEPMF
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
60
Freescale Semiconductor
Thermal
21 Thermal
This section describes the thermal specifications of the MPC8306S.
21.1
Thermal Characteristics
The following table provides the package thermal characteristics for the 369, 19  19 mm MAPBGA of
the MPC8306S.
Table 55. Package Thermal Characteristics for MAPBGA
Characteristic
Board type
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection
Single-layer board (1s)
RJA
39
°C/W
1, 2
Junction-to-ambient natural convection
Four-layer board (2s2p)
RJA
24
°C/W
1, 2, 3
Junction-to-ambient (@200 ft/min)
Single-layer board (1s)
RJMA
32
°C/W
1, 3
Junction-to-ambient (@200 ft/min)
Four-layer board (2s2p)
RJMA
21
°C/W
1, 3
Junction-to-board
—
RJB
14
°C/W
4
Junction-to-case
—
RJC
9
°C/W
5
Natural convection
JT
2
°C/W
6
Junction-to-package top
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
21.1.1
Thermal Management Information
For the following sections, PD = (VDD  IDD) + PI/O, where PI/O is the power dissipation of the I/O
drivers.
21.1.2
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA  PD)
Eqn. 1
where:
TJ = junction temperature (C)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
61
Thermal
TA = ambient temperature for the package (C)
RJA = junction-to-ambient thermal resistance (C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. As a general statement, the value obtained on a single layer board is
appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible.
21.1.3
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB  PD)
Eqn. 2
where:
TJ = junction temperature (C)
TB = board temperature at the package perimeter (C)
RJB = junction-to-board thermal resistance (C/W) per JESD51-8
PD = power dissipation in package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
21.1.4
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (JT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (JT  PD)
Eqn. 3
where:
TJ = junction temperature (C)
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
62
Freescale Semiconductor
Thermal
TT = thermocouple temperature on top of package (C)
JT = thermal characterization parameter (C/W)
PD = power dissipation in package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
21.1.5
Heat Sinks and Junction-to-Case Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of
the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case to ambient thermal resistance as shown in the following equation:
RJA = RJC + RCA
Eqn. 4
where:
RJA = junction-to-ambient thermal resistance (C/W)
RJC = junction-to-case thermal resistance (C/W)
RCA = case-to-ambient thermal resistance (C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit
board, or change the thermal dissipation on the printed-circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been
simulated with a few commercially available heat sinks. The heat sink choice is determined by the
application environment (temperature, air flow, adjacent component power dissipation) and the physical
space available. Because there is not a standard application environment, a standard heat sink is not
required.
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.
21.2
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
63
System Design Information
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
21.2.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface.
From this case temperature, the junction temperature is determined from the junction-to-case thermal
resistance using the following equation:
TJ = TC + (RJC  PD)
Eqn. 5
where:
TC = case temperature of the package (C)
RJC = junction-to-case thermal resistance (C/W)
PD = power dissipation (W)
22 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8306S.
22.1
System Clocking
The MPC8306S includes three PLLs.
• The system PLL (AVDD2) generates the system clock from the externally supplied SYS_CLK_IN
input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL
ratio configuration bits as described in Section 20.2, “System PLL Configuration.”
• The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency
ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio
configuration bits as described in Section 20.3, “Core PLL Configuration.”
• The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC
Engine block generates or uses external sources for all required serial interface clocks.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
64
Freescale Semiconductor
System Design Information
22.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The voltage
level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived
directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 41, one to each of the three AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
The following figure shows the PLL power supply filter circuit.
VDD
10
AVDD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors (<0.5 nH)
GND
Figure 41. PLL Power Supply Filter Circuit
22.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8306S can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8306S system, and MPC8306S
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, OVDD, and GVDD pins of the MPC8306S.
These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, and GVDD planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
65
System Design Information
to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo
OSCON).
22.4
Output Buffer DC Impedance
For all buses, the driver is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 42). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
OVDD
RN
SW2
Data
Pad
SW1
RP
OGND
Figure 42. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource  Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2 = (1/(1/R1 + 1/R2))  Isource. Solving for the output impedance gives
Rsource = Rterm  (V1/V2 – 1). The drive current is then Isource = V1/Rsource.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
66
Freescale Semiconductor
Ordering Information
The following table summarizes the signal impedance targets. The driver impedance is targeted at
minimum VDD, nominal OVDD, 105C.
Table 56. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART, Control,
Configuration and Power Management
DDR DRAM
Symbol
Unit
RN
42 Target
20 Target
Z0
Ω
RP
42 Target
20 Target
Z0
Ω
Differential
NA
NA
ZDIFF
Ω
Note: Nominal supply voltages. See Table 1, Tj = 105C.
22.5
Configuration Pin Multiplexing
The MPC8306S provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking
and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family
Reference Manual). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these
pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize
the disruption of signal quality or speed for output pins thus configured.
23 Ordering Information
This section presents ordering information for the devices discussed in this document, and it shows an
example of how the parts are marked. Ordering information for the devices fully covered by this document
is provided in Section 23.1, “Part Numbers Fully Addressed by This Document.”
23.1
Part Numbers Fully Addressed by This Document
The following table provides the Freescale part numbering nomenclature for the MPC8306S family. Note
that the individual part numbers correspond to a maximum processor core frequency. For available
frequencies, contact your local Freescale sales office. In addition to the maximum processor core
frequency, the part numbering scheme also includes the maximum effective DDR memory speed and
QUICC Engine bus frequency. Each part number also contains a revision code which refers to the die mask
revision number.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
67
Ordering Information
Table 57. Part Numbering Nomenclature
MPC
nnnn
C
VM
AF
D
C
A
Product
Code
Part
Identifier
Temperature
Range1
Package2
e300 Core
Frequency3
DDR2
Frequency
QUICC
Engine
Frequency
Revision
Level
MPC
8306S
VM = Pb-free
AB = 133MHz
AC = 200 MHz
AD = 266 MHz
AF = 333 MHz
Blank = 0 to
105C
C = –40 to
105C
D = 266 MHz
F = 333 MHz
C = 233 MHz
Contact local
Freescale
sales office
Notes:
1. Contact local Freescale office on availability of parts with C temperature range.
2. See Section 19, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.
23.2
Part Marking
Parts are marked as in the example shown in the following figure.
MPCnnnnetppaaar
core/platform MHZ
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
MAPBGA
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
Figure 43. Freescale Part Marking for MAPBGA Devices
The following table shows the SVR Settings.
Table 58. SVR Settings
Device
MPC8306S
Package
MAPBGA
SVR (Rev 1.0)
SVR (Rev 1.1)
0x8110_0210
0x8110_0211
Note: PVR = 0x8085_0020
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
68
Freescale Semiconductor
Document Revision History
24 Document Revision History
The following table provides a revision history for this document.
Table 59. Document Revision History
Rev.
No.
Date
1
09/2011
•
•
•
•
•
•
•
•
•
0
03/2011
Initial Release
Substantive Change(s)
Added Power numbers for core frequency of 333 MHz in Table 5.
Updated QUICC Engine frequency in Table 5.
Added SPISEL_BOOT in MPC8306 Pin out Listing Table 46.
Corrected SPISEL Pin Type in Table 46
Updated QUICC Engine frequency from 200 MHz to 233 MHz in Table 48.
Added new PLL configurations as per new core frequency in Table 54.
Updated CEPMF and CEDF as per new QE frequency in Table 54.
Added AF to indicate 333 MHz in Table 57
Updated QE Frequency to 233 MHz in Table 57.
MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
69
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or
+1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
[email protected]
For Literature Requests Only:
Freescale Semiconductor
Literature Distribution Center
1-800 441-2447 or
+1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor
@hibbertgroup.com
Document Number: MPC8306SEC
Rev. 1
09/2011
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale, the Freescale logo, CodeWarrior, ColdFire, PowerQUICC,
StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.
Reg. U.S. Pat. & Tm. Off. CoreNet, QorIQ, QUICC Engine, and VortiQa are
trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. The Power Architecture
and Power.org word marks and the Power and Power.org logos and related
marks are trademarks and service marks licensed by Power.org.
© 2011 Freescale Semiconductor, Inc.