Fairchild FM24C64V 64k-bit standard 2-wire bus interface serial eeprom Datasheet

FM24C64 – 64K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
Features
FM24C64 is a 64Kbit CMOS non-volatile serial EEPROM organized as 8K x 8 bit memory. This device confirms to Extended IIC
2-wire protocol that allows accessing of memory in excess of
16Kbit on an IIC bus. This serial communication protocol uses a
Clock signal (SCL) and a Data signal (SDA) to synchronously
clock data between a master (e.g. a microcontroller) and a slave
(EEPROM). FM24C64 is designed to minimize pin count and
simplify PC board layout requirements.
■ Extended operating voltage: 2.5V to 5.5V
■ Up to 400 KHz clock frequency at 2.5V to 5.5V
■ Low power consumption
— 0.5mA active current typical
— 10µA standby current typical
— 1µA standby current typical (L version)
— 0.1µA standby current typical (LZ version)
■ Schmitt trigger inputs
FM24C64 offers hardware write protection where by the entire
memory array can be write protected by connecting WP pin to VCC.
This section of memory then becomes unalterable until the WP pin
is switched to VSS.
■ 32 byte page write mode
■ Self timed write cycle (6ms typical)
■ Hardware Write Protection for the entire array
“LZ” and “L” versions of FM24C64 offer very low standby current
making them suitable for low power applications. This device is
offered in SO, TSSOP and DIP packages.
■ Endurance: up to 100K data changes
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consumption.
■ Temperature range
— Commercial: 0°C to +70°C
— Industrial (E): -40°C to +85°C
— Automotive (V): -40°C to +125°C
■ Data Retention: Greater than 40 years
■ Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP
Block Diagram
VSS
WRITE
LOCKOUT
VCC
H.V. GENERATION
TIMING &CONTROL
WP
START
STOP
LOGIC
SDA
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
SCL
XDEC
A2
A1
A0
E2PROM
ARRAY
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DATA REGISTER
DIN
© 2001 Fairchild Semiconductor Corporation
FM24C64 Rev. C
1
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
December 2001
FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Connection Diagram
Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)
A0
1
A1
2
8
VCC
7
WP
FM24C64
A2
3
6
SCL
VSS
4
5
SDA
See Package Number N08E, M08A and MTC08
Pin Names
VSS
Ground
SDA
Serial Data I/O
SCL
Serial Clock Input
WP
Write Protect
VCC
Power Supply
A0, A1, A2
Device Address Inputs
2
FM24C64 Rev. C
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FM
24
C
XX
F
LZ
E
YY
X
Letter
Description
Blank
X
Tube
Tape and Reel
N
M8
MT8
8-pin DIP
8-pin SOIC
8-pin TSSOP
Temp. Range
Blank
E
V
0 to 70°C
-40 to +85°C
-40 to +125°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V and
<1µA Standby Current
SCL Clock Frequency
Blank
F
100KHz
400KHz
64
64K with write protect
C
CMOS
24
IIC - 2 Wire
FM
Fairchild Non-Volatile
Memory
Package
Density
Interface
3
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Ordering Information
Operating Conditions
Absolute Maximum Ratings
Ambient Storage Temperature
Ambient Operating Temperature
FM24C64
FM24C64E
FM24C64V
–65°C to +150°C
All Input or Output Voltages
with Respect to Ground
6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Positive Power Supply
FM24C64
FM24C64L
FM24C64LZ
2000V min.
4.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
(Note 1)
Max
Units
0.5
1.0
ICCA
Active Power Supply Current
fSCL = 400 KHz
fSCL = 100 KHz
ISB
Standby Current
VIN = GND or VCC
10
50
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA
mA
Low VCC (2.5V to 5 .5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
(Note 1)
Max
Active Power Supply Current fSCL = 400 KHz
fSCL = 100 KHz
0.5
1.0
mA
Standby Current
VIN = GND
or VCC
1
0.1
10
10
1
50
µA
µA
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
VOUT = GND to VCC
Min
ICCA
ISB
(Note 3)
VCC = 2.5V - 4.5V (L)
VCC = 2.5V - 4.5V (LZ)
VCC = 4.5V - 5.5V
Units
ILO
Output Leakage Current
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
0.1
IOL = 2.1 mA
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
Test
Conditions
Max
Units
CI/O
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
Note 3: The "L" and "LZ" versions can be operated in the 2.5V to 5.5V VCC range. However the ISB values for L and LZ are applicable only when VCC is in the 2.5V to 4.5V range.
4
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Product Specifications
AC Testing Input/Output Waveforms
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
0.9VCC
0.7VCC
Input Rise and Fall Times
10 ns
0.1VCC
0.3VCC
Input & Output Timing Levels
VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.5V - 5.5V)
Symbol
f SCL
TI
Parameter
100 KHz
Min
Max
400 KHz
Min
Max
Units
SCL Clock Frequency
100
400
KHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
50
ns
0.9
µs
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
µs
Start Condition Hold Time
4.0
0.6
µs
tLOW
Clock Low Period
4.7
1.5
µs
tHIGH
Clock High Period
4.0
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data in Hold Time
0
0
ns
tSU:DAT
Data in Setup Time
250
120
ns
tHD:STA
tR
SDA and SCL Rise Time
1
0.3
µs
tF
SDA and SCL Fall Time
300
300
ns
tSU:STO
Stop Condition Setup Time
4.7
t DH
Data Out Hold Time
100
t WR
Write Cycle Time
µs
0.6
50
6
ns
6
ms
Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle,
the FM24C64 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address. Refer "Write Cycle Timing" diagram.
Bus Timing
tR
tF
tHIGH
tLOW
tLOW
SCL
tSU:STA
SDA
tHD:DAT
tHD:STA
tSU:DAT
IN
tSU:STO
tBUF
tAA
tDH
SDA
OUT
5
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
AC Test Conditions
SCL
SDA
8th BIT
ACK
WORD n
tWR
STOP
CONDITION
Note:
START
CONDITION
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Typical System Configuration
VCC
VCC
SDA
SCL
Master
Transmitter/
Receiver
Note:
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)
6
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Cycle Timing
Device Type
Extended IIC specification is an extension of Standard IIC specification to allow addressing of EEPROMs with more than 16Kbits
of memory on an IIC bus. The difference between the two
specifications is that Extended IIC specification defines two bytes
of “Array Address” information while Standard IIC specification
defines only one. All other aspects are identical between the two
specifications. Using two bytes of Array Address and 3 address
signals (A2, A1 and A0), it is now possible to address up to 4 Mbits
(28 * 28 * 23 * 8 = 4 Mbits) of memory on an IIC bus.
IIC bus is designed to support a variety of devices such as RAMs,
EPROMs etc., along with EEPROMS. Hence to properly identify
various devices on the IIC bus, a 4-bit “Device Type” identifier
string is used. For EEPROMS, this 4-bit string is 1-0-1-0. Every IIC
device on the bus internally compares this 4-bit string to its own
“Device Type” string to ensure proper device selection.
Device/Page Block Selection
When multiple devices of the same type (e.g. multiple EEPROMS)
are present on the IIC bus, then the A2, A1 and A0 address
information bits are used in device selection. Every IIC device on
the bus internally compares this 3-bit string to its own physical
configuration (A2, A1 and A0 pins) to ensure proper device
selection. This comparison is in addition to the “Device Type”
comparison.
Note that due to format difference, it is not possible to have
peripherals which follow Standard IIC specification (e.g. 16K bit
EEPROM) and peripherals which follow Extended IIC specification (e.g. 64K bit EEPROM) on a common IIC bus.
IIC bus allows synchronous bi-directional communication between a TRANSMITTER and a RECEIVER using a Clock signal
(SCL) and a Data signal (SDA). Additionally there are up to three
Address signals (A2, A1 and A0) which collectively serve as “chip
select signal” to a device (e.g. EEPROM) on the bus.
In addition to selecting an EEPROM, these 3 bits are also used to
select a “page block” within the selected EEPROM. Each page
block is 512Kbit (64 K Bytes) in size. If an EEPROM contains more
than one page bock then the selection of a page block within the
EEPROM is by using A2, A1 and A0 bits.
All communication on the IIC bus must be started with a valid
START condition (by a MASTER), followed by transmittal (by the
MASTER) of byte(s) of information (Address/Data). For every byte
of information received, the addressed RECEIVER provides a
valid ACKNOWLEDGE pulse to further continue the communication unless the RECEIVER intends to discontinue the communication. Depending on the direction of transfer (Write or Read), the
RECEIVER can be a SLAVE or the MASTER. A typical IIC
communication concludes with a STOP condition (by the MASTER).
Read/Write Bit
Last bit of the Slave Address indicates if the intended access is
Read or Write. If the bit is "1," then the access is Read, whereas
if the bit is "0," then the access is Write.
Acknowledge
Acknowledge is an active LOW pulse on the SDA line driven by an
addressed receiver to the addressing transmitter to indicate
receipt of 8-bits of data. The receiver provides an ACK pulse for
every 8-bits of data received. This handshake mechanism is done
as follows: After transmitting 8-bits of data, the transmitter releases the SDA line and waits for the ACK pulse. The addressed
receiver, if present, drives the ACK pulse on the SDA line during
the 9th clock and releases the SDA line back (to the transmitter).
Refer Figure 3.
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE/PAGE BLOCK SELECTION]—[R/W
BIT]—[ARRAY ADDRESS#1]—[ARRAY ADDRESS#0]
Slave Address
Slave Address is an 8-bit information consisting of a Device type
field (4bits), Device/Page block selection field (3bits) and Read/
Write bit (1bit).
Array Address#1
This is an 8-bit information containing the most significant 8-bits of
16-bit memory array address of a location to be selected within a
page block of the device.
Slave Address Format
Device Type
Identifier
1
0
1
Array Address#0
Device/Page Block
Selection
0
A2
A1
A0
This is an 8-bit information containing the least significant 8-bits of
16-bit memory array address of a location to be selected within a
page block of the device.
R/W
(LSB)
7
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Background Information (IIC Bus)
Device Operation
Serial Clock (SCL)
SDA is a bi-directional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
The FM24C64 supports a bi-directional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the FM24C64 will be considered a slave in
all applications.
Write Protect (WP)
Clock and Data Conventions
If tied to VCC, PROGRAM operations onto the entire memory will
not be executed. READ operations are possible. If tied to VSS,
normal operation is enabled, READ/WRITE over the entire memory
is possible.
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer Figure 1.
This feature allows the user to assign the entire memory as ROM
which can be protected against accidental programming. When
write is disabled, slave address and word address will be acknowledged but data will not be acknowledged.
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The FM24C64
continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has
been met. Refer Figure 2.
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
Start Condition
This pin has an internal pull-down circuit. However, on systems
where write protection is not required it is recommended that this
pin is tied to VSS.
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C64 to place the device in the
standby power mode. Refer Figure 2.
Device Selection Inputs A2, A1 and A0 (as
appropriate)
These inputs collectively serve as “chip select” signal to an
EEPROM when multiple EEPROMs are present on the same IIC
bus. Hence these inputs should be connected to VCC or VSS in a
unique manner to allow proper selection of an EEPROM amongst
multiple EEPROMs. During a typical addressing sequence, every
EEPROM on the IIC bus compares the configuration of these
inputs to the respective 3 bit “Device/Page block selection”
information (part of slave address) to determine a valid selection.
For e.g. if the 3 bit “Device/Page block selection” is 1-0-1, then the
EEPROM whose “Device Selection inputs” (A2, A1 and A0) are
connected to VCC-VSS-VCC respectively, is selected.
FM24C64 Array Addressing
During Read/Write operations, addressing the EEPROM memory
array involves in providing 2 address bytes, “Word Address 1” and
“Word Address 0." However on FM24C64 only the 5 least significant bits (LSB) of “Word Address 1” byte are used in decoding the
access location. The remaining 3 bits are not used and are
recommended to be set to “0." All 8 bits of the “Word Address 0”
byte are used in decoding the access location.
8
FM24C64 Rev. C
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Pin Descriptions
FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Data Validity (Figure 1)
SCL
SDA
DATA STABLE
DATA
CHANGE
Start and Stop Definition (Figure 2)
SCL
SDA
START
CONDITION
STOP
CONDITION
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
tDH
tAA
DATA OUTPUT
FROM
RECEIVER
START
CONDITION
ACKNOWLEDGE
PULSE
9
FM24C64 Rev. C
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Page Write is initiated in the same manner as the Byte Write
operation; but instead of terminating the cycle after transmitting
the first data byte, the master can further transmit up to 31 more
bytes. After the receipt of each byte, FM24C64 will respond with
an acknowledge pulse, increment the internal address counter to
the next address, and is ready to accept the next data. If the master
should transmit more than 32 bytes prior to generating the STOP
condition, the address counter will “roll over” and previously
loaded data will be re-loaded. As with the Byte Write operation, all
inputs are disabled until completion of the internal write cycle.
Refer Figure 5 for the address, acknowledge, and data transfer
sequence.
BYTE WRITE
For byte write operation, two bytes of address are required after
the slave address. These two bytes select 1 out of the 8192
locations in the memory. The master provides these two address
bytes and for each address byte received, FM24C64 responds
with an acknowledge pulse. Master then provides a byte of data
to be written into the memory. Upon receipt of this data, FM24C64
responds with an acknowledge pulse. The master then terminates
the transfer by generating a stop condition, at which time the
FM24C64 begins the internal write cycle to the memory. While the
internal write cycle is in progress the FM24C64 inputs are disabled, and the device will not respond to any requests from the
master for the duration of tWR. Refer Figure 4 for the address,
acknowledge and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation, the FM24C64 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves issuing the
start condition followed by the slave address for a write operation.
If the FM24C64 is still busy with the write operation, no ACK will
be returned. If the FM24C64 has completed the write operation,
an ACK will be returned and the host can then proceed with the
next read or write operation.
PAGE WRITE
To minimize write cycle time, FM24C64 offers Page Write feature,
which allows simultaneous programming of up to 32 contiguous
bytes. To facilitate this feature, the memory array is organized in
terms of “Pages”. A Page consists of 32 contiguous byte locations
starting at every 32-Byte address boundary (for example, starting
at array address 0x0000, 0x0020, 0x0040 etc.). Page Write
operation is confined to a single page. In other words a Page Write
operation will not cross over to locations on the next page but will
“roll over” to the beginning of the same page whenever end of
page is reached and additional data bytes are a continued to be
provided. A Page Write operation can be initiated to begin at any
location within a page (starting address of the Page Write operation need not be the starting address of a Page).
Write Protection
Programming of the entire memory will not take place if the WP pin
of the FM24C64 is connected to VCC. The FM24C64 will respond
to slave and byte addresses; but if the memory accessed is write
protected by the WP pin, the FM24C64 will not generate an
acknowledge after the first byte of data has been received. Thus
the program cycle will not be started when the stop condition is
asserted.
Byte Write (Figure 4)
S
T
Bus Activity: A
Master R
T
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
S
T
O
P
DATA
SDA Line
A
C
K
Bus Activity:
EEPROM
A
C
K
A
C
K
A
C
K
Page Write (Figure 5)
S
T
Bus Activity: A
Master R
T
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
DATA n
S
T
O
P
DATA n+31
SDA Line
Bus Activity:
EEPROM
A
C
K
A
C
K
A
C
K
10
FM24C64 Rev. C
A
C
K
A
C
K
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Write Operations
not acknowledge the transfer but does generate the stop condition, and therefore the FM24C64 discontinues transmission.
Refer Figure 7 for the address, acknowledge, and data transfer
sequence.
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C64 continues to output data for each acknowledge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condition.
Current Address Read
Internally the FM24C64 contains an address counter that maintains the address of the last byte accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to "1," the
FM24C64 issues an acknowledge and transmits the eight bit
word. The master will not acknowledge the transfer but does
generate a stop condition, and therefore the FM24C64 discontinues transmission. Refer Figure 6 for the sequence of address,
acknowledge and data transfer.
The data output is sequential with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" to the
beginning of the memory. FM24C64 continues to output data for
each acknowledge received. Refer Figure 8 for the address,
acknowledge, and data transfer sequence.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1," the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address with the R/W bit set to "0" and then the byte
address. After the byte address acknowledge, the master immediately issues another start condition and the slave address with
the R/W bit set to one. This will be followed by an acknowledge
from the FM24C64 and then by the eight bit word. The master will
Current Address Read (Figure 6)
S
T
A
R
T
Bus Activity:
Master
1 0 1 0
SDA Line
S
T
O
P
SLAVE
ADDRESS
1
A
C
K
Bus Activity:
EEPROM
DATA
NO
A
C
K
Random Read (Figure 7)
S
T
A
Bus Activity: R
Master T
SLAVE
ADDRESS
WORD
ADDRESS (1)
S
T
A
R
T
WORD
ADDRESS (0)
SLAVE
ADDRESS
0
SDA Line
1
A
C
K
Bus Activity:
EEPROM
DATA
A
C
K
A
C
K
A
C
K
NO
A
C
K
Sequential Read (Figure 8)
Bus Activity:
Master
S
T
O
P
A
C
K
Slave
Address
A
C
K
S
T
O
P
A
C
K
SDA Line
Bus Activity:
EEPROM
A
C
K
DATA n +1
DATA n +1
DATA n + 2
11
FM24C64 Rev. C
DATA n + x
NO
A
C
K
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FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Read Operations
FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.150 - 0.157
(3.810 - 3.988)
0.010 - 0.020
x 45¡
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
8¡ Max, Typ.
All leads
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.004
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
8-Pin Molded Small Outline Package (M8)
Package Number M08A
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0118
(0.19 - 0.30)
Gage
plane
0¡-8¡
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Lead Molded Thin Shrink Small Outline Package (MT8)
Package Number MTC08
12
FM24C64 Rev. C
www.fairchildsemi.com
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
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13
FM24C64 Rev. C
www.fairchildsemi.com
FM24C64 – 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted