HANBit HSD8M64D8A Synchronous DRAM Module 64Mbyte (8Mx64bit),DIMM, 4Banks, 4K Ref., 3.3V Part No. HSD8M64D8A GENERAL DESCRIPTION The HSD8M64D8A is a 8M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of eight CMOS 2M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M64D8A is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES • Part Identification HSD8M64D8A-F/10H : 100MHz (CL=2&3) HSD8M64D8A-F/10L : 100MHz (CL=3) HSD8M64D8A-F/10 : 100MHz (CL=2) HSD8M64D8A-F/13 : 133MHz (CL=3) F means Auto & Self refresh with Low-Power (3.3V) • Burst mode operation • Auto & self refresh capability (4096 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ±0.3V power supply • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • The used device is 2M x 8bit x 4Banks SDRAM URL : www.hbe.co.kr REV.1.0(August.2002) - 1- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A PIN ASSIGNMENT PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 Vss 29 DQM1 57 DQ18 85 Vss 113 DQM5 141 DQ50 2 DQ0 30 /CS0 58 DQ19 86 DQ32 114 /CS1 142 DQ51 3 DQ1 31 NC 59 VDD 87 DQ33 115 /RAS 143 VDD 4 DQ2 32 Vss 60 DQ20 88 DQ34 116 Vss 144 DQ52 5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC 6 VDD 34 A2 62 VREF 90 VDD 118 A3 146 VREF 7 DQ4 35 A4 63 CKE1 91 DQ36 119 A5 147 NC 8 DQ5 36 A6 64 Vss 92 DQ37 120 A7 148 Vss 9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53 10 DQ7 38 A10 66 DQ22 94 DQ39 122 BA0 150 DQ54 11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55 12 Vss 40 VDD 68 Vss 96 Vss 124 VDD 152 Vss 13 DQ9 41 VDD 69 DQ24 97 DQ41 125 CLK1 153 DQ56 14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 A12 154 DQ57 15 DQ11 43 Vss 71 DQ26 99 127 Vss 155 DQ58 16 DQ12 44 NC 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 /CS2 73 VDD 101 DQ45 129 CS3 157 VDD 18 VDD 46 DQM2 74 DQ28 102 VDD 130 DQM6 158 DQ60 19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61 20 DQ15 48 NC 76 DQ30 104 DQ47 132 A13 160 DQ62 21 NC 49 VDD 77 DQ31 105 NC 133 VDD 161 DQ63 22 NC 50 NC 78 Vss 106 NC 134 NC 162 Vss 23 Vss 51 NC 79 CLK2 107 Vss 135 NC 163 CLK3 24 NC 52 NC 80 NC 108 NC 136 NC 164 NC 25 NC 53 NC 81 WP 109 NC 137 NC 165 SA0 26 VDD 54 Vss 82 SDA 110 VDD 138 Vss 166 SA1 27 /WE 55 DQ1C6 83 SCL 111 /CAS 139 DQ48 167 SA2 28 DQM0 56 DQ17 84 VDD 112 DQM4 140 DQ49 168 VDD URL : www.hbe.co.kr REV.1.0(August.2002) - 2- DQ43 HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A FUNCTIONAL BLOCK DIAGRAM DQ0-63 CKE0 /CA CKE CAS /RAS RAS /CS0 CE U1 WE CKE CAS U6 RAS /CS CE WE CKE CAS WE CKE CAS WE CKE CAS WE CKE CAS WE CKE CAS WE CKE CAS A0-A12 U9 RAS CE A0-A12 U4 RAS CE A0-A12 U8 RAS CE A0-A12 U3 RAS CE A0-A12 U7 RAS CE A0-A12 U2 RAS CE A0-A12 WE A0-A12 CLK DQ0-7 CLKA DQM0 DQM0 BA0-1 CLK DQ16-23 CLKB DQM2 DQM2 BA0-1 CLK DQ32-39 DQM4 DQM4 BA0-1 CLK DQ48-55 DQM6 DQM6 BA0-1 CLK DQ8-15 DQM1 DQM1 BA0-1 CLK DQ24-31 DQM3 DQM3 BA0-1 CLK DQ40-47 DQM5 DQM5 BA0-1 CLK DQ56-63 DQM7 DQM7 BA0-1 /WE A0 - A12 BA0-1 Vcc Two 0.1uF Capacitors per each SDRAM Vss URL : www.hbe.co.kr REV.1.0(August.2002) - 3- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A PIN FUNCTION DESCRIPTION PIN NAME INPUT FUNCTION CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS /WE Column address Latches column addresses on the positive going edge of the CLK with CAS low. strobe Enables column access. Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output Makes data output Hi-Z, tSHZ after the clock and masks the output. mask Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Power and ground for the input buffers and the core logic. supply/ground ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 8W TSTG -55oC to 150oC Voltage on Any Pin Relative to Vss Storage Temperature Short Circuit Output Current IOS 400mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. URL : www.hbe.co.kr REV.1.0(August.2002) - 4- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70° C) ) PARAMETER Supply Voltage SYMBOL Vcc MIN 3.0 TYP. 3.3 MAX 3.6 UNIT V NOTE Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23° C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS CCLK 2.5 4.0 pF CIN 2.5 5.0 pF Address CADD 2.5 5.0 pF DQ (DQ0 ~ DQ7) COUT 4.0 6.5 pF Clock /RAS, /CAS,/WE,/CS, CKE, DQM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70° C) PARAMETER TEST CONDITION SYMBOL VERSION -13 -12 -10 -10L 75 75 70 70 UNIT NOTE mA 1 Burst length = 1 Operating current (One bank active) ICC1 tRC ≥ tRC(min) IO = 0mA CKE ≤ VIL(max) Precharge standby current in power-down mode ICC2P tCC=10ns 1 mA 1 mA CKE & CLK ≤ VIL(max) ICC2PS tCC=∞ CKE ≥ VIH(min) CS* ≥ VIH(min), ICC2N tCC=10ns Input signals are changed Precharge standby current in one time during 20ns non power-down mode CKE ≥ VIH(min) ICC2NS CLK ≤ VIL(max), tCC=∞ 15 mA 6 Input signals are stable URL : www.hbe.co.kr REV.1.0(August.2002) - 5- HANBit Electronics Co.,Ltd. HANBit Active HSD8M64D8A standby current power-down mode in CKE ≤ VIL(max), tCC=10ns ICC3P 3 CKE&CLK ≤ VIL(max) ICC3PS mA 3 tCC=∞ CKE≥VIH(min), CS*≥VIH(min), Active standby current in ICC3N tCC=10ns 25 Input signals are changed one time during 20ns non power-down mode mA CKE≥VIH(min) (One bank active) CLK ≤VIL(max), ICC3NS tCC=∞ 15 Input signals are stable IO = 0 mA Page burst Operating current ICC4 (Burst mode) 4Banks Activated 115 110 95 95 mA 1 135 130 125 125 mA 2 tCCD = 2CLKs Refresh current ICC5 Self refresh current ICC6 tRC ≥ tRC(min) CKE ≤ 0.2V 1 mA 400 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70° C) PARAMETER Value UNIT 2.4/0.4 V 1.4 V tr/tf = 1/1 Ns 1.4 V AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 +3.3V Vtt=1.4V 50Ω 1200Ω DOUT DOUT 870Ω Z0=50Ω 50pF 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 2) AC output load circuit (Fig. 1) DC output load URL : www.hbe.co.kr REV.1.0(August.2002) - 6- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) Row cycle time 100 tRC(min) 65 ns 68 70 70 2 ns 1 CLK 2.5 Last data in to row precharge tRDL(min) Last data in to Active delay tDAL(min) Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 ea 4 2 CLK + 20 ns CAS latency=3 2 Number of valid output data CAS latency=2 - 1 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. . AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 PARAMETER -12 -10 -10L SYMBOL MIN MAX MIN MAX MIN MAX MIN UNIT NOTE ns 1 ns 1,2 ns 2 MAX CAS 7.5 8 10 10 latency=3 CLK cycle time tCC 1000 1000 1000 1000 CAS - - 10 12 latency=2 CAS 5.4 CLK to valid latency=3 output delay CAS 6 6 6 tSAC - - 6 7 latency=2 CAS 2.7 Output data hold time 3 3 3 latency=3 tOH CAS - - 3 3 latency=2 URL : www.hbe.co.kr REV.1.0(August.2002) - 7- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 2 CLK to output CAS in Hi-Z latency=3 5.4 6 6 6 ns - - 6 7 ns tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND Register Mode register set Auto refresh Refresh Entry Self refres Exit h Bank active & row addr. Read & column address Write & column address Auto CKE n /C S /R A S /C A S /W E D Q M H X L L L L X OP code L L L H X X X X H H L BA 0,1 L H H H H X X X X L L H H X V X L H L H X V L H H H precharge disable Auto CKE n-1 precharge Auto L H L L X All banks Clock suspend or active power down Precharge power down mode 3 3 X H X Entry H L Exit L H Entry H L Exit L H DQM H No operation command H Address 4,5 L L H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X H X X X L H H H X X X - 8- 4 4,5 X V L X H 6 X X X X X X V X X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) URL : www.hbe.co.kr REV.1.0(August.2002) 4 (A0 ~ A9) H H e 3 (A0 ~ A9) V disable Bank selection 3 Column L X precharge Precharg 1,2 Column H Burst Stop NOTE Address H precharge disable A11 A9~A0 Row address L disable Auto A10/ AP HANBit Electronics Co.,Ltd. 7 HANBit HSD8M64D8A Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) TIMING DIAGRAMS Please refer to attached timing diagram chart (II) PACKAGING INFORMATION Unit : mm Front View URL : www.hbe.co.kr REV.1.0(August.2002) - 9- HANBit Electronics Co.,Ltd. HANBit HSD8M64D8A ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE HMD8M64D8A-13 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-10L 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-10 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-10H 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-F13 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-F10L 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-F10 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM HMD8M64D8A-F10H 64Byte 8M x 64 168 Pin-DIMM 4K 3.3V SDRAM MAX.frq CL3 133MHz CL3 100MHz CL2 100MHz CL 2&3 100MHz CL3 133MHz CL3 100MHz CL2 100MHz CL 2&3 100MHz F means Auto & Self refresh with Low-Power (3.3V) URL : www.hbe.co.kr REV.1.0(August.2002) - 10 - HANBit Electronics Co.,Ltd.