LINER LTC4214-2IMS Negative low voltage hot swap controller Datasheet

LTC4214-1/LTC4214-2
Negative Low Voltage
Hot Swap Controllers
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DESCRIPTIO
FEATURES
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The LTC®4214 negative voltage Hot SwapTM controller
allows a board to be safely inserted and removed from a
live backplane. Output current is controlled by three stages
of current limiting: a timed circuit breaker, active current
limiting and a fast feedforward path that limits peak
current under worst-case catastrophic fault conditions.
Allows Safe Board Insertion and Removal from a
Live Backplane
Controls Supplies from 0V to –16V
Adjustable Analog Current Limit With Circuit
Breaker Timer
Fast Response Time Limits Peak Fault Current
Adjustable Soft-Start Current Limit
Adjustable Timer with Drain Voltage Accelerated
Response
Adjustable Undervoltage/Overvoltage Protection
LTC4214-1: Latch Off After Fault
LTC4214-2: Automatic Retry After Fault
Available in the 10-Pin MSOP Package
Adjustable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the
desired operating range. The LTC4214 controls negative
supplies ranging from near zero to –16V. A multifunction
timer delays initial start-up and controls the circuit breaker’s
response time. This response time is accelerated by
sensing excessive MOSFET drain voltage, keeping the
MOSFET within its safe operating area (SOA). An adjustable soft-start circuit controls MOSFET inrush current at
start-up. A power good status output can enable a power
module at start-up or disable it if the circuit breaker trips.
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APPLICATIO S
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Hot Board Insertion
Electronic Circuit Breaker
Negative Power Supply Control
Central Office Switching
High Availability Servers
Disk Arrays
Optical Networking/Switching
ECL
The LTC4214-1 latches off after a circuit breaker fault times
out. The LTC4214-2 provides automatic retry after a fault.
The LTC4214 is available in the 10-pin MSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
– 5.2V/5A ECL Supply Hot Swap Controller
Start-Up Behavior
3.3V
EN
2k
BSS138
GND
GND
10Ω
470Ω
CLOAD
100µF
SMAJ7A
100nF
–5.2V
ECL
1
GND
(SHORT PIN)
34k
1%
32.4k
1%
5.6nF
1nF
PUSH
RESET
VIN
LTC4214-1
2
PWRGD
9, 8
7
UV/OV DRAIN
10
6
TIMER
GATE
3
4
SS
SENSE
VEE
3.3nF
+
0.1µF
GATE
5V/DIV
SENSE
20mV/DIV
75k
IRF7413
22Ω
10Ω
0.01Ω
5
10nF
VOUT
5V/DIV
PWRGD
5V/DIV
4214 TA02
–5.2V
4214 TA01
421412f
1
LTC4214-1/LTC4214-2
U
W W
W
ABSOLUTE
AXI U RATI GS
U
W
U
PACKAGE/ORDER I FOR ATIO
All Voltages Referred to VEE (Note 1)
VIN ............................................................ – 0.3V to 17V
Input/Output Pins
(Except SENSE and DRAIN) Voltage ..........– 0.3V to 17V
SENSE Pin Voltage ................................... – 0.6V to 17V
Current Out of SENSE Pin (20µs Pulse) ........... – 200mA
DRAIN Pin Minimum Voltage .............................. – 0.3V
Current into DRAIN Pin (100µs Pulse) ................... 5mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4214-1C/LTC4214-2C ....................... 0°C to 70°C
LTC4214-1I/LTC4214-2I ................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
VIN
PWRGD
SS
SENSE
VEE
1
2
3
4
5
10
9
8
7
6
TIMER
UV
OV
DRAIN
GATE
LTC4214-1CMS
LTC4214-2CMS
LTC4214-1IMS
LTC4214-2IMS
MS PACKAGE
10-LEAD PLASTIC MSOP
MS PART MARKING
TJMAX = 125°C, θJA = 160°C/W
LTABH
LTABK
LTABJ
LTABL
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UV = OV = 2.5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Supply Voltage
IIN
VIN Supply Current
UV = OV = 2.5V
●
VLKO
VIN Undervoltage Lockout
Coming Out of UVLO (Rising VIN)
●
VLKH
VIN Undervoltage Lockout Hysteresis
VCB
Circuit Breaker Current Limit Voltage
VCB = (VSENSE – VEE)
●
44
50
56
mV
VACL
Analog Current Limit Voltage
VACL = (VSENSE – VEE), SS = Open
●
60
70
80
mV
VFCL
Fast Current Limit Voltage
VFCL = (VSENSE – VEE)
●
150
200
300
mV
VSS
SS Voltage
After End of SS Timing Cycle
RSS
SS Output Impedance
ISS
SS Pin Current
VOS
Analog Current Limit Offset Voltage
●
TYP
6
MAX
16
V
0.8
2
mA
5.1
5.6
0.3
UV = OV = 2.5V, VSENSE = VEE, VSS = 0V (Sourcing)
UV = OV = 0V, VSENSE = VEE, VSS = 1V (Sinking)
VACL+VOS Ratio (VACL + VOS) to SS Voltage
VSS
UNITS
V
V
1.6
V
73
kΩ
–22
14
µA
mA
10
mV
0.05
V/V
IGATE
GATE Pin Output Current
VSENSE = VEE, VGATE = 0V (Sourcing)
VSENSE – VEE = 0.15V, VGATE = 3V (Sinking)
VSENSE – VEE = 0.3V, VGATE = 1V (Sinking)
●
–30
–50
17
190
–70
µA
mA
mA
VGATE
External MOSFET Gate Drive
VGATE – VEE
●
10
11
12
V
VGATEH
Gate High Threshold
VGATEH = VIN – VGATE for PWRGD Status
2.8
V
VGATEL
Gate Low Threshold
(Before Gate Ramp-Up)
0.5
V
VUVHI
UV Pin Threshold
UV Rising
VUVHST
UV Pin Hysteresis
VOVHI
OV Pin Threshold
VOVHST
OV Pin Hysteresis
OV Rising
●
2.137
2.25
2.363
V
●
0.22
0.25
0.28
V
●
2.85
3
3.15
V
●
0.12
0.15
0.18
V
421412f
2
LTC4214-1/LTC4214-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UV = OV = 2.5V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
ISENSE
SENSE Pin Input Current
VSENSE = 50mV
IINP
UV, OV Pin Input Current
UV = OV = 2.5V
VTMRH
TIMER Pin Voltage High Threshold
3
V
VTMRL
TIMER Pin Voltage Low Threshold
1.7
V
ITMR
TIMER Pin Current
Timer On (Initial Cycle/Latchoff/
Shutdown Cooling, Sourcing), VTMR = 2.2V
–5
µA
Timer Off (Initial Cycle, Sinking), VTMR = 2.2V
28
mA
Timer On (Circuit Breaker, Sourcing,
IDRN = 0µA), VTMR = 2.2V
–40
µA
Timer On (Circuit Breaker, Sourcing,
IDRN = 20µA), VTMR = 2.2V
–200
µA
Timer Off (Circuit Breaker/
Shutdown Cooling, Sinking), VTMR = 2.2V
5
µA
∆ITMRACC [(ITMR at IDRN = 20µA) – (ITMR at IDRN = 0µA)]
∆IDRN
20µA
Timer On (Circuit Breaker with IDRN = 20µA)
8
µA/µA
VDRNL
DRAIN Pin Voltage Low Threshold
For PWRGD Status
IDRNL
DRAIN Leakage Current
VDRAIN = 2.5V
VDRNCL
DRAIN Pin Clamp Voltage
IDRN = 20µA
VPGL
PWRGD Output Low Voltage
IPG = 1.6mA
IPG = 5mA
●
●
IPGH
PWRGD Pull-Up Current
VPWRGD = 0V (Sourcing)
●
tSS
SS Default Ramp Period
SS Pin Floating, VSS Ramps from 0.2V to 1.4V
tPLLUG
tPHLOG
●
–15
–30
µA
●
±0.1
±1
µA
●
1.109
–30
UNITS
1.232
1.355
V
±0.1
±1
µA
4.2
5
V
0.2
0.4
1.1
V
V
–50
–70
µA
130
µs
UV Low to Gate Low
0.4
µs
OV High to Gate Low
0.4
µs
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to VEE unless otherwise
specified.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
otherwise specified.
IIN vs Temperature
All voltages are referenced to VEE Unless
Undervoltage Lockout
VLKO vs Temperature
IIN vs VIN
1.6
1000
1.2
900
1.0
IIN (mA)
1.4
800
0.6
600
0.4
500
0.2
5.8
5.6
5.4
0.8
700
6
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
VLKO (V)
VIN = 12V
1100
IIN (µA)
MAX
3.5
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
1200
TYP
5.2
5
4.8
4.6
400
–55 –35 –15
5
25
45
65
85 105 125
TEMPERATURE (°C)
0
4.4
4.2
0
2
4
6
8
10 12 14 16 18 20
VIN (V)
4214 G01
4214 G02
4
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G03
421412f
3
LTC4214-1/LTC4214-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
otherwise specified.
Undervoltage Lockout Hysteresis
VLKH vs Temperature
Circuit Breaker Current Limit
Voltage VCB vs Temperature
0.7
56
Analog Current Limit Voltage
VACL vs Temperature
80
VIN = 12V
54
0.5
76
74
0.3
72
VACL (mV)
VCB (mV)
52
0.4
50
70
68
48
66
0.2
64
46
0.1
62
0
–55 –35 –15
44
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
60
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G04
4214 G06
VSS vs Temperature
1.80
VIN = 12V
RSS vs Temperature
85
VIN = 12V
83
1.75
275
79
225
RSS (kΩ)
1.65
VSS (V)
VFCL (mV)
250
1.60
1.55
200
75
73
69
175
1.45
150
–55 –35 –15
67
1.40
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
VOS vs Temperature
11.0
VIN = 12V
UV = OV = VSENSE = VEE
VSS = 1V
10.8
(VACL + VOS)/VSS vs Temperature
0.060
VIN = 12V
0.058
10.6
(VACL + VOS)/VSS (V/V)
VOS (mV)
10
10.2
10.0
9.8
9.6
5
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G10
0.054
0.052
0.050
0.048
0.046
9.4
0.044
9.2
0.042
9.0
–55 –35 –15
VIN = 12V
0.056
10.4
15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G09
4214 G08
ISS (Sinking) vs Temperature
0
–55 –35 –15
65
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G07
ISS (mA)
77
71
1.50
20
VIN = 12V
81
1.70
25
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G05
Fast Current Limit Voltage
VFCL vs Temperature
300
VIN = 12V
78
0.6
VLKH (V)
All voltages are referenced to VEE Unless
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G11
0.040
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G12
421412f
4
LTC4214-1/LTC4214-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
otherwise specified.
IGATE (ACL, Sinking)
vs Temperature
IGATE (Sourcing) vs Temperature
58
56
20
52
50
48
400
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
VSENSE – VEE = 0.15V
VGATE = 3V
25
IGATE (mA)
IGATE (µA)
54
30
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
VSENSE = VEE
VGATE = 0V
IGATE (FCL, Sinking)
vs Temperature
15
300
10
46
5
40
–55 –35 –15
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
3.4
VGATEH (V)
VGATE (V)
11.4
10.8
VIN = 12V
UV/OV = 2.5V
VGATEH = VIN – VGATE
0.7
3.2
0.6
3.0
0.5
2.8
10.4
10.2
0.3
2.4
0.2
2.2
0.1
2.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5
25
45
65
VIN = 12V
VIN = 12V
2.30
0.26
3.05
VOVHI (V)
3.10
0.25
0.24
2.95
2.15
0.23
2.90
0.22
–55 –35 –15
65
85 105 125
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G20
VIN = 12V
3.00
2.20
4214 G19
45
VOVHI vs Temperature
3.15
0.27
5 25 45 65 85 105 125
TEMPERATURE (°C)
25
4214 G18
2.35
2.10
–55 –35 –15
5
TEMPERATURE (°C)
VUVHST vs Temperature
0.28
VUVHST (V)
VUVHI (V)
0
–55 –35 –15
85 105 125
4214 G17
VUVHI vs Temperature
85 105 125
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP-UP
TEMPERATURE (°C)
4214 G16
2.25
65
0.4
2.6
10.6
10.0
–55 –35 –15
45
VGATEL vs Temperature
0.8
VGATEL (V)
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
VSENSE = VEE
11.0
25
4214 G15
VGATEH vs Temperature
3.6
11.2
5
TEMPERATURE (°C)
4214 G14
VGATE vs Temperature
2.40
150
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G13
11.6
200
50
42
11.8
250
100
44
12.0
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
VSENSE – VEE = 0.3V
VGATE = 1V
350
IGATE (mA)
60
All voltages are referenced to VEE Unless
2.85
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G21
421412f
5
LTC4214-1/LTC4214-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
otherwise specified.
VIN = 12V
0.17
–5
0.16
–10
ISENSE (µA)
VOVHST (V)
ISENSE vs Temperature
0
0.15
0.14
ISENSE vs (VSENSE – VEE)
0.01
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
GATE = HIGH
VSENSE – VEE = 50mV
0.10
–ISENSE (mA)
VOVHST vs Temperature
0.18
All voltages are referenced to VEE Unless
–15
–30
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G22
7.0
6.5
VTMRL
1.5
1.0
0.5
–55 –35 –15
50
VIN = 12V
TIMER = 2.2V
45
6.0
40
5.5
35
5.0
25
4.0
20
3.5
15
5
25
45
65
220
215
7.0
VIN = 12V
TIMER = 2.2V
IDRN = 20µA
6.5
45
205
5.5
ITMR (µA)
6.0
ITMR (µA)
210
200
195
4.5
30
190
4.0
25
185
3.5
25
45
65
85 105 125
TEMPERATURE (°C)
180
–55 –35 –15
5
25
45
65
85 105 125
TEMPERATURE (°C)
4214 G28
65
85 105 125
VIN = 12V
TIMER = 2.2V
5.0
35
5
45
ITMR (Cooling Cycle, Sinking)
vs Temperature
50
20
–55 –35 –15
25
4214 G27
ITMR (Circuit Breaker, IDRN =
20µA, Sourcing) vs Temperature
VIN = 12V
TIMER = 2.2V
IDRN = 0µA
40
5
TEMPERATURE (°C)
4214 G26
ITMR (Circuit Breaker, Sourcing)
vs Temperature
ITMR (µA)
10
–55 –35 –15
85 105 125
TEMPERATURE (°C)
4214 G25
55
VIN = 12V
TIMER = 2.2V
30
4.5
3.0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
2.0
ITMR (Initial Cycle, Sinking)
vs Temperature
ITMR (mA)
VTMRH
ITMR (µA)
TIMER THRESHOLD (V)
3.5
2.0
1.5
4214 G24
ITMR (Initial Cycle, Sourcing)
vs Temperature
VIN = 12V
2.5
1000
0.5
0
1.0
–1.5 –1.0 –0.5
(VSENSE – VEE) (V)
4214 G23
TIMER Threshold vs Temperature
3.0
VIN = 12V
UV/OV = 2.5V
TIMER = 0V
GATE = HIGH
TA = 25°C
100
–25
0.12
–55 –35 –15
60
10
–20
0.13
4.0
1
3.0
–55 –35 –15
5
25
45
65
85 105 125
TEMPERATURE (°C)
4214 G29
4214 G30
421412f
6
LTC4214-1/LTC4214-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
otherwise specified.
ITMR (Circuit Breaker, Sourcing)
vs IDRN
∆ITMRACC/∆IDRN vs Temperature
9.0
8.8
ITMR (mA)
1
0.1
8.6
IDRN vs VDRAIN
100
VIN = 12V
TIMER ON
(CIRCUIT BREAKING, IDRN = 20µA)
VIN = 12V
10
1
8.4
8.2
IDRN (mA)
VIN = 12V
TIMER = 2.2V
TA = 25°C
(∆ITMRACC/∆IDRN (µA/µA)
10
All voltages are referenced to VEE Unless
8.0
7.8
0.1
0.01
7.6
0.001
TA = –40°C
TA = 25°C
TA = 85°C
TA = 125°C
7.4
0.0001
7.2
0.01
0.001
0.01
0.1
IDRN (mA)
1
7.0
–55 –35 –15
10
0.00001
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G31
4
6
VIN = 12V
FOR PWRGD STATUS
4.8
10
12
14
VPGL vs Temperature
2.5
VIN = 12V
IDRN = 20µA
VIN = 12V
2.0
IPG = 10mA
VDRNCL (V)
VPGL (V)
4.4
1.30
16
4214 G33
4.6
1.25
8
VDRAIN (V)
VDRNCL vs Temperature
5.0
1.35
VDRNL (V)
2
4214 G32
VDRNL vs Temperature
1.40
0
4.2
4.0
1.5
IPG = 5mA
1.0
3.8
1.20
3.6
0.5
1.15
IPG = 1.6mA
3.4
1.10
–55 –35 –15
3.2
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
IPGH (Sourcing) vs Temperature
65
4214 G36
tPLLUG and tPHLOG
vs Temperature
tSS vs Temperature
160
VIN = 12V
VPWRGD = 0V
150
0.8
VIN = 12V
SS PIN FLOATING,
VSS RAMPS FROM 0.2V TO 1.4V
0.6
55
50
45
DELAY (µs)
140
tSS (µs)
IPGH (µA)
VIN = 12V
0.7
60
130
120
0.5
0.4
0.3
tPLLUG
tPHLOG
0.2
40
110
35
30
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G35
4214 G34
70
0
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
5
25
45
65
85 105 125
TEMPERATURE (°C)
4214 G37
100
–55 –35 –15
0.1
5 25 45 65 85 105 125
TEMPERATURE (°C)
4214 G38
0
–55 –35 –15
5
25
45
65
85 105 125
TEMPERATURE (°C)
4214 G39
421412f
7
LTC4214-1/LTC4214-2
U
U
U
PI FU CTIO S
VIN (Pin 1): Positive Supply Input. Connect this pin to the
positive side of the supply via a resistor. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO (5.1V), overriding UV and
OV. If UV is high, OV is low and VIN comes out of UVLO,
TIMER starts an initial timing cycle before initiating a GATE
ramp-up. If VIN drops below approximately 4.8V, GATE
pulls low immediately.
PWRGD (Pin 2): Power Good Status Output. At start-up,
PWRGD latches low if DRAIN is below 1.232V and GATE
is within 2.8V of VIN. PWRGD status is reset by UV, VIN
(UVLO) or a circuit breaker fault timeout. This pin is
internally pulled high by a 50µA current source.
SS (Pin 3): Soft-Start Pin. This pin is used to ramp inrush
current during start up, thereby effecting control over di/
dt. A 20x attenuated version of the SS pin voltage is
presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (CSS) is
ramped by a 22µA current source. The GATE pin is held
low until SS exceeds 20 • VOS = 0.2V. SS is internally
shunted by a 73k resistor (RSS) which limits the SS pin
voltage to 1.6V. This corresponds to an analog current
limit SENSE voltage of 70mV. If the SS capacitor is
omitted, the SS pin ramps from 0V to 1.6V in about 220µs.
The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4): Circuit Breaker/Current Limit Sense Pin.
Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three
steps. If SENSE exceeds VCB (50mV), the circuit breaker
comparator activates a (40µA + 8 • IDRN) TIMER pull-up
current. If SENSE exceeds VACL (70mV), the analog current limit amplifier pulls GATE down to regulate the MOSFET
current at VACL/RS. In the event of a catastrophic shortcircuit, SENSE may overshoot 70mV. If SENSE reaches
VFCL (200mV), the fast current limit comparator pulls
GATE low with a strong pull-down. To disable the circuit
breaker and current limit functions, connect SENSE to VEE.
VEE (Pin 5): Negative Supply Voltage Input. Connect this
pin to the negative side of the power supply.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This
pin is pulled high by a 50µA current source. GATE is pulled
low by invalid conditions at VIN (UVLO), UV, OV, or a circuit
breaker fault timeout. GATE is actively servoed to control
the fault current as measured at SENSE. A compensation
capacitor at GATE stabilizes this loop. A comparator
monitors GATE to ensure that it is low before allowing an
initial timing cycle, GATE ramp-up after an overvoltage
event or restart after a current limit fault. During GATE
start-up, a second comparator detects if GATE is within
2.8V of VIN before PWRGD is set.
DRAIN (Pin 7): Drain Sense Input. DRAIN measures the
drain-source voltage of the external N-channel MOSFET
switch for two purposes: first, a comparator detects when
VDS < 1.232V and together with the GATE high comparator, controls the status of the PWRGD output. Second, if
VDS is greater than the DRAIN clamp of approximately
4.2V (VDRNCL), the current through resistor RD is multiplied by 8 and added to the TIMER’s 40µA pull-up current
during a circuit breaker fault cycle. This reduces the
fault time and MOSFET heating under conditions of high
dissipation.
OV (Pin 8): Overvoltage Input. The active high threshold at
the OV pin is set at 3V with respect to VEE and exhibits
0.15V hysteresis. If OV > 3V, GATE pulls low. When OV
returns below 2.85V, GATE start-up begins without an
initial timing cycle. If an overvoltage condition occurs in
the middle of an initial timing cycle, the initial timing cycle
is restarted after the overvoltage condition goes away. An
overvoltage condition does not reset the PWRGD flag. The
internal UVLO at VIN always overrides OV. A 1nF to 10nF
capacitor at OV prevents transients and switching noise
from affecting the OV thresholds and prevents glitches at
the GATE pin.
421412f
8
LTC4214-1/LTC4214-2
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PI FU CTIO S
UV (Pin 9): Undervoltage Input. The active high threshold
at the UV pin is set at 2.25V with respect to VEE and exhibits
0.25V hysteresis. If UV < 2V, PWRGD pulls high, both
GATE and TIMER pull low. If UV rises above 2.25V, this
initiates an initial timing cycle followed by GATE start-up.
The internal UVLO at VIN always overrides UV. A low at UV
resets an internal fault latch. A 1nF to 10nF capacitor at UV
prevents transients and switching noise from affecting the
UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 10): Timer Input. TIMER is used to generate
an initial timing delay at start-up and to delay shutdown in
the event of an output overload (circuit breaker fault).
TIMER starts an initial timing cycle when the following
conditions are met: UV is high, OV is low, VIN clears UVLO,
TIMER pin is low, GATE is lower than VGATEL, SS < 0.2V,
and VSENSE – VEE < VCB. A pull-up current of 5µA then
charges CT, generating a time delay. If CT charges to
VTMRH (3V), the timing cycle terminates, TIMER quickly
pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 40µA pull-up current charging
CT. If DRAIN is approximately 4.2V during this cycle, the
timer pull-up has an additional current of 8 • IDRN. If SENSE
drops below 50mV before TIMER reaches 3V, a 5µA pulldown current slowly discharges the CT. In the event that CT
eventually integrates up to the VTMRH threshold, the circuit
breaker trips, GATE quickly pulls low and PWRGD pulls
high. The LTC4214-1 TIMER pin latches high with a 5µA
pull-up source. This latched fault is cleared by either
pulling TIMER low with an external device or by pulling UV
below 2V. The LTC4214-2 starts a shutdown cooling cycle
following an overcurrent fault. This cycle consists of 4
discharging ramps and 3 charging ramps. The charging
and discharging currents are 5µA and TIMER ramps
between its 1.7V and 3V thresholds. At the completion of
a shutdown cooling cycle, the LTC4214-2 attempts a startup cycle.
421412f
9
LTC4214-1/LTC4214-2
W
BLOCK DIAGRA
VIN
1
–
7 DRAIN
VIN
+
1.232V
8×
3V
1×
VIN
1×
1×
50µA
VEE
2 PWRGD
VIN
3V
–
50µA
VEE
6 GATE
+
OV 8
2.8V
–
VEE
–
UV 9
–+
VIN
+
2.25V
+
VIN
LOGIC
VIN
–
+
3V
5µA
–
40µA
+
0.5V
TIMER 10
+
–
VIN
1.7V
200mV
–
5µA
VEE
FCL
+
+–
VEE
VEE
22µA
+
SS 3
VOS = 10mV
69.35k
3.65k
VEE
ACL
–
+
RSS
–+
CB
VEE
4 SENSE
50mV
–
5
VEE
VEE
+–
VEE
4214 BD
421412f
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LTC4214-1/LTC4214-2
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OPERATIO
Hot Circuit Insertion
3. The voltage at OV < 2.85V.
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4214 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
4. The (SENSE – VEE) voltage is < 50mV (VCB).
Initial Start-Up
The LTC4214 resides on a removable circuit board and
controls the path between the connector and the load with
an external MOSFET switch (see Figure 1). Both inrush
control and short-circuit protection are provided by the
MOSFET.
A detailed schematic is shown in Figure 2. – 12V and
GND receive power through the longest connector pins
and are the first to connect when the board is inserted. The
GATE pin holds the MOSFET off during this time. UV/OV
determines whether or not the MOSFET should be turned
on based upon internal high accuracy thresholds and an
external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the
divider detects GND by way of a short connector pin that
is the last to mate during the insertion sequence.
5. The voltage at SS is < 0.2V (20 • VOS).
6. The voltage on the TIMER capacitor (CT) is < 1.7V (VTMRL).
7. The voltage at GATE is < 0.5V (VGATEL).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5µA into
CT. If VIN, UV or OV falls out of range, the start-up cycle
stops and TIMER discharges CT to less than 1.7V, then
waits until the aforementioned conditions are once again
met. If CT successfully charges to 3V, TIMER pulls low
and both SS and GATE pins are released. GATE sources
50µA (IGATE), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits VSENSE to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of VIN and DRAIN is lower than VDRNL.
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will
LONG
Interlock Conditions
GND
GND
RX
10Ω
CX
100nF
A start-up sequence commences once these “interlock”
conditions are met.
SHORT
1. The input voltage VIN exceeds 5.1V (UVLO).
R1
121k
1%
2. The voltage at UV > 2.25V.
LONG
RIN
470Ω
CIN
0.1µF
C1
1nF
GND
+
CLOAD
LOAD
LONG
R2
32.4k
1%
CSS
22nF
CT
47nF
CLOAD
100µF
TYP
1
8
VIN
OV
9
2
UV
PWRGD
LTC4214-1
10
TIMER
3
7
SS
DRAIN
VEE
PLUG-IN BOARD
LTC4214
Z1
R3
10k
SENSE
5
CC
10nF
4
+
EN
R4
10k
GATE
6
RD
RC 10Ω 475k
–12V
LONG
Z1: SMAJ15A
–12V
RS
0.025Ω
Q1
IRF7413
4214 F02
VOUT
BACKPLANE
4214 F01
Figure 2. –12V, 2A Hot Swap Controller
Figure 1. Basic LTC4214 Hot Swap Topology
421412f
11
LTC4214-1/LTC4214-2
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OPERATIO
turn on gradually so that the inrush into the load capacitance remains a low value. The output will simply ramp to
–12V and the LTC4214 will fully enhance the MOSFET. A
second possibility is that the load current exceeds the
soft-start current limit threshold of [VSS(t)/20 – VOS]/RS.
In this case the LTC4214 will ramp the output by sourcing
soft-start limited current into the load capacitance. If the
soft-start voltage is below 1.2V, the circuit breaker TIMER
is held low. Above 1.2V, TIMER ramps up. It is important
to set the timer delay so that, regardless of which start-up
mode is used, the TIMER ramp is less than one circuit
breaker delay time. If this condition is not met, the
LTC4214-1 may shut down after one circuit breaker delay
time whereas the LTC4214-2 may continue to autoretry.
Board Removal
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
Current Control
Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 70mV for an
analog current limit loop; and 200mV for a fast, feedforward
comparator which limits peak current in the event of a
catastrophic short-circuit.
If, owing to an output overload, the voltage drop across
RS exceeds 50mV, TIMER sources 40µA into CT. CT
eventually charges to a 3V threshold and the LTC4214
shuts off. If the overload goes away before CT reaches 3V
and SENSE measures less than 50mV, CT slowly discharges (5µA). In this way the LTC4214’s circuit breaker
function responds to low duty cycle overloads and accounts for fast heating and slow cooling characteristics of
the MOSFET.
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches 70mV, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of 70mV/RS. In current limit
mode, VOUT typically rises and this increases MOSFET
heating. If VOUT > VDRNCL (4.2V), connecting an external
resistor, RD, between VOUT and DRAIN allows the fault
timing cycle to be shortened by accelerating the charging
of the TIMER capacitor. The TIMER pull-up current is
increased by 8 • IDRN. Note that because SENSE > 50mV,
TIMER charges CT during this time and the LTC4214 will
eventually shut down.
Low impedance failures on the load side of the LTC4214
can produce high current slew rates. Under these conditions, overshoot is inevitable. A fast SENSE comparator
with a threshold of 200mV detects overshoot and pulls
GATE low much harder and hence much faster than the
weaker current limit loop. The 70mV/RS current limit loop
then takes over and servos the current as previously
described. As before, TIMER runs and shuts down the
LTC4214 when CT reaches 3V.
If CT reaches 3V, the LTC4214-1 latches off with a 5µA
pull-up current source whereas the LTC4214-2 starts a
shutdown cooling cycle. The LTC4214-1 circuit breaker
latch is reset by either pulling UV momentarily low or dropping the input voltage VIN below the internal UVLO threshold of 4.8V or pulling TIMER momentarily low with a switch.
The LTC4214-2 retries after its shutdown cooling cycle.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, transient
currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hotswappable products could cause higher than anticipated
input current and temporary detection of an overcurrent
condition. The action of TIMER and CT rejects these events
allowing the LTC4214 to “ride out” temporary overloads and
disturbances that could trip a simple current comparator
and, in some cases, blow a fuse.
421412f
12
LTC4214-1/LTC4214-2
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APPLICATIO S I FOR ATIO
An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds:
SUPPLY VOLTAGE
The LTC4214 requires a (VIN – VEE) voltage of 6V to 16V
to function. This can be derived from GND and –12V of a
–12V system or the 3.3V and –5.2V of a –5.2V system. The
positive supply is connected to VIN via an RC network
so that the LTC4214 can have a usable VIN during load
short or other transient events when (VIN – VEE) glitches
below 6V.
OV low-to-high (VOVHI) = 3V
OV high-to-low (VOVHI – V0VHST) = 2.85V
In Figure 2, a divider (R1-R2) is used to scale the supply
voltage of 12V ±10%. Using R1 = 121k and R2 = 32.4k
gives a typical operating range of 10.7V to 13.5V. The
under and overvoltage shutdown thresholds are then 9.5V
to 14.2V. 1% divider resistors are recommended to preserve threshold accuracy.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors VIN for
undervoltage. The thresholds are defined by VLKO and its
hysteresis, VLKH. When VIN rises above 5.1V (VLKO) the
chip is enabled; below 4.8V (VLKO – VLKH) it is disabled and
GATE is pulled low. The UVLO function at VIN should not
be confused with the UV/OV pins. These are completely
separate functions.
The R1-R2 divider values shown in Figure 2 set a standing
current of slightly more than 75µA and define an impedance at UV/OV of 25kΩ. In most applications, 25kΩ
impedance coupled with 250mV UV hysteresis makes the
LTC4214 insensitive to noise. If more noise immunity is
desired, add a 1nF to 10nF filter capacitor from UV/OV
to VEE.
Separate UV and OV pins can be used for a wider
operating range such as 10V to 14V as shown in Figure␣ 3.
Other combinations are possible with different resistor
arrangements.
UV/OV COMPARATORS
An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds:
UV low-to-high (VUVHI) = 2.25V
UV high-to-low (VUVHI – VUVHST) = 2V
GND
GND
RX
10Ω
CX
100nF
GND
(SHORT PIN)
RIN
470Ω
Z1
1
R1
124k
1%
9
R2
3.65k
1%
8
10
R3
32.4k
1%
CT
47nF
C2
1nF
3
R4
100k
+
CIN
0.1µF
Q2
NDS0605
CL
100µF
VIN
EN
LTC4214-1
RPULLDN
10k
UV
PWRGD
OV
DRAIN
TIMER
GATE
SS
SENSE
VEE
CSS
22nF
5
2
7
RD
475k
6
VOUT
Q1
IRF7413
4
RC
10Ω
CC
10nF
RS
0.025Ω
4214 F03
–12V
Z1: SMAJ15A
Figure 3. – 12V/2A Application with Wider Input Operating Range
421412f
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LTC4214-1/LTC4214-2
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APPLICATIO S I FOR ATIO
UV/OV OPERATION
A low input to the UV comparator will reset the LTC4214
and pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4214,
pulls the MOSFET gate low and resets the latched PWRGD
high.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
DRAIN
Connecting an external resistor, RD, to the dual function
DRAIN pin allows VOUT sensing without it being damaged
by large voltage transients. Below 3V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less
than 1.232V (VDRNL). This condition, together with the
GATE low comparator, sets the PWRGD flag.
If VOUT > VDRNCL (4.2V), the DRAIN pin is clamped at about
4.2V and the current flowing in RD is given by:
IDRN ≈
VOUT − VDRNCL
RD
(1)
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 40µA TIMER current. This
accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds 4.2V and effectively shortens the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor CT is used at
TIMER to provide timing for the LTC4214. Four different
charging and discharging modes are available at TIMER:
1) A 5µA slow charge; initial timing and shutdown cooling
delay.
2) A (40µA + 8 • IDRN) fast charge; circuit breaker delay.
3) A 5µA slow discharge; circuit breaker "cool off" and
shutdown cooling.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5µA pull-up is used. The low
impedance switch is turned off and the 5µA current source
is enabled when the interlock conditions are met. CT
charges to 3V in a time period given by:
t=
3 V • CT
5µA
(2)
When CT reaches 3V (VTMRH), the low impedance switch
turns on and discharges CT. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
RS, the TIMER pin charges CT with (40µA + 8 • IDRN). If CT
charges to 3V, the GATE pin pulls low and the LTC4214-1
latches off while the LTC4214-2 starts a shutdown cooling
cycle. The LTC4214-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or VIN dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
t=
3 V • CT
40µA + 8 • IDRN
(3)
If VOUT < 3V, an internal PMOS device isolates any DRAIN
pin leakage current, making IDRN = 0µA in Equation (3). If
VOUT > 4.2V (VDRNCL) during the circuit breaker fault period,
the charging of CT accelerates by 8 • IDRN of Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
will not reach 3V and the LTC4214 will not shut the external
421412f
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LTC4214-1/LTC4214-2
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APPLICATIO S I FOR ATIO
MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermittent overload with VOUT < 3V and an aggregate duty cycle
of 12.5% or more will eventually trip the circuit breaker
and shut down the LTC4214. Figure 4 shows the circuit
breaker response time in seconds normalized to 1µF for
IDRN = 0µA. The asymmetric charging and discharging of
CT is a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
t
3
=
CT (µF) (40 + 8 • IDRN ) • D − 5
[
]
NORMALIZED RESPONSE TIME (s/µF)
100
(4)
10
t
1
3
=
[(40 + 8 • IDRN) • D – 5]
0.1
0.01
0
tSHUTDOWN =
7 • 1.3V • CT
5µA
(5)
At the 1.7V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
IDRN = 0µA
CT(µF)
pull-down cycles and three 5µA pull-up cycles occur
between the 1.7V and 3V thresholds, creating a time
interval given by:
10 20 30 40 50 60 70 80 90 100
FAULT DUTY CYCLE (%)
4214 F04
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
1.6V in about 220µs. Connecting an external capacitor CSS
from SS to ground modifies the ramp to approximate an
RC response of:

t 

 − R •C 
VSS (t) ≈ VSS •  1 − e  SS SS  




An internal resistor divider (69.35k/3.65k) scales VSS(t)
down by 20 times to give the analog current limit threshold:
Figure 4. Circuit-Breaker Response Time
SHUTDOWN COOLING CYCLE
For the LTC4214-1 (latchoff version), TIMER latches high
with a 5µA pull-up after the circuit breaker fault TIMER
reaches 3V. For the LTC4214-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 3V
threshold. TIMER starts with a 5µA pull-down until it
reaches the 1.7V threshold. Then, the 5µA pull-up turns
back on until TIMER reaches the 3V threshold. Four 5µA
(6)
VACL (t) =
VSS (t)
− VOS
20
(7)
This allows the inrush current to be limited to VACL(t)/RS.
The offset voltage, VOS (10mV), ensures CSS is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
421412f
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LTC4214-1/LTC4214-2
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GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 50µA current source charges the MOSFET gate and
any associated external capacitance. The gate drive is
limited to no more than VIN.
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥ 5nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
relative to VIN and, together with the DRAIN low comparator, sets PWRGD status during GATE start-up.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
40µA TIMER pull-up. At 70mV, the ACL amplifier servos
the MOSFET current and, at 200mV, the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 3V (see Equation␣ 3), the LTC4214 shuts down and pulls GATE low.
If the SENSE pin encounters a voltage greater than 70mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE
overdrives the MOSFET in normal operation, the ACL
amplifier needs time to discharge GATE to the threshold
of the MOSFET. For a mild overload the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV
the FCL comparator takes over, quickly discharging the
GATE pin to near VEE potential. FCL then releases and the
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop and GATE undershoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5 for the LTC4214. Initially, the
current overshoots the fast current limit level of VSENSE =
200mV (Trace 2) as the GATE pin works to bring VGS under
control (Trace 3). The overshoot glitches the backplane in
the negative direction and when the current is reduced to
70mV/RS, the backplane responds by glitching in the
positive direction.
SUPPLY RING
OWING TO CURRENT
OVERSHOOT
GND WITH
RESPECT TO –12V
0.1ms
10V
SENSE
0.1ms
200mV
GATE
0.1ms
10V
TIMER
0.1ms
2V
SUPPLY RING
OWING TO MOSFET
TURN-OFF
TRACE 1
ONSET OF OUTPUT
SHORT CIRCUIT
FAST
CURRENT
LIMIT
TRACE 2
ANALOG
CURRENT
LIMIT
TRACE 3
TRACE 4
CTIMER RAMP
LATCH OFF
4214 F05
Figure 5. Output Short-Circuit Behavior of LTC4214
421412f
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TIMER commences charging CT (Trace 4) while the analog
current limit loop maintains the fault current at 70mV/RS,
which in this case is 3.5A (Trace 2). Note that the backplane voltage (Trace 1) sags under load. Timer pull-up is
accelerated by VOUT. When CT reaches 3V, GATE turns off,
PWRGD pulls high, the load current drops to zero and the
backplane rings in the positive direction. The transient
associated with the GATE turn off can be controlled with a
snubber to reduce ringing and transient voltage suppressor to clip off large spikes. The choice of RC for the
snubber is usually done experimentally. The value of the
snubber capacitor is usually chosen between 10 to 100
times the MOSFET COSS. The value of the snubber resistor
is typically between 3Ω to 100Ω. In many cases, a simple
short-circuit test can be performed to determine the
component values needed.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 5 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4214s are used by the other
cards, they respond by limiting the inrush current to a
value of 70mV/RS. If CT is sized correctly, the capacitors
will recharge long before CT times out.
POWER GOOD, PWRGD
PWRGD latches low if GATE charges up to within 2.8V of
VIN and DRAIN pulls below VDRNL during start-up. PWRGD
is reset in UVLO, in a UV condition or if CT charges up to
3V. An overvoltage condition has no effect on PWRGD
status. A 50µA current pulls this pin high during reset.
Various ways of using the PWRGD pin for interfacing with
a Power Module load are shown in the Typical Application
as well as Figures 2, 3, 18 and 19.
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate
SOA for a given application can always handle the required
current, but the opposite may not be true. Consult the
manufacturer’s MOSFET data sheet for safe operating area
and effective transient thermal impedance curves.
MOSFET selection is a 3-step process by assuming the
absense of a soft-start capacitor. First, RS is calculated and
then the time required to charge the load capacitance is
determined. This timing, along with the maximum shortcircuit current and maximum input voltage defines an
operating point that is checked against the MOSFET’s SOA
curve.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker
current trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at VSUPPLY(MIN).
RS is given by:
RS =
VCB(MIN)
IL(MAX)
(8)
where VCB(MIN) = 44mV represents the guaranteed minimum circuit breaker threshold.
During the initial charging process, the LTC4214 may
operate the MOSFET in current limit, forcing (VACL) between 60mV to 80mV across RS. The minimum inrush
current is given by:
IINRUSH(MIN)=
60mV
RS
(9)
Maximum short-circuit current limit is calculated using
the maximum VSENSE. This gives
I SHORTCIRCUIT(MAX)=
80mV
RS
(10)
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
421412f
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LTC4214-1/LTC4214-2
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for CT is calculated based on the maximum time it takes the
load capacitor to charge. That time is given by:
tCL(CHARGE) =
C • V C L• V SUPPLY(MAX)
=
I
IINRUSH(MIN)
(11)
The maximum current flowing in the DRAIN pin is given
by:
IDRN(MAX) =
V SUPPLY(MAX)− V DRNCL
RD
(12)
Approximating a linear charging rate as IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3) can
be approximated with 0.5 • IDRN(MAX). Rearranging equation, TIMER capacitor CT is given by:
CT =
(
tCL(CHARGE) • 40µA + 4 • IDRN(MAX)
3V
)
(13)
Returning to Equation (3), the TIMER period is calculated
and used in conjunction with V SUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET.
As a numerical design example, consider a 10W load,
which requires 1.1A input current at – 10.8V. If
VSUPPLY(MAX) = 13.2V and CL = 100µF, RD = 475k, Equation (8) gives RS = 40mΩ; Equation (13) gives CT = 34nF.
To account for errors in RS, CT, TIMER current (40µA),
TIMER threshold (3V), RD, DRAIN current multiplier and
DRAIN voltage clamp (VDRNCL), the calculated value should
be multiplied by 1.5, giving the nearest standard value of
CT = 56nF.
If a short-circuit occurs, a current of up to 80mV/
40mΩ␣ =␣ 2A will flow in the MOSFET for 0.9ms as dictated
by CT␣ =␣ 56nF in Equation (3). The MOSFET must be
selected based on this criterion. The IRF7413 can handle
20V and 2A for 9ms and is safe to use in this application.
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
56mV
(14)
RS
From the SOA curves of a prospective MOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
I CB(MAX)=
tSOA(MAX)
(15)
1.61 • RSS
In the above example, 56mV/40mΩ gives 1.4A. tSOA(MAX)
for the IRF7413 is 8ms for 1.4A at 30V. From Equation
(15), CSS = 68nF. Actual board evaluation showed that
CSS = 33nF was appropriate. The ratio (RSS • CSS) to
tCL(CHARGE) is a good gauge as a large ratio may result in
the time-out period expiring. This gauge is determined
empirically with board level evaluation.
CSS =
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2. It was designed for 12W for a –10V to
–14V supply.
Calculate the maximum load current: 12W/10V = 1.2A;
allowing for 75% converter efficiency, IIN(MAX) = 1.6A.
Calculate RS: from Equation (8) RS = 25mΩ.
Calculate I SHORTCIRCUIT(MAX) : from Equation (10)
ISHORTCIRCUIT(MAX) = 3.2A.
Select a MOSFET that can handle 3.2A at 14V: IRF7413.
Calculate CT: from Equation (13) CT = 24nF. Select
CT␣ =␣ 47nF, which gives the circuit breaker time-out period
tMAX␣ = 0.7ms.
Consult MOSFET SOA curves: the IRF7413 can handle
3.2A at 20V for 3.5ms, so it is safe to use in this
application.
Calculate CSS: using Equations (14) and (15) select
CSS␣ =␣ 22nF.
FREQUENCY COMPENSATION
The LTC4214 typical frequency compensation network for
the analog current limit loop is a series RC (10Ω) and CC
connected to VEE. Figure 6 depicts the relationship be421412f
18
LTC4214-1/LTC4214-2
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COMPENSATION CAPACITANCE, CC (nF)
25
CURRENT FLOW
FROM LOAD
Si4864DY •
CURRENT FLOW
TO –12V BACKPLANE
20
SENSE RESISTOR
•
Si4876DY
15
IRF7413
•
10
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
Si4410DY
•
4214 F07
• Si4412ADY
•
5
IRF7803
TO
SENSE
0
0
1000 2000 3000 4000 5000 6000 7000
MOSFET, CISS (pF)
4214 F06
Figure 6. Recommended Compensation
Capacitor CC vs MOSFET CISS
tween the compensation capacitor CC and the MOSFET’s
CISS. The line in Figure 6 is used to select a starting value
for CC based upon the MOSFET’s CISS specification. Optimized values for CC are shown for several popular
MOSFETs. Differences in the optimized value of CC versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
As seen in Figure 5 previously, at the onset of a shortcircuit event, the input supply voltage can ring dramatically owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4214’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4214 and the sense resistor.
PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TO
VEE
Figure 7. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
VIN, VOUT, DRAIN and PWRGD. At time point 2, VIN
exceeds VLKO and the internal logic checks for UV > VUVHI,
OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5µA current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the
conditions of GATE < V GATEL , SENSE < V CB and
SS␣ <␣ 20␣ •␣ VOS must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by RSS • CSS (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • VOS. Upon releasing
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) (Equation 7) and soft-start limits the slew rate of
421412f
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LTC4214-1/LTC4214-2
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VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2
3 4 56
7
8 9 10 11
GND – (–12V)
UV/OV
VIN
VLKO
VTMRH
40µA + 8 • IDRN
5µA
TIMER
5µA
VTMRL
50µA
GATE
5µA
VIN – VGATEH
50µA
VGATEL
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
SS
VACL
SENSE
VCB
VOUT
VDRNCL
DRAIN
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F08
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, the circuit
breaker TIMER activates. The TIMER capacitor, CT, is
charged by a (40µA + 8 • IDRN) current pull-up. As the load
capacitor nears full charge, load current begins to decline.
At time point 8, the load current falls and the SENSE
voltage drops below VACL(t). The analog current limit loop
shuts off and the GATE pin ramps further. At time point 9,
the SENSE voltage drops below VCB, the fault TIMER cycle
ends, followed by a 5µA discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
GATE ramp-up. When GATE ramps past the VGATEH threshold at time point 10, PWRGD pulls low. At time point␣ 11,
GATE reaches its maximum voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 9, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4214 is
activated. At time point 1, the power pins make contact and
VIN ramps through VLKO. At time point 2, the UV/OV divider
421412f
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LTC4214-1/LTC4214-2
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UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2
3 4 56
7
8 9 1011
GND – (–12V)
UV/OV
VIN
VUVHI
VLKO
VTMRH
5µA
TIMER
40µA + 8 • IDRN
5µA
VTMRL
50µA
GATE
VIN – VGATEH
50µA
VGATEL
SS
5µA
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
VACL
VCB
SENSE
VOUT
VDRNCL
DRAIN
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
makes contact and its voltage exceeds VUVHI. In addition,
the internal logic checks for OV < VOVHI, GATE < VGATEL,
SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all
conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5µA current source pullup. At time point 3, TIMER reaches the VTMRH threshold
and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the V TMRL
threshold is reached and the conditions of GATE < VGATEL,
SENSE < VCB and SS < 20 • VOS must be satisfied before
a GATE start-up cycle begins. SS ramps up as dictated by
RSS␣ •␣ CSS; GATE is held low by the analog current limit
amplifier until SS crosses 20 • VOS. Upon releasing GATE,
50µA sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) and soft-start limits the slew rate of the load
current. If the SENSE voltage (VSENSE – VEE) reaches the
VCB threshold at time point 7, the circuit breaker TIMER
activates. The TIMER capacitor, CT, is charged by a
421412f
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LTC4214-1/LTC4214-2
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(40µA + 8 • IDRN) current pull-up. As the load capacitor
nears full charge, load current begins to decline. At point
8, the load current falls and the SENSE voltage drops below
VACL(t). The analog current limit loop shuts off and the
GATE pin ramps further. At time point 9, the SENSE voltage
drops below VCB and the fault TIMER cycle ends, followed
by a 5µA discharge cycle (cool off). When GATE ramps
past VGATEH threshold at time point 10, PWRGD pulls low.
At time point 11, GATE reaches its maximum voltage as
determined by VIN.
Undervoltage Timing
In Figure 10 when the UV pin drops below VUVHI – VUVHST
(time point␣ 1), the LTC4214 shuts down with TIMER, SS
and GATE all pulling low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
When UV recovers and clears VUVHI (time point 2), an
initial timer cycle begins followed by a start-up cycle.
UV DROPS BELOW VUVHI – VUVHST. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
UV
2
VUVHI –
VUVHST
3 4 56
8 9 10 11
VUVHI
VTMRH
5µA
TIMER
7
40µA + 8 • IDRN
5µA
VTMRL
5µA
50µA
GATE
SS
VIN – VGATEH
50µA
VGATEL
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
VACL
SENSE
VCB
VDRNCL
DRAIN
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F10
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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VIN Undervoltage Lockout Timing
Undervoltage Timing with Overvoltage Glitch
The VIN undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
In Figure 11, both UV and OV pins are connected together.
When UV clears VUVHI (time point 1), an initial timing
cycle starts. If the system bus voltage overshoots VOVHI
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the VOVHI
– VOVHST threshold. The initial timing cycle restarts,
followed by a GATE start-up cycle.
UV/OV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE
UV/OV DROPS BELOW VOVHI – VOVHST AND TIMER RESTARTS INITIAL TIMING CYCLE
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
2
VOVHI
UV/OV
3
4 5 67
8
10 12
9 11
VOVHI – VOVHST
VUVHI
VTMRH
40µA + 8 • IDRN
5µA
TIMER
50µA
GATE
50µA
VGATEL
SS
5µA
VTMRL
5µA
VIN – VGATEH
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
VACL
VCB
SENSE
VDRNCL
DRAIN
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F11
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shown at time point 1 of Figure 12, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull
down and the load is disconnected. At time point 2, OV
recovers and drops below the VOVHI – VOVHST threshold. A
GATE start-up cycle begins. If the overvoltage glitch is
long enough to deplete the load capacitor, a full start-up
cycle as shown between time points 4 through 7 may
occur.
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
OV DROPS BELOW VOVHI – VOVHST, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
1
OV
2 34
VOVHI
5
67 8 9
VOVHI – VOVHST
VTMRH
50µA
GATE
5µA
40µA + 8 • IDRN
TIMER
VGATEL
5µA
VIN – VGATEH
50µA
20 • (VACL + VOS)
SS
20 • (VCB + VOS)
20 • VOS
VACL
VCB
SENSE
GATE
START-UP
4214 F12
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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Circuit Breaker Timing
In Figure 13a, the TIMER capacitor charges at 40µA if the
SENSE pin exceeds VCB but VDRN is less than 4.2V. If the
SENSE pin drops below VCB before TIMER reaches the
VTMRH threshold, TIMER is discharged by 5µA. In Figure
13b, when TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4214 shuts down. In Figure 13c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach VTMRH. GATE pull down follows and
the LTC4214 shuts down. During shutdown, the LTC4214-1
latches TIMER high with a 5µA pull-up current source; the
LTC4214-2 activates a shutdown cooling cycle.
CB TIMES OUT
1
2
1
VTMRH
2
1
VTMRH
5µA
TIMER
CB TIMES OUT
VTMRH
TIMER
40µA + 8 • IDRN
40µA + 8 • IDRN
GATE
GATE
SS
SS
SS
SENSE
VACL
VCB
VCB
SENSE
VOUT
VOUT
3
4
5µA
40µA + 8 • IDRN
40µA + 8 • IDRN
TIMER
GATE
VACL
2
VACL
VCB
SENSE
VOUT
VDRNCL
VDRNCL
DRAIN
DRAIN
DRAIN
PWRGD
PWRGD
PWRGD
4214 F13
CB FAULT
CB FAULT
(13a) Momentary Circuit-Breaker Fault
(13b) Circuit-Breaker Time Out
CB FAULT
CB FAULT
(13c) Multiple Circuit-Breaker Fault
Figure 13. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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Resetting a Fault Latch (LTC4214-1)
The duration of the TIMER reset pulse should be smaller
than the time taken to reach 0.2V at SS pin. With a single
pole mechanical pushbutton switch, this may not be
feasible. A double pole, single throw pushbutton switch
removes this restriction by connecting the second switch
to the SS pin. With this method, both the SS and TIMER
pins are released at the same time.
The latched circuit breaker fault of LTC4214-1 benefits
from long cooling time. It is reset by pulling the UV pin
below VUVHI – VUVHST with a switch. Reset is also accomplished by pulling the VIN pin momentarily below (VLKO –
VLKH). A third reset method involves pulling the TIMER pin
below VTMRL as shown in Figure 14. An initial timing cycle
is skipped if TIMER is used for reset. An initial timing cycle
is generated if reset by the UV pin or the VIN pin.
SWITCH RESETS LATCHED TIMER
SWITCH RELEASES SS
5µA
1
2 34
5
67 8 9
TIMER
VTMRH
40µA + 8 • IDRN
VTMRL
GATE
50µA
50µA
VGATEL
SS
5µA
5µA
VIN – VGATEH
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
VACL
VCB
SENSE
VDRNCL
DRAIN
VDRNL
PWRGD
GATE START-UP
MOMENTARY DPST SWITCH RESET
4214 F14
Figure 14. Pushbutton Reset of LTC4214-1’s Latched Fault (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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Shutdown Cooling Cycle (LTC4214-2)
and three 5µA charge phases in this shutdown cooling
cycle spanning time points 2 and 3. At time point 3, the
LTC4214 automatic retry occurs with a start-up cycle.
Good thermal management techniques are highly recommended; power and thermal dissipation must be carefully
evaluated when implementing the automatic retry scheme.
Figure 15 shows the timer behavior of the LTC4214-2. At
time point 2, TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4214 shuts down. TIMER starts
a shutdown cooling cycle by discharging TIMER with 5µA
to the VTMRL threshold. TIMER then charges with 5µA to
the VTMRH threshold. There are four 5µA discharge phases
RETRY
CIRCUIT BREAKER TIMES OUT
1
2
40µA + 8 • IDRN
TIMER
3 45
5µA
5µA
5µA
5µA
5µA
5µA
6
78 9 10
VTMRH
40µA + 8 • IDRN
5µA
5µA
5µA
VTMRL
50µA
50µA
VGATEL
GATE
VIN – VGATEH
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
SS
VACL
VCB
SENSE
VOUT
VDRNCL
DRAIN
VDRNL
PWRGD
CB
SHUTDOWN COOLING
GATE
START-UP
4214 F15
Figure 15. Shutdown Cooling Timing Behavior of LTC4214-2 (All Waveforms are Referenced to VEE)
421412f
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LTC4214-1/LTC4214-2
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Analog Current Limit and Fast Current Limit
In Figure 16a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 16b, when a severe fault occurs, SENSE exceeds
VFCL and GATE immediately pulls down until the analog
current amplifier can establish control. If the severe fault
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 40µA. This accelerated TIMER current of
[40µA+8 • IDRN] produces a shorter circuit breaker fault
delay. Careful selection of CT, RD and MOSFET can help
prevent SOA damage in a low impedance fault condition.
CB TIMES OUT
12
34
40µA + 8 • IDRN
TIMER
VTMRH
5µA
5µA
1
VTMRH
40µA + 8 • IDRN
TIMER
GATE
GATE
SS
SS
VACL
SENSE
VCB
VOUT
SENSE
2
VFCL
VACL
VCB
VOUT
VDRNCL
DRAIN
DRAIN
PWRGD
PWRGD
4214 F16
(16a) Analog Current Limit Fault
(16b) Fast Current Limit Fault
Figure 16. Current Limit Behavior (All Waveforms are Referenced to VEE)
421412f
28
LTC4214-1/LTC4214-2
U
U
W
U
APPLICATIO S I FOR ATIO
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 1.6V in about 220µs at GATE
start-up, as shown in Figure 17a. If a soft-start capacitor,
CSS, is connected to this SS pin, the soft-start response is
modified from a linear ramp to an RC response (Equation␣ 6), as shown in Figure 17b. This feature allows load
current to slowly ramp-up at GATE start-up. Soft-start is
initiated at time point 3 by a TIMER transition from VTMRH
to VTMRL (time points 1 to 2) or by the OV pin falling below
the VOVHI – VOVHST threshold after an OV condition. When
the SS pin is below 0.2V, the analog current limit amplifier
holds GATE low. Above 0.2V, GATE is released and 50µA
ramps up the compensation network and GATE capacitance at time point 4. Meanwhile, the SS pin voltage
continues to ramp up. When GATE reaches the MOSFET’s
threshold, the MOSFET begins to conduct. Due to the
MOSFET’s high gm, the MOSFET current quickly reaches
the soft-start control value of VACL(t) (Equation 7). At time
point 6, the GATE voltage is controlled by the current limit
amplifier. The soft-start control voltage reaches the circuit
breaker voltage, VCB, at time point 7 and the circuit breaker
TIMER activates. As the load capacitor nears full charge,
load current begins to decline below VACL(t). The current
limit loop shuts off and GATE releases at time point 8. At
time point␣ 9, the SENSE voltage falls below VCB and
TIMER deactivates.
Large values of CSS can cause premature circuit breaker
time out as VACL(t) may exceed the VCB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large CSS values is SOA duration may
be exceeded during soft-start into a low impedance load.
A soft-start voltage below VCB will not activate the circuit
breaker TIMER.
END OF INTIAL TIMING CYCLE
12 34 567
VTMRH
TIMER
7a
END OF INTIAL TIMING CYCLE
8 9
10
11
5µA
40µA + 8 • IDRN
VTMRL
50µA
GATE
VIN – VGATEH
12 3 4 5 6
VTMRH
TIMER
5µA
40µA + 8 • IDRN
VIN – VGATEH
50µA
20 • (VACL + VOS)
20 • (VCB + VOS)
SS
20 • VOS
20 • VOS
VACL
VCB
VACL
SENSE
VDRNCL
DRAIN
11
50µA
50µA
20 • (VACL + VOS)
SENSE
10
VTMRL
VGS(th)
20 • (VCB + VOS)
8 9
GATE
VGS(th)
SS
7
VDRNL
PWRGD
VCB
VDRNCL
DRAIN
VDRNL
PWRGD
4214 F17
(17a) Without External CSS
(17b) With External CSS
Figure 17. Soft-Start Timing (All Waveforms are Referenced to VEE)
421412f
29
LTC4214-1/LTC4214-2
U
W
U
U
APPLICATIO S I FOR ATIO
Power Limit Circuit Breaker
when
Figure 18 shows the LTC4214-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, VSUPPLY. The zener voltage, VZ is set
to be the same as the low supply operating voltage,
VSUPPLY(MIN) = 10V. If the goal is to have the high supply
operating voltage, VSUPPLY(MAX) = 14V give the same
power at VSUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
R6
VCB
=
R4 VSUPPLY(MAX)
VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 12V.
The peak power at the fault current limit occurs at the
supply overvoltage threshold. The fault current limited
power is:
POWERFAULT =
VSUPPLY 
R6 
•  VACL – (VSUPPLY – VZ ) • 

RS
R4 
(18)
(16)
If R6 is 20Ω, R4 is 5.6k. The peak circuit breaker power
limit is:
POWERMAX
2
VSUPPLY(MIN) + VSUPPLY(MAX) )
(
=
4 • VSUPPLY(MIN) • VSUPPLY(MAX)
• POWERSUPPLY(MIN)
(17)
= 1.029 • POWERSUPPLY(MIN)
VLOGIC
RPULLUP
EN
GND
GND
RX
10Ω
CX
100nF
GND
(SHORT PIN)
D2
1N4148
R4
5.6k
RIN
470Ω
Z1
Q2
2N2222
CIN
0.1µF
1
9
R2
3.65k
1%
10
LTC4214-1
8
CT
47nF
R3
32.4k
1%
C1
1nF
3
UV
PWRGD
OV
DRAIN
TIMER
GATE
SS
SENSE
VEE
CSS
22nF
5
CL
100µF
D1
BZX84C10
VIN
R1
124k
1%
+
2
R5
10k
7
6
4
R6 20Ω
RC
10Ω
CC
10nF
VOUT
RD
475k
Q1
IRF7413
RS
0.025Ω
4214 F18
–12V
Z1: SMAJ15A
Figure 18. Power Limit Circuit Breaking Application
421412f
30
LTC4214-1/LTC4214-2
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
421412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC4214-1/LTC4214-2
U
TYPICAL APPLICATIO
GND
GND
RX
10Ω
CX
100nF
GND
(SHORT PIN)
RIN
470Ω
Z1
EN
GATE
5V/DIV
*
VIN
LTC4214-1
8
9
R2
32.4k
1%
OV
PWRGD
UV
DRAIN
2
7
10
6
TIMER
GATE
3
4
CT
SS
SENSE
47nF
VEE
C1
1nF
CSS
22nF
Start-Up Behavior
CL
100µF
CIN
0.1µF
1
R1
121k
1%
+
R3
5.1k
5
CONTROLLER VEE
RD
475k
VOUT
SENSE
50mV/DIV
Q1
IRF7413
RC
10Ω
CC
10nF
–12V
VOUT
10V/DIV
RS
0.025Ω
PWRGD
10V/DIV
4214 F19
*M0C207
Z1:SMAJ15A
4214 TA03
Figure 19. – 12V/2A Hot Swap Controller
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Two Channels, Hot Swap Controller
Operates from 3V to 12V and Supports –12V
LTC1642
Fault Protected Hot Swap Controller
3V to 16.5V, Overvoltage Protection up to 33V
LTC1644
PCI Hot Swap Controller
3.3V, 5V and ±12V; 1V Precharge; PCI Reset Logic
LTC4210
Hot Swap Controller in SOT-23
Active Current Limiting, 2.7V to 16.5V
LTC4211
Single Hot Swap with Multifunction Current Control
Operates from 2.5V to 16.5V
LT4220
Dual Hot Swap Controller for Positive/Negative Supplies
Operates from ±2.7V to ±16.5V
LTC4230
Triple Hot Swap Controller with Multifunction Current Control
Operates from 1.7V to 16.5V
421412f
32
Linear Technology Corporation
LT/TP 0204 1K PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002