Cypress CY25100SXCF Field- and factory-programmable spread spectrum clock generator for emi reduction Datasheet

CY25100
Field- and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
Benefits
• Wide operating output (SSCLK) frequency range
— 3–200 MHz
• Programmable spread spectrum with nominal 31.5-kHz
modulation frequency
— Center spread: ±0.25% to ±2.5%
— Down spread: –0.5% to –5.0%
• Input frequency range
— External crystal: 8–30 MHz fundamental crystals
— External reference: 8–166 MHz Clock
• Integrated phase-locked loop (PLL)
• Field-programmable
— CY25100SCF and CY25100SIF, 8-pin SOIC
— CY25100ZCF and CY25100ZIF, 8-pin TSSOP
• Programmable crystal load capacitor tuning array
• Low cycle-to-cycle jitter
• 3.3V operation
• Services most PC peripherals, networking, and consumer
applications.
• Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC)
requirements. Reduces development and manufacturing
costs and time-to-market.
• Eliminates the need for expensive and difficult to use
higher-order crystals.
• Internal PLL to generate up to 200-MHz output. Able to
generate custom frequencies from an external crystal or a
driven source.
• In-house programming of samples and prototype quantities
is available using the CY3672 programming kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s
value-added distribution partners or by using third-party
programmers from BP Microsystems, HiLo Systems, and
others.
• Enables fine-tuning of output clock frequency by adjusting
CLoad of the crystal. Eliminates the need for external CLoad
capacitors.
• Commercial and Industrial operation
• Spread Spectrum On/Off function
• Suitable for most PC, consumer, and networking applications
• Power-down or Output Enable function
• Application compatibility in standard and low-power
systems
• Provides ability to enable or disable spread spectrum with
an external pin.
• Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
Pin Configuration
CY25100
8-pin SOIC/TSSOP
RFB
PLL
with
MODULATION
CONTROL
3
XIN
1 VDD
SSON# 8
2
XOUT
SSCLK 7
3 XIN/CLKIN
REFCLK 6
C XIN
PROGRAMMABLE
CONFIGURATION
2
XOUT
C XOUT
6
OUTPUT
DIVIDERS
and
MUX
REFCLK
7
4
SSCLK
4 PD#/OE
VSS 5
PD# or OE
8
SSON#
1
5
VDD
VSS
Cypress Semiconductor Corporation
Document #: 38-07499 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised March 24, 2004
CY25100
Pin Description
Pin
Name
Description
1
VDD
3.3V power supply.
2
XOUT
Crystal output. Leave this pin floating if external clock is used.
3
XIN/CLKIN
Crystal input or reference clock input.
4
PD#/OE
Power-down pin: Active LOW. If PD# = 0, the PLL and Xtal are powered down,
and outputs are weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
User has the option of choosing either PD# or OE function.
5
VSS
Power supply ground.
6
REFCLK
Buffered reference output.
7
SSCLK
Spread spectrum clock output.
8
SSON#
Spread spectrum control. 0 = Spread on. 1 = Spread off.
General Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing EMI found in today’s
high-speed digital electronic systems.
The spread% is programmed to either center spread or down
spread with various spread percentages. The range for center
spread is from ±0.25% to ±2.50%. The range for down spread
is from –0.5% to –5.0%. Contact the factory for smaller or
larger spread % amounts if required.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The input to the CY25100 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25100 uses a factory/field-programmable configuration memory array to synthesize output frequency, spread%,
crystal load capacitor, reference clock output on/off, spread
spectrum on/off function and PD#/OE options.
The CY25100 products are available in an 8-pin SOIC and
TSSOP packages with commercial and industrial operating
temperature ranges.
The CY25100 has two clock outputs, REFCLK and SSCLK.
The non-spread spectrum REFCLK output has the same
frequency as the input of the CY25100. The frequency
modulated SSCLK output can be programmed from 3–200
MHz.
Table 1.
Total Xtal
Load
Capacitance
Output
Frequency
Spread Percent
(0.5% – 5%,
0.25% Intervals)
Reference
Output
Power-down or
Output Enable
Frequency
Modulation
XIN and
XOUT
XIN and XOUT
SSCLK
SSCLK
REFOUT
PD#/OE
SSCLK
3 and 2
3 and 2
7
7
6
4
7
MHz
pF
MHz
%
On or Off
Select PD# or OE
kHz
ENTER
DATA
ENTER DATA
ENTER
DATA
ENTER DATA
31.5
Pin
Function
Input
Frequency
Pin Name
Pin#
Unit
Program
Value
ENTER DATA ENTER DATA
Document #: 38-07499 Rev. *D
Page 2 of 11
CY25100
Programming Description
Product Functions
Field-Programmable CY25100
Input Frequency (XIN, pin 3 and XOUT, pin 2)
The CY25100 is programmed at the package level, i.e., in a
programmer socket. The CY25100 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock
signals is 8 to 166 MHz.
Samples and small prototype quantities can be programmed
on the CY3672 programmer with CY3690 (TSSOP) or
CY3691 (SOIC) socket adapter.
The load capacitors at Pin 1 (CXIN) and Pin 8 (CXOUT) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
CyberClocks Online Software
CyberClocks Online Software is a web-based software application that allows the user to custom-configure the CY25100.
All the parameters in Table 1 given as “Enter Data” can be
programmed into the CY25100. CyberClocks Online outputs
an industry-standard JEDEC file used for programming the
CY25100. CyberClocksOnline is available at www.cyberclocksonline.com website through user registration. To register,
fillout the registration form and make sure to check the
“non-standard devices” box. For more information on the
registration process refer to CY3672 datasheet
For information regarding Spread Spectrum software
programming solutions, please contact your local Cypress
Sales or Field Application Engineer (FAE), representative for
details.
CY3672 FTG Programming Kit and CY3690/CY3691 Socket
Adapter
The Cypress CY3672 FTG programmer and CY3690/CY3691
Socket Adapter are needed to program the CY25100. The
CY3690 enables user to program CY25100ZCF and
CY25100ZIF (TSSOP) and CY3691 gives the user the ability
to program CY25100SCF and CY25100SIF (SOIC). Each
socket adapter comes with small prototype quantities of
CY25100. The CY3690/CY3691 is a separate orderable item,
so the existing users of the CY3672 FTG development kit or
CY3672-PRG programmer need to order only the socket
adapters to program the CY25100.
Factory-Programmable CY25100
Factory programming is available for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. A
sample request form (refer to “CY25100 Sample Request
Form” at www.cypress.com) must be completed. Once the
request has been processed, you will receive a new part
number, samples, and data sheet with the programmed
values. This part number will be used for additional sample
requests and production orders.
Additional information on the CY25100 can be obtained from
the Cypress web site at www.cypress.com.
Document #: 38-07499 Rev. *D
CXIN and CXOUT (pin 3 and pin 2)
The required values of CXIN and CXOUT can be calculated
using the following formula:
CXIN = CXOUT = 2CL – CP
where CL is the crystal load capacitor as specified by the
crystal manufacturer and CP is the parasitic PCB capacitance.
For example, if a fundamental 16-MHz crystal with CL of 16-pF
is used and CP is 2 pF, CXIN and CXOUT can be calculated as:
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
If using a driven reference, set CXIN and CXOUT to the
minimum value 12 pF.
Output Frequency, SSCLK Output (SSCLK, pin 7)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is
the nominal value of the synthesized frequency without
modulation (spread % = 0). The range of synthesized clock is
from 3–200 MHz.
Spread Percentage (SSCLK, pin 7)
The SSCLK spread can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
Reference Output (REFOUT, pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be
programmed to be enabled (clock on) or disabled (High-Z,
clock off). If this output is not needed, it is recommended that
users request the disabled (High-Z, Clock Off) option.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher-modulation frequency is required.
Power-down or Output Enable (PD# or OE, pin 4):
The part can be programmed to include either PD# or OE
function. PD# function powers down the oscillator and PLL.
The OE function disables the outputs.
Page 3 of 11
CY25100
Absolute Maximum Rating
Junction Temperature ................................ –40°C to +125°C
Supply Voltage (VDD) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to VDD + 0.5
Storage Temperature (Non-condensing)..... –55°C to +125°C
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter
Description
Comments
Min. Typ. Max. Unit
FNOM
Nominal Crystal Frequency
CLNOM
Nominal Load Capacitance
Internal load caps
6
R1
Equivalent Series Resistance (ESR)
Fundamental mode
–
R3/R1
Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much
Fundamental Mode ESR
less than the maximum spec
3
DL
Crystal Drive Level
–
Parallel resonance, fundamental mode, AT cut
8
No external series resistor assumed
–
30
MHz
–
30
pF
–
25
Ω
–
–
–
0.5
2
mW
Operating Conditions
Parameter
Description
VDD
Supply Voltage
TA
Ambient Commercial Temperature
Ambient Industrial Temperature
Min.
Typ.
Max.
Unit
3.13
3.30
3.45
V
0
–
70
°C
–40
–
85
°C
CLOAD
Max. Load Capacitance @ pin 6 and pin 7
–
–
15
pF
Fref
External Reference Crystal
(Fundamental tuned crystals only)
8
–
30
MHz
External Reference Clock
8
–
166
MHz
FSSCLK
SSCLK output frequency, CLOAD = 15 pF
3
–
200
MHz
FREFCLK
REFCLK output frequency, CLOAD = 15 pF
8
–
166
MHz
FMOD
Spread Spectrum Modulation Frequency
30.0
31.5
33.0
kHz
TPU
Power-up time for all VDDs to reach minimum specified voltage (power ramp must be monotonic)
0.05
–
500
ms
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V (source)
10
12
mA
IOL
Output Low Current
VOL = 0.5, VDD= 3.3V (sink)
10
12
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7VDD
–
VDD
V
VIL
Input Low Voltage
CMOS levels, 30% of VDD
–
–
0.3VDD
V
IIH
Input High Current, PD#/OE and
SSON# pins
Vin = VDD
–
–
10
µA
IIL
Input Low Current, PD#/OE and
SSON# pins
Vin = VSS
–
–
10
µA
Three-state output, PD#/OE = 0
10
µA
–
12
–
pF
–
60
–
pF
–
5
7
pF
VDD = 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
CLOAD = 15 pF, PD#/OE = SSON# = VDD
–
25
35
mA
VDD = 3.45V, Device powered down with
PD# = 0V (driven reference pulled down)
–
15
30
µA
IOZ
Output Leakage Current
CXIN or CXOUT[1]
Programmable Capacitance at pin Capacitance at minimum setting
2 and pin 3
Capacitance at maximum setting
CIN[1]
Input Capacitance at pin 4 and pin Input pins excluding XIN and XOUT
8
IVDD
Supply Current
IDDS
Standby current
–10
Notes:
1. Guaranteed by characterization, not 100% tested.
Document #: 38-07499 Rev. *D
Page 4 of 11
CY25100
AC Electrical Characteristics[1]
Parameter
Min.
Typ.
Max.
Unit
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
Output Duty Cycle
REFCLK, Measured at VDD/2
Duty Cycle of CLKIN = 50% at input bias
40
50
60
%
SR1
Rising Edge Slew Rate
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
MHz. 20%–80% of VDD
0.7
1.1
3.6
V/ns
SR2
Falling Edge Slew Rate
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
MHz. 80%–20% of VDD
0.7
1.1
3.6
V/ns
SR3
Rising Edge Slew Rate
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 20%–80% of VDD
1.2
1.6
4.0
V/ns
SR4
Falling Edge Slew Rate
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 80%–20% of VDD
1.2
1.6
4.0
V/ns
TCCJ1[2]
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK off
–
90
120
ps
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK off
–
100
130
ps
DC
TCCJ2[2]
TCCJ3
[2]
Description
Condition
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Cycle-to-Cycle Jitter
REFCLK (Pin 6)
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK off
–
130
170
ps
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
–
100
130
ps
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK on
–
105
140
ps
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
–
200
260
ps
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
–
80
100
ps
CLKIN = SSCLK = 66 MHz, 2% spread REFCLK on
–
100
130
ps
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
–
135
180
ps
tSTP
Power-down Time
(pin 4 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
–
150
350
ns
TOE1
Output Disable Time
(pin 4 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
–
150
350
ns
TOE2
Output Enable Time
(pin 4 = OE)
Time from rising edge on OE to outputs at a valid frequency (Asynchronous)
–
150
350
ns
tPU1
Power-up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid frequency (Asynchronous)
–
3.5
5
ms
tPU2
Power-up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid frequency (Asynchronous), reference clock at correct
frequency
–
2
3
ms
Application Circuit[3, 4, 5]
Pow er
1
VDD
2
XOUT
SSON#
8
0 .1 u F
SSCLK
7
CY25100
VDD
3
X IN /C L K IN
4
P D # /O E
REFCLK
6
VSS
5
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temperature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at
http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer.
3. Since the load capacitors (CXIN and CXOUT) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
capacitor (CL). Only a single 0.1-µF bypass capacitor is required on the VDD pin.
4. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected).
5. If SSON# (pin 8) is LOW (VSS), the frequency modulation will be on at SSCLK pin (pin 7).
Document #: 38-07499 Rev. *D
Page 5 of 11
CY25100
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
t1A
OUTPUT
t1B
Output Rise/Fall Time (SSCLK and REFCLK)
VDD
OUTPUT
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
POWERDOWN
VDD
0V
VIH
VIL
tPU
High Impedance
CLKOUT
(Asynchronous)
tSTP
Output Enable/Disable Timing
OUTPUT
ENABLE
VDD
0V
VIH
VIL
TOE2
High Impedance
CLKOUT
(Asynchronous)
TOE1
Document #: 38-07499 Rev. *D
Page 6 of 11
CY25100
Informational Graphs [6]
172.5
161.5
169.5
169
168.5
168
167.5
167
166.5
166
165.5
165
164.5
164
163.5
163
160.5
162.5
171.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
170.5
169.5
168.5
167.5
166.5
Fnominal
165.5
164.5
163.5
162.5
159.5
0
20
68.5
40
60
80
100
120
Time (us)
140
160
180
Fnominal
0
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
68
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
20
67.5
40
60
80
100 120
Time (us)
140
160
180
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
67.5
67
66.5
66.5
Fnominal
66
Fnominal
66
65.5
65.5
65
64.5
65
64
64.5
63.5
0
20
40
60
80
100
120
Time (us)
140
160
180
200
0
40
60
80
100 120
Time (us)
140
160
180
200
IDD vs. SSCLK
Duty Cycle vs. REFCLK
Te m pe r atu r e =25C, V DD=3.3V , CLOAD=15p F, SS off,
( C L OA D =1 5 p F )
Re fclk = 30M Hz
60
58
56
54
52
50
48
46
44
42
40
30
25
IDD (m A)
Duty Cycle (%)
20
20
15
10
5
0
50
100
REFCLK (MHz)
150
200
0
0
50
100
150
200
SSCLK (M Hz )
Note:
6. The “Informational Graphs” are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on
pages 4 and 5 for device specifications.
Document #: 38-07499 Rev. *D
Page 7 of 11
CY25100
Informational Graphs (continued)[6]
Measured Spread% vs. VDD over Tem perature
(Target Spread = 0.5%, Fout=100MHz, CLOA D =15pF)
Measured Spread% vs. VDD over
Tem perature
(Target Spread = 5.0%, Fout=100MHz, CLOA D =15pF)
0.55%
-40C
0.50%
25C
0.45%
85C
6.00%
Spread%
Spread%
0.60%
5.50%
-40C
5.00%
25C
4.50%
85C
4.00%
0.40%
2.7
3
3.3
3.6
2.7
3.9
3
0
-2
-40C
-4
25C
-6
85C
-8
-10
3.3
3.9
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, CLOAD=15pF)
3.6
Attenuation (dB)
Attenuation (dB)
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOA D =15pF)
3
3.6
VDD (V)
VDD (V)
2.7
3.3
-10
-12
-14
-16
-18
-20
-40C
25C
85C
2.7
3.9
3
3.3
3.6
3.9
VDD (V)
VDD (V)
SSCLK EMI Attenuation vs. Spread%
(Measured at 7th Harmonic Temp=25C, VDD=3.3V,
SSCLK=100MHz, Measured on Cypress
Characterization board w ith CLOAD=15pF)
Max Cycle-Cycle Jitter on SSCLK vs.
Tem perature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/2%spread, REFCLK off)
200
-4
175
-6
150
Jitter (ps)
Attenuation (dB)
0
-2
-8
-10
-12
-14
125
100
75
50
25
-16
0.0%
0.5%
1.0%
1.5%
2.0%
2.5%
3.0%
Spread %
Document #: 38-07499 Rev. *D
3.5%
4.0%
4.5%
5.0%
0
-40
- 20
0
20
40
60
80
100
Tem perature (deg C)
Page 8 of 11
CY25100
Ordering Information
Part Number[7]
Package description
Product Flow
CY25100SCF
8-pin Small Outline Integrated Circuit(SOIC)
Commercial, 0 to 70°C
CY25100SXCF
8-pin Small Outline Integrated Circuit (SOIC) - Lead Free
Commercial, 0 to 70°C
CY25100SIF
8-pin Small Outline Integrated Circuit (SOIC)
Industrial, –40 to 85°C
CY25100SXIF
8-pin Small Outline Integrated Circuit (SOIC) - Lead Free
Industrial, –40 to 85°C
CY25100ZCF
8-pin Thin Shrunk Small Outline Package (TSSOP)
Commercial, 0 to 70°C
CY25100ZXCF
8-pin Thin Shrunk Small Outline Package (TSSOP) - Lead Free
Commercial, 0 to 70°C
CY25100ZIF
8-pin Thin Shrunk Small Outline Package (TSSOP)
Industrial, –40 to 85°C
CY25100ZXIF
8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free
Industrial, –40 to 85°C
CY25100SXC-XXXW
8-pin Small Outline Integrated Circuit (SOIC)- Lead Free
Commercial, 0 to 70°C
CY25100SXC-XXXWT 8-pin Small Outline Integrated Circuit (SOIC) – Tape and Reel- Lead Free
CY25100SXI-XXXW
8-pin Small Outline Integrated Circuit (SOIC)- Lead Free
Commercial, 0 to 70°C
Industrial, –40 to 85°C
CY25100SXI-XXXWT 8-pin Small Outline Integrated Circuit (SOIC)–Tape and Reel- Lead Free
Industrial, –40 to 85°C
CY25100ZXC-XXXW
Commercial, 0 to 70°C
8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free
CY25100ZXC-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Commercial, 0 to 70°C
CY25100ZXI-XXXW
8-pin Thin Shrunk Small Outline Package (TSSOP)- Lead Free
Industrial, –40 to 85°C
CY25100ZXI-XXXWT 8-pin Thin Shrunk Small Outline Package (TSSOP)–Tape and Reel- Lead Free Industrial, –40 to 85°C
CY3672
FTG Development Kit
n/a
CY3672-PRG
FTG programmer
n/a
CY3690
CY25100ZCF Socket adapter (TSSOP)
n/a
CY3691
CY25100SCF Socket adapter (SOIC)
n/a
Package Diagrams
8 Lead (150 Mil) SOIC
- S08 (150-Mil) SOIC S8
8-lead
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
0.0075[0.190]
0.0098[0.249]
51-85066-*C
Note:
7. “XXX” denotes the assigned product dash number. “W” denotes the different programmed frequency and/or spread % options.
Document #: 38-07499 Rev. *D
Page 9 of 11
CY25100
Package Diagrams (continued)
8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
2.90[0.114]
3.10[0.122]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85093-*A
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07499 Rev. *D
Page 10 of 11
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25100
Document History Page
Document Title: CY25100 Field-and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07499
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
126578
06/27/03
CKN
*A
128753
08/29/03
IJATMP
*B
130342
12/02/03
RGL
Changes to Application Circuit diagram and correction to the package description listed under the Ordering Information table for CY3690 and CY3691.
*C
204121
See ECN
RGL
Add Industrial Temperature Range
Corrected the Ordering Information to match the DevMaster
*D
215392
See ECN
RGL
Added Lead Free devices
Document #: 38-07499 Rev. *D
New Data Sheet
Changes to reflect field programmability
Page 11 of 11
Similar pages