Cypress CY7C1328F-200AC 4-mb (256k x 18) pipelined dcd sync sram Datasheet

CY7C1328F
4-Mb (256K x 18) Pipelined DCD Sync SRAM
Functional Description[1]
Features
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 256K × 18-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V / 2.5V I/O supply (VDDQ)
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:B], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing system performance.
The CY7C1328F operates from a +3.3V core power supply
while all outputs operate with a +3.3V or a +2.5V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Unit
Maximum Access Time
2.6
2.6
2.8
3.5
4.0
4.5
ns
Maximum Operating Current
325
290
265
240
225
205
mA
Maximum CMOS Standby Current
40
40
40
40
40
40
mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05220 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 19, 2004
CY7C1328F
Functional Block Diagram—256Kx18
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
DQB , DQPB
BYTE
WRITE DRIVER
DQB, DQPB
BYTE
WRITE REGISTER
DQA, DQPA
BYTE
WRITE DRIVER
DQA , DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs,
DQPA
DQPB
E
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document #: 38-05220 Rev. *A
Page 2 of 17
CY7C1328F
Pin Configurations
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
100-pin TQFP
Top View
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1328F
(256K x 18)
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
BYTE A
Document #: 38-05220 Rev. *A
A
A
A
A
A
A
A
NC
NC
NC
NC
VSS
VDD
MODE
A
A
A
A
A1
A0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE B
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Page 3 of 17
CY7C1328F
Pin Descriptions
Pin
TQFP
Type
Description
A0, A1, A
37,36,32,33
34,35,44,45,
46,47,48,49,
50,80,81,82,
99,100
InputAddress Inputs used to select one of the 256K address locations. Sampled at
Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] are fed to the two-bit counter.
BWA ,BWB
93,94
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous to the SRAM. Sampled on the rising edge of CLK.
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge
Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW[A:B] and BWE).
GW
88
BWE
87
CLK
89
CE1
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
CE2
97
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
CE3
92
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
OE
86
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
ADV
83
InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted, it automatically increments the address in a burst cycle.
ADSP
84
InputAddress Strobe from Processor, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
85
InputAddress Strobe from Controller, sampled on the rising edge of CLK, active
Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
64
InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
DQP[A:B]
58,59,62,63
68,69,72,73,
74,8,9,
12,13
18,19,22,23,
24
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are
placed in a three-state condition.
VDD
15,41,65,91 Power Supply Power supply inputs to the core of the device.
VSS
17,40,67,90
Ground
Ground for the core of the device.
VDDQ
4,11,20,27,
54,61,70,77
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
5,10,21,26,
55,60,71,76
I/O Ground
Ground for the I/O circuitry.
31
InputStatic
ADSC
ZZ
MODE
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous signal must be asserted LOW to conduct a byte write.
InputClock
Document #: 38-05220 Rev. *A
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
Page 4 of 17
CY7C1328F
Pin Descriptions (continued)
Pin
NC
TQFP
1,2,3,6,7,14,
16,25,28,29,
30,38,39,42,
43,51,52,53,
56,57,66,75,
78,79,95,96
Type
Description
No Connects. Not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1328F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
The CY7C1328F is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will three-state immediately
after the next clock rise.
Document #: 38-05220 Rev. *A
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW[A:B]) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW[A:B]
signals. The CY7C1328F provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1328F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BW[A:B]) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1328F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will three-state the output drivers.
As a safety precaution, DQX are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Page 5 of 17
CY7C1328F
Burst Sequences
The CY7C1328F provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Both read and write burst operations
are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A1, A0
Linear Burst Address Table
(MODE = GND)
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD − 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to snooze current
This parameter is sampled
tRZZI
ZZ inactive to exit snooze current
This parameter is sampled
Document #: 38-05220 Rev. *A
2tCYC
ns
2tCYC
0
ns
ns
Page 6 of 17
CY7C1328F
Truth Table [2, 3, 4, 5, 6]
Operation
Address
Used CE1 CE2 CE3
Deselected Cycle, Power Down
None
H
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
L
Deselected Cycle, Power Down
None
L
ZZ Mode, Power-Down
ADV
WRITE
OE
X
L
X
L
X
X
X
L-H Three-State
L
X
L
L
X
X
X
X
L-H Three-State
X
H
L
L
X
X
X
X
L-H Three-State
L
X
L
H
L
X
X
X
L-H Three-State
X
H
L
H
L
X
X
X
L-H Three-State
X
ZZ
ADSP ADSC
CLK
DQ
None
X
X
X
H
X
X
X
X
X
X
Three-State
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L-H Three-State
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L-H Three-State
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H Three-State
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H Three-State
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H Three-State
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H Three-State
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Q
Q
Q
Truth Table for Read/Write[2]
Function
GW
BWE
BWA
BWB
Read
H
H
X
X
Read
H
L
H
H
Write byte A - (DQA and DQPA)
H
L
L
H
Write byte B - (DQB and DQPB)
H
L
H
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Three-State when
OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05220 Rev. *A
Page 7 of 17
CY7C1328F
Maximum Ratings
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883,Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch -up Current..................................................... >200 mA
Storage Temperature .................................... –65°C to +150°
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient
Temperature (TA)
Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Commercial
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to VDDQ + 0.5V
Industrial
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V −5%/+10% 2.5V −5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
Input HIGH
Voltage[7]
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
V
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
0.4
V
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
Input Load Current except ZZ GND ≤ VI ≤ VDDQ
and MODE
–5
5
µA
Input Current of MODE
–30
Input LOW
Voltage[7]
Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Output Leakage Current
VDD Operating Supply Current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
30
GND ≤ VI ≤ VDDQ, Output Disabled
IOZ
µA
µA
–5
Input = VDD
IDD
µA
5
µA
5
µA
4-ns cycle, 250 MHz
325
mA
4.4-ns cycle, 225 MHz
290
mA
5-ns cycle, 200 MHz
265
mA
–5
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100 MHz
205
mA
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 4.4-ns cycle, 225 MHz
1/tCYC
5-ns cycle, 200 MHz
120
mA
115
mA
110
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133 MHz
90
mA
10-ns cycle, 100 MHz
80
mA
Shaded areas contain advance information.
Notes:
7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05220 Rev. *A
Page 8 of 17
CY7C1328F
Electrical Characteristics Over the Operating Range[7, 8]
Parameter
Description
Test Conditions
Min.
Max.
Unit
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max., Device Deselected, All speeds
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f=0
40
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max., Device Deselected, 4-ns cycle, 250 MHz
or VIN ≤ 0.3V or VIN > VDDQ – 4.4-ns cycle, 225 MHz
0.3V, f = fMAX = 1/tCYC
5-ns cycle, 200 MHz
105
mA
100
mA
95
mA
6-ns cycle, 166 MHz
85
mA
7.5-ns cycle, 133 MHz
75
mA
10-ns cycle, 100 MHz
ISB4
Automatic CE Power-down
Current—TTL Inputs
VDD = Max., Device Deselected, All speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
65
mA
45
mA
Thermal Characteristics[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring thermal impedance, per EIA /
JESD51.
TQFP
Package
Unit
41.83
°C/W
9.99
°C/W
Max.
Unit
5
pF
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ = 3.3V
5
pF
5
pF
Note:
9. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05220 Rev. *A
Page 9 of 17
CY7C1328F
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
VL = 1.5V
(a)
ALL INPUT PULSES
VDD
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R =1538Ω
VL = 1.25V
(a)
Document #: 38-05220 Rev. *A
ALL INPUT PULSES
VDD
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Page 10 of 17
CY7C1328F
Switching Characteristics Over the Operating Range
250 MHz
Parameter
Description
[10, 11]
225 MHz
200 MHz
166 MHz
133 MHz
100 MHz
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
VDD(Typical) to the First Access[12] 1.0
1.0
1.0
1.0
1.0
1.0
ms
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
3.5
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
3.5
ns
tPOWER
Clock
Output Times
tCO
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
tCLZ
Clock to Low-Z[13, 14, 15]
tCHZ
[13, 14, 15]
tOEV
tOELZ
2.6
2.6
2.8
3.5
4.0
4.5
ns
1.0
1.0
1.0
2.0
2.0
2.0
ns
0
0
0
0
0
0
ns
Clock to High-Z
2.6
2.6
2.8
3.5
4.0
4.5
ns
OE LOW to Output Valid
OE LOW to Output Low-Z[13, 14, 15]
2.6
2.6
2.8
3.5
4.5
4.5
ns
0
tOEHZ
0
2.6
OE HIGH to Output
[13, 14, 15]
High-Z
Set-up Times
0
2.6
0
2.8
0
3.5
0
4.0
ns
4.5
ns
tAS
Address Set-up before CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tADS
ADSC, ADSP Set-up before CLK
Rise
ADV Set-up Before CLK Rise
GW, BWE, BW[A:B] Set-up before
CLK Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
0.8
1.2
1.2
1.5
1.5
1.5
ns
0.8
1.2
1.2
1.5
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise 0.8
1.2
1.2
1.5
1.5
1.5
ns
tCES
Chip Enable Set-up before CLK
Rise
0.8
1.2
1.2
1.5
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tADH
ADSP , ADSC Hold after CLK Rise 0.4
0.4
ADV Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
ns
0.5
0.5
0.5
0.5
0.5
ns
0.4
0.5
0.5
0.5
0.5
0.5
ns
tDH
GW,BWE, BW[A:B] Hold after CLK
Rise
Data Input Hold after CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.4
0.5
0.5
0.5
0.5
0.5
ns
tADVS
tWES
Hold Times
tADVH
tWEH
Shaded areas contain advance information.
Notes:
10. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 38-05220 Rev. *A
Page 11 of 17
CY7C1328F
Switching Waveforms
Read Timing[16]
tCYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
tWES
A3
Burst continued with
new base address
tWEH
GW, BWE,BW
[A:B]
tCES
Deselect
cycle
tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note:
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05220 Rev. *A
Page 12 of 17
CY7C1328F
Switching Waveforms (continued)
Write Timing[16, 17]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS
tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BW[A :B]
tWES tWEH
GW
tCES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
tDS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Note:
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document #: 38-05220 Rev. *A
Page 13 of 17
CY7C1328F
Switching Waveforms (continued)
Read/Write Timing[16, 18, 19]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE,
BW[A:B]
tCES
tCEH
CE
ADV
OE
tDS
tCO
tDH
tOELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A4)
Q(A2)
Single WRITE
Q(A4+1)
Q(A4+2)
BURST READ
DON’T CARE
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes:
18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
19. GW is HIGH.
Document #: 38-05220 Rev. *A
Page 14 of 17
CY7C1328F
Switching Waveforms (continued)
ZZ Mode Timing [20, 21]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
20. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
21. DQs are in high-Z when exiting ZZ sleep mode.
Ordering Information
Speed
(MHz)
250
225
200
166
133
100
Package
Name
Package Type
Operating
Range
CY7C1328F-250AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-250AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1328F-225AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-225AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1328F-200AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-200AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1328F-166AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-166AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1328F-133AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-133AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
CY7C1328F-100AC
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1328F-100AI
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
Ordering Code
Shaded area contains advance information.
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05220 Rev. *A
Page 15 of 17
CY7C1328F
Package Diagram
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05220 Rev. *A
Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1328F
Document History Page
Document Title: CY7C1328F 4-Mb (256K x 18) Pipelined DCD Sync SRAM
Document Number: 38-05220
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
119825
03/04/03
HGK
New Data Sheet
*A
200143
See ECN
REF
Final Data Sheet
Document #: 38-05220 Rev. *A
Page 17 of 17