ON MC14007UBCP Dual complementary pair plus inverter Datasheet

MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three N−Channel
and three P−Channel enhancement mode devices packaged to provide
access to each device. These versatile parts are useful in inverter
circuits, pulse−shapers, linear amplifiers, high input impedance
amplifiers, threshold detectors, transmission gating, and functional
gating.
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MARKING
DIAGRAMS
Features
14
PDIP−14
P SUFFIX
CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
•
•
•
1
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
Pb−Free Packages are Available
14
SOIC−14
D SUFFIX
CASE 751A
VDD
Parameter
14
Unit
−0.5 to +18.0
V
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8 second Soldering)
260
°C
Iin, Iout
DC Supply Voltage Range
Value
−0.5 to VDD +0.5
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
14007UG
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
MC14007UBCP
AWLYYWWG
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/°C from 65°C 5o 125°C.
SOEIAJ−14
F SUFFIX
CASE 965
MC14007UB
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
PIN ASSIGNMENT
D−PB
1
14
VDD
S−PB
2
13
D−PA
GATEB
3
12
OUTC
S−NB
4
11
S−PC
D−NB
5
10
GATEC
GATEA
6
9
S−NC
VSS
7
8
D−NA
D = DRAIN
S = SOURCE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 8
1
Publication Order Number:
MC14007UB/D
MC14007UB
A
A
12
B
9
B
1
C
2
3
INPUT
4
5
VDD
14
C
11
INPUT
OUTPUT CONDITION
1
0
A = C, B = OPEN
A = B, C = OPEN
13
INPUT
6
8
7
Substrates of P−Channel devices internally
connected to VDD; substrates of N−Channel
devices internally connected to VSS.
10
VSS
Figure 1. Typical Application: 2−Input Analog Multiplexer
14
13
2
1
11
6
12
7
8
3
4
5
10
VDD = PIN 14
VSS = PIN 7
Figure 2. Schematic
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2
9
MC14007UB
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55°C
Symbol
Characteristic
25°C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
125°C
Max
Min
Max
Unit
VOL
Output Voltage
Vin = VDD or 0
“0” Level
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH
Vin = 0 or VDD
“1” Level
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
5.0
10
15
−
−
−
1.0
2.0
2.5
−
−
−
2.25
4.50
6.75
1.0
2.0
2.5
−
−
−
1.0
2.0
2.5
“1” Level
5.0
10
15
4.0
8.0
12.5
−
−
−
4.0
8.0
12.5
2.75
5.50
8.25
−
−
−
4.0
8.0
12.5
−
−
−
Source
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
−
−
−
−
–2.4
–0.51
−1.3
−3.4
–5.0
–1.0
–2.5
–10
−
−
−
−
–1.7
−0.36
–0.9
−2.4
−
−
−
−
Sink
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
1.0
2.5
10
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
VIL
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
VIH
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
IOH
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOL
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
“0” Level
Vdc
Vdc
mAdc
Iin
Input Current
15
−
±0.1
−
± 0.00001
±0.1
−
±1.0
mAdc
Cin
Input Capacitance
(Vin = 0)
−
−
−
−
5.0
7.5
−
−
pF
IDD
Quiescent Current
(Per Package)
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
Total Supply Current (Notes 3 and 4)
(Dynamic plus Quiescent,
Per Gate) (CL = 50 pF)
5.0
10
15
IT
IT = (0.7 mA/kHz) f + IDD/6
IT = (1.4 mA/kHz) f + IDD/6
IT = (2.2 mA/kHz) f + IDD/6
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.003.
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3
mAdc
MC14007UB
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25°C)
Symbol
Characteristic
VDD
Vdc
Min
Typ
(Note 6)
Max
tTLH
Output Rise Time
tTLH = (1.2 ns/pF) CL + 30 ns
tTLH = (0.5 ns/pF) CL + 20 ns
tTLH = (0.4 ns/pF) CL + 15 ns
5.0
10
15
−
−
−
90
45
35
180
90
70
tTHL
Output Fall Time
tTHL = (1.2 ns/pF) CL + 15 ns
tTHL = (0.5 ns/pF) CL + 15 ns
tTHL = (0.4 ns/pF) CL + 10 ns
5.0
10
15
−
−
−
75
40
30
150
80
60
tPLH
Turn−Off Delay Time
tPLH = (1.5 ns/pF) CL + 35 ns
tPLH = (0.2 ns/pF) CL + 20 ns
tPLH = (0.15 ns/pF) CL + 17.5 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
tPHL
Turn−On Delay Time
tPHL = (1.0 ns/pF) CL + 10 ns
tPHL = (0.3 ns/pF) CL + 15 ns
tPHL = (0.2 ns/pF) CL + 15 ns
5.0
10
15
−
−
−
60
30
25
125
75
55
Unit
ns
ns
ns
ns
5. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD = −VGS
VDD = VGS
14
IOH
7
14
VDS = VOH − VDD
IOL
VSS
7
All unused inputs connected to ground.
All unused inputs connected to ground.
20
c
VGS = −5.0 Vdc
a TA = −55°C
b TA = +25°C
c TA = +125°C
−8.0
b
a
c
−12
b
b
c
−10 Vdc
−16
IOL , DRAIN CURRENT (mAdc)
IOH , DRAIN CURRENT (mAdc)
0
−4.0
−15 Vdc
a
a
−20
−10
−8.0
−6.0
−4.0
VDS, DRAIN VOLTAGE (Vdc)
VDS = VOL
VSS
−2.0
a
VGS = 15 Vdc
b
c
16
a
12
10 Vdc
b
c
a TA = −55°C
b TA = +25°C
c TA = +125°C
8.0
a
4.0
c
0
−0
0
Figure 3. Typical Output Source Characteristics
2.0
b 5.0 Vdc
4.0
6.0
VDS, DRAIN VOLTAGE (Vdc)
8.0
Figure 4. Typical Output Sink Characteristics
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
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4
10
MC14007UB
VDD
500mF
ID
VDD
VSS
tPHL
Vout
7
20 ns
90%
50%
10%
Vin
14
Vin
PULSE
GENERATOR
20 ns
0.01 mF
CERAMIC
VSS
tPLH
CL
VOH
90%
50%
10%
Vout
VOL
tTHL
tTLH
Figure 5. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
The MC14007UB dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications.
Figures 1, 6, and 7 are a few examples of the device flexibility.
+V DD
2
VDD
14
1
13
OUT = A+B•C
DISABLE3
11
INPUT10
11
12OUTPUT
B
10
2
12
1
8
OUTPUT
9
9
8
7
5
DISABLE6
7
C
3
4
INPUT
DISABLE
OUTPUT
1
0
X
0
0
1
0
1
OPEN
A
6
Substrates of P−Channel devices internally connected to VDD;
Substrates of N−Channel devices internally connected to VSS.
X = Don’t Care
Figure 7. AOI Functions Using Tree Logic
Figure 6. 3−State Buffer
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5
MC14007UB
ORDERING INFORMATION
Device
Shipping †
Package
MC14007UBCP
PDIP−14
MC14007UBCPG
PDIP−14
(Pb−Free)
MC14007UBD
SOIC−14
MC14007UBDG
SOIC−14
(Pb−Free)
MC14007UBDR2
SOIC−14
MC14007UBDR2G
SOIC−14
(Pb−Free)
MC14007UBFEL
SOEIAJ−14
MC14007UBFELG
SOEIAJ−14
(Pb−Free)
25 Units / Rail
55 Units / Rail
2500 / Tape & Reel
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MC14007UB
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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7
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC14007UB
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC14007UB
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
1.42
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.056
ON Semiconductor and
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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