Renesas M37905F8CFP 16-bit cmos microcomputer Datasheet

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
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DESCRIPTION
These are single-chip 16-bit microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash
memory and, being packaged in 64-pin plastic molded QFP or shrink
plastic molded DIP. These microcomputers support the 7900 Series
instruction set, which are enhanced and expanded instruction set
and are upper-compatible with the 7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data.
Also, they are suitable for motor-control equipment since each of
them includes the motor control circuit.
For the internal flash memory, single-power-supply programming
and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain
software which controls programming and erasure (reprogramming
control software). Therefore, on these microcomputers, the program
can easily be changed even after they are mounted on the board.
DISTINCTIVE FEATURES
<Microcomputer mode>
Number of basic machine instructions .................................... 203
Memory
Flash memory (User ROM area) ................................... 60 Kbytes
RAM ............................................................................. 3072 bytes
Flash memory (Boot ROM area) ..................................... 8 Kbytes
Instruction execution time
The fastest instruction at 20 MHz frequency ........................ 50 ns
Single power supply .................................................... 5 V ± 0.5 V
Interrupts ........... 8 external sources, 23 internal sources, 7 levels
Multi-functional 16-bit timer ................................................. 10 + 3
(Three-phase motor drive waveform or Pulse motor drive waveform
output is available.)
Serial I/O (UART or Clock synchronous) ..................................... 3
10-bit A-D converter .......................................... 12-channel inputs
8-bit D-A converter ............................................ 2-channel outputs
12-bit watchdog timer
Programmable input/output (ports P1, P2, P4, P5, P6, P7, P8) ...... 50
•
•
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•
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M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
<Flash memory mode>
Power supply voltage .................................................. 5 V ± 0.5 V
Programming/Erase voltage ........................................ 5 V ± 0.5 V
Programming method .................... Programming in a unit of word
Erase method ............................................ Block erase or Total erase
M37905F8CFP, M37905F8CSP
............... 4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1)
Programming/Erase control by software command
Maximum number of reprograms ............................................ 100
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APPLICATION
• Control devices for office equipment such as copiers and facsimiles
• Control devices for industrial equipment such as communication
and measuring instruments
• Control devices for equipment, requiring motor control, such as
inverter air conditioners and general-purpose inverters
MI
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P13/TxD0
P14/CTS1/RTS1
P15/CTS1/CLK1
P16/RxD1
P17/TxD1
P20/TA4OUT
P21/TA4IN
P22/TA9OUT
P23/TA9IN
P24(/TB0IN)
P25(/TB1IN)
Note
P26(/TB2IN)
P27
MD1
P40/TA5OUT/RTP20
P41/TA5IN/RTP21
M37905F8CFP PIN CONFIGURATION (TOP VIEW)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M37905F8CFP
P42/TA6OUT/RTP22
P43/TA6IN/RTP23
P44/TA7OUT/RTP30
P45/TA7IN/RTP31
P46/TA8OUT/RTP32
P47/TA8IN/RTP33
P4OUTCUT/INT0
P51/INT1
P52/INT2/RTPTRG1
P53/INT3/RTPTRG0
VSS
VCONT
XOUT
XIN
RESET
MD0
Note
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P67/TA3IN/RTP13
P66/TA3OUT/RTP12
P65/TA2IN/U/RTP11
P64/TA2OUT/V/RTP10
P63/TA1IN/W/RTP03
P62/TA1OUT/U/RTP02
P61/TA0IN/V/RTP01
P60/TA0OUT/W/RTP00
P57/INT7/TB2IN/IDU
P56/INT6/TB1IN/IDV
P55/INT5/TB0IN/IDW
P6OUTCUT/INT4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P12/RXD0
P11/CTS0/CLK0
P10/CTS0/RTS0
VCC
AVCC
VREF
AVSS
VSS
P83/AN11/TXD2
P82/AN10/RXD2
P81/AN9/CTS2/CLK2
P80/AN8/CTS2/RTS2/DA1
P77/AN7/DA0
P76/AN6
P75/AN5
P74/AN4
Outline 64P6N-A
2
Note: Allocation of pins TB0IN to TB2IN
can be switched by software.
MI
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
M37905F8CSP PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
M37905F8CSP
P83/AN11/TxD2
P82/AN10/RxD2
P81/AN9/CTS2/CLK2
P80/AN8/CTS2/RTS2/DA1
P77/AN7/DA0
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P67/TA3IN/RTP13
P66/TA3OUT/RTP12
P65/TA2IN/U/RTP11
P64/TA2OUT/V/RTP10
P63/TA1IN/W/RTP03
P62/TA1OUT/U/RTP02
P61/TA0IN/V/RTP01
P60/TA0OUT/W/RTP00
P57/INT7/TB2IN/IDU
Note
P56/INT6/TB1IN/IDV
P55/INT5/TB0IN/IDW
P6OUTCUT/INT4
MD0
RESET
XIN
XOUT
VCONT
VSS
P53/INT3/RTPTRG0
P52/INT2/RTPTRG1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS
AVSS
VREF
AVCC
VCC
P10/CTS0/RTS0
P11/CTS0/CLK0
P12/RxD0
P13/TxD0
P14/CTS1/RTS1
P15/CTS1/CLK1
P16/RxD1
P17/TxD1
P20/TA4OUT
P21/TA4IN
P22/TA9OUT
P23/TA9IN
P24(/TB0IN)
Note
P25(/TB1IN)
P26(/TB2IN)
P27
MD1
P40/TA5OUT/RTP20
P41/TA5IN/RTP21
P42/TA6OUT/RTP22
P43/TA6IN/RTP23
P44/TA7OUT/RTP30
P45/TA7IN/RTP31
P46/TA8OUT/RTP32
P47/TA8IN/RTP33
P4OUTCUT/INT0
P51/INT1
Note: Allocation of pins TB0IN to TB2IN
can be switched by software.
Outline 64P4B
3
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
Data Bus (Even)
Data Bus (Odd)
Data Buffer DQ0 (8)
P6OUTCUT
Data Buffer DQ1 (8)
Data Buffer DQ2 (8)
Address Bus
P4OUTCUT
Data Buffer DQ3 (8)
Instruction Queue Buffer Q0 (8)
Instruction Queue Buffer Q1 (8)
Instruction Queue Buffer Q2 (8)
Reference
Voltage Input
VREF
Instruction Queue Buffer Q3 (8)
Instruction Queue Buffer Q4 (8)
Instruction Queue Buffer Q5 (8)
MD0
Arithmetic Logic
Unit (16)
Input/Output P1
P1(8)
A-D Converter (12)
Input/Output P4
P4(8)
Timer TB0 (16)
Timer TA5 (16)
Timer TA0 (16)
Timer TB2 (16)
Input/Output P5
Input/Output P6
P5(6)
P6(8)
Input/Output P7
Accumulator A (16)
Input/Output P8
Accumulator B (16)
P7(8)
Clock Generating Circuit
Clock output
XOUT
Clock input
XIN
Index Register X (16)
P8(4)
Stack Pointer S (16)
Index Register Y (16)
RAM
3072 bytes
Reset input
RESET
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
ROM
60 Kbytes
Direct Page Register DPR1 (16)
VCONT
Timer TB1 (16)
Timer TA2 (16)
VCC
Direct Page Register DPR0 (16)
Central Processing Unit (CPU)
Input Buffer Register IB (16)
Processor Status Register PS (11)
BLOCK DIAGRAM
Timer TA6 (16)
Timer TA7 (16)
Timer TA3 (16)
(0V)
VSS
Data Bank Register DT (8)
Timer TA1 (16)
Watchdog Timer
Timer TA9 (16)
Timer TA8 (16)
Timer TA4 (16)
Program Counter PC (16)
Program Bank Register PG (8)
4
Input/Output P2
Incrementer/Decrementer (24)
P2(8)
UART2 (9)
Data Address Register DA (24)
UART1 (9)
MD1
Program Address Register PA (24)
Bus
Interface
Unit
(BIU)
Incrementer (24)
UART0 (9)
Instruction Queue Buffer Q9 (8)
D-A0 Converter (8)
D-A1 Converter (8)
Instruction Queue Buffer Q7 (8)
Instruction Queue Buffer Q8 (8)
(0V)
AVSS
AVCC
Instruction Register (8)
Instruction Queue Buffer Q6 (8)
MI
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MITSUBISHI MICROCOMPUTERS
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NAR
M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
FUNCTIONS (Microcomputer mode)
Parameter
Number of basic machine instructions
203
Functions
Instruction execution time
50 ns (the fastest instruction at f(fsys) = 20 MHz)
External clock input frequency f(XIN)
20 MHz (Max.)
System clock frequency f(fsys)
20 MHz (Max.)
Flash memory (User ROM area)
60 Kbytes
RAM
3072 bytes
Flash memory (Boot ROM area)
8 Kbytes
Programmable input/output
P1, P2, P4, P6, P7
8-bit ✕ 5
ports
P5
6-bit ✕ 1
P8
4-bit ✕ 1
TA0–TA9
16-bit ✕ 10
TB0–TB2
16-bit ✕ 3
UART0, UART1, and UART2
(UART or Clock synchronous serial I/O) ✕ 3
Memory size
Multi-functional timers
Serial I/O
A-D converter
10-bit successive approximation method ✕ 1 (12 channels)
D-A converter
8-bit ✕ 2
Dead-time timer
8-bit ✕ 3
Watchdog timer
12-bit ✕ 1
Interrupts
Maskable interrups
8 external sources, 20 internal sources. Each interrupt can be set
to a priority level within the range of 0–7 by software.
Non-maskable interrups
3 internal sources.
Incorporated (externally connected to a ceramic resonator or
quartz crystal resonator).
Clock generating circuit
PLL frequency multiplier
The following multiplication ratios are available: ✕2, ✕3, ✕4.
Power supply voltage
5 V±0.5 V
Power dissipation
125 mW (at f(fsys) = 20 MHz, Typ., ; the PLL frequency multiplier
is inactive.)
Ports’ input/output
characteristics
Memory expansion
Input/Output withstand voltage
5V
Output current
5 mA
Not available (single-chip mode only).
Operating ambient temperature range
–20 to 85 °C
Device structure
CMOS high-performance silicon gate process
Package
(Note)
Note:
Packages
M37905F8CFP
64-pin plastic molded QFP (64P6N-A)
M37905F8CSP
64-pin shrink plastic moldeds DIP (64P4B)
5
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
FUNCTIONS (Flash memory mode)
Parameter
Functions
Power supply voltage
5 V±0.5 V
Programming/Erase voltage
5 V±0.5 V
Flash memory mode
3 modes: parallel I/O, serial I/O, and CPU reprogramming modes
Block division for erasure
User ROM area
Boot ROM area
4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1); total of
60 Kbytes
1 block (8 Kbytes ✕ 1) (Note)
Programmed per word
Programming method
Flash memory parallel I/O mode
User ROM area + Boot ROM area
Flash memory serial I/O mode
User ROM area
Flash memory CPU reprogramming mode
User ROM area
Total erase/Block erase
Erase method
Flash memory parallel I/O mode
User ROM area + Boot ROM area
Flash memory serial I/O mode
User ROM area
Flash memory CPU reprogramming mode
User ROM area
Programming/Erase control
Programming/Erase control by software commands
Number of commands
6 commands
Maximum number of reprograms
100
Note: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.
6
MI
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MITSUBISHI MICROCOMPUTERS
Y
NAR
M37905F8CFP, M37905F8CSP
.
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icat
ecif ct to c
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a fin are su
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16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (MICROCOMPUTER MODE)
Pin
Name
Input/
Output
Functions
Vcc, Vss
Power supply input
MD0
MD0
Input
Connect this pin to VSS.
MD1
MD1
Input
Connect this pin to Vss.
RESET
Reset input
Input
The microcomputer is reset when “L” level is applies to this pin.
XIN
Clock input
Input
XOUT
Clock output
These are input and output pins of the internal clock generating circuit. Connect a
ceramic resonator or quartz-crystal oscillator between pins XIN and XOUT. When an
external clock is used, the clock source should be connected to pin XIN, and pin
XOUT should be left open.
VCONT
Filter circuit connection
—
When using the PLL frequency multiplier, connect this pin to the filter circuit. When
not using the PLL frequency multiplier, this pin should be left open.
AVcc,
AVss
Analog power supply input
—
Power supply input pins for the A-D and D-A converters. Connect AVcc to Vcc, and
AVss to Vss externally.
VREF
Reference voltage input
P10–P17
I/O port P1
I/O
Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pin can
be programmed for input or output. These pins enter the input mode ar reset. These
pins also function as I/O pins of UART0, 1.
P20–P27
I/O port P2
I/O
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A4 and A9. Also, they can be programmed to function as input pins for timers B0 to B2.
P40–P47
I/O port P4
I/O
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A5 to A8. Also, they function as output pins for motor drive waveform.
P51–P53,
P55–P57
I/O port P5
I/O
In addition to having the same functions as port P1, these pins function as input pins
for INT1 to INT3 and INT5 to INT7. Also, pins P55 to P57 function as input pins for timers B0 to B2 and as input pins for position data in the three-phase waveform mode;
and pins P52 and P53 function as trigger-input pins in the pulse output port mode.
P60–P67
I/O port P6
I/O
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A0 to A3. Also, they function as motor drive waveform output pins.
P70–P77
I/O port P7
I/O
In addition to having the same functions as port P1, these pins function as input pins
for the A-D converter. Also, P77 functions as an output pin for the D-A converter.
P80–P83
I/O port P8
I/O
In addition to having the same functions as port P1, these pins function as input pins
for the A-D converter. Also, these pins function as I/O pins for UART2, and pin P80
functions as an output pin for the D-A converter.
P4OUTCUT
P4OUTCUT input
Input
This pin has the function to forcibly place port P4 pins in the input mode. Also, this
pin functions as an input pin for INT0; and this pin is used to input a signal, which
forcibly cuts off a motor drive waveform output.
P6OUTCUT
P6OUTCUT input
Input
This pin has the function to forcibly place port P6 pins in the input mode. Also, this
pin functions as an input pin for INT4; and this pin is used to input a signal, which
forcibly cuts off a motor drive waveform output.
—
Output
Input
Apply 5 V±0.5 V to Vcc, and 0 V to Vss.
This is the reference voltage input pin for the A-D and D-A converters.
7
MI
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MITSUBISHI MICROCOMPUTERS
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NAR
M37905F8CFP, M37905F8CSP
ge.
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icat to chan
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a
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not mits ar
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16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)
Pin
Name
Input
/Output
—
Functions
VCC, VSS
Power supply input
MD0
MD0
MD1
Input
Input
Connect this pin to Vss.
Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ.
Reset input
Input
The reset input pin.
XIN
Clock input
Input
XOUT
Clock output
AVcc, AVss
Analog supply input
VREF
Reference voltage input
—
Input
P10–P17
Input port P1
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
P20–P23, P27 Input port P2
SCLK input
P24
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input
This is an input pin for a serial clock.
MD1
_____
RESET
P25
P26
P4OUTCUT
SDA I/O
BUSY output
Output
I/O
Output
Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss.
Connect a ceramic oscillator between the XIN and XOUT pins, or input an external
clock from the XIN pin with the XOUT pin left open.
Connect AVcc to Vcc, and AVss to Vss.
Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.)
This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ).
This is an output pin for the BUSY signal.
P4OUTCUT input
Input
P6OUTCUT
P6OUTCUT input
Input
Input “H”.
P40–P47
Input port P4
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
P55–P53,
Input port P5
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
P60–P67
Input port P6
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
P70–P74
Input port P7
Input
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
P80–P83
Input port P8
Input
VCONT
Filter circuit connection
Input “H”.
P55–P57
8
—
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash
memory serial I/O mode.)
MI
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MITSUBISHI MICROCOMPUTERS
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NAR
M37905F8CFP, M37905F8CSP
.
ion. hange
icat
ecif ct to c
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s
al
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a fin are su
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T
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Not e para
Som
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16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
Each of the M37905F8CFP and M37905F8CSP has the same function as that of the M37905M4C-XXXFP except for the following.
Therefore, for details except for the following, refer to the datasheet
of the M37905M4C-XXXFP.
• Internal ROM: type (flash memory) and size
• RAM size
MEMORY
Figure 1 shows the memory map.
00000016
00000016
0000FF16
00010016
0003FF16
00040016
Peripheral devices
control registers
Peripheral devices
control registers
(See Figures 2 and 3.)
Unused area
Bank 016
Internal RAM
3072 bytes
00FFFF16
00000016
000FFF16
00100016
0000FF16
00FFB416
Internal ROM
60 Kbytes
Interrupt vector table
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT7
INT6
INT5
Reserved area
Address matching detect
Reserved area
Reserved area
00FFB416
INT4
INT3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
00FFFF16
INT2
INT1
INT0
Reserved area
Watchdog timer
00FFFE16
DBC
BRK instruction
Zero divide
RESET
Fig. 1 Memory map of M37905F8CFP, M37905F8CSP (Single-chip mode)
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Address (Hexadecimel notation)
00000016
00000116
00000216
00000316
00000416
00000516
00000616
00000716
00000816
00000916
00000A16
00000B16
00000C16
00000D16
00000E16
00000F16
00001016
00001116
00001216
00001316
00001416
00001516
00001616
00001716
00001816
00001916
00001A16
00001B16
00001C16
00001D16
00001E16
00001F16
00002016
00002116
00002216
00002316
00002416
00002516
00002616
00002716
00002816
00002916
00002A16
00002B16
00002C16
00002D16
00002E16
00002F16
00003016
00003116
00003216
00003316
00003416
00003516
00003616
00003716
00003816
00003916
00003A16
00003B16
00003C16
00003D16
00003E16
00003F16
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Port P1 register
Reserved area (Note)
Port P1 direction register
Port P2 register
Reserved area (Note)
Port P2 direction register
Reserved area (Note)
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
A-D control register 0
A-D control register 1
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART0 transmit/receive mode register
UART0 band rate register (BRG0)
UART0 transmit buffer register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 baud rate register (BRG1)
UART1 transmit buffer register
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimel notation)
00004016
00004116
00004216
00004316
00004416
00004516
00004616
00004716
00004816
00004916
00004A16
00004B16
00004C16
00004D16
00004E16
00004F16
00005016
00005116
00005216
00005316
00005416
00005516
00005616
00005716
00005816
00005916
00005A16
00005B16
00005C16
00005D16
00005E16
00005F16
00006016
00006116
00006216
00006316
00006416
00006516
00006616
00006716
00006816
00006916
00006A16
00006B16
00006C16
00006D16
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
Count start register 0
Count start register 1
One-shot start register 0
One-shot start register 1
Up-down register 0
Timer A clock division select register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency select register
Particular function select register 0
Particular function select register 1
Particular function select register 2
Reserved area (Note)
Debug control register 0
Debug control register 1
Address comparison register 0
Address comparison register 1
INT3 interrupt control register
INT4 interrupt control register
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
Note: Do not write to this address.
Fig. 2 Location of SFRs (1)
10
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Address (Hexadecimel notation)
00008016
00008116
00008216
00008316
00008416
00008516
00008616
00008716
00008816
00008916
00008A16
00008B16
00008C16
00008D16
00008E16
00008F16
00009016
00009116
00009216
00009316
00009416
00009516
00009616
00009716
00009816
00009916
00009A16
00009B16
00009C16
00009D16
00009E16
00009F16
0000A016
0000A116
0000A216
0000A316
0000A416
0000A516
0000A616
0000A716
0000A816
0000A916
0000AA16
0000AB16
0000AC16
0000AD16
0000AE16
0000AF16
0000B016
0000B116
0000B216
0000B316
0000B416
0000B516
0000B616
0000B716
0000B816
0000B916
0000BA16
0000BB16
0000BC16
0000BD16
0000BE16
0000BF16
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
External interrupt input read-out register
D-A control register
D-A register 0
D-A register 1
Reserved area (Note)
Reserved area (Note)
Flash memory control register
Pulse output control register
Pulse output data register 0
Pulse output data register 1
Waveform output mode register
Dead-time timer
Three-phase output data register 0
Three-phase output data register 1
Position-data-retain function control register
Serial I/O pin control register
Port P2 pin function control register
UART2 transmit/receive mode register
UART2 band rate register (BRG2)
UART2 transmit buffer register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Clock control register 0
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Address (Hexadecimel notation)
0000C016
0000C116
0000C216
0000C316
0000C416
0000C516
0000C616
0000C716
0000C816
0000C916
0000CA16
0000CB16
0000CC16
0000CD16
0000CE16
0000CF16
0000D016
0000D116
0000D216
0000D316
0000D416
0000D516
0000D616
0000D716
0000D816
0000D916
0000DA16
0000DB16
0000DC16
0000DD16
0000DE16
0000DF16
0000E016
0000E116
0000E216
0000E316
0000E416
0000E516
0000E616
0000E716
0000E816
0000E916
0000EA16
0000EB16
0000EC16
0000ED16
0000EE16
0000EF16
0000F016
0000F116
0000F216
0000F316
0000F416
0000F516
0000F616
0000F716
0000F816
0000F916
0000FA16
0000FB16
0000FC16
0000FD16
0000FE16
0000FF16
Up-down register 1
Timer A5 register
Timer A6 register
Timer A7 register
Timer A8 register
Timer A9 register
Timer A01 register
Timer A11 register
Timer A21 register
Timer A5 mode register
Timer A6 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
A-D control register 2
Comparator function select register 0
Comparator function select register 1
Comparator result register 0
Comparator result register 1
A-D register 8
A-D register 9
A-D register 10
A-D register 11
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
UART2 transmit interrupt control register
UART2 receive interrupt control register
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 interrupt control register
Timer A8 interrupt control register
Timer A9 interrupt control register
INT5 interrupt control register
INT6 interrupt control register
INT7 interrupt control register
Note: Do not write to this address.
Fig. 3 Location of SFRs (2)
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FLASH MEMORY MODE
These microcomputers contain the flash memory; and single-powersupply reprogramming is available to this. These microcomputers
have the following three modes, enabling reading/programming/erasure for the flash memory:
• Flash memory parallel I/O mode and Flash memory serial I/O
mode, where the flash memory is handled by using an external programmer.
• CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU).
As shown in Figure 4, the flash memory is divided into several
blocks, and erasure per block is possible.
00100016
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
This internal flash memory has the boot ROM area storing the reprogramming control software for reprogramming in the CPU reprogramming mode and flash memory serial I/O mode, as well as the
user ROM area storing a certain control software for the normal operation in the microcomputer mode.
Although our reprogramming control firmware for the flash memory
serial I/O mode has been stored into this boot ROM area on shipment, the user-original reprogramming control software which is
more appropriate for the user’s system is reprogrammable into this
area, instead. Note that the reprogramming for the boot ROM area is
enabled only in the flash memory parallel I/O mode.
00100016
28 Kbytes
007FFF16
00800016
00FFFF16
16 Kbytes
00BFFF16
00C00016
8 Kbytes
00DFFF16
00E00016
00FFFF16
Fig. 4 M37905F8CFP, M37905F8CSP: block configuration of internal flash memory
12
8 Kbytes
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MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Flash Memory Parallel I/O Mode
User ROM Area and Boot ROM Area
The flash memory parallel I/O mode is used to manipulate the internal flash memory with a parallel programmer. This parallel programmer uses the software commands listed in Table 1 to do the flash
memory manipulations, such as read/programming/erase operations.
The user ROM area and boot ROM area can be reprogrammed in
the flash memory parallel I/O mode.
The programming and block erase operations can be performed only
to these areas.
The boot ROM area, 8 Kbytes in size, is assigned to addresses
000016–1FFF16, so that programming and block erase operations
can be performed only to this area. (Access to any address out of
this area is prohibited).
The erasable block in the boot ROM area is only one block, consisting of 8 Kbytes. The reprogramming control firmware to be used in
the flash memory serial I/O mode has been stored to this boot ROM
area on our shipment. Therefore, do not reprogram the boot ROM
area if the user uses the flash memory serial I/O mode.
Do not program to addresses FF9016 to FF9F16 because this area is
the reserved area for the programmer.
Note that, when the boot ROM area is read out from the CPU in the
CPU reprogramming mode, described later, its addresses will be
shifted to E00016—FFFF16.
Table 1. Software commands (flash memory parallel I/O mode
Software Command
Read Array
Read Status Register
Clear Status Register
Programming
Block Erase
Erase All Block
Addresses FF9016 to FF9F16 are the reserved area for the parallel
programmer. Therefore, when the user uses the flash memory parallel I/O mode, do not program to this area.
13
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Flash Memory Serial I/O Mode
In the flash memory serial I/O mode, addresses, data, and software
commands, which are required to read/program/erase the internal
flash memory, are serially input and output with a fewer pins and the
dedicated serial programmer.
In this mode, being different from the flash memory parallel I/O
mode, the CPU controls reprogramming of the flash memory (using
the CPU reprogramming mode), serial input of the reprogramming
data, etc.
The reprogramming control firmware for the flash memory serial I/O
mode has been stored in the boot ROM area on shipment of the
product from us. Note that, then, the flash memory serial I/O mode
will become unavailable if the boot ROM area has been reprogrammed in the flash memory parallel I/O mode.
Note that, also, this reprogramming control firmware for the flash
memory serial I/O mode is subject to change.
Figures 5 and 6 show the pin connections in the flash memory serial
I/O mode.
The three pins, SCLK, SDA, and BUSY, are used to input and output
serial data.
The SCLK pin is the input pin of external transfer clocks. The SDA
pin is the I/O pin of transmit and receive data, and its output acts as
the N-channel open-drain output. To the SDA pin, connect an external pullup resistor (about 1 kΩ). The BUSY pin is the output pin of the
BUSY flag (CMOS output) and goes “H” during BUSY periods owing
to a certain operation, such as transmit, receive, erase, programming, etc.
Transmit and receive data are serially transferred 8 bits at a time.
In the flash memory serial I/O mode, only the user ROM area can be
reprogrammed; the boot ROM area is not accessible.
Addresses FF9016 to FF9F16 are the reserved area for the serial
programmer. Therefore, when the user uses the flash memory serial
I/O mode, do not program to this area.
14
MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
A
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
MD1
33
34
36
35
37
38
40
39
42
41
P17/TxD1
P20/TA4OUT
P21/TA4IN
P22/TA9OUT
P23/TA9IN
P24(/ TB0IN)
P25(/ TB1IN)
P26(/ TB2IN)
P27
MD1
P40/TA5OUT/R TP20
P41/TA5IN/R TP21
44
43
46
45
20
62
19
63
18
64
17
VCONT
XOUT
XIN
R ESET
MD0
(Note 3)
(Note 2)
R ESET
P6OUTCUT/INT4
(Note 3)
(Note 1)
P73/AN 3
P72/AN 2
P71/AN 1
P70/AN 0
P67/TA3IN/R TP13
P66/TA3OUT/R TP12
P65/TA2IN/U/R TP11
P64/TA2OUT/V/R TP10
P63/TA1IN/W/R TP03
P62/TA1OUT/U/R TP02
P61/TA0IN/V/R TP01
P60/TA0OUT/W/R TP00
P57/INT7/TB2IN/IDU
P56/INT6/TB1IN/IDV
P55/INT5/TB0IN/IDW
P42/TA6OUT/R TP22
P43/TA6IN/R TP23
P44/TA7OUT/R TP30
P45/TA7IN/R TP31
P46/TA8OUT/R TP32
P47/TA8IN/R TP33
P4OUTCUT/INT0
P51/INT1
P52/INT2/R TPTRG 1
P53/INT3/R TPTRG 0
Vss
16
21
61
15
22
60
13
23
59
14
24
58
12
57
11
25
9
26
56
10
27
55
7
28
54
8
29
53
5
30
52
6
51
3
31
4
32
1
P83/AN 11 /TxD2
P82/AN 10 /R xD2
P81/AN 9/CTS2/CLK2
P80/AN 8/CTS2/R TS2/DA1
P77/AN 7/DA0
P76/AN 6
P75/AN 5
P74/AN 4
49
50
2
P12/R xD0
P11/CTS0/CLK0
P10/CTS0/R TS0
Vcc
AVcc
VR EF
AVss
Vss
47
48
P13/TxD0
P14/CTS1/R TS1
P15/CTS1/CLK1
P16/R xD1
VSS
VCC
SCLK
SDA
BUSY
(Note 1)
PRE
Notes 1: Allocation of pins TB0IN to TB2IN
can be switched by software.
2: Connected to the oscillation circuit.
3: Recommended to be connected with
VCC via a resistor.
: Connected to a serial programmer.
Outline 64P6N-A
Fig. 5 Pin connection of M37905F8CFP in flash memory serial I/O mode (outline: 64P6N-A)
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16-BIT CMOS MICROCOMPUTER
VCC
(Note 1)
(Note 3)
R ESET
(Note 2)
P83/AN 11 /TXD2
P82/AN 10 /RXD2
P81/AN 9/CTS2/CLK2
P80/AN 8/CTS2/R TS2/DA1
P77/AN 7/DA0
P76/AN 6
P75/AN 5
P74/AN 4
P73/AN 3
P72/AN 2
P71/AN 1
P70/AN 0
P67/TA3IN/R TP13
P66/TA3OUT/R TP12
P65/TA2IN/U/R TP11
P64/TA2OUT/V/R TP10
P63/TA1IN/W/R TP03
P62/TA1OUT/U/R TP02
P61/TA0IN/V/R TP01
P60/TA0OUT/W/R TP00
P57/INT7/TB2IN/IDU
P56/INT6/TB1IN/IDV
P55/INT5/TB0IN/IDW
P6OUTCUT/INT4
MD0
R ESET
XIN
XOUT
VCONT
Vss
P53/INT3/R TPTRG 0
P52/INT2/R TPTRG 1
64
1
2
63
62
3
4
61
5
6
60
7
8
58
57
59
9
56
10
11
55
54
12
13
53
52
14
15
51
16
17
49
50
48
47
18
19
46
20
21
45
22
23
43
44
42
41
40
24
25
26
39
38
27
28
37
36
29
30
31
35
34
32
33
Vss
AVss
VR EF
AVcc
Vcc
P10/CTS0/R TS0
P11/CTS0/CLK0
P12/RXD0
P13/TXD0
P14/CTS1/R TS1
P15/CTS1/CLK1
P16/RXD1
P17/TXD1
P20/TA4OUT
P21/TA4IN
P22/TA9OUT
P23/TA9IN
P24(/ TB0IN)
P25(/ TB1IN)
P26(/ TB2IN)
P27
MD1
P40/TA5OUT/R TP20
P41/TA5IN/R TP21
P42/TA6OUT/R TP22
P43/TA6IN/R TP23
P44/TA7OUT/R TP30
P45/TA7IN/R TP31
P46/TA8OUT/R TP32
P47/TA8IN/R TP33
P4OUTCUT/INT0
P51/INT1
SCLK
SDA
BUSY
MD1
(Note 3)
VSS
Notes 1: Allocation of pins TB0IN to TB2IN
can be switched by software.
2: Connected to the oscillation circuit.
3: Recommended to be connected with
VCC via a resistor.
: Connected to a serial programmer.
Outline 64P4B
Fig. 6 Pin connection of M37905F8CSP in flash memory serial I/O mode (outline: 64P4B)
16
(Note 1)
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MITSUBISHI MICROCOMPUTERS
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M37905F8CFP, M37905F8CSP
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16-BIT CMOS MICROCOMPUTER
CPU Reprogramming Mode
The CPU reprogramming mode is used to perform the operations for
the internal flash memory (reading, programming, erasing) under
control of the CPU.
In this mode, only the user ROM area can be reprogrammed; the
boot ROM area cannot be reprogrammed.
The user-original reprogramming control software for the CPU reprogramming mode can be stored in either the user ROM area or the
boot ROM area.
Because the CPU cannot read out the flash memory in the CPU reprogramming mode, the above software must be transferred to the
internal RAM in advance to be executed.
Boot Mode
The user-original reprogramming control software for the CPU reprogramming mode must be stored into the user ROM area or the boot
ROM area in the flash memory parallel I/O mode in advance. (If this
program has been stored into the boot ROM area, the flash memory
serial I/O mode will become unavailable).
7
6
5
4
3
2
1
Note that addresses of the boot ROM area depend on the accessing
ways to the boot ROM area, When accessing in the flash memory
parallel I/O mode, these addresses will be shifted to 000016 to
1FFF16. On the other hand, when accessing with the CPU, these addresses will be shifted to E00016 to FFFF16.
Reset removal with both of the MD0 and MD1 pins held “L” invokes
the normal microcomputer mode, and the CPU operates using the
control software stored in the user ROM area. In this case, the boot
ROM area is not accessible.
Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the
CPU starts its operation using the reprogramming control software
stored in the boot ROM area. This mode is called the boot mode. The
reprogramming control software in the boot ROM area can also reprogram the user ROM area.
After reset removal, be sure not to change the status at pins MD0
and MD1.
0
Flash memory control register
Address
9E16
RY/BY status bit
0: Busy (Programming or erasing is active.)
1: Ready
CPU reprogramming mode select bit (Note 2)
0: Normal mode (Software commands are ignored.)
1: CPU reprogramming mode (Software commands are acceptable.)
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area select bit (Note 4)
(Valid only in the boot mode.)
0: Boot ROM area access
1: User ROM area access
Notes 1: The contents of the flash memory control register after reset is removed are “XX000001”.
2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be
performed by the user-original reprogramming control software in the internal RAM.
3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after
setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”.
4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM.
Fig. 7 Bit configuration of flash memory control register
17
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Function overview (CPU reprogramming mode)
The CPU reprogramming mode is available in the single-chip mode,
memory expansion mode, and boot mode to reprogram the user
ROM area only.
In the CPU reprogramming mode, the CPU erases, programs, and
reads the internal flash memory by writing software commands. Note
that the user-original reprogramming control software must be transferred to the internal RAM in advance to be executed.
The CPU reprogramming mode becomes active when “1” is written
into the flash memory control register’s bit 1 (the CPU reprogramming mode select bit) shown in Figure 7, and software commands
become acceptable.
In the CPU reprogramming mode, software commands and data are
all written to and read from even addresses (Note that address A0 in
byte addresses = “0”.) 16 bits at a time. Therefore, a software command consisting of 8 bits must be written to an even address; therefore, any command written to an odd address will be invalid. Since
the write data at the 2nd cycle of a programming command consists
of 16 bits, this data must be written to even and odd addresses.
The seaquencer in the flash memory controls the erase and programming operations. What the status of the seaquencer operation
is and whether the programming or erase operation has been completed normally or terminated by an error can be examined by reading the flash memory control register.
Figure 7 shows the bit configuration of the flash memory control register.
Bit 0 (the RY/BY status bit) is a read-only bit for indicating the seaquencer operation. This bit goes to “0” (BUSY) while the automatic
programming/erase operation is active and goes to “1” (READY) during the other operations.
Bit 1 serves as the CPU reprogramming mode select bit. Writing of
“1” to this bit selects the CPU reprogramming mode, and software
commands will be acceptable. Because the CPU cannot directly access the internal flash memory in the CPU reprogramming mode,
writing to this bit 1 must be performed by the user-original reprogramming control software which has been transferred to the internal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and
“1” to this bit 1 successively. On the other hand, to clear this bit to “0”,
it is sufficient only to write “0”.
Bit 3 (the flash memory reset bit) resets the control circuit of the internal flash memory and is used when the CPU reprogramming
mode is terminated or when an abnormal access to the flash
memory happens. Writing of “1” to bit 3 with the CPU reprogramming
mode select bit = “1” preforms the reset operation. To remove the
reset, write “0” to bit 3 after confirming bit 0 (the RY/BY status bit) becomes “1”.
Bit 5 serves as the user ROM area select bit and is valid only in the
boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the
CPU reprogramming mode in the boot mode, set this bit to “1”. Note
that when the microcomputer is booted up in the user ROM area,
only the user ROM area is accessible and bit 5 is invalid; on the other
hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the CPU reprogramming mode. To rewrite bit 5, execute the user-original reprogramming control software transferred
to the internal RAM in advance.
Figure 8 shows the CPU reprogramming mode set/termination flow-
18
MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
chart, and be sure to follow this flowchart. As shown in Note 1 of Figure 8, before selecting the CPU reprogramming mode, set “0” to the
processor mode register 1’s bit 7 (the internal ROM bus cycle select
bit) and set flag I to “1” to avoid an interrupt request input.
When a watchdog timer interrupt request is generated in the CPU
reprogramming mode, when an input to the RESET pin is “L”, or
when the software reset is performed, the flash memory control circuit and flash memory control register will be reset.
When the flash memory is reset during the erase or programming
operation, this operation is cancelled and the target block’s data will
be invalid. Just before writing a software command related to the
erase/programming operation, be sure to write to the watchdog
timer. In the CPU reprogramming mode, be sure not to use the STP
and WIT instructions.
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M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Software Commands
Start
Single-chip mode,
Memory expansion mode,
or Boot mode
The processor mode register 1 is set (Note 1).
Flag I is set to “1”.
The user-original reprogramming control software
for the CPU reprogramming mode is transferred to
the internal RAM.
Jump to the above software in the internal RAM.
(The operations shown below will be executed by
the above software in this RAM.)
(Only in the boot mode.)
The user ROM area select bit is set to “1”.
Table 2 lists the software commands.
By writing a software command after the CPU reprogramming mode
select bit has been set to “1”, erasing, programming, etc. can be
specified. Note that, at software commands’ input, the high-order
byte (D8–D15) is ignored. (Except for the write data at the 2nd cycle
of a programming command.)
Software commands are explained as below.
Read Array Command (FF16)
By writing command code “FF16” at the 1st bus cycle, the microcomputer enters the read array mode. If an address to be read is input in
the next or the following bus cycles, the contents at the specified address are output to the data bus (D0 to D15) in a unit of 16 bits.
The read array mode is maintained until writing of another software
command.
Read Status Register Command (7016)
Writing command code “7016” at the 1st bus cycle outputs the contents of the status register to the data bus (D0-D7) by a read at the
2nd bus cycle.
The status register is explained later.
Clear Status Register Command (5016)
Writing of “1” to the CPU reprogramming mode select bit.
(Writing of “0” → Writing of “1”)
Operations such as erasing, programming are
executed by using software commands.
Read array command is executed, or reset is
performed by setting the flash memory reset bit.
(Writing of “1” → Writing of “0”) (Note 2)
Writing of “0” to the CPU reprogramming mode
select bit.
(Only in the boot mode.)
Writing of “0” to user ROM area select bit (Note 3).
Completed
Notes 1: The processor mode register 1’s bit 7 (address 5F16, the
internal ROM bus cycle select bit) must be “0” (bus cycle
= 3φ).
2: To terminate the CPU reprogramming mode after the
erase and programming operations have been
completed, be sure to execute the read array command
or perform the flash memory reset operation.
3: This bit may remain “1”. However, if this bit is “1”, the
user ROM area access is specified.
Fig. 8 CPU reprogramming mode set/termination flowchart
This command clears two status bits (SR.4, 5) each of which is set
to “1” to indicate that the operation has been terminated by an error.
To clear these bits, write command code “5016” at the 1st bus cycle.
Programming Command (4016)
This command facilitates programming of 1 word (2 bytes) at a time.
To initiate programming, write command code “4016” at the 1st bus
cycle; when write data is written in a unit of 16 bits at the 2nd bus
cycle, the address is specified at the same time. Upon completion of
data writing, automatic programming (data programming and verification) operation is started.
The completion of the automatic programming operation is confirmed by a read of the flash memory control register. The RY/BY status bit of the flash memory control register goes “0” during the
automatic programming operation; and also, it goes “1” after the
end of it.
Before execution of the next command, be sure to confirm that the
RY/BY status bit is set to “1” (READY). During the automatic programming operation, writing of commands and access to the flash
memory must not be performed.
When programming continuously, the programming command can
be executed with the read status register mode kept if there is no
programming error. Simultaneously with start of the automatic programming, the read status register mode is automatically active. In
this case, the read status register mode is retained until the next read
array command (FF16) is written or until the reset is performed by
using the flash memory reset bit.
Reading out the status register after the automatic programming operation is completed reports the result of it. For details, refer to the
section on the status register.
Figure 9 shows an example of the programming flowchart.
Additional programming to any word that has already been programmed is prohibited.
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16-BIT CMOS MICROCOMPUTER
Table 2. Software commands (CPU reprogramming mode)
1st cycle
Command
2nd cycle
Mode
Address
Data
(D0 to D7)
Read Array
Write
X (Note 2)
Read Status Register
Write
X
Clear Status Register
Write
X
5016
—
Programming
Block Erase
Write
X
4016
Write
Write
X
2016
Write
Erase All Block
Write
X
2016
Write
Mode
Address
Data
FF16
—
7016
Read
—
X
SRD (Note 3)
—
—
WA (Note 4) WD (Note 4)
BA (Note 5)
D016
X
Notes 1: At software commands’ input, the high-order byte of data (D8–D15) is ignored.
2: X = An arbitrary address in the user ROM area. (Note that A0 = “0”.)
3: SRD = Status Register Data
4: WA = Write Address, WD = Write Data (16 bits).
5: Block address: the maximum address of each block must be input. Note that address A0 = “0”.
Block Erase Command (2016/D016)
Writing command code “2016” at the 1st bus cycle and writing confirmation command code “D016” and the maximum address of the
block (Note that address A0 = “0”.) at the subsequent 2nd bus cycle
initiate the automatic erase (erasing and erase verification) operation
for the specified block.
The completion of the automatic erase operation is confirmed by a
read of the flash memory control register. The RY/BY status bit of the
flash memory control register goes “0” simultaneously with start of
the automatic erase operation; and also, it goes “1” simultaneously
with completion of it.
Before execution of the next command, be sure to confirm that the
RY/BY status bit is set to “1” (READY). During the automatic erase
operation, writing of commands and access to the flash memory
must not be performed.
Simultaneously with start of the automatic erase, the read status register mode is automatically active. In this case, the read status register mode is retained until the next read array command (FF16) is
written or until the reset is performed by using the flash memory reset bit.
Reading out the status register after the automatic erase operation
is completed reports the result of it. For details, refer to the section
on the status register.
Figure 10 shows an example of the block erase flowchart.
20
—
2016
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16-BIT CMOS MICROCOMPUTER
Erase All Block Command (2016/2016)
Writing command code “2016” at the 1st bus cycle and writing command code “2016” at the subsequent 2nd bus cycle initiate the continuous block erase (chip erase) operations for all the blocks.
The completion of the chip erase operation, as well as of the block
erase operation, is confirmed by a read of the flash memory control
register. The result of the automatic erase operation is also reported
by a read of the status register.
During the automatic erase operation (when the RY/BY status bit =
“0”), writing of commands and access to the flash memory must not
be performed.
Start
Write 4016
Write,
Address, Data
Flash memory control
register Read
RY/BY Status
Bit = 1?
NO
Status Register
The status register is used to indicate whether the programming/
erase operation has been completed normally or terminated by an
error. By writing the read status register command (7016), the contents of the status register can be read out; by writing the clear status register command (5016), the contents of the status register can
be cleared.
Table 3 lists the definition of each bit of the status register.
The status register outputs “8016” after reset is removed.
The status of each bit is described below.
YES
Full status check
Programming
Completed
Fig. 9 Programming flowchart
Start
Write 2016
Write D016,
Block address
Flash memory control
register Read
RY/BY Status
Bit = 1?
NO
YES
Full status check
Block erase Completed
Fig. 10 Block erase flowchart
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16-BIT CMOS MICROCOMPUTER
Erase Status Bit (SR.5)
This bit reports the status of the automatic erase operation. This bit
is set to “1” if an erase error occurs and returns to “0” if the clear status register command (5016) is written.
(1) when data other than “D016” and “FF16” is written to the data in
the 2nd bus cycle of the block erase command (2016/D016)
(2) when data other than “2016” and “FF16” is written to the data in
the 2nd bus cycle of the erase all block command
(2016/2016)
Programming Status Bit (SR.4)
This bit reports the status of the automatic programming operation.
This bit is set to “1” if a programming error occurs and returns to “0”
if the clear status register command (5016) is written.
Under the condition that any of SR.5, SR.4 = “1”, none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear
status register command (5016), in advance, to clear these status
bits.
Both of SR.4, SR.5 are set to “1” under the following conditions
(Command Sequence Error):
Note that, writing of “FF16” forces the microcomputer into the read
array mode. Simultaneously with this, the command written in the 1st
bus cycle will be canceled.
Full Status Check
The full status check reports the results of the erase or programming
operation.
Figure 11 shows the full status check flowchart and actions to be
taken if an error has occurred.
Table 3. Bit definition of status register
Status
Symbol
22
SR.7 (D7)
Reserved
SR.6 (D6)
Reserved
SR.5 (D5)
SR.4 (D4)
Erase Status
Programming Status
SR.3 (D3)
Reserved
SR.2 (D2)
Reserved
SR.1 (D1)
Reserved
SR.0 (D0)
Reserved
Definition
“1”
“0”
Terminated by error.
Terminated normally.
Terminated normally.
Terminated by error.
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16-BIT CMOS MICROCOMPUTER
Status Register Read
SR.4 = 1
and
SR.5 = 1
?
YES
Command Sequence
Error
➀ Execute the clear status register command (5016) to clear the status register.
➁ Confirm whether the command has correctly been input or not; and then,
start the operation again.
NO
NO
SR.5 = 0?
Block Erase Error
Perform the block erase operation again.
If an error occurs even after the above operation is performed, the block cannot be used.
Programming Error
Perform the programming operation again.
If an error occurs even after the above operation is performed, the word cannot be used.
YES
NO
SR.4 = 0?
YES
End
(Block erase, Programming)
Note: Under the condition that any of SR.5 and SR.4 = 1 , none of the programming,
block erase, and erase all block commands can be accepted. Before execution
of these commands, execute the clear status register command (5016) in advance.
Fig. 11 Full status check flowchart and actions to be taken if an error has ocurred
DC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note))
Parameter
Symbol
Icc1
Icc2
Icc3
Icc4
Min.
VCC power source current (at read)
VCC power source current (at write)
VCC power source current (at programming)
VCC power source current (at erasing)
Limits
Typ.
30
Max.
48
48
54
54
Unit
mA
mA
mA
mA
Limits of VIH, VIL, VOH, VOL, IIH, and IIL for each pin are the same as those in the microcomputer mode.
Note: f(fsys) indicates the system clcok (fsys) frequency.
AC Electrical Characteristics (VCC = 5 V ± 0.5 V, Ta = 0 to 60 °C, f(fsys) = 20 MHz (Note))
Parameter
Min.
256-byte programming time
Block erase time
Erase all block time
Limits
Typ.
4
0.6
0.6 ✕ n
Max.
40
8
8✕n
Unit
ms
s
s
n = Number of blocks to be erased
The limits of parameters other than the above are same as those in the microcomputer mode.
Note: f(fsys) indicates the system clock (fsys) frequency.
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16-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Ratings
Unit
VCC
Power source voltage
–0.3 to 6.5
V
AVCC
Analog power source voltage
–0.3 to 6.5
V
VI
Input voltage
P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, VCONT, VREF,
XIN, RESET, MD0, MD1
–0.3 to VCC+0.3
V
VO
Output voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67,
–0.3 to VCC+0.3
V
300
Parameter
Symbol
P70–P77, P80–P83, XOUT
Pd
Topr
Tstg
Power dissipation
Operating ambient temperature
–20 to 85
mW
°C
Storage temperature
–40 to 150
°C
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
VCC
Power source voltage
AVCC
Analog power source voltage
VSS
AVSS
VIH
Min.
4.5
Typ.
Max.
5.0
5.5
Unit
V
VCC
V
Power source voltage
0
V
Analog power source voltage
High-level Input voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET,
MD0, MD1
0
V
0.8 Vcc
Vcc
V
0
0.2 VCC
V
VIL
Low-level Input voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83, P4OUTCUT, P6OUTCUT, XIN, RESET,
MD0, MD1
IOH(peak)
High-level peak output current
P10–P17, P20–P27, P55–P57, P60–P67, P70–P77
–10
mA
IOH(avg)
High-level average output current P10–P17, P20–P27, P55–P57, P60–P67, P70–P77
–5
mA
IOL(peak)
Low-level peak output current
P10–P17, P20–P27, P51–P53, P55–P57, P70–P77
10
mA
IOL(peak)
20
mA
IOL(avg)
Low-level peak output current
P40–P47, P60–P67
Low-level average output current P10–P17, P20–P27, P51–P53, P55–P57, P70–P77
5
mA
IOL(avg)
Low-level average output current P40–P47, P60–P67
f(XIN)
f(fsys)
External clock input frequency (Note 1)
15
20
MHz
System clock frequency
20
MHz
Notes 1: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less.
2: Average output current is the average value of an interval of 100 ms.
3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less.
24
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16-BIT CMOS MICROCOMPUTER
DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz)
Symbol
VOH
VOL
Parameter
High-level output voltage P10–P17, P20–P27, P40–P47,
P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83
Low-level output voltage P10–P17, P20–P27, P40–P47,
P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83
VT+ —VT– Hysteresis
Test conditions
IOH = –10 mA
Min.
Limits
Typ.
Max.
Unit
V
3
IOL = 10 mA
2
V
TA0IN–TA9IN, TA0OUT–TA9OUT,
TB0IN–TB2IN, INT0–INT7, CTS0, CTS1,
CTS2, CLK0, CLK1, CLK2, RxD0, RxD1,
RxD2, RTPTRG0, RTPTRG1, P4OUTCUT,
P6OUTCUT
0.4
1
V
VT+ —VT– Hysteresis RESET
VT+ —VT– Hysteresis XIN
IIH
High-level input current P10–P17, P20–P27, P40–P47,
P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83, P4OUTCUT,
P6OUTCUT, XIN, RESET, MD0,
MD1
0.5
1.5
V
0.1
0.3
IIL
Low-level input current P10–P17, P20–P27, P40–P47,
P51–P53, P55–P57, P60–P67,
P70–P77, P80–P83, P4OUTCUT,
P6OUTCUT, XIN, RESET, MD0,
MD1
VRAM
RAM hold voltage
ICC
Power source current
VI = 5.0 V
5
V
µA
VI = 0 V
–5
µA
50
mA
Ta = 25 °C when
clock is inactive.
1
µA
Ta = 85 °C when
clock is inactive.
20
When clock is stoped.
Output-only pins
are open, and the
other pins are connected to Vss or
Vcc. An external
square-waveform
clock is input. (Pin
XOUT is open.) The
PLL frequency
multiplier is inactive.
f(fsys) = 20 MHz.
CPU is active.
V
2
25
25
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16-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
—————
Parameter
Resolution
Test conditions
VREF = VCC
—————
Absolute accuracy
VREF = VCC
RLADDER
Ladder resistance
VREF = VCC
tCONV
Conversion time
VREF
Reference voltage
VIA
Analog input voltage
f(fsys) ≤ 20 MHz
Limits
Min.
Typ.
10
A-D converter
Comparator
Unit
Bits
1
VREF V
256
±3
LSB
±2
LSB
± 40
mV
kΩ
10-bit resolution mode
8-bit resolution mode
Comparater
10-bit resolution mode
8-bit resolution mode
Comparater
Max.
5
5.9
µs
2.45 (Note)
0.7 (Note)
2.7
VCC
0
VREF
V
V
Note: This is applied when A-D conversion freguency (φAD) = f1 (φ).
D-A CONVERTER CHARACTERISTICS
(VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Test conditions
Parameter
——
Resolution
——
Absolute accuracy
tsu
Set time
RO
Output resistance
IVREF
Reference power source input current
Min.
Limits
Typ.
Max.
8
Bits
± 1.0
%
µs
kΩ
mA
3
2
3.5
(Note)
Unit
4.5
3.2
Note: The test conditions are as follows:
• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded.
RESET INPUT
Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tw(RESETL)
Parameter
RESET input low-level pulse width
RESET input
tw(RESETL)
26
Min.
10
Limits
Typ.
Max.
Unit
µs
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16-BIT CMOS MICROCOMPUTER
PERIPHERAL DEVICE INPUT/OUTPUT TIMING
(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted)
For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ).
∗
Timer A input (Count input in event counter mode)
Symbol
Limits
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
80
ns
tw(TAH)
TAiIN input high-level pulse width
40
ns
tw(TAL)
TAiIN input low-level pulse width
40
ns
Timer A input (Gating input in timer mode)
Symbol
Limits
Parameter
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
f(fsys) ≤ 20 MHz
16 ×
f(fsys)
(800)
ns
tw(TAH)
TAiIN input high-level pulse width
f(fsys) ≤ 20 MHz
8 × 109
f(fsys)
(400)
ns
tw(TAL)
TAiIN input low-level pulse width
f(fsys) ≤ 20 MHz
8 × 109
f(fsys)
(400)
ns
109
Note : The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.
Timer A input (External trigger input in one-shot pulse mode)
Symbol
Limits
Parameter
Min.
f(fsys) ≤ 20 MHz
8×
f(fsys)
109
Max.
Unit
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input high-level pulse width
80
ns
tw(TAL)
TAiIN input low-level pulse width
80
ns
ns
(400)
Timer A input (External trigger input in pulse width modulation mode)
Symbol
Parameter
Limits
Min.
Max.
Unit
tw(TAH)
TAiIN input high-level pulse width
80
ns
tw(TAL)
TAiIN input low-level pulse width
80
ns
Timer A input (Up-down input and Count input in event counter mode)
Symbol
Parameter
Limits
Min.
Max.
Unit
tc(UP)
tw(UPH)
TAiOUT input cycle time
TAiOUT input high-level pulse width
2000
1000
ns
ns
tw(UPL)
TAiOUT input low-level pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
27
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16-BIT CMOS MICROCOMPUTER
Timer A input (Two-phase pulse input in event counter mode)
Symbol
Limits
Parameter
Min.
Max.
Unit
tc(TA)
TAjIN input cycle time
800
ns
tsu(TAjIN-TAjOUT)
TAjIN input setup time
200
ns
tsu(TAjOUT-TAjIN)
TAjOUT input setup time
200
ns
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
• Up-down and Count input in event counter mode
tc(UP)
tw(UPH)
TAiOUT input
(Up-down input)
tw(UPL)
TAiOUT input
(Up-down input)
TAiIN input
(When count by falling)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count by rising)
• Two-phase pulse input in event counter mode
tc(TA)
TAjIN input
tsu(TAjIN-TAjOUT)
tsu(TAjIN-TAjOUT)
tsu(TAjOUT-TAjIN)
TAjOUT input
tsu(TAjOUT-TAjIN)
Test conditions
• VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
28
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16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
Limits
Parameter
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (one edge count)
80
ns
tw(TBH)
TBiIN input high-level pulse width (one edge count)
40
ns
tw(TBL)
TBiIN input low-level pulse width (one edge count)
40
ns
tc(TB)
TBiIN input cycle time (both edge count)
160
ns
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
80
80
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
Limits
Parameter
TBiIN input cycle time
Min.
Unit
Max.
f(fsys) ≤ 20 MHz
16 ×
f(fsys)
(800)
ns
109
tw(TBH)
TBiIN input high-level pulse width
f(fsys) ≤ 20 MHz
8×
f(fsys)
(400)
ns
tw(TBL)
TBiIN input low-level pulse width
f(fsys) ≤ 20 MHz
8 × 109
f(fsys)
(400)
ns
109
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.
Timer B input (Pulse width measurement mode)
Symbol
tc(TB)
Limits
Parameter
TBiIN input cycle time
Min.
Unit
Max.
f(fsys) ≤ 20 MHz
16 ×
f(fsys)
(800)
ns
109
tw(TBH)
TBiIN input high-level pulse width
f(fsys) ≤ 20 MHz
8×
f(fsys)
(400)
ns
tw(TBL)
TBiIN input low-level pulse width
f(fsys) ≤ 20 MHz
8 × 109
f(fsys)
(400)
ns
109
Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz.
Serial I/O
Symbol
Parameter
Limits
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high-level pulse width
100
ns
tw(CKL)
td(C-Q)
CLKi input low-level pulse width
TXDi output delay time
100
th(C-Q)
TXDi hold time
0
ns
tsu(D-C)
RXDi input setup time
20
ns
th(C-D)
RXDi input hold time
90
ns
80
ns
ns
29
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16-BIT CMOS MICROCOMPUTER
External interrupt (INTi) input
Symbol
Limits
Parameter
Min.
Max.
Unit
tw(INH)
INTi input high-level pulse width
250
ns
tw(INL)
INTi input low-level pulse width
250
ns
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(CK)
tw(CKH)
CLKi input
tw(CKL)
th(C-Q)
TxDi output
td(C-Q)
tsu(D-C)
RxDi input
tw(INL)
INTi input
tw(INH)
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF
30
th(C-D)
A
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16-BIT CMOS MICROCOMPUTER
External clock input
Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
Max.
Unit
ns
50
tc
External clock input cycle time
tw(half)
External clock input pulse width with half input-voltage
0.45 tc
tw(H)
External clock input high-level pulse width
0.5 tc – 8
tw(L)
External clock input low-level pulse width
0.5 tc – 8
tr
External clock input rise time
8
ns
tf
External clock input fall time
8
ns
External clock input
tw(L)
tw(H)
tr
tf
0.55 tc
ns
ns
ns
tc
tw(half)
XIN
Test conditions
• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage
: VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 2.5 V (tc, tw(half))
31
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16-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
64P6N-A
Plastic 64pin 14✕14mm body QFP
EIAJ Package Code
QFP64-P-1414-0.80
Weight(g)
1.11
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
64
b2
ME
D
49
1
I2
48
Recommended Mount Pad
HE
E
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
33
16
A
32
L1
c
A2
17
b
x
A1
F
e
M
y
b2
I2
MD
ME
L
Detail F
MMP
64P4B
JEDEC Code
–
Plastic 64pin 750mil SDIP
Weight(g)
7.9
Lead Material
Alloy 42/Cu Alloy
33
1
32
E
64
e1
c
EIAJ Package Code
SDIP64-P-750-1.78
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0
0.1
0.2
2.8
–
–
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
13.8
14.0
14.2
0.8
–
–
16.5
16.8
17.1
16.5
16.8
17.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
0°
10°
–
–
–
0.5
1.3
–
–
14.6
–
–
14.6
–
–
Symbol
A1
L
A
A2
D
e
SEATING PLANE
32
b1
b
b2
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
Dimension in Millimeters
Min
Nom
Max
–
–
5.08
0.38
–
–
–
3.8
–
0.4
0.5
0.59
0.9
1.0
1.3
0.65
0.75
1.05
0.2
0.25
0.32
56.2
56.4
56.6
16.85
17.0
17.15
–
1.778
–
–
19.05
–
2.8
–
–
0°
–
15°
A
IMIN
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MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit
application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to
change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these
inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making
a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
•
© 2001 MITSUBISHI ELECTRIC CORP.
New publication, effective May., 2001.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
M37905F8CFP, M37905F8CSP DATASHEET
Date
Description
Page
1.0
5/28/01
—
Summary
First Edition
(1/1)