Austin AS8nvC512K32QC-20XT 512k x 32 module nvsram 5.0v high speed sram with non-volatile storage Datasheet

AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
AVAILABLE AS MILITARY
SPECIFICATIONS
512K x 32 Module nvSRAM
5.0V High Speed SRAM with
Non-Volatile Storage
• Military Processing (MIL-STD-883C para 1.2.2)
• Temperature Range -55C to 125C
FEATURES
• -55oC to 125oC Operation
• True non-volatile SRAM (no batteries)
• 20 ns, 25 ns, and 45 ns access times
• Automatic STORE on power down with only a small
•
•
•
•
•
•
•
nvSRAM
FUNCTIONAL DESCRIPTION
The Austin Semiconductor AS8nvC512K32 is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits for each of 4 die to form 512Kx32.
The embedded nonvolatile elements incorporate QuantumTrap
technology, producing the world’s most reliable nonvolatile memory.
The SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
capacitor
STORE to QuantumTrap® nonvolatile elements initiated by
software, device pin, or AutoStore® on power down
RECALL to SRAM initiated by software or power up
Infinite Read, Write, and Recall cycles
200,000 STORE cycles to QuantumTrap
20 year data retention
Single 5.0V ±10% power supply
Ceramic Hermetic 68 Quad Flatpak
-Can order with X7R CAPS on package
-Matches compatible pinout footprint of SRAM & EEPROM
Module
LOGIC BLOCK DIAGRAM
m[1, 2, 3]
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AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
PIN ASSIGNMENT
(Top View)
MILITARY PINOUT/BLOCK DIAGRAM
M4
CS
VCAP 1
68 Lead CQFP (Q)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
M3
CS
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
M2
CS
CS
M1
Vcc
A11
A12
A13
A14
A15
A16
CS1\
OE\
CS2\
A17
WE2\
WE3\
WE4\
A18
NC
HSB\
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
VCAP
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
Vcc
HSB 2
Notes:
1. This pin left open if ordered with capacitors already mounted in
package.
2. HSB\ signal is wired to all 4 die in module. This can be left open if
not used.
PinName
A0–A18
A0–A17
DQ0–DQ7
DQ0–DQ15
DQ16ͲDQ23
DQ24ͲDQ31
I/OType
Input
Input/Output BidirectionalDataI/OLinesfordieM1(DQ0Ͳ7),M2(DQ8Ͳ15),M3(DQ16Ͳ23),M4(DQ24Ͳ31)
WE\1Ͳ4
Input
CE\1Ͳ4
Input
OE\
Input
VSS
VCC
HSB\
VCAP
NC
AS8nvC512K32
Rev. 0.0 08/09
Description
AddressInputsUsedtoSelectoneofthe524,288bytesofthenvSRAMforx8Configuration.
AddressInputsUsedtoSelectoneofthe262,144wordsofthenvSRAMforx16Configuration.
Ground
WriteEnableInput,ActiveLOW.WhenselectedLOW,dataontheI/Opinsiswrittentothespecific
addresslocation.
ChipEnableInput,ActiveLOW.WhenLOW,selectsthechip.WhenHIGH,deselectsthechip.
OutputEnable,ActiveLOW.TheactiveLOWOEinputenablesthedataoutputbuffersduringreadcycles.
I/OpinsaretriͲstatedondeassertingOEHIGH.
GroundfortheDevice.Mustbeconnectedtothegroundofthesystem.
PowerSupply PowerSupplyInputstotheDevice.
HardwareStoreBusy(HSB\).WhenLOWthisoutputindicatesthatahardwarestoreisinprogress.When
pulledLOWexternaltothechipitinitiatesanonvolatileSTOREoperation.Aweakinternalpullupresistor
Input/Output
keepsthispinHIGHifnotconnected(connectionoptional).AftereachstoreoperationHSB\isdriven
HIGHforshorttimewithstandardoutputhighcurrent.
AutoStoreCapacitor.SuppliespowertothenvSRAMduringpowerlosstostoredatafromSRAMto
PowerSupply
nonvolatileelements.(leavepinopenifcapsmountedonpackage)
NoConnect NoConnect.Thispinisnotconnectedtothedie.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
for automatic store operation. Refer to DC Electrical Characteristics
for the size of VCAP. The voltage on the VCAP pin is driven to VCC
by a regulator on the chip. A pull up should be placed on WE\ to hold
it inactive during power up. This pull up is effective only if the WE\
signal is tri-state during power up. Many MPUs tri-state their
controls on power up. This should be verified when using the pull
up. When the nvSRAM comes out of power-on-recall, the MPU
must be active or the WE\ held inactive until the MPU comes out of
reset.
Device Operation
The AS8nvC512K32 nvSRAM is made up of two functional
components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE operation),
or from the nonvolatile cell to the SRAM (the RECALL operation).
Using this unique architecture, all cells are stored and recalled in
parallel. During the STORE and RECALL operations, SRAM read
and write operations are inhibited. The AS8nvC512K32 supports
infinite reads and writes similar to a typical SRAM. In addition, it
provides infinite RECALL operations from the nonvolatile cells and
up to 200K STORE operations. See the Truth Table For SRAM
Operations for a complete description of read and write modes.
To reduce unnecessary nonvolatile stores, AutoStore and hardware
store operations are ignored unless at least one write operation has
taken place since the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of whether a write
operation has taken place. The HSB\ signal is monitored by the
system to detect if an AutoStore cycle is in progress.
Figure 2. AutoStore Mode
SRAM Read
The AS8nvC512K32 performs a read cycle when CE\ and OE\ are
LOW and WE\ and HSB\ are HIGH. The address specified on pins
A0-18 determines which of the 524,288 data bytes. When the read is
initiated by an address transition, the outputs are valid after a delay
of tAA (read cycle 1). If the read is initiated by CE\ or OE\, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The data
output repeatedly responds to address changes within the tAA access
time without the need for transitions on any control input pins. This
remains valid until another address change or until CE\ or OE\ is
brought HIGH, or WE\ or HSB\ is brought LOW.
Vcc
10kOhm
0.1uF
WE1-4
VCAP
VSS
SRAM Write
A write cycle is performed when CE\ and WE\ are LOW and HSB\ is
HIGH. The address inputs must be stable before entering the write
cycle and must remain stable until CE\ or WE\ goes HIGH at the end
of the cycle. The data on the common I/O pins DQ0–31 are written
into the memory if the data is valid tSD before the end of a WE\
controlled write or before the end of an CE\ controlled write. It is
recommended that OE\ be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE\ is left LOW,
internal circuitry turns off the output buffers tHZWE after WE\ goes
LOW.
VCAP
Hardware STORE Operation
The AS8nvC512K32 provides the HSB\ 6 pin to control and
acknowledge the STORE operations. Use the HSB\ pin to request a
hardware STORE cycle. When the HSB pin is driven LOW, the
AS8nvC512K32 conditionally initiates a STORE operation after tDELAY.
An actual STORE cycle only begins if a write to the SRAM has taken
place since the last STORE or RECALL cycle. The HSB\ pin also
acts as an open drain driver that is internally driven LOW to indicate
a busy condition when the STORE (initiated by any means) is in
progress.
AutoStore Operation
The AS8nvC512K32 stores data to the nvSRAM using one of the
following three storage operations: Hardware Store activated by HSB\;
Software Store activated by an address sequence; AutoStore on device
power down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
AS8nvC512K32.
SRAM read and write operations that are in progress when HSB is
driven LOW by any means are given time to complete before the
STORE operation is initiated. After HSB\ goes LOW, the
AS8nvC512K32 continues SRAM operations for tDELAY. If a write
is in progress when HSB\ is pulled LOW it is enabled a time, tDELAY to
complete. However, any SRAM write cycles requested after HSB\
goes LOW are inhibited until HSB\ returns HIGH. In case the write
latch is not set, HSB\ is not driven LOW by the AS8nvC512K32. But
any SRAM read and write cycles are inhibited until HSB\ is returned
HIGH by MPU or other external source.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored charge is
used by the chip to perform a single STORE operation. If the voltage
on the VCC pin drops below VSWITCH, the part automatically disconnects
the VCAP pin from VCC. A STORE operation is initiated with power
provided by the VCAP capacitor.
During any STORE operation, regardless of how it is initiated, the
AS8nvC512K32 continues to drive the HSB\ pin LOW, releasing it
only when the STORE is complete. When the STORE operation is
completed, the AS8nvC512K32 remains disabled until the HSB\ pin
returns HIGH. Leave the HSB\ unconnected if it is not used..
Figure 2 shows the proper connection of the storage capacitor (VCAP)
AS8nvC512K32
Rev. 0.0 08/09
Vcc
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
Hardware RECALL (Power Up)
AS8nvC512K32
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled. HSB
is driven LOW. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW for a
valid sequence. After the tSTORE cycle time is fulfilled, the SRAM
is activated again for the read and write operation.
During power up or after any low power condition (VCC<
VSWITCH), an internal RECALL request is latched. When VCC
again exceeds the sense voltage of VSWITCH, a RECALL cycle is
automatically initiated and takes tHRECALL to complete. During
this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The AS8nvC512K32 software STORE
cycle is initiated by executing sequential CE controlled read cycles
from six specific address locations in exact order. During the STORE
cycle an erase of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements. After a STORE
cycle is initiated, further input and output are disabled until the
cycle is completed.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is initiated
with a sequence of read operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the following
sequence of CE controlled read operations must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation does
not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used for
STORE initiation, it is important that no other read or write accesses
intervene in the sequence, or the sequence is aborted and no STORE
or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
Mode Selection
CE\1Ͳ4
WE\1Ͳ4
OE\13
A15ͲA07
H
L
L
X
H
L
X
L
X
X
X
X
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Mode
NotSelected
ReadSRAM
WriteSRAM
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
AutoStore
Disable
I/O0Ͳ31
OutputHighZ
OutputData
InputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
Power
Standby
Active
Active
Active8
Notes
7. While there are 19 address lines on the AS8nvC512K32, only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address
lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
13.WE\ must be HIGH during SRAM read cycles.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
AS8nvC512K32
Mode Selection (continued)
OE\
CE\1Ͳ4
WE\1Ͳ4
L
H
L
L
H
L
L
H
L
13
A15ͲA0
7
Mode
I/O0Ͳ31
Power
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
AutoStoreEnable
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
NonvolatileStore
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputData
OutputHighZ
Active8
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
ReadSRAM
Nonvolatile
Recall
OutputData
OutputData
OutputData
OutputData
OutputData
OutputHighZ
ActiveICC28
Active8
Preventing AutoStore
Data Protection
The AutoStore function is disabled by initiating an AutoStore disable
sequence. A sequence of read operations is performed in a manner
similar to the software STORE initiation. To initiate the AutoStore
disable sequence, the following sequence of CE controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a manner
similar to the software RECALL initiation. To initiate the AutoStore
enable sequence, the following sequence of CE controlled read
operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual STORE
operation (hardware or software) must be issued to save the AutoStore
state through subsequent power down cycles. The part comes from
the factory with AutoStore enabled.
The AS8nvC512K32 protects data from corruption during low voltage
conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is detected
when VCC < VSWITCH. If the AS8nvC512K32 is in a write mode
(both CE and WE are LOW) at power up, after a RECALL or STORE,
the write is inhibited until the SRAM is enabled after tLZHSB (HSB
to output active). This protects against inadvertent writes during
power up or brown out conditions.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
Best Practices
„ Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard against
events that might flip the bit inadvertently such as program bugs
and incoming inspection routines.
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has resulted
in the following suggestions as best practices:
„ The nonvolatile cells in this nvSRAM product are delivered from
Austin Semiconductor with 0x00 written in all cells. Incoming
inspection routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are typically
repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s
firmware should not assume an NV array is in a set programmed
state. Routines that check memory content values to determine
first time system configuration, cold or warm boot status, and so
on should always program a unique NV pattern (that is, complex
4-byte pattern of 46 E6 49 53 hex or more random bytes) as part
of the final system manufacturing test to ensure these system
routines work consistently.
AS8nvC512K32
Rev. 0.0 08/09
„ The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this requirement
and not exceed the maximum VCAP value because the nvSRAM
internal algorithm calculates VCAP charge and discharge time based
on this max VCAP value. Customers that want to use a larger VCAP
value to make sure there is extra store charge and store time should
discuss their VCAP size selection with Austin Semiconductor to
understand any impact on the VCAP voltage level at the end of a
tRECALL period.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
nvSRAM
AS8nvC512K32
Austin Semiconductor, Inc.
Any Pin to Ground Potential............................–2.0V to Vcc + 2.0V
Package Power Dissipation
Capability (TA = 25°C) ...........................................................1.0W
Surface Mount Pb Soldering
Temperature (3 Seconds)......................................................+260°C
DC Output Current (1 output at a time, 1s duration) ..............15 mA
Static Discharge Voltage .................................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current............................................................. > 200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .............................................–65°C to +150°C
Maximum Accumulated Storage Time
At 150°C Ambient Temperature...............................1000h
At 85°C Ambient Temperature.............................20 Years
Ambient Temperature with
Power Applied ......................................................–55°C to +125°C
Supply Voltage on Vcc Relative to GND................... –0.5V to 6.0V
Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to Vcc + 0.5V
Input Voltage .................................................. –0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Operating Range
Range
AmbientTemperature
Vcc
o
o
Ͳ55 Cto+125 C
5.0V±10%
Military
o
o
5.0V±10%
Industrial Ͳ40 Cto+85 C
DC Electrical Characteristics
Over the Operating Range (VCC = 5.0V ±10%)
Description
Parameter
AverageVCCCurrent
ICC1
TestConditions
tRC=20ns
tRC=25ns
tRC=45ns
Valuesobtainedwithoutoutputloads(IOUT=0mA)
Military
Industrial
AverageVCCCurrent
duringSTORE
ICC2
ICC4
AverageVccCurrentat
tRC=200ns,5V,25°C
typical
AverageVCAPCurrent
duringAutoStoreCycle
ISB
VCCStandbyCurrent
IIX10
InputLeakageCurrent
(exceptHSB\)
InputLeakageCurrent
(forHSB\)
ICC39
Min Max
450
400
350
350
325
275
Unit
mA
mA
mA
mA
mA
mA
AllInputsDon’tCare,VCC=Max
AveragecurrentfordurationtSTORE
60
AllI/PcyclingatCMOSlevels.
Valuesobtainedwithoutoutputloads(IOUT=0mA).
220 mA
AllInputsDon’tCare,VCC=Max
AveragecurrentfordurationtSTORE
40
mA
CE\ш(VCC–0.2V).AllothersVINч0.2Vorш(VCC–0.2V).Standby
currentlevelafternonvolatilecycleiscomplete.
Inputsarestatic.f=0MHz.
40
mA
5
μA
VCC=Max,VSSчVINчVCC
Ͳ400 10
μA
VCC=Max,VSSчVOUTчVCC,CE\orOE\шVIHorBHE\/BLE\шVIH
orWE\чVIL
Ͳ10
μA
VCC=Max,VSSчVINчVCC
Ͳ5
mA
IOZ
OffͲStateOutput
LeakageCurrent
VIH
InputHIGHVoltage
2.2
VIL
InputLOWVoltage
VSSͲ
0.8
0.3
V
VOH
OutputHIGHVoltage
IOUT=–2mA
2.4
V
VOL
OutputLOWVoltage
IOUT=4mA
StorageCapacitor
BetweenVCAPpinandVSS,10.0VRated
VCAP
11
80
10
VCC +
V
0.3
0.45
V
180
μF
Notes
9. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and VCC = 5V. Not
100% tested.
10. The HSB\ pin has IOUT = -8 uA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are
valid. This parameter is characterized but not tested.
11. VCAP (storage capacitor) nominal value is 88 uF total cap.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
Data Retention and Endurance
Parameter
DATAR
Description
DataRetention
Min
20
Unit
Years
NVC
NonvolatileSTOREOperation
200
Cycles
Capacitance
In the following table, the capacitance parameters are listed. 12
Parameter
Description
CIN
InputCapacitance(Addr,OE\,HSB\)
CIN
InputCapacitance(CE\1Ͳ4,WE\1Ͳ4
COUT(DQ)
I/OCapacitance
TestConditions
TA=25°C,f=1MHz,
VCC=0to3.0V
Min
50
Unit
pF
20
pF
25
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed. 12
Parameter
ȺJA
ȺJC
Description
ThermalResistance
(JunctiontoAmbient)
ThermalResistance
(JunctiontoCase)
TestConditions
44ͲTSOPII
Testconditionsfollowstandardtestmethods
andproceduresformeasuringthermal
impedance,inaccordancewithEIA/JESD51.
44ͲGullwing Unit
TBD
TBD
o
TBD
TBD
o
C/W
C/W
AC Test Loads
577:
577:
5.0V
5.0V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
789:
5 pF
R2
789:
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
12. These parameters are guaranteed but not tested.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
AC Switching Characteristics
Parameters
AustinSemi
Alt
Parameters Parameters
Description
SRAMReadCycle
tACE
tACS
ChipEnableAccessTime
tRC13
tAA14
tRC
ReadCycleTime
tAA
AddressAccessTime
20ns
Min
25ns
Max
Min
20
20
tDOE
tOE
OutputEnabletoDataValid
tOH
OutputHoldAfterAddressChange
2
tLZCE12,15
tLZ
ChipEnabletoOutputActive
2
tHZCE12,15
tHZ
ChipDisabletoOutputActive
tLZOE12,15
tOLZ
OutputEnabletoOutputActive
tHZOE12,15
tOHZ
OutputDisabletoOutputInactive
tPU12
tPA
ChipEnabletoPowerActive
12
Max
Min
25
25
20
tOHA14
45ns
12
2
0
0
0
ns
45
ns
20
ns
ns
ns
2
10
8
45
2
2
8
Unit
45
25
10
Max
ns
15
ns
15
ns
0
10
0
ns
0
ns
tPD
tPS
ChipDisabletoPowerStandby
20
25
45
ns
tDBE
Ͳ
ByteEnabletoDataValid
10
12
20
ns
tLZBE12
Ͳ
ByteEnabletoOutputActive
15
ns
tHZBE12
Ͳ
SRAMWriteCycle
tWC
tWC
0
0
ByteDisabletoOutputInactive
8
0
10
ns
WriteCycleTime
20
25
45
ns
ns
tPWE
tWP
WritePulseWidth
15
20
30
tSCE
tCW
ChipEnabletoEndofWrite
15
20
30
ns
tSD
tDW
DataSetuptoEndofWrite
8
10
15
ns
tHD
tDH
DataHoldAfterEndofWrite
0
0
0
ns
tAW
tAW
AddressSetuptoEndofWrite
15
20
30
ns
tSA
tAS
AddressSetuptoEndofWrite
0
0
0
ns
tHA
tWR
AddressHoldAfterEndofWrite
0
tHZWE12,15,16
tLZWE12,15
tWZ
WriteEnabletoOutputDisable
tOW
OutputActiveafterEndofWrite
2
2
2
ns
tBW
Ͳ
ByteEnabletoEndofWrite
15
20
30
ns
0
8
0
10
ns
15
ns
Switching Waveforms
SRAM Read Cycle #1: Address Controlled 13, 14, 17
tRC
Address
Address Valid
tAA
Data Output
Output Data Valid
Previous Data Valid
tOHA
Notes
13.WE\ must be HIGH during SRAM read cycles.
14. Device is continuously selected with CE\, OE\ LOW.
15.Measured ±200 mV from steady state output voltage.
16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state.
17. HSB\ must remain HIGH during read and write cycles.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
nvSRAM
AS8nvC512K32
Austin Semiconductor, Inc.
SRAM Read Cycle #2: CE\ and OE\ Controlled 3, 13, 17
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
SRAM Write Cycle #1: WE\ Controlled 3, 16, 17,18
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
tSA
tSD
Data Input
Input Data Valid
tLZWE
tHZWE
Data Output
tHD
Previous Data
High Impedance
Note
18. CE\ or WE\ must be >VIH during address transitions.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
SRAM Write Cycle #2: CE\ Controlled3, 16, 17, 18
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Data Input
Data Output
AS8nvC512K32
Rev. 0.0 08/09
Input Data Valid
High Impedance
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
AutoStore/Power Up RECALL
20ns
Min
Max
20
Parameters
Description
19
tHRECALL
PowerUpRECALLDuration
tSTORE20
tDELAY
21
Unit
ms
10
10
10
ms
TimeAllowedtoCompleteSRAMCycle
20
25
25
ns
3.65
3.65
3.65
V
LowVoltageTriggerLevel
tVCCRISE
VCCRiseTime
VHDIS
45ns
Min
Max
20
STORECycleDuration
VSWITCH
12
25ns
Min
Max
20
150
HSB\OutputDriverDisableVoltage
tLZHSB
HSB\ToOutputActiveTime
tHHHD
HSB\HighActiveTime
150
150
μs
1.9
1.9
1.9
V
5
5
5
μs
500
500
500
ns
Switching Waveforms
AutoStore or Power Up RECALL22
VSWITCH
VHDIS
V VCCRISE
Note20
Note20
tSTORE
tHHHD
tSTORE
Note23
tHHHD
HSB OUT
tDELAY
tLZHSB
Autostore
tLZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
Autostore
POWER-UP
RECALL
Read & Write
POWER
DOWN
Autostore
Notes
19. tHRECALL starts from the time VCC rises above VSWITCH.
20. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
21. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be
enabled for time tDELAY.
22. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
23. HSB\ pin is driven HIGH to VCC only by internal 100 kOhm resistor, HSB\ driver is disabled.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
nvSRAM
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
AS8nvC512K32
Austin Semiconductor, Inc.
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.24, 25
Parameters
Description
tRC
STORE/RECALLInitiationCycleTime
20ns
Min
Max
20
25ns
Min
Max
25
45ns
Min
Max
45
Unit
ns
tSA
AddressSetupTime
0
0
0
ns
tCW
ClockPulseWidth
15
25
30
ns
tHA
AddressHoldTime
0
0
0
ns
tRECALL
RECALLDuration
200
200
200
μs
Switching Waveforms
CE\ and OE \Controlled Software STORE/RECALL Cycle25
W5&
$GGUHVV
W5&
$GGUHVV
W6$
$GGUHVV
W&:
W&:
&(
W+$
W6$
W+$
W+$
W+$
2(
W+++'
+6% 6725(RQO\
W+=&(
W/=&(
W'(/$<
W/=+6%
+LJK,PSHGDQFH
W6725(W5(&$//
'4 '$7$
5:,
g AutoStore
$GGUHVV
W6$
&(
Enable/Disable yCycle
W5&
W5&
$GGUHVV
$GGUHVV
W&:
W&:
W+$
W6$
W+$
W+$
W+$
2(
W/=&(
W66
W+=&(
W'(/$<
'4 '$7$
5:,
Notes
24. The software sequence is clocked with CE\ controlled or OE\ controlled reads.
25. The six consecutive addresses must be read in the order listed in the MODE Selection Table. WE\ must be HIGH during all six consecutive cycles.
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
Truth Table For SRAM Operations
HSB\ should remain HIGH for SRAM Operations.
Forx32Configuration
CE\1Ͳ4 WE\1Ͳ4
OE\
H
X
X
L
H
L
L
H
H
L
L
X
AS8nvC512K32
Rev. 0.0 08/09
Inputs/Outputs
HighZ
DataOut(DQ0ͲDQ31)
HighZ
DataIn(DQ0ͲDQ31)
Mode
Deselect/PowerDown
Read
OutputDisabled
Write
Power
Standby
Active
Active
Active
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
Ceramic 68 Quad Flatpak
AS8nvC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
Ordering Information
ASIPartNumber
AS8nvC512K32QCͲ20XT
AS8nvC512K32QCͲ25XT
AS8nvC512K32QCͲ45XT
AS8nvC512K32QͲ20XT
AS8nvC512K32QͲ25XT
AS8nvC512K32QͲ45XT
Configuration
512Kx32
512Kx32
512Kx32
512Kx32
512Kx32
512Kx32
PackageType Speed OperatingRange
68QuadFlatpak
20
XT
68QuadFlatpak
25
XT
68QuadFlatpak
45
XT
68QuadFlatpak
20
IT
68QuadFlatpak
25
IT
68QuadFlatpak
45
IT
QC=Capacitors&resistorsmountedonpackage
Q=Nocapacitororresistor
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Military Temperature Range
AS8nvC512K32
Rev. 0.0 08/09
Temperature
-40oC to +85oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
AUSTIN SEMICONDUCTOR,
INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
nvSRAM
AS8nvC512K32
DOCUMENT TITLE
512K x 32 nvSRAM 5.0V High Speed SRAM with Non-Volatile Storage
REVISION HISTORY
Rev #
0.0
AS8nvC512K32
Rev. 0.0 08/09
History
Document Creation
Release Date
August 2009
Status
Advance
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
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