AD AD8000YRDZ-REEL7 1.5 ghz ultrahigh speed op amp Datasheet

1.5 GHz Ultrahigh Speed Op Amp
AD8000
FEATURES
CONNECTION DIAGRAMS
High speed
1.5 GHz, −3 dB bandwidth (G = +1)
650 MHz, full power bandwidth (G = +2, VO = 2 V p-p)
Slew rate: 4100 V/µs
0.1% settling time: 12 ns
Excellent video specifications
0.1 dB flatness: 170 MHz
Differential gain: 0.02%
Differential phase: 0.01°
Output overdrive recovery: 22 ns
Low noise: 1.6 nV/√Hz input voltage noise
Low distortion over wide bandwidth
75 dBc SFDR @ 20 MHz
62 dBc SFDR @ 50 MHz
Input offset voltage: 1 mV typ
High output current: 100 mA
Wide supply voltage range: 4.5 V to 12 V
Supply current: 13.5 mA
Power-down mode
AD8000
POWER DOWN 1
8 +VS
FEEDBACK 2
7 OUTPUT
6 NC
+IN 4
5 –VS
05321-001
–IN 3
NC = NO CONNECT
Figure 1. 8-Lead AD8000, 3 mm × 3 mm LFCSP (CP-8-2)
AD8000
1
8
POWER DOWN
–IN
2
7
+VS
+IN
3
6
OUTPUT
–VS
4
5
NC
05321-002
FEEDBACK
NC = NO CONNECT
Figure 2. 8-Lead AD8000 SOIC/EP (RD-8-1)
APPLICATIONS
The AD8000 is an ultrahigh speed, high performance, current
feedback amplifier. Using ADI’s proprietary eXtra Fast Complementary Bipolar (XFCB) process, the amplifier can achieve a
small signal bandwidth of 1.5 GHz and a slew rate of 4100 V/µs.
VS = ±5V
RL = 150Ω
VOUT = 2V p-p
2
1
0
–1
–2
–3
G = +2, RF = 432Ω
–4
–5
05321-003
GENERAL DESCRIPTION
3
NORMALIZED GAIN (dB)
Professional video
High speed instrumentation
Video switching
IF/RF gain stage
CCD imaging
–6
The AD8000 has low spurious-free dynamic range (SFDR) of
75 dBc @ 20 MHz and input voltage noise of 1.6 nV/√Hz. The
AD8000 can drive over 100 mA of load current with minimal
distortion. The amplifier can operate on +5 V to ±6 V. These
specifications make the AD8000 ideal for a variety of applications, including high speed instrumentation.
With a differential gain of 0.02%, differential phase of 0.01°, and
0.1 dB flatness out to 170 MHz, the AD8000 has excellent video
specifications, which ensure that even the most demanding
video systems maintain excellent fidelity.
–7
1
10
100
1000
FREQUENCY (MHz)
Figure 3. Large Signal Frequency Response
The AD8000 power-down mode reduces the supply current to
1.3 mA. The amplifier is available in a tiny 8-lead LFCSP package, as well as in an 8-lead SOIC package. The AD8000 is rated
to work over the extended industrial temperature range (−40°C
to +125°C). A triple version of the AD8000 (AD8003) is underdevelopment.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
AD8000
TABLE OF CONTENTS
Specifications with ±5 V Supply ..................................................... 3
Video Line Driver....................................................................... 14
Specifications with +5 V Supply ..................................................... 4
Low Distortion Pinout............................................................... 15
Absolute Maximum Ratings............................................................ 5
Exposed Paddle........................................................................... 15
Thermal Resistance ...................................................................... 5
Printed Circuit Board Layout ................................................... 15
ESD Caution.................................................................................. 5
Signal Routing............................................................................. 15
Typical Performance Characteristics ............................................. 6
Power Supply Bypassing ............................................................ 15
Test Circuits..................................................................................... 13
Grounding ................................................................................... 16
Applications..................................................................................... 14
Outline Dimensions ....................................................................... 17
Circuit Configurations............................................................... 14
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/05—Rev. 0: Initial Version
Rev. 0 | Page 2 of 20
AD8000
SPECIFICATIONS WITH ±5 V SUPPLY
At TA = 25°C, VS = ±5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic
Second/Third Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current (Enabled)
Transimpedance
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Overdrive Recovery
POWER DOWN PIN
Power-Down Input Voltage
Turn-Off Time
Turn-On Time
Input Bias Current
Enabled
Power-Down
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Swing
Linear Output Current
Overdrive Recovery
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Power-Down)
Power Supply Rejection Ratio
Conditions
Min
Typ
Max
Unit
G = +1, VO = 0.2 V p-p, SOIC/LFCSP
G = +2, VO = 2 V p-p, SOIC/LFCSP
VO = 2 V p-p, SOIC/LFCSP
G = +2, VO = 4 V step
G = +2, VO = 2 V step
1580/1350
650/610
190/170
4100
12
MHz
MHz
MHz
V/µs
ns
VO = 2 V p-p, f = 5 MHz, LFCSP only
VO = 2 V p-p, f = 20 MHz, LFCSP only
f = 100 kHz
f = 100 kHz, −IN
f = 100 kHz, +IN
NTSC, G = +2
NTSC, G = +2
86/89
75/79
1.6
26
3.4
0.02
0.01
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
+IB
−IB
570
VCM = ±2.5 V
G = +1, f = 1 MHz, triangle wave
−52
Power-down
Enabled
50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
RL = 100 Ω
RL = 1 kΩ
VO = 2 V p-p, second HD < −50 dBc
G = + 2, f = 1 MHz, triangle wave
G = +2, VIN = 2.5 V to 0 V step
−PSRR/+PSRR
Rev. 0 | Page 3 of 20
1
11
−5
−3
890
2/3.6
−3.5 to +3.5
−54
30
+4
+45
1600
−56
mV
µV/°C
µA
µA
kΩ
MΩ/pF
V
dB
ns
< +VS – 3.1
> +VS – 1.9
150
V
V
ns
300
ns
−1.1
−300
+0.17
−235
±3.7
±3.9
±3.9
±4.1
100
45
22
4.5
12.7
1.1
−56/−61
10
13.5
1.3
−59/−63
+1.4
−160
µA
µA
V
V
mA
ns
ns
12
14.3
1.65
V
mA
mA
dB
AD8000
SPECIFICATIONS WITH +5 V SUPPLY
At TA = 25°C, VS = +5 V, RL = 150 Ω, Gain = +2, RF = RG = 432 Ω, unless otherwise noted. Exposed paddle should be connected to ground.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic
Second/Third Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain Error
Differential Phase Error
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current (Enabled)
Transimpedance
INPUT CHARACTERISTICS
Noninverting Input Impedance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Overdrive Recovery
POWER DOWN PIN
Power-Down Input Voltage
Turn-Off Time
Turn-On Time
Input Current
Enabled
Power-Down
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Overdrive Recovery
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Power-Down)
Power Supply Rejection Ratio
Conditions
Min
Typ
Max
Unit
G = +1, VO = 0.2 V p-p
G = +2, VO = 2 V p-p
G = +10, VO = 0.2 V p-p
VO = 0.2 V p-p
VO = 2 V p-p
G = +2, VO = 2 V step
G = +2, VO = 2 V step
980
477
328
136
136
2700
16
MHz
MHz
MHz
MHz
MHz
V/µs
ns
VO = 2 V p-p, 5 MHz, LFCSP only
VO = 2 V p-p, 20 MHz, LFCSP only
f = 100 kHz
f = 100 kHz, −IN
f = 100 kHz, +IN
NTSC, G = +2
NTSC, G = +2
71/71
60/62
1.6
26
3.4
0.01
0.06
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
Degree
+IB
−IB
440
VCM = ±2.5 V
G = +1, f = 1 MHz, triangle wave
−51
Power-down
Enable
50% of power-down voltage to
10% of VOUT final, VIN = 0.3 V p-p
50% of power-down voltage to
90% of VOUT final, VIN = 0.3 V p-p
RL = 100 Ω
RL = 1 kΩ
VO = 2 V p-p, second HD < −50 dBc
G = +2, f = 100 kHz, triangle wave
−PSRR/+PSRR
Rev. 0 | Page 4 of 20
1.3
18
−5
−1
800
2/3.6
1.5 to 3.6
−52
60
+3
+45
1500
−54
mV
µV/°C
µA
µA
kΩ
MΩ/pF
V
dB
ns
< +VS − 3.1
> +VS − 1.9
200
V
V
ns
300
ns
−1.1
−50
+0.17
−40
1.1 to 3.9
1 to 3.1
1.05 to 4.1
0.85 to 4.15
70
65
4.5
11
0.7
−55/−60
10
12
0.95
−57/−62
+1.4
−30
µA
µA
V
V
mA
ns
12
13
1.25
V
mA
mA
dB
AD8000
ABSOLUTE MAXIMUM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the AD8000 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
Rating
12.6 V
See Figure 4
−VS − 0.7 V to +VS + 0.7 V
±VS
−VS
−65°C to +125°C
−40°C to +125°C
300°C
PD = Quiescent Power + (Total Drive Power – Load Power)
⎛V V
PD = (VS × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
SOIC-8
3 mm × 3 mm LFCSP
θJA
80
93
θJC
30
35
Unit
°C/W
°C/W
⎞ VOUT 2
⎟–
⎟
RL
⎠
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
(VS / 4 )2
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and the LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
3.0
Maximum Power Dissipation
MAXIMUM POWER DISSIPATION (W)
The maximum safe power dissipation for the AD8000 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric performance of the AD8000. Exceeding a junction temperature of
175°C for an extended period of time can result in changes
in silicon devices, potentially causing degradation or loss of
functionality.
2.5
2.0
SOIC
1.5
LFCSP
1.0
0.5
05321-063
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering, 10 sec)
Junction Temperature
0
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90 100 110 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
Rev. 0 | Page 5 of 20
AD8000
TYPICAL PERFORMANCE CHARACTERISTICS
3
9
VS = ±5V
RL = 150Ω
VOUT = 200mV p-p
2
G = +1, RF = 432Ω
RF = 392Ω
6
0
–1
GAIN (dB)
G = +2, RF = 432Ω, RG = 432Ω
–2
–3
RF = 432Ω
3
RF = 487Ω
G = +10, RF = 357Ω, RG = 40.2Ω
–4
05321-006
–6
–7
1
10
100
–3
1
1000
10
FREQUENCY (MHz)
1000
Figure 8. Small Signal Frequency Response vs. RF
3
9
VS = ±5V
RL = 150Ω
VOUT = 200mV p-p
2
1
G = –1, RF = RG = 249Ω
RF = 392Ω
6
0
–1
RF = 432Ω
GAIN (dB)
–2
–3
3
RF = 487Ω
G = –10, RF = 432Ω, RG = 43.2Ω
–4
05321-007
G = –2, RF = 432Ω, RG = 215Ω
–6
–7
1
10
100
05321-012
VS = ±5V
G = +2
RL = 150Ω
VOUT = 2V p-p
LFCSP
0
–5
–3
1
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response vs. RF
Figure 6. Small Signal Frequency Response vs. Various Gains
1000
3
VS = ±5V
RL = 150Ω
VOUT = 2V p-p
1
150
TRANSIMPEDANCE (kΩ)
2
200
VS = ±5V
RL = 100Ω
G = +1, RF = 432Ω
0
–1
G = +4, RF = 357Ω, RG = 121Ω
–2
G = +10, RF = 357Ω, RG = 40.2Ω
–3
G = +2, RF = RG = 432Ω
–4
100
100
10
50
PHASE
TZ
0
PHASE (Degrees)
NORMALIZED GAIN (dB)
100
FREQUENCY (MHz)
Figure 5. Small Signal Frequency Response vs. Various Gains
1
–5
50
05321-008
NORMALIZED GAIN (dB)
05321-011
VS = ±5V
G = +2
RL = 150Ω
VOUT = 200mV p-p
LFCSP
0
–5
–6
–7
1
10
100
0.1
0.1
1000
1
10
100
1000
100
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Transimpedance and Phase vs. Frequency
Figure 7. Large Signal Frequency Response vs. Various Gains
Rev. 0 | Page 6 of 20
05321-027
NORMALIZED GAIN (dB)
1
AD8000
9
3
RL = 1kΩ
G = +1
RF = 432Ω
VOUT = 200mV p-p
LFCSP
2
1
VS = +5V, RS = 0Ω
6
–2
3
–40°C
VS = +5V, RS = 50Ω
–3
–4
VS = ±5V
G = +2
RL = 150Ω
VOUT = 200mV p-p
LFCSP
0
–5
05321-010
VS = ±5V, RS = 50Ω
–6
–7
0.1
1
10
100
+125°C
+25°C
–3
1
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response vs. Temperature
Figure 11. Small Signal Frequency Response vs. Supply Voltage
9
9
RL = 150Ω
G = +1
RF = 432Ω
VOUT = 200mV p-p
LFCSP
6
6
VS = ±5V
+25°C
GAIN (dB)
3
GAIN (dB)
05321-014
VS = ±5V, RS = 0Ω
–1
GAIN (dB)
GAIN (dB)
0
0
–40°C
3
VS = +5V
–3
VS = ±5V
G = +2
RL = 1kΩ
VOUT = 200mV p-p
LFCSP
05321-009
–9
1
10
100
+125°C
05321-015
0
–6
–3
1
1000
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response vs. Temperature
Figure 12. Small Signal Frequency Response vs. Supply Voltage
9
6.5
VS = ±5V
RL = 150Ω
VOUT = 2V p-p
G = +2
RF = 432Ω
6.4
6.3
6
GAIN (dB)
6.1
SOIC
6.0
5.9
3
–40°C
LFCSP
+25°C
VS = ±5V
G = +2
RL = 150Ω
VOUT = 2V p-p
LFCSP
0
5.7
5.6
5.5
1
10
+125°C
05321-016
5.8
05321-013
GAIN (dB)
6.2
–3
1
100
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Large Signal Frequency Response vs. Temperature
Figure 13. 0.1 dB Flatness
Rev. 0 | Page 7 of 20
AD8000
–40
9
VOUT = 1V p-p
–60
DISTORTION (dBc)
6
3
VOUT = 2V p-p
–3
1
10
SECOND HD
–80
–90
THIRD HD
–100
VOUT = 4V p-p
VS = ±5V
G = +2
RL = 150Ω
LFCSP
–70
–110
100
05321-042
0
05321-017
–120
1
1000
10
Figure 17. Large Signal Frequency Response vs. Various Outputs
Figure 20. Harmonic Distortion vs. Frequency
–40
–20
VS = ±5V
VOUT = 2V p-p
G = +1
RL = 150Ω
LFCSP
–40
DISTORTION (dBc)
SECOND HD
–70
THIRD HD
–80
–90
–50
–70
THIRD HD
–80
–110
–90
–120
1
10
SECOND HD
–60
–100
05321-040
DISTORTION (dBc)
–60
VS = ±5V
VOUT = 4V p-p
G = +1
RL = 1kΩ
LFCSP
–30
05321-041
–50
–100
100
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency
Figure 21. Harmonic Distortion vs. Frequency
–40
–40
VS = ±5V
G = +10
VOUT = 2V p-p
RL = 1kΩ
LFCSP
–60
–70
VS = ±5V
VOUT = 2V p-p
G = +2
RL = 150Ω
–50
LFCSP SECOND HD
DISTORTION (dBc)
–50
SECOND HD
–80
THIRD HD
–90
–60
SOIC SECOND HD
–70
–80
–100
LFCSP THIRD HD
–90
–110
05321-039
DISTORTION (dBc)
100
FREQUENCY (MHz)
FREQUENCY (MHz)
–120
1
10
SOIC THIRD HD
–100
1
100
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. Harmonic Distortion vs. Frequency
Figure 19. Harmonic Distortion vs. Frequency
Rev. 0 | Page 8 of 20
05321-043
GAIN (dB)
VS = ±5V
VOUT = 2V p-p
G = +1
RL = 1kΩ
LFCSP
–50
100
AD8000
–20
–20
VS = 5V
VOUT = 2V p-p
G = +2
RL = 150Ω
LFCSP
–40
SECOND HD
–50
–60
THIRD HD
–70
–80
–90
–50
–60
THIRD HD
–70
SECOND HD
–80
–90
05321-044
–100
–100
–110
1
10
05321-048
DISTORTION (dBc)
–40
VS = ±2.5V
VOUT = 2V p-p
G = –1
RL = 150Ω
LFCSP
–30
DISTORTION (dBc)
–30
–110
–120
1
100
10
Figure 23. Harmonic Distortion vs. Frequency
Figure 26. Harmonic Distortion vs. Frequency
–20
–20
VS = 5V
VOUT = 2V p-p
G = +2
RL = 1kΩ
LFCSP
–40
–40
THIRD HD
–50
VS = 5V
VOUT = 2V p-p
G = –1
RL = 1kΩ
LFCSP
–30
DISTORTION (dBc)
–30
DISTORTION (dBc)
100
FREQUENCY (MHz)
FREQUENCY (MHz)
–60
SECOND HD
–70
–50
THIRD HD
–60
–70
SECOND HD
–80
–90
–80
05321-045
–100
1
10
05321-049
–100
–90
–110
–120
100
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 24. Harmonic Distortion vs. Frequency
–20
–40
–40
VS = ±5V
VOUT = 2V p-p
G = –1
RL = 150Ω
LFCSP
–50
–60
DISTORTION (dBc)
–50
SECOND HD
–60
–70
–80
THIRD HD
–90
SECOND HD
–70
THIRD HD
–80
–90
–100
–110
–120
1
10
05321-050
–100
05321-047
DISTORTION (dBc)
Figure 27. Harmonic Distortion vs. Frequency
VS = ±5V
VOUT = 2V p-p
G = +2
RL = 1kΩ
LFCSP
–30
100
–110
1
100
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 28. Harmonic Distortion vs. Frequency
Figure 25. Harmonic Distortion vs. Frequency
Rev. 0 | Page 9 of 20
100
AD8000
–40
–50
–60
VS = ±5V
VIN = 2V p-p
RL = 100Ω
G = +1
RF = 432Ω
–15
–20
–25
–PSRR
–30
SECOND HD
–70
PSRR (dB)
–80
THIRD HD
–90
–35
–40
+PSRR
–45
–50
–55
–100
–60
–65
05321-051
–110
–120
1
10
05321-021
DISTORTION (dBc)
–10
VS = ±5V
VOUT = 2V p-p
G = –1
RL = 1kΩ
LFCSP
–70
–75
100
0.1
1
FREQUENCY (MHz)
Figure 29. Harmonic Distortion vs. Frequency
100
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency
1k
–25
VS = ±5V
VIN = 0.2V p-p
RF = 432Ω
LFCSP
100
10
FREQUENCY (MHz)
VS = ±5V
VIN = 1V p-p
RL = 100Ω
LFCSP
–30
10
CMRR (dB)
1
–40
–45
–50
–55
G = +1
OR G = +2
–60
05321-023
0.1
0.01
0.1
1
10
100
05321-031
IMPEDANCE (Ω)
–35
–65
0.1
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 33. Common-Mode Rejection Ratio vs. Frequency
Figure 30. Output Impedance vs. Frequency
0.175
2.65
0.150
G = +1
G = +1
0.125
2.60
0.075
RESPONSE (V)
2.55
2.50
2.45
0.050
G = +2
0.025
0
–0.025
–0.050
2.40
2.35
0
5
10
15
20
25
30
35
40
45
VS = ±5V
RF = 432Ω
RS = 0Ω
RL = 100Ω
–0.100
–0.125
–0.150
–0.175
50
0
5
10
15
20
25
30
35
40
TIME (ns)
TIME (ns)
Figure 34. Small Signal Transient Response
Figure 31. Small Signal Transient Response
Rev. 0 | Page 10 of 20
45
05321-066
–0.075
VS = 5V
RF = 432Ω
RS = 0Ω
RL = 100Ω
05321-072
RESPONSE (V)
0.100
G = +2
50
AD8000
5
1.75
VS = ±5V, VIN
1.50
4
G = +1
1.25
OUTPUT VOLTAGE (V)
0.75
0.50
G = +2
0.25
0
–0.25
–0.50
–0.75
VS = ±5V
RF = 432Ω
RS = 0Ω
RL = 100Ω
–1.25
–1.50
–1.75
0
5
10
15
20
25
30
35
40
45
1
VS = ±2.5V, VOUT
0
–1
VS = ±2.5V, VIN
–2
–3
05321-067
–1.00
2
G = +1
RL = 150Ω
RF = 432Ω
–4
05321-019
RESPONSE (V)
VS = ±5V, VOUT
3
1.00
–5
0
50
200
400
600
800
1000
TIME (ns)
TIME (ns)
Figure 35. Large Signal Transient Response
Figure 38. Input Overdrive
6
0.5
G = +2
VS = ±5V, 2 × VIN
5
VIN
0.4
VS = ±5V, VOUT
4
0.3
OUTPUT VOLTAGE (V)
SETTLING TIME (%)
3
1V
0.2
0.1
0
–0.1
–0.2
2
1
0
VS = ±2.5V, 2 × VIN
–1
–2
VS = ±2.5V, VOUT
–3
05321-068
–4
–0.4
t = 0s
5ns/DIV
–0.5
–5
–4
–3
–2
–1
0
1
2
G = +2
RL = 150Ω
RF = 432Ω
–5
05321-020
–0.3
–6
3
0
200
400
800
1000
Figure 39. Output Overdrive
Figure 36. Settling Time
6k
100
G = +2
RF = 432Ω
RL = 150Ω
LFCSP, VS = ±5V
3k
SOIC, VS = +5V
2k
LFCSP, VS = +5V
05321-018
1k
0
1
2
3
4
5
6
10
1
0.1
10
7
VOUT (V p-p)
05321-058
4k
0
VS = ±5V
G = +10
RF = 432Ω
RN = 47.5Ω
SOIC, VS = ±5V
INPUT VOLTAGE NOISE (nV/ Hz)
5k
SR (V/µs)
600
TIME (ns)
VCM (V)
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 40. Input Voltage Noise
Figure 37. Slew Rate vs. Output Level
Rev. 0 | Page 11 of 20
10M
100M
AD8000
1000
0
VS = ±5V
VS = ±5V
–10
100
VS = +5V
–15
INVERTING CURRENT NOISE, RF = 1kΩ
IB (µA)
–20
10
–25
–30
–35
1
0.1
10
100
1k
10k
100k
1M
10M
100M
05321-070
–40
NONINVERTING CURRENT NOISE, RF = 432Ω
05321-055
INPUT CURRENT NOISE (pA/ Hz)
–5
–45
–50
1G
–5
–4
–3
–2
FREQUENCY (Hz)
1
2
3
4
5
Figure 44. Input Bias Current vs. Common-Mode Voltage
20
–5
15
–10
RBACK TERM = 50
VS = ±5V
G = +2
POUT = –10dBm
SOIC
–15
10
–20
VS = ±5V
S22 (dB)
VOS (mV)
0
VCM (V)
Figure 41. Input Current Noise
5
–1
0
–25
–30
–5
–35
–10
VS = +5V
–20
–5
–4
–3
–2
–1
0
1
2
3
4
05321-065
05321-024
–40
–15
–45
–50
5
10
VCM (V)
1000
Figure 45. Output Voltage Standing Wave Ratio (S22)
Figure 42. Input VOS vs. Common-Mode Voltage
25
–5
20
–10
15
G = +10
–15
G = +2
10
–20
S11 (dB)
5
VS = ±5V
0
–5
–25
G = +1
–30
–20
–25
–5
–4
–3
–2
–1
0
1
2
INPUT RS = 0Ω
VS = ±5V
POUT = –10dBm
SOIC
–40
VS = +5V
–15
3
4
–45
–50
5
10
VOUT (V)
100
FREQUENCY (MHz)
Figure 46. Input Voltage Standing Wave Ratio (S11)
Figure 43. Input Bias Current vs. Output Voltage
Rev. 0 | Page 12 of 20
05321-064
–35
–10
05321-069
IB (µA)
100
FREQUENCY (MHz)
1000
AD8000
TEST CIRCUITS
+VS
10µF
0.1µF
RF
432Ω
50Ω
TRANSMISSION
LINE
AD8000
432Ω
50Ω
TRANSMISSION
LINE
49.9Ω
VIN
60.4Ω
200Ω
49.9Ω
200Ω
05321-028
0.1µF
10µF
–VS
Figure 47. CMRR
VP = VS + VIN
49.9Ω
50Ω
TRANSMISSION
LINE
TERMINATION
50Ω
AD8000
50Ω
TRANSMISSION
LINE
49.9Ω
49.9Ω
RF
432Ω
TERMINATION
50Ω
0.1µF
RG
432Ω
05321-029
10µF
–VS
Figure 48. Positive PSRR
+VS
10µF
0.1µF
TERMINATION
50Ω
AD8000
50Ω
TRANSMISSION
LINE
49.9Ω
49.9Ω
TERMINATION
50Ω
RF
432Ω
RG
432Ω
49.9Ω
VN = –VS + VIN
Figure 49. Negative PSRR
Rev. 0 | Page 13 of 20
05321-030
50Ω
TRANSMISSION
LINE
AD8000
APPLICATIONS
+VS
All current feedback amplifier operational amplifiers are
affected by stray capacitance at the inverting input pin. As a
practical consideration, the higher the stray capacitance on
the inverting input to ground, the higher RF needs to be to
minimize peaking and ringing.
0.1µF
FB
RG
VIN
AD8000
Table 5 provides a quick reference for the circuit values, gain,
and output voltage noise.
+VS
10µF
+
–VS
Figure 51. Inverting Configuration
VIDEO LINE DRIVER
The AD8000 is designed to offer outstanding performance as a
video line driver. The important specifications of differential
gain (0.02%), differential phase (0.01°), and 650 MHz bandwidth at 2 V p-p meet the most exacting video demands. Figure 52
shows a typical noninverting video driver with a gain of +2.
432Ω
432Ω
+VS
FB
4.7µF
+
+V
–
AD8000
FB
VO
+
–V
05321-036
10µF
+
75Ω
RL
VOUT
75Ω
CABLE
4.7µF
VIN
–VS
75Ω
05321-035
75Ω
0.1µF
+
10µF
+
NONINVERTING
75Ω
CABLE
AD8000
0.1µF
–VS
0.1µF
VO
+
05321-071
RS
RL
–V 0.1µF
0.1µF
VIN
VO
VO
+
Figure 50 and Figure 51 show typical schematics for noninverting and inverting configurations. For current feedback
amplifiers, the value of feedback resistance determines the
stability and bandwidth of the amplifier. The optimum
performance values are shown in Table 5 and should not be
deviated from by more than ±10% to ensure stable operation.
Figure 8 shows the influence varying RF has on bandwidth. In
noninverting unity-gain configurations, it is recommended that
an RS of 50 Ω be used, as shown in Figure 50.
RG
+V
–
CIRCUIT CONFIGURATIONS
RF
10µF
+
RF
Figure 52. Video Line Driver
Figure 50. Noninverting Configuration
Table 5. Typical Values (LFCSP/SOIC)
Gain
1
2
4
10
Component
Values (Ω)
RG
RF
432
--432
432
357
120
357
40
−3 dB SS
Bandwidth
(MHz)
LFCSP
SOIC
1380
1580
600
650
550
550
350
365
−3 dB LS
Bandwidth
(MHz)
LFCSP
SOIC
550
600
610
650
350
350
370
370
Slew Rate
(V/µsec)
Output Noise
(nV/√Hz)
Total Output
Noise Including
Resistors (nV/√Hz)
2200
3700
3800
3200
10.9
11.3
10
18.4
11.2
11.9
12
19.9
Rev. 0 | Page 14 of 20
AD8000
LOW DISTORTION PINOUT
PRINTED CIRCUIT BOARD LAYOUT
The AD8000 LFCSP features ADI’s new low distortion pinout.
The new pinout lowers the second harmonic distortion and
simplifies the circuit layout. The close proximity of the noninverting input and the negative supply pin creates a source of
second harmonic distortion. Physical separation of the noninverting input pin and the negative power supply pin reduces
this distortion significantly, as seen in Figure 22.
Laying out the printed circuit board (PCB) is usually the last
step in the design process and often proves to be one of the
most critical. A brilliant design can be rendered useless because
of a poor or sloppy layout. Since the AD8000 can operate into
the RF frequency spectrum, high frequency board layout considerations must be taken into account. The PCB layout, signal
routing, power supply bypassing, and grounding all must be
addressed to ensure optimal performance.
By providing an additional output pin, the feedback resistor
can be connected directly across Pin 2 and Pin 3. This greatly
simplifies the routing of the feedback resistor and allows a more
compact circuit layout, which reduces its size and helps to
minimize parasitics and increase stability.
The SOIC also features a dedicated feedback pin. The feedback
pin is brought out on Pin 1, which is typically a No Connect on
standard SOIC pinouts.
SIGNAL ROUTING
The AD8000 LFCSP features the new low distortion pinout
with a dedicated feedback pin and allows a compact layout. The
dedicated feedback pin reduces the distance from the output to
the inverting input, which greatly simplifies the routing of the
feedback network.
Existing applications that use the standard SOIC pinout can
take full advantage of the performance offered by the AD8000.
For drop-in replacements, ensure that Pin 1 is not connected to
ground or to any other potential because this pin is connected
internally to the output of the amplifier. For existing designs,
Pin 6 can still be used for the feedback resistor.
To minimize parasitic inductances, ground planes should be
used under high frequency signal traces. However, the ground
plane should be removed from under the input and output pins
to minimize the formation of parasitic capacitors, which
degrades phase margin. Signals that are susceptible to noise
pickup should be run on the internal layers of the PCB, which
can provide maximum shielding.
EXPOSED PADDLE
POWER SUPPLY BYPASSING
The AD8000 features an exposed paddle, which can lower the
thermal resistance by 25% compared to a standard SOIC plastic
package. The paddle can be soldered directly to the ground plane
of the board. Figure 53 shows a typical pad geometry for the
LFCSP, the same type of pad geometry can be applied to the
SOIC package.
Power supply bypassing is a critical aspect of the PCB design
process. For best performance, the AD8000 power supply pins
need to be properly bypassed.
05321-034
Thermal vias or “heat pipes” can also be incorporated into the
design of the mounting pad for the exposed paddle. These additional vias improve the thermal transfer from the package to
the PCB. Using a heavier weight copper on the surface to which
the amplifier’s exposed paddle is soldered also reduces the overall thermal resistance “seen” by the AD8000.
Figure 53. LFCSP Exposed Paddle Layout
A parallel connection of capacitors from each of the power
supply pins to ground works best. Paralleling different values
and sizes of capacitors helps to ensure that the power supply
pins “see” a low ac impedance across a wide band of frequencies.
This is important for minimizing the coupling of noise into the
amplifier. Starting directly at the power supply pins, the smallest
value and sized component should be placed on the same side
of the board as the amplifier, and as close as possible to the
amplifier, and connected to the ground plane. This process
should be repeated for the next larger value capacitor. It is
recommended for the AD8000 that a 0.1 µF ceramic 0508 case
be used. The 0508 offers low series inductance and excellent
high frequency performance. The 0.1 µF case provides low
impedance at high frequencies. A 10 µF electrolytic capacitor
should be placed in parallel with the 0.1 µF. The 10 µf capacitor
provides low ac impedance at low frequencies. Smaller values
of electrolytic capacitors can be used, depending on the circuit
requirements. Additional smaller value capacitors help to
provide a low impedance path for unwanted noise out to higher
frequencies but are not always necessary.
Rev. 0 | Page 15 of 20
AD8000
Placement of the capacitor returns (grounds), where the capacitors enter into the ground plane, is also important. Returning
the capacitors grounds close to the amplifier load is critical for
distortion performance. Keeping the capacitors distance short,
but equal from the load, is optimal for performance.
In some cases, bypassing between the two supplies can help to
improve PSRR and to maintain distortion performance in
crowded or difficult layouts. This is as another option to
improve performance.
Minimizing the trace length and widening the trace from the
capacitors to the amplifier reduce the trace inductance. A series
inductance with the parallel capacitance can form a tank circuit,
which can introduce high frequency ringing at the output. This
additional inductance can also contribute to increased distortion due to high frequency compression at the output. The use
of vias should be minimized in the direct path to the amplifier
power supply pins since vias can introduce parasitic inductance,
which can lead to instability. When required, use multiple large
diameter vias because this lowers the equivalent parasitic
inductance.
GROUNDING
The use of ground and power planes is encouraged as a method
of proving low impedance returns for power supply and signal
currents. Ground and power planes can also help to reduce stray
trace inductance and to provide a low thermal path for the
amplifier. Ground and power planes should not be used under
any of the pins of the AD8000. The mounting pads and the
ground or power planes can form a parasitic capacitance at the
amplifiers input. Stray capacitance on the inverting input and
the feedback resistor form a pole, which degrades the phase
margin, leading to instability. Excessive stray capacitance on the
output also forms a pole, which degrades phase margin.
Rev. 0 | Page 16 of 20
AD8000
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
BOTTOM VIEW
(PINS UP)
2.29 (0.092)
5
1
2.29 (0.092)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
TOP VIEW
4
1.27 (0.05)
BSC
0.50 (0.020)
× 45°
0.25 (0.010)
1.75 (0.069)
1.35 (0.053)
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
SEATING
0.10
PLANE
0.51 (0.020)
0.31 (0.012)
8°
0.25 (0.0098) 0° 1.27 (0.050)
0.40 (0.016)
0.17 (0.0068)
COMPLIANT TO JEDEC STANDARDS MS-012
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 54. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters and (inches)
3.00
BSC SQ
0.50
0.40
0.30
0.60 MAX
0.45
1
8
PIN 1
INDICATOR
0.90
0.85
0.80
SEATING
PLANE
TOP
VIEW
2.75
BSC SQ
0.50
BSC
1.50
REF
EXPOSED
PAD
(BOTTOM VIEW)
5
0.25
MIN
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
1.90
1.75
1.60
4
1.60
1.45
1.30
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
Figure 55. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body (CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8000YRDZ1
AD8000YRDZ-REEL1
AD8000YRDZ-REEL71
AD8000YCPZ-R21
AD8000YCPZ-REEL1
AD8000YCPZ-REEL71
1
Minimum Ordering Quantity
1
2,500
1,000
250
5,000
1,500
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Z = Pb-free part.
Rev. 0 | Page 17 of 20
Package Description
8-Lead SOIC/EP
8-Lead SOIC/EP
8-Lead SOIC/EP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
Branding
HNB
HNB
HNB
Package Option
RD-8-1
RD-8-1
RD-8-1
CP-8-2
CP-8-2
CP-8-2
AD8000
NOTES
Rev. 0 | Page 18 of 20
AD8000
NOTES
Rev. 0 | Page 19 of 20
AD8000
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05321–0–1/05(0)
Rev. 0 | Page 20 of 20