LINER LTC2624 Quad 16-bit rail-to-rail dacs in 16-lead ssop Datasheet

LTC2604/LTC2614/LTC2624
Quad 16-Bit Rail-to-Rail DACs
in 16-Lead SSOP
FEATURES
DESCRIPTION
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The LTC®2604/LTC2614/LTC2624 are quad 16-,14- and
12-bit 2.5V to 5.5V rail-to-rail voltage output DACs in
16-lead narrow SSOP packages. These parts have separate
reference inputs for each DAC. They have built-in high performance output buffers and are guaranteed monotonic.
Smallest Pin Compatible Quad 16-Bit DAC:
LTC2604: 16-Bits
LTC2614: 14-Bits
LTC2624: 12-Bits
Guaranteed 16-Bit Monotonic Over Temperature
Separate Reference Inputs for each DAC
Wide 2.5V to 5.5V Supply Range
Low Power Operation: 250μA per DAC at 3V
Individual DAC Power-Down to 1μA, Max
Ultralow Crosstalk Between DACs (<5μV)
High Rail-to-Rail Output Drive (±15mA)
Double Buffered Digital Inputs
LTC2604-1/LTC2614-1/LTC2624-1: Power-On Reset
to Midscale
16-Lead Narrow SSOP Package
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These parts establish advanced performance standards
for output drive, crosstalk and load regulation in singlesupply, voltage output multiples.
The parts use a simple SPI/MICROWIRE compatible
3-wire serial interface which can be operated at clock rates
up to 50MHz. Daisy-chain capability and a hardware CLR
function are included.
The LTC2604/LTC2614/LTC2624 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2604-1/LTC2614-1
/LTC2624-1 to midscale. The voltage outputs stay at midscale until a valid write and update take place.
APPLICATIONS
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Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
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L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
BLOCK DIAGRAM
VCC
GND
1
REF LO
2
REF A
REF B
DAC B
DAC
REGISTER
VOUT D
1.0
14
0.8
VCC = 5V
VREF = 4.096V
0.6
DAC
REGISTER
VOUT C
DAC C
13
REF C
12
ERROR (LSB)
5
DAC D
Differential Nonlinearity (LTC2604)
0.4
INPUT
REGISTER
VOUTB
INPUT
REGISTER
DAC A
INPUT
REGISTER
4
DAC
REGISTER
VOUTA
DAC
REGISTER
3
INPUT
REGISTER
16
REF D
15
0.2
0
–0.2
–0.4
CLR
11
6
–0.6
–0.8
CS/LD
7
CONTROL
LOGIC
DECODE
SCK
8
32-BIT SHIFT REGISTER
SDO
10
SDI
9
–1.0
0
16384
32768
CODE
49152
65535
2604 TA01
2604 BD
2604fd
1
LTC2604/LTC2614/LTC2624
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
Any Pin to GND ............................................ –0.3V to 6V
Any Pin to VCC ............................................. –6V to 0.3V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC2604C/LTC2614C/LTC2624C ............. 0°C to 70°C
LTC2604C-1/LTC2614C-1/
LTC2624C-1 ............................................. 0°C to 70°C
LTC2604I/LTC2614I/LTC2624I .............–40°C to 85°C
LTC2604I-1/LTC2614I-1/
LTC2624I-1 ..........................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
GND
1
16 VCC
REF LO
2
15 REF D
REF A
3
14 VOUT D
VOUT A
4
13 VOUT C
VOUT B
5
12 REF C
REF B
6
11 CLR
CS/LD
7
10 SDO
SCK
8
9
SDI
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 150°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2604CGN#PBF
LTC2604CGN#TRPBF
2604
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2604CGN-1#PBF
LTC2604CGN-1#TRPBF
26041
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2604IGN#PBF
LTC2604IGN#TRPBF
2604I
16-Lead Narrow SSOP Package
–40°C to 85°C
LTC2604IGN-1#PBF
LTC2604IGN-1#TRPBF
2604I1
16-Lead Narrow SSOP Package
–40°C to 85°C
LTC2614CGN#PBF
LTC2614CGN#TRPBF
2614
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2614CGN-1#PBF
LTC2614CGN-1#TRPBF
26141
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2614IGN#PBF
LTC2614IGN#TRPBF
2614I
16-Lead Narrow SSOP Package
–40°C to 85°C
LTC2614IGN-1#PBF
LTC2614IGN-1#TRPBF
2614I1
16-Lead Narrow SSOP Package
–40°C to 85°C
LTC2624CGN#PBF
LTC2624CGN#TRPBF
2624
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2624CGN-1#PBF
LTC2624CGN-1#TRPBF
26241
16-Lead Narrow SSOP Package
0°C to 70°C
LTC2624IGN#PBF
LTC2624IGN#TRPBF
2624I
16-Lead Narrow SSOP Package
–40°C to 85°C
LTC2624IGN-1#PBF
LTC2624IGN-1#TRPBF
2624I1
16-Lead Narrow SSOP Package
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B =
REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL PARAMETER
CONDITIONS
LTC2624/LTC2624-1
LTC2614/LTC2614-1
LTC2604/LTC2604-1
MIN
MIN
MIN
TYP
MAX
TYP
MAX
TYP
MAX
UNITS
DC Performance
Resolution
l
12
Monotonicity
12
(Note 2)
l
DNL
Differential Nonlinearity (Note 2)
l
INL
Integral Nonlinearity
l
(Note 2)
14
16
14
16
±0.5
±0.9
±4
Bits
Bits
±1
±4
±16
±1
±14
±64
LSB
LSB
2604fd
2
LTC2604/LTC2614/LTC2624
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B =
REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL PARAMETER
Load Regulation
ZSE
VOS
CONDITIONS
LTC2614/LTC2614-1
LTC2604/LTC2604-1
MIN
MIN
MIN
TYP
MAX
0.025 0.125
0.025 0.125
0.1
0.1
VREF = VCC = 2.5V, Midscale
IOUT = 0mA to 7.5mA Sourcing l
IOUT = 0mA to 7.5mA Sinking l
0.05
0.05
0.25
0.25
l
1.5
l
±1.5
VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing
IOUT = 0mA to 15mA Sinking
Zero-Scale Error
Offset Error
LTC2624/LTC2624-1
(Note 7)
l
l
VOS Temperature
Coefficient
GE
TYP
MAX
TYP
MAX
0.5
0.5
0.3
0.3
2
2
LSB/mA
LSB/mA
0.2
0.2
1
1
0.7
0.7
4
4
LSB/mA
LSB/mA
9
1.5
9
1.5
9
mV
±9
±1.5
±9
±1.5
±9
±5
l
Gain Error
Gain Temperature
Coefficient
±0.1
±5
±0.7
±5
±0.1
±5
±0.7
±0.1
±5
UNITS
mV
μV/°C
±0.7
±5
%FSR
ppm/°C
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF
A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded,
unless otherwise noted. (Note 10)
SYMBOL
PARAMETER
CONDITIONS
PSR
Power Supply Rejection
VCC = 5V ±10%
VCC = 3V ±10%
ROUT
DC Output Impedance
VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.5mA
DC Crosstalk (Note 4)
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (per Channel)
Short-Circuit Output Current
VCC = 5.5V, VREF = 5.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
15
15
34
36
60
60
mA
mA
VCC = 2.5V, VREF = 2.5V
Code: Zero Scale; Forcing Output to VCC
Code: Full Scale; Forcing Output to GND
l
l
7.5
7.5
18
24
50
50
mA
mA
VCC
μA
128
160
kΩ
ISC
MIN
TYP
MAX
–80
–80
l
l
0.025
0.030
UNITS
dB
dB
0.15
0.15
±5
±1
±3.5
Ω
Ω
μV
μV/mA
μV
Reference Input
Input Voltage Range
Resistance
Normal Mode
l
0
l
88
Capacitance
14
Reference Current, Power Down Mode All DACs Powered Down
l
VCC
Positive Supply Voltage
For Specified Performance
l
ICC
Supply Current
VCC = 5V (Note 3)
VCC = 3V (Note 3)
All DACs Powered Down (Note 3) VCC = 5V
All DACs Powered Down (Note 3) VCC = 3V
l
l
l
l
Digital Input High Voltage
VCC = 2.5V to 5.5V
VCC = 2.5V to 3.6V
l
l
IREF
0.001
pF
1
μA
Power Supply
2.5
1.3
1
0.35
0.10
5.5
V
2
1.6
1
1
mA
mA
μA
μA
Digital I/O
VIH
2.4
2.0
V
V
2604fd
3
LTC2604/LTC2614/LTC2624
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B =
REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
l
l
VOH
Digital Output High Voltage
Load Current = –100μA
l
VOL
Digital Output Low Voltage
Load Current = +100μA
l
0.4
V
±1
μA
8
pF
ILK
Digital Input Leakage
VIN = GND to VCC
l
CIN
Digital Input Capacitance
(Note 6)
l
TYP
MAX
UNITS
0.8
0.6
V
V
VCC – 0.4
V
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REF
A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D = 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded,
unless otherwise noted. (Note 10)
SYMBOL PARAMETER
CONDITIONS
LTC2624/LTC2624-1
LTC2614/LTC2614-1
LTC2604/LTC2604-1
MIN
MIN
MIN
TYP
MAX
TYP
MAX
TYP
MAX
UNITS
AC Performance
ts
Settling Time (Note 8)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7
9
7
9
10
μs
μs
μs
Settling Time for
1LSB Step (Note 9)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
2.7
4.8
2.7
4.8
5.2
μs
μs
μs
Voltage Output Slew Rate
0.80
0.80
0.80
V/μs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Midscale Transition
Multiplying Bandwidth
en
12
12
12
nV • s
180
180
180
kHz
Output Voltage Noise
Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV√Hz
nV√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
μVP–P
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D
= 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.5V to 5.5V
t1
SDI Valid to SCK Setup
l
4
ns
t2
SDI Valid to SCK Hold
l
4
ns
t3
SCK High Time
l
9
ns
t4
SCK Low Time
l
9
ns
t5
CS/LD Pulse Width
l
10
ns
t6
LSB SCK High to CS/LD High
l
7
ns
t7
CS/LD Low to SCK High
l
7
ns
t8
SDO Propagation Delay from SCK Falling Edge
t9
CLR Pulse Width
CLOAD = 10pF
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
l
l
l
20
45
20
ns
ns
ns
2604fd
4
LTC2604/LTC2614/LTC2624
TIMING CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. REF A = REF B = REF C = REF D = 4.096V (VCC = 5V), REF A = REF B = REF C = REF D
= 2.048V (VCC = 2.5V), REF LO = 0V, VOUT unloaded, unless otherwise noted. (Note 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
t10
CS/LD High to SCK Positive Edge
l
SCK Frequency
l
50% Duty Cycle
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16,
kL = 256, linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with
the measured DAC at midscale, unless otherwise noted.
TYP
MAX
UNITS
7
ns
50
MHz
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Guaranteed by design and not production tested.
Note 7: Inferred from measurement at code 256 (LTC2604), code 64
(LTC2614) or code 16 (LTC2624), and at full scale.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between half scale
and half scale –1. Load is 2k in parallel with 200pF to GND.
Note 10: These specifications apply to LTC2604/LTC2604-1, LTC2614/
LTC2614-1, LTC2624/LTC2624-1.
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
Current Limiting
CODE = MIDSCALE
0.4
0.02
0
–0.02
VREF = VCC = 3V
–0.04
0.2
0
–0.2
VREF = VCC = 5V
–0.4
VREF = VCC = 5V
–0.06
2
0.6
VREF = VCC = 3V
0.04
CODE = MIDSCALE
0.8
VREF = VCC = 5V
0.06
Offset Error vs Temperature
3
OFFSET ERROR (mV)
0.08
ΔVOUT (V)
Load Regulation
1.0
ΔVOUT (mV)
0.10
–1
–2
–0.8
–0.10
–40 –30 –20 –10 0
10
IOUT (mA)
20
30
–1.0
–35
40
–25
–15
–5
5
IOUT (mA)
15
2604 G01
25
–3
–50
35
Zero-Scale Error vs Temperature
Gain Error vs Temperature
90
Offset Error vs VCC
2
0.2
OFFSET ERROR (mV)
GAIN ERROR (%FSR)
1.0
70
3
0.3
2.5
1.5
–10 10
30
50
TEMPERATURE (°C)
2604 G03
0.4
2.0
–30
2604 G02
3
ZERO-SCALE ERROR (mV)
0
VREF = VCC = 3V
–0.6
–0.08
1
0.1
0
–0.1
1
0
–1
–0.2
–2
0.5
0
–50
–0.3
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
2604 G04
–0.4
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
2604 G05
–3
2.5
3
3.5
4
VCC (V)
4.5
5
5.5
2604 G06
2604fd
5
LTC2604/LTC2614/LTC2624
TYPICAL PERFORMANCE CHARATERISTICS
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
Gain Error vs VCC
ICC Shutdown vs VCC
Large-Signal Settling
450
0.3
400
0.2
350
0.1
300
ICC (nA)
GAIN ERROR (%FSR)
0.4
0
–0.1
VOUT
0.5V/DIV
250
200
VREF = VCC = 5V
1/4-SCALE TO 3/4-SCALE
150
–0.2
100
–0.3
2.5μs/DIV
50
–0.4
2.5
3.5
3
4
VCC (V)
4.5
5
0
2.5
5.5
3.5
3
4
VCC (V)
4.5
5
2604 G07
2604 G09
5.5
2604 G08
Midscale Glitch Impulse
Power-On Reset Glitch
Power-On Reset to Midscale
VREF = VCC
VOUT
10mV/DIV
VCC
1V/DIV
12nV-s TYP
VOUT
10mV/DIV
2604 G10
2.5μs/DIV
2604 G11
250μs/DIV
Headroom at Rails
vs Output Current
500μs/DIV
Supply Current vs Logic Voltage
2604 G34
Exiting Power-Down to Midscale
2.0
5.0
VCC = 5V
SWEEP SCK, SDI
AND CS/LD
0V TO VCC
5V SOURCING
4.5
1.8
4.0
3.5
3.0
VCC = 5V
VREF = 2V
VOUT
0.5V/DIV
1.6
3V SOURCING
ICC (mA)
VOUT (V)
VCC
1V/DIV
VOUT
1V/DIV
4mV PEAK
CS/LD
5V/DIV
2.5
2.0
DACs A-C IN
POWER-DOWN MODE
1.4
CS/LD
5V/DIV
1.2
1.5
5V SINKING
1.0
1.0
3V SINKING
0.5
0
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
10
2604 G12
2.5μs/DIV
2604 G14
0.8
0
0.5
1
1.5 2 2.5 3 3.5
LOGIC VOLTAGE (V)
4
4.5
5
2604 G13
2604fd
6
LTC2604/LTC2614/LTC2624
TYPICAL PERFORMANCE CHARATERISTICS
(LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/LTC2624-1)
Hardware CLR
Hardware CLR to Midscale
Multiplying Frequency Response
0
VCC = 5V
VREF = 4.096V
CODE = FULL SCALE
VOUT
1V/DIV
VOUT
1V/DIV
–3
–6
–9
–12
dB
–15
CLR
5V/DIV
–18
–21
CLR
5V/DIV
–24
VCC = 5V
VREF (DC) = 2V
VREF (AC) = 0.2VP-P
CODE = FULL SCALE
–27
2604 G15
1μs/DIV
–30
2604 G35
1μs/DIV
–33
–36
1k
1M
10k
100k
FREQUENCY (Hz)
2604 G16
Output Voltage Noise,
0.1Hz to 10Hz
Short-Circuit Output Current vs
VOUT (Sourcing)
Short-Circuit Output Current vs
VOUT (Sinking)
0
50
V CC = 5.5V
V REF = 5.6V
CODE = 0
V OUT SWEPT 0V TO V CC
10mA/DIV
VOUT
10μV/DIV
0
1
2
3
4 5 6
SECONDS
7
8
9
–10
10mA/DIV
40
30
20
0
2604 G17
–20
–30
–40
10
10
V CC = 5.5V
V REF = 5.6V
CODE = FULL SCALE
V OUT SWEPT V CC TO 0V
–50
0
2
1
3
1V/DIV
4
5
6
0
1
2
3
1V/DIV
4
5
6
2604 G19
2604 G18
(LTC2604/LTC2604-1)
Integral Nonlinearity (INL)
32
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
24
INL vs Temperature
32
VCC = 5V
VREF = 4.096V
0.8
24
0.6
16
16
0
–8
0.2
INL (LSB)
DNL (LSB)
INL (LSB)
0.4
8
0
–0.2
–32
16384
32768
CODE
49152
65535
2604 G20
–1.0
INL (NEG)
–24
–0.8
0
0
–16
–0.6
–24
INL (POS)
8
–8
–0.4
–16
VCC = 5V
VREF = 4.096V
0
16384
32768
CODE
49152
65535
2604 G21
–32
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
2604 G22
2604fd
7
LTC2604/LTC2614/LTC2624
TYPICAL PERFORMANCE CHARATERISTICS
(LTC2604/LTC2604-1)
DNL vs Temperature
INL vs VREF
1.0
32
VCC = 5V
0.8 VREF = 4.096V
DNL vs VREF
1.5
VCC = 5.5V
24
1.0
0.6
16
DNL (POS)
0
–0.2
0.5
INL (POS)
8
INL (LSB)
0.2
DNL (LSB)
0.4
DNL (LSB)
VCC = 5.5V
0
–8
DNL (NEG)
INL (NEG)
DNL (POS)
0
DNL (NEG)
–0.5
–0.4
–16
–0.6
–1.0
–24
–0.8
–1.0
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
–32
90
1
0
2
3
VREF (V)
4
2604 G23
5
–1.5
0
1
2
3
VREF (V)
4
2604 G24
Settling to ±1LSB
5
2604 G25
Settling of Full-Scale Step
VOUT
100μV/DIV
VOUT
100μV/DIV
12.3μs
9.7μs
CS/LD
2V/DIV
CS/LD
2V/DIV
2604 G26
2μs/DIV
5μs/DIV
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2604 G27
VCC = 5V, VREF = 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
SETTLING TO ±1LSB
(LTC2614/LTC2614-1)
Integral Nonlinearity (INL)
8
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
6
Settling to ±1LSB
VCC = 5V
VREF = 4.096V
0.8
0.6
4
0.4
DNL (LSB)
INL (LSB)
2
0
–2
VOUT
100μV/DIV
0.2
0
CS/LD
2V/DIV
–0.2
–0.4
–4
–0.6
–6
–8
2μs/DIV
–0.8
0
4096
8192
CODE
12288
16383
2604 G28
–1.0
8.9μs
0
4096
8192
CODE
12288
16383
2604 G30
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2604 G29
2604fd
8
LTC2604/LTC2614/LTC2624
TYPICAL PERFORMANCE CHARATERISTICS
(LTC2624/LTC2624-1)
Integral Nonlinearity (INL)
2.0
Differential Nonlinearity (DNL)
1.0
VCC = 5V
VREF = 4.096V
1.5
0.6
6.8μs
0.4
0.5
DNL (LSB)
INL (LSB)
VCC = 5V
VREF = 4.096V
0.8
1.0
0
–0.5
VOUT
1mV/DIV
0.2
0
CS/LD
2V/DIV
–0.2
–0.4
–1.0
–0.6
–1.5
–2.0
Settling to ±1LSB
2μs/DIV
–0.8
0
1024
2048
CODE
3072
4095
–1.0
0
1024
2604 G31
2048
CODE
3072
4095
2604 G33
VCC = 5V, VREF = 4.096V
1/4-SCALE TO 3/4-SCALE STEP
RL = 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
2604 G32
PIN FUNCTIONS
GND (Pin 1): Analog Ground.
REF LO (Pin 2): Reference Low. The voltage at this pin
sets the zero scale (ZS) voltage of all DACs. This pin can
be raised up to 1V above ground at VCC = 5V or 100mV
above ground at VCC = 3V.
REF A, REF B, REF C, REF D (Pins 3, 6, 12, 15): Reference Voltage Inputs for each DAC. REF x sets the full scale
voltage of the DACs. 0V ≤ REF x ≤ VCC.
VOUT A to VOUT D (Pins 4, 5, 13, 14): DAC Analog Voltage
Outputs. The output range is from REF LO to REF x.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When
CS/LD is low, SCK is enabled for shifting data on SDI into
the register. When CS/LD is taken high, SCK is disabled
and the specified command (see Table 1) is executed.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 9): Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK.
The LTC2604/LTC2604-1, LTC2614/LTC2614-1, LTC2624/
LTC2624-1 accept input word lengths of either 24 or
32 bits.
SDO (Pin 10): Serial Interface Data Output. This pin is
used for daisy-chain operation. The serial output of the
shift register appears at the SDO pin. The data transferred
to the device via the SDI pin is delayed 32 SCK rising
edges before being output at the next falling edge. SDO
is an active output and does not go high impedance, even
when CS/LD is taken to a logic high level.
CLR (Pin 11): Asynchronous Clear Input. A logic low at
this level-triggered input clears all registers and causes
the DAC voltage outputs to drop to 0V for the LTC2604/
LTC2614/LTC2624. A logic low at this input sets all registers
to midscale code and causes the DAC voltage outputs to
go to midscale for the LTC2604-1/LTC2614-1/LTC2624-1.
CMOS and TTL compatible.
VCC (Pin 16): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V.
2604fd
9
LTC2604/LTC2614/LTC2624
BLOCK DIAGRAM
VCC
GND
1
REF LO
2
REF A
16
REF D
15
DAC B
5
REF B
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
VOUTB
VOUT D
DAC D
INPUT
REGISTER
DAC
REGISTER
DAC A
4
INPUT
REGISTER
DAC
REGISTER
VOUTA
INPUT
REGISTER
3
DAC C
14
VOUT C
13
REF C
12
CLR
11
6
CONTROL
LOGIC
CS/LD
7
SDO
DECODE
10
SCK
SDI
9
32-BIT SHIFT REGISTER
8
2604 BD
TIMING DIAGRAM
t1
t2
SCK
t3
1
t6
t4
2
3
23
24
t10
SDI
t5
t7
CS/LD
t8
SDO
2604 F01
Figure 1
OPERATION
Power-On Reset
The LTC2604/LTC2614/LTC2624 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2604-1/
LTC2614-1/LTC2624-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2604/
LTC2614/LTC2624 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
2604fd
10
LTC2604/LTC2614/LTC2624
OPERATION
Power Supply Sequencing
Table 1.
The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range – 0.3V ≤ REF x ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken
to observe these limits during power supply turn-on and
turn-off sequences, when the voltage at VCC (Pin 16) is
in transition.
Transfer Function
The digital-to-analog transfer function is
k VOUT(IDEAL) = [REF x – REFLO]+REFLO
2N where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF
A, REF B, REF C and REF D (Pins 3, 6, 12 and 15).
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
COMMAND*
C3 C2 C1 C0
0
0
0
0 Write to Input Register n
0
0
0
1 Update (Power Up) DAC Register n
0
0
1
0 Write to Input Register n, Update (Power Up) All n
0
0
1
1 Write to and Update (Power Up) n
0
1
0
0 Power Down n
1
1
1
1 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0
0
0
0 DAC A
0
0
0
1 DAC B
0
0
1
0 DAC C
0
0
1
1 DAC D
1
1
1
1 All DACs
*Command and address codes not shown are reserved and should not
be used.
(LTC2604, LTC2614 and LTC2624 respectively). Data can
only be transferred to the device when the CS/LD signal
is low. The rising edge of CS/LD ends the data transfer
and causes the device to carry out the action specified in
the 24-bit input word. The complete sequence is shown
in Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
INPUT WORD (LTC2604)
COMMAND
C3
C2
C1 C0
ADDRESS
A3
A2
A1
DATA (16 BITS)
A0
D15 D14 D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1 D0
MSB
LSB
2604 TBL01
INPUT WORD (LTC2614)
COMMAND
C3
C2
C1 C0
ADDRESS
A3
A2
A1
DATA (14 BITS + 2 DON’T-CARE BITS)
A0
D13 D12 D11 D10 D9
D8 D7 D6 D5
D4
D3
D2
D1 D0
MSB
X
X
LSB
2604 TBL02
INPUT WORD (LTC2624)
COMMAND
C3
C2
C1 C0
ADDRESS
A3
A2
A1
DATA (12 BITS + 4 DON’T-CARE BITS)
A0
D11 D10 D9
MSB
D8 D7 D6 D5
D4
D3
D2
D1 D0
X
X
X
X
LSB
2604 TBL03
2604fd
11
LTC2604/LTC2614/LTC2624
OPERATION
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path
and registers are shown in the block diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don’t-care bits are transferred to the device first, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisychain operation, and is also available to accommodate
microprocessors which have a minimum word width of
16 bits (2 bytes).
Daisy-Chain Operation
The serial output of the shift register appears at the SDO
pin. Data transferred to the device from the SDI input is
delayed 32 SCK rising edges before being output at the
next SCK falling edge.
The SDO output can be used to facilitate control of multiple
serial devices from a single 3-wire serial port (i.e., SCK,
SDI and CS/LD). Such a “daisy-chain” series is configured
by connecting SDO of each upstream device to SDI of the
next device in the chain. The shift registers of the devices
are thus connected in series, effectively forming a single
input shift register which extends through the entire
chain. Because of this, the devices can be addressed and
controlled individually by simply concatenating their input
words; the first instruction addresses the last device in
the chain and so forth. The SCK and CS/LD signals are
common to all devices in the series.
In use, CS/LD is first taken low. Then the concatenated
input data is transferred to the chain, using SDI of the
first device as the data input. When the data transfer is
complete, CS/LD is taken high, completing the instruction
sequence for all devices simultaneously. A single device
can be controlled by using the no-operation command
(1111) for the other devices in the chain.
Power-Down Mode
For power-constrained applications, power-down mode can
be used to reduce the supply current whenever less than
four outputs are needed. When in power-down, the buffer
amplifiers, bias circuits and reference inputs are disabled,
and draw essentially zero current. The DAC outputs are
put into a high-impedance state, and the output pins are
passively pulled to ground through individual 90k resistors. Input- and DAC-register contents are not disturbed
during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply current is reduced by
approximately 1/4 for each DAC powered down. The effective resistance at REF x (pins 3, 6, 12 and 15) are at
high-impedance input (typically > 1GΩ) when the corresponding DACs are powered down.
Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than four DACs are in a powered-down state prior to
the update command, the power-up delay time is 5μs. If on
the other hand, all four DACs are powered down, then the
main bias generation circuit block has been automatically
shut down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power up delay time is
12μs (for VCC = 5V) or 30μs (for VCC = 3V).
Voltage Outputs
Each of the four rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
2604fd
12
X
X
SDI
SDO
SCK
CS/LD
1
X
X
2
3
X
4
X
X
C3
SDI
X
5
X
DON’T CARE
X
C2
2
C1
3
X
X
6
X
X
7
COMMAND WORD
1
SCK
CS/LD
C0
X
X
4
8
A3
A2
6
A1
7
A0
8
D15
9
D14
10
D12
12
D11
13
D10
14
24-BIT INPUT WORD
D13
11
D9
15
D7
17
DATA WORD
D8
16
D6
18
D5
19
C1
11
C2
C1
COMMAND WORD
C2
10
C0
C0
A3
A3
A2
14
A1
15
A2
A1
ADDRESS WORD
13
A0
A0
16
17
D15
D15
PREVIOUS 32-BIT INPUT WORD
12
D14
D14
18
t2
t8
D9
D9
t4
23
PREVIOUS D15
t3
17
D10
D10
22
SDO
t1
D11
D11
21
D15
D12
D12
20
SDI
SCK
D13
D13
19
Figure 2b. LTC2604 32-Bit Load Sequence
LTC2614 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t Care Bits
C3
C3
9
Figure 2a. LTC2604 24-Bit Load Sequence (Minimum Input Word)
LTC2614 SDI Data Word: 14-Bit Input Code + 2 Don’t Care Bits
LTC2624 SDI Data Word: 12-Bit Input Code + 4 Don’t Care Bits
ADDRESS WORD
5
24
25
D7
D3
21
18
D7
D6
D6
26
22
D2
PREVIOUS D14
D14
D8
DATA WORD
D8
D4
20
27
D5
D5
D1
23
28
D4
D4
D0
24
D3
D3
29
2604 F02a
D2
D2
30
D1
D1
31
2604 F02b
CURRENT
32-BIT
INPUT WORD
D0
D0
32
LTC2604/LTC2614/LTC2624
OPERATION
2604fd
13
LTC2604/LTC2614/LTC2624
OPERATION
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The GND pin functions as a return path for power supply currents in the device and should be connected to
analog ground. Resistance from the GND pin to system
star ground should be as low as possible. When a zero
scale DAC output voltage of zero is desired, the REFLO pin
(pin 2) should be connected to system star ground.
The amplifiers are stable driving capacitive loads of up
to 1000pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 3b. Similarly, limiting can occur near full scale when
the REF pins are tied to VCC. If REF x = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 3c. No full-scale
limiting can occur if REF x is less than VCC – FSE.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
VREF = VCC
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
OUTPUT
VOLTAGE
(c)
0
NEGATIVE
OFFSET
0V
INPUT CODE
32,768
INPUT CODE
65,535
(a)
2600 F03
(b)
Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
2604fd
14
LTC2604/LTC2614/LTC2624
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2604fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2604/LTC2614/LTC2624
TYPICAL APPLICATION
5V
5V
1k
1k
10k
10k
0.1μF
10k
0.01μF
0.1μF
10k
20Ω
49.9Ω
70MHz IN
47pF
ZC830
0.01μF
OUT
10pF
49.9Ω
20pF
49.9Ω
ZC830
DAC A
DAC B
DAC C
DAC D
OPTIONAL
20k
0.1μF
OPTIONAL
20k
0.1μF
CS/LD
SCK
SDI
LTC2604
5V
5V
LO
2.74k
1%
100k
2.74k
1%
100k
2.74k
1%
90°
2.74k
1%
I+Q
MODULATOR
Q INPUT
I INPUT
5V
5V
2.74k
1%
0°
2.74k
1%
RF
*ZETEX
2.74k
1%
2.74k
1%
2604 F04
(516) 543-7100
Figure 4. Using DAC A and DAC B for Nearly Continuous Attenuation Control and DAC C and
DAC D to Trim for Minimum LO Feedthrough in a Mixer
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1654
Dual 14-Bit Rail-to-Rail VOUT DAC
Programmable Speed/Power
LTC1655/LTC1655L
Single 16-Bit VOUT DAC with Serial Interface in SO-8
VCC = 5V(3V), Low Power, Deglitched
LTC1657/LTC1657L
Parallel 5V/3V 16-Bit VOUT DAC
Low Power, Deglitched, Rail-to-Rail VOUT
LTC1660/LTC1665
Octal 8-Bit/10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1821
Parallel 16-Bit Voltage Output DAC
Precision 16-Bit Settling in 2μs for 10V Step
LTC2600/LTC2610/LTC2620
Octal 16-Bit/14-Bit/12-Bit Rail-to-Rail DACs in 16-Lead SSOP
250μA per DAC, 2.5V to 5.5V Supply Range
LTC2602/LTC2612/LTC2622
Dual 16-Bit/14-Bit/12-Bit Rail-to-Rail DACs in 8-Lead MSOP
300μA per DAC, 2.5V to 5.5V Supply Range
2604fd
16 Linear Technology Corporation
LT 0309 REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004