MC74VHCT86A Quad 2-Input XOR Gate / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHCT86A is an advanced high speed CMOS 2−input Exclusive−OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high−voltage power supply. The MC74VHCT86A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows it to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. • • • • • • • • • • • High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V These Devices are Pb−Free and are RoHS Compliant LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 14−LEAD SOIC D SUFFIX CASE 751A 14−LEAD TSSOP DT SUFFIX CASE 948G PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8 1 2 3 4 5 6 7 A1 B1 Y1 A2 B2 Y2 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. FUNCTION TABLE Inputs Output A B Y L L H H L H L H L H H L ORDERING INFORMATION 1 3 2 Device Y1 MC74VHCT86ADR2G 4 6 5 Y2 9 Y = A)B 8 10 Package Shipping SOIC−14 2500 / Tape & (Pb−Free) Reel MC74VHCT86ADTR2G TSSOP−14 2500 / Tape & Reel (Pb−Free) Y3 12 11 13 © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 3 http://onsemi.com Y4 1 Publication Order Number: MC74VHCT86A/D MC74VHCT86A MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage Parameter – 0.5 to + 7.0 V Vin DC Input Voltage – 0.5 to + 7.0 V Vout DC Output Voltage – 0.5 to + 7.0 – 0.5 to VCC + 0.5 V VCC = 0 High or Low State IIK Input Diode Current − 20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage VCC 2.0 5.5 V DC Input Voltage VIN 0.0 5.5 V VOUT 0.0 0.0 5.5 VCC V TA −55 +85 °C tr , tf 0 0 100 20 ns/V DC Output Voltage VCC = 0 High or Low State Operating Temperature Range Input Rise and Fall Time VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V, Measured in SOIC Package) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V VOLV Quiet Output Minimum Dynamic VOL − 0.3 − 0.8 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 2 MC74VHCT86A DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions Min 1.2 2.0 2.0 VIH Minimum High−Level Input Voltage 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL Maximum Low−Level Output Voltage VIN = VIH or VIL TA ≤ 85°C TA = 25°C (V) Typ Max Min 1.2 2.0 2.0 3.0 4.5 2.9 4.4 VIN = VIH or VIL IOH = −4mA IOH = −8mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50μA 3.0 4.5 VIN = VIH or VIL IOL = 4mA IOL = 8mA Min 0.53 0.8 0.8 3.0 4.5 Max 1.2 2.0 2.0 0.53 0.8 0.8 VIN = VIH or VIL IOH = −50μA TA ≤ 125°C Max V 0.53 0.8 0.8 2.9 4.4 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V V 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V V IIN Maximum Input Leakage Current VIN = 5.5V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 μA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 2.0 20 40 μA ICCT Quiescent Supply Current Input: VIN = 3.4V 5.5 1.35 1.50 1.65 mA IOPD Output Leakage Current VOUT = 5.5V 0.0 0.5 5.0 10 μA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C Symbol Parameter Propagation Delay, A or B to Y tPLH, tPHL Cin Test Conditions Min TA = − 40 to 85°C Typ Max Min Max Unit ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF 7.0 9.5 11.0 14.5 1.0 1.0 13.0 16.5 VCC = 5.0 ± 0.5V CL = 15pF CL = 50pF 4.8 6.3 6.8 8.8 1.0 1.0 8.0 10.0 4 10 Input Capacitance 10 pF Typical @ 25°C, VCC = 5.0V 18 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. TEST POINT 3.0V A or B OUTPUT 50% DEVICE UNDER TEST GND tPLH Y tPHL CL* VOH 50% VCC VOL *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit http://onsemi.com 3 MC74VHCT86A MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 14 13 12 11 10 8 2 3 4 8 6 7 VHCT 86A ALYWG G VHCT86AG AWLYWW* 1 9 5 6 7 1 2 14−LEAD SOIC D SUFFIX CASE 751A 3 4 5 14−LEAD TSSOP DT SUFFIX CASE 948G 14 13 12 11 10 9 8 6 7 74VHCT86A ALYWG* 1 2 3 4 5 14−LEAD SOEIAJ M SUFFIX CASE 965 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHCT86A PACKAGE DIMENSIONS TSSOP−14 CASE 948G ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 5 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHCT86A PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M B M 7 1 G F R X 45 _ C −T− SEATING PLANE D 14 PL 0.25 (0.010) M T B J M K S A DIM A B C D F G J K M P R S MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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