Gennum GS1540 Hdtv serial digital non-equalizing receiver Datasheet

HD-LINX ™ GS1540
HDTV Serial Digital
Non-Equalizing Receiver
PRELIMINARY DATA SHEET
DESCRIPTION
• SMPTE 292M compliant
The GS1540 is a high performance integrated Receiver
designed for HDTV component signals, conforming to the
SMPTE 292M standard. The GS1540 includes adjustment
free clock and data recovery, and 1:20 serial to parallel
conversion.
• 1.485 and 1.485/1.001Gb/s operation
• integrated adjustment-free reclocker
• 1:20 serial to parallel conversion
• selectable reclocked serial output
The Clock and Data Recovery stage was designed to
automatically recover the embedded clock signal and
retime the data from SMPTE 292M compliant digital video
signals. There is also a selectable reclocked serial data
buffer output and the ability to bypass the reclocker stage.
• reclocker BYPASS capability
• LOCK detect
• input jitter indicator (IJI)
• 20 bit output
• 74.25MHz or 74.25/1.001MHz clock output
• single +5.0V power supply
• minimal component count for HD SDI receive
solutions
APPLICATIONS
SMPTE 292M Serial
Digital Interfaces for Production
Switchers, Master Control Switchers, NLE's, and VTR's.
A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.
The Serial to Parallel conversion stage provides 1:20 S/P
conversion.
The GS1540 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
ORDERING INFORMATION
BUFFER1
DDI
(opt) DDI_VTT
DDI
PART NUMBER
PACKAGE
TEMPERATURE
GS1540-CQR
128 pin MQFP
0°C to 70°C
SDOint
SDOint
RECLOCKER
CORE
DATA_OUT[19:0]
S/P CONVERTER
PCLK_OUT
BUFFER2
SDO
SDO
SDO_EN
SIMPLIFIED BLOCK DIAGRAM
Revision Date: August 2000
Document No. 522 - 27- 00
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS1540
FEATURES
LBCONT
GO1515
LFA LFS
LFS
PLCAP PLCAP IJI
VCO
CHARGE
PUMP
PHASE
LOCK
LOGIC
PLL_LOCK
GS1540
PHASE
DETECTOR
PCLK_OUT
S/P CONVERTER
CORE
DATA_OUT[19:0]
MUTE
BUFFER2
BYPASS
MUX
BUFFER1
DDI
(opt) DDI_VTT
SDO
SDO
DDI
RECLOCKER CORE
BYPASS
SDO_EN
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise indicated.
PARAMETER
VALUE
Supply Voltage (VS)
Input Voltage Range (any input)
5.5V
VEE – 0.5 < VIN < VCC+ 0.5
0°C ≤ TA ≤ 70°C
Operating Temperature Range
Storage Temperature Range
-40°C ≤ TS ≤ 150°C
Power Dissipation (VCC = 5.25V)
1.85W
Lead Temperature (soldering 10 seconds)
260°C
Input ESD Voltage
TBD
Junction Temperature
125°C
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DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s.
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
TEST LEVEL
Operating range
VCC
4.75
5.00
5.25
V
1
Power Consumption
VCC = 5; TA = 25°c
PD
-
1050
-
mW
5
Supply Current
VCC = 5; TA = 25°C
IS
-
210
-
mA
1
VCM
3.75
4.0
4.25
V
5
-
4.0
-
V
1
Output CM Voltage (SDO, SDO)
Input DC Voltage (DDI, DDI)
Serial Inputs (DDI, DDI)
Differential mode
VSID
100
-
1000
mV
7
Common mode
VCM
2.5+VSID/2
-
VCC-VSID/2
V
7
High Level Input Voltage (BYPASS)
VCC = 5, TA = 25°C
VIH
2.0
-
-
V
1
Low Level Input Voltage (BYPASS)
VCC = 5, TA = 25°C
VIL
-
-
0.8
V
1
High Level Output Voltage
VCC = 5, TA = 25°C,
VOH
2.4
-
3.0
V
1
(D[19:0], PCLK)
ISOURCE = 1.0mA
Low Level Output Voltage
VCC = 5, TA = 25°C,
VOL
-
-
0.4
V
1
VOH
3.0
-
-
V
1
VOL
-
-
0.4
V
1
(D[19:0], PCLK)
ISINK = 1.0mA
High Level Output Voltage
(PLL_LOCK)
VCC = 5, TA = 25°C,
Low Level Output Voltage
VCC = 5, TA = 25°C,
(PLL_LOCK)
GS1540
Positive Supply Voltage
ISOURCE = 200µA
ISINK = 500µA
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
AC ELECTRICAL CHARACTERISTICS - RECLOCKER STAGE
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
Serial Input –
SYMBOL
MIN
TYP
MAX
UNITS
TEST
LEVEL
BRSDI
1.485/1.001
1.485
-
Gb/s
1
JTOL
-
0.5
-
UI
1
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
TALOCK
-
200
250
ms
7
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
TSLOCK
-
2
4
µs
7
CONDITIONS
SMPTE 292M
Data Rate
Serial Input –
Sinewave Modulation (p – p)
Jitter Tolerance
Phase Lock Time Asynchronous
Phase Lock Time Synchronous
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AC ELECTRICAL CHARACTERISTICS - RECLOCKER STAGE (Continued)
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
TEST
LEVEL
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
-
12
-
ms
7
Phase Lock/Unlock Timer
Loop bandwidth approximately
1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).
60
-
-
µs
7
VSDO
320
400
480
mV
1
tR-SDO, tF-SDO
-
150
270
ps
7
-
-
100
ps
7
-
10
-
ps
2
-
1.4
-
MHz
7
-
-
0.1
dB
7
(1nF PLCAP)
Serial Output – Signal Swing
Serial Digital Output –
Rise and Fall Time
Serial Digital Output –
Rise and Fall Time Mismatch
Serial Digital Output –
Intrinsic Jitter
(RMS Jitter for clean PRN 223 – 1
input on DDI/DDI inputs)
Loop bandwidth
@ 0.2UI jitter modulation
tIJ
LBCONT floating
Jitter peaking
AC ELECTRICAL CHARACTERISTICS - SERIAL TO PARALLEL STAGE
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
TEST LEVEL
SMPTE 292M
PCLK_OUT
74.25/1.001
74.25
-
MHz
1
Clock Pulse Width Low
15pF load
tPWL
5
7
-
ns
7
Clock Pulse Width High
15pF load
tPWH
5
6
-
ns
7
Output signal Rise/Fall time
15pF load
tr, tf
-
2000
4000
ps
7
Output Signal Rise/Fall Time Matching
15pF load
trfm
-
1000
2000
ps
7
Output Setup Time
15pF load
tOD
4
6
-
ns
2
Output Hold Time
15pF load
tOH
5
7
-
ns
2
Parallel Output Clock Frequency
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
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GS1540
Carrier Detect Timer
NC
PLL_LOCK
NC
PLCAP
NC
NC
PLCAP
NC
VCO
NC
VCO
NC
NC
IJI
LFS
NC
NC
NC
LFS
DM
DM
NC
NC
DFT_VEE
LFA_VEE
LBCONT
LFA
LFA_VCC
NC
NC
NC
NC
NC
NC
NC
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SDO
SDO
SDO_VEE
SDO_EN
SDO_VCC
NC
NC
NC
NC
NC
NC
NC
NC
SP_VCC
SP_VCC
SP_VEE
SP_VEE
PCLK_OUT
PCLK_VCC
PCLK_VEE
NC
NC
PIN CONNECTIONS
NC
102
GS1540
TOP
VIEW
NC
5
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
GENNUM CORPORATION
NC
NC
BYPASS
DDI_VTT
NC
DDI
DDI
PD_VCC
NC
PDSUB_VEE
PD_VEE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
DATA_OUT[14]
NC
NC
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
NC
NC
DATA_OUT[9]
DATA_OUT[8]
DATA_OUT[7]
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
NC
NC
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GS1540
PIN DESCRIPTIONS
NUMBER
SYMBOL
1, 2, 3, 4, 6, 5,
7, 8, 9, 10, 11,
12, 13, 14, 15,
16, 22, 23, 24,
25, 26, 27, 28,
29, 37, 38, 39,
40, 51, 52, 57,
58, 65, 66, 67,
68, 69, 70, 71,
77, 78, 82, 83,
84, 87, 88, 90,
92, 94, 95, 97,
99, 100, 101,
102, 103, 104,
107, 111, 114,
115, 116, 117,
118, 119, 120,
121, 122, 123,
124, 125, 126,
127, 128
LEVEL
TYPE
NC
DESCRIPTION
No Connect. Leave these pins floating.
GS1540
17, 18
SDO, SDO
ECL/PECL
compatible
Output
Serial Data Output. Differential outputs. 50Ω pull up resistors are
included on chip.
Ensure that the trace length between the GS1540 and the GS1508
Cable driver is kept to a minimum and that a PCB trace characteristic
impedance of 50Ω is maintained between the GS1508 and the
GS1540. 50Ω end termination is recommended.
19
SDO_VEE
Power
Input
Negative Supply. Most negative power supply connection for serial
data output stage.
20
SDO_EN
Power
Input
Control Signal Input. Used to enable or disable the serial output stage.
If a loop through function is not required, then this pin should be tied
to the most positive power supply voltage.
When SDO_EN is tied to the most negative power supply voltage, the
SDO, SDO outputs are enabled.
When SDO_EN is tied to the most positive power supply voltage, the
SDO, SDO outputs are disabled.
21
SDO_VCC
Power
Input
Positive Supply. Most positive power supply connection for serial data
output stage.
30, 31
SP_VCC
Power
Input
Positive Supply. Most positive power supply connection for serial to
parallel converter stage.
32, 33
SP_VEE
Power
Input
Negative Supply. Most negative power supply connection for the
parallel output stage.
34
PCLK_OUT
TTL
Output
35
PCLK_VCC
Power
Input
Positive Supply. Most positive supply connection for parallel clock
output stage.
36
PCLK_VEE
Power
Input
Negative Supply. Most negative power supply connection for parallel
clock output stage.
DATA_OUT[19:0]
TTL
Output
41, 42, 43, 44,
45, 46, 47, 48,
49, 50, 53, 54,
55, 56, 59, 60,
61, 62, 63, 64
Output Clock. The device uses PCLK_OUT for clocking the output
data stream from DATA_OUT[19:0]. This clock is also used to clock
the data into the GS1500 HDTV Deformatter, or GS1510 HDTV
Deformatter.
Parallel Data Output Bus. The device outputs a 20 bit parallel data
stream running at 74.25 or 74.25/1.001MHz on DATA_OUT[19:0].
DATA_OUT[19] is the MSB and DATA_OUT[0] is the LSB.
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PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
LEVEL
TYPE
DESCRIPTION
72
LFA_VCC
Power
Input
73
LFA
Analog
Output
74
LBCONT
Analog
Input
Control Signal Input. Used to provide electronic control of Loop
Bandwidth.
75
LFA_VEE
Power
Input
Negative Supply. Loop filter most negative power supply connection.
76
DFT_VEE
Power
Input
Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340µA.
79, 80
DM, DM
Analog
Output
Positive Supply. Loop filter most positive power supply connection.
Control Signal Output. Control voltage for GO1515 VCO.
These pins must be floating for normal operation.
81, 85
LFS, LFS
Analog
Input
86
IJI
Analog
Output
Status Signal Output. Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
89
VCO
Analog
Input
Control Signal Input. Input pin is AC coupled to ground using a 50Ω
transmission line.
91
VCO
Analog
Input
Control Signal Input. Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
Loop Filter Connections.
This pin must be connected to the GO1515 VCO output pin via a 50Ω
transmission line.
93, 96
PLCAP, PLCAP
Analog
Input
PLL_LOCK
TTL
Output
98
Control Signal Input. Phase lock detect time constant capacitor.
Status Indicator Signal. This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
105
BYPASS
TTL
Input
Control Signal Input. Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
106
DDI_VTT
Analog
Input
Bias Input. Selectable input for interfacing standard ECL outputs
requiring 50Ω pull down to VTT power supply for a seamless interface.
See Typical Application Circuit for recommended circuit application.
108, 109
DDI, DDI
Differential
ECL/PECL
Input
Digital Data Input Signals. Digital input signals from a GS1504
Equalizer or HD crosspoint switch.
Because of on chip 50Ω termination resistors, a PCB trace
characteristic impedance of 50Ω is recommended.
110
PD_VCC
Power
Positive Supply. Phase detector most positive power supply
connection.
112
PDSUB_VEE
Power
Input
Substrate Connection. Connect to phase detector’s most negative
power supply.
113
PD_VEE
Power
Input
Negative Supply. Phase detector most negative power supply
connection.
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GS1540
Test Signal. Used for manufacturing test only.
INPUT/OUTPUT CIRCUITS
PD_VCC
5k
PD_VCC
10k
PLCAP
GS1540
20k
PLCAP
20k
100µA
PD_VEE
DDI
50
DDI
50
PD_VEE
DDI_VTT
Fig. 4 PLCAP/PLCAP Output Circuit
Fig. 1 DDI/DDI Input Circuit
PD_VCC
5k
LFA_VCC
5k
500
LFA
10k
10k
40
40
31p
5mA
VCO
100µA
PD_VEE
50
LFA_VEE
VCO
Fig. 5 LFA Circuit
Fig. 2 VCO/VCO Input Circuit
LFA_VCC
PD_VCC
25k
10k
10k
DM
DM
LFS
400µA
85µA
LFA_VEE
DFT_VEE
Fig. 6 LFS Output Circuit
Fig. 3 DM/DM Output Circuit
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LFA_VCC
10k
PD_VCC
5k
16k
GS1540
LFS
100µA
+
-
BYPASS
V = 2.4V
100µA
100µA
100µA
100µA
LFA_VEE
PD_VEE
Fig. 7 LFS Input Circuit
Fig. 10 BYPASS Circuit
PD_VCC
LFA_VCC
10k
20k
LBCONT
PLL_LOCK
5k
PD_VEE
LFA_VEE
Fig. 8 PLL_LOCK Output Circuit
Fig. 11 LBCONT Circuit
PD_VCC
10k
SP_VCC
IJI
5k
100
D[19:0]
VCC
30k A
27k
SP_VEE
PD_VEE
Fig. 9 IJI Output Circuit
Fig. 12 D[19:0] Output Circuit
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DETAILED DESCRIPTION
The GS1540 is a single standard receiver for serial digital
HDTV signals at 1.485Gb/s and 1.485/1.001Gb/s.
PCLK_VCC
UNIQUE SLEW PHASE LOCK LOOP (S-PLL):
PCLK
27k
PCLK_VEE
Fig. 13 PCLK Output Circuit
PHASE (UI)
0.2
SDO_VCC
SDO_EN
INPUT
0.1
OUTPUT
0.0
20k
SLEW PLL RESPONSE
2k
0.2
PHASE (UI)
SDO_VEE
Fig. 14 SDO_EN Circuit
INPUT
0.1
OUTPUT
0.0
LINEAR (CONVENTIONAL) PLL RESPONSE
Fig. 16 PLL Characteristics
Slew PLLs offer several advantages such as excellent noise
immunity. Because of the infinite bandwidth for an infinitely
small input jitter modulation (or jitter introduced by VCO),
the loop corrects for that immediately thus the small signal
noise of the VCO is cancelled. The GS1540 uses a very
clean, external VCO called the GO1515 (refer to the
GO1515 Data Sheet for details). In addition, the bi-level
digital phase detector provides constant loop bandwidth
that is predominantly independent of the data transition
density. The loop bandwidth of a conventional tri-stable
charge pump drops with reducing data transitions. During
pathological signals, the data transition density reduces
from 0.5 to 0.05, but the slew PLL’s performance essentially
remains unchanged.
SDO_VCC
50
50
SDO
SDO
SDO_VEE
Fig. 15 Serial Output Stage Circuit
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GS1540
A unique feature of the GS1540 is the innovative slew phase
lock loop (S-PLL). When a step phase change is applied to
the PLL, the output phase gains constant rate of change
with respect to time. This behaviour is termed slew.
Figure 16 shows an example of input and output phase
variation over time for slew and linear (conventional) PLLs.
Since the slewing is a nonlinear behavior, the small signal
analysis cannot be done in the same way as the standard
PLL. However, it is still possible to plot input jitter transfer
characteristics at a constant input jitter modulation.
100
DIGITAL INPUT BUFFER
The input buffer is a self-biased circuit. On-chip 50Ω
termination resistors provide a seamless interface for other
HD-LINX™ products such as the GS1504 Adaptive Cable
Equalizer.
PHASE DETECTOR
The phase detector portion of the slew PLL used in the
GS1540 is a bi-level digital phase detector. It indicates
whether the data transition occurred before or after with
respect to the falling edge of the internal clock. When the
phase detector is locked, the data transition edges are
aligned to the falling edge of the clock. The input data is
then sampled by the rising edge of the clock, as shown in
Figure 17. In this manner, the allowed input jitter is 1UI p-p
in an ideal situation. However, due to setup and hold time,
the GS1540 typically achieves 0.5UI p-p input jitter
tolerance without causing any errors in this block. When the
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
PHASE ALIGNMENT
EDGE
RE-TIMING
EDGE
IN-PHASE CLOCK
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
CCP1, which is connected between LFS and LFS. The other
capacitor, CCP2 between LFS and LFA_GND is used to
remove common mode noise. Both CCP1 and CCP2 should
be the same value. The second function of the charge
pump is to provide a binary control voltage to the VCO
depending upon the phase detector output. The output pin,
LFA controls the VCO. Internally there is a 500Ω pull-up
resistor, which is driven with a 100µA current called ΙP.
Another analog current ΙF, with 5mA maximum drive
proportional to the voltage across the CCP1, is applied at the
same node. The voltage at the LFA node is
VLFA_VCC - 500(ΙP+ΙF) at any time.
Because of the integrator, ΙF changes very slowly whereas
ΙP could change at the positive edge of the data transition
as often as a clock period. In the locked position, the
average voltage at the LFA (VLFA_VCC – 500(ΙP/2+ΙF) is such
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since ΙP is changing all the time between
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1540 over process, power supply and temperature.
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, it is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x ΙP/2.
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x ΙP/2.
0.5UI
INPUT DATA
WITH JITTER
LBCONT
OUTPUT DATA
Fig. 17 Phase Detector Characteristics
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
The LBCONT pin is used to adjust the loop bandwidth by
externally changing the internal charge pump current. For
maximum loop bandwidth, connect LBCONT to the most
positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (RPULL-UP). For
low loop bandwidth, leave LBCONT floating. The formula
below shows the loop bandwidth for various configurations.
( 25kΩ + R PULL – UP )
LBW = LBW NOMINAL × ----------------------------------------------------( 5kΩ + R PULL – UP )
where LBW nominal is the loop bandwidth when LBCONT is
left floating.
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GENNUM CORPORATION
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GS1540
Because most of the PLL circuitry is digital, it is more like
other digital systems which are generally more robust than
their analog counterparts. Additionally, signals like DM/DM
which represent the internal functionality can be generated
without adding additional artifacts. Thus, system debugging
is also possible with these features. The complete slew PLL
is made up of several blocks including the phase detector,
the charge pump and an external Voltage Controlled
Oscillator (VCO).
INPUT JITTER INDICATOR (IJI)
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index.
This signal indicates the amount of excessive jitter (beyond
the quadrature clock window 0.5UI), which occurs beyond
the quadrature clock window (see Figure 18). All the input
data transitions occurring outside the quadrature clock
window, will be captured and filtered by the low pass filter
as mentioned in the Phase Lock section. The running time
average of the ratio of the transitions inside the quadrature
clock and outside the quadrature is available at the
PLCAP/PLCAP pins. A signal, IJI, which is the buffered
signal available at the PLCAP is provided so that loading
does not effect the filter circuit. The signal at IJI is
referenced with the power supply such that the factor
VIJI /V CC is a constant over process and power supply for a
given input jitter modulation. The IJI signal has 10kΩ output
impedance. Figure 19 shows the relationship of the IJI
signal with respect to the sine wave modulated input jitter.
PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock (the clock whose
falling edge is aligned to the data transition) by 166ps
(0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the
PLL is locked, the falling edge of the in-phase clock is
aligned with the data edges as shown in Figure 18. The
quadrature clock is in a logic high state in the vicinity of
input data transitions. The quadrature clock is sampled and
latched by positive edges of the data transitions. The
generated signal is low pass filtered with an RC network.
The R is an on-chip 20kΩ resistor and CPL is an external
capacitor (recommended value 10nF). The time constant is
about 67µs, or more than a video line.
PHASE ALIGNMENT
EDGE
P-P SINE WAVE JITTER IN UI
IJI VOLTAGE
0.00
4.75
0.15
4.75
0.30
4.75
0.39
4.70
0.45
4.60
0.48
4.50
0.52
4.40
0.55
4.30
0.58
4.20
0.60
4.10
0.63
3.95
RE-TIMING
EDGE
IN-PHASE CLOCK
0.5UI
INPUT DATA
WITH JITTER
0.25UI
QUADERATURE
CLOCK
PLCAP SIGNAL
5.0
PLCAP SIGNAL
Fig. 18 PLL Circuit Principles
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock will be 0.5. When VCO is
locked to the incoming data, data will only sample the
quadrature clock when it is logic high. The normalized
filtered sample quadrature clock will be 1.0. We chose a
threshold of 0.66 to generate the phase lock signal.
Because the threshold is lower than 1, it allows jitter to be
greater than 0.5UI before the phase lock circuit reads it as
“not phase locked”.
IJI SIGNAL (V)
4.8
4.6
4.4
4.2
4.0
3.8
3.6
0.00
0.20
0.40
0.60
0.80
INPUT JITTER (UI)
Fig. 19 Input Jitter Indicator (Typical at TA = 25°C)
12
GENNUM CORPORATION
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GS1540
LOOP BANDWIDTH OPTIMIZATION
LOCK LOGIC
The differential jitter demodulation (DM) signal is available
at the DM and DM pins. This signal is the phase correction
signal of the PLL loop, which is amplified and buffered. If
the input jitter is modulated, the PLL tracks the jitter if it is
within loop bandwidth. To track the input jitter, the VCO has
to be adjusted by the phase detector via the charge pump.
Thus, the signal which controls the VCO contains the
information of the input jitter modulation. The jitter
demodulation signal is only valid if the input jitter is less
than 0.5UIp-p. The DM/DM signals have 10kΩ output
impedance, which could be low pass filtered with
appropriate capacitors to eliminate high frequency noise.
DFT_VEE should be connected to GND to activate DM/DM
signals.
Logic is used to produce the PLL_LOCK signal which is
based on the LFS signal and phase lock signal. When there
is not any data input, the integrator will charge and
eventually saturate at either end. By sensing the saturation
of the integrator, it is determined that no data is present. If
either data is not present or phase lock is low, the lock
signal is made low. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled once phase lock is asserted.
The direction of the sweep is also changed once LFS
saturates at either end.
The DM signals can be used as diagnostic tools. Assume
there is an HDTV SDI source, which contains excessive
noise during the horizontal blanking because of the
transient current flowing in the power supply. In order to
discover the source of the noise, one could probe around
the source board with a low frequency oscilloscope
(Bandwidth < 20MHz) that is triggered with an appropriately
filtered DM/DM signal. The true cause of the modulation will
be synchronous and will appear as a stationary signal with
respect to the DM/DM signal.
Figure 20 shows an example of such a situation. An HDTV
SDI signal is modulated with a modulation signal causing
about 0.2UI jitter in Figure 20 (Channel 1). The GS1540
receives this signal and locks to it. Figure 20 (Channel 2)
shows the DM signal. Notice the wave shape of the DM
signal, which is synchronous to the modulating signal. The
DM/DM signal could also be used to compare the output
jitter of the HDTV signal source.
BYPASS
The BYPASS block bypasses the reclocked/mute path of
the data whenever a logic low input is applied to the
BYPASS input. In the bypass mode, the mute does not have
any effect on the outputs. Also, the internal PLL still locks to
a valid HDTV signal and shows PLL_LOCK.
SERIAL OUTPUT STAGE
The serial output signals have a nominal voltage of
400mVpp differential, or 200mVpp single ended when
terminated with 50Ω.
SDO_EN
The SDO_EN enables or disables the serial output driver. To
disable the driver, tie SDO_EN to VCC. To enable the driver,
tie SDO_EN to VEE. When disabled, the supply current is
reduced by approximately 10mA.
SERIAL TO PARALLEL CONVERTER
The high-speed serial to parallel converter accepts
differential clock and data signals from the reclocker core.
The S/P core converts this serial output into a 20-bit wide
data stream (D[19:0]). It also provides a parallel clock,
which is 1/20th the serial clock rate (PCLK_OUT). The
outputs of the S/P block are TTL compatible. When the PLL
loses lock, the parallel clock continues to freewheel. The
parallel clock and data outputs were designed for seamless
interfaces to the GS1500 and GS1510.
Fig. 20 Jitter Demodulation Signal
13
GENNUM CORPORATION
522 - 27- 00
GS1540
JITTER DEMODULATION (DM)
GENNUM CORPORATION
VCC
VCC
VCO
5k
LFA
nc 65
nc 67
nc 66
nc 69
nc 68
LFA_VCC 72
nc 71
nc 70
EE
LBCONT 74
LFA 73
DFT_VEE 76
75
LFA_V
DM 80
79
DM
nc 78
nc 77
nc 82
81
LFS
LFS 85
84
nc
nc 83
nc 87
IJI 86
VCO 89
nc 88
nc 95
nc 94
93
PLCAP
92
nc
91
VCO
nc 90
98
PLL_LOCK
nc 97
PLCAP 96
L10
L11
GS1540
MAIN POWER PLANE
VCC
VCC
NOTE: L8 to L11 are
nc 51
D9 50
C52
0Ω RESISTORS.
100n
C49
D8
D7
NOISY ENVIRONMENTS.
10µ
D6
L8
D5
L9
D4
C51
10µ
C50
49
48
47
46
45
D3 44
43
D2
42
D1
41
D0
nc 40
nc 39
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
37 nc
38 nc
EE
CC
EE
33 SP_V
EE
34
PCLK_OUT
35 PCLK_V
CC
36 PCLK_V
100n
31 SP_V
CC
32 SP_V
14 nc
15 nc
16 nc
12 nc
13 nc
10 nc
11 nc
nc
8 nc
9 nc
DIGITAL POWER PLANE
7
60
D10 53
nc 52
C59
VCC
14
10µ
5 nc
6 nc
61
56
D13
D12 55
D11 54
C60
3 nc
4 nc
62
59
D14
nc 58
nc 57
USE 12nH INDUCTORS IN
1 nc
2 nc
10n
C61
123 nc
124 nc
125 nc
126
nc
127 nc
128 nc
522 - 27- 00
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
C65
10n
D15
100n
VCO POWER PLANE
C31
10n
10µ
100n
116 nc
117 nc
118 nc
119 nc
120
nc
121 nc
122 nc
C30
10n
D19 64
D18 63
D16
29 nc
30 SP_V
4µ7
106 DDI_V
TT
107 nc
108
DDI
109
DDI
110 PD_V
CC
111 nc
112
PDSUB_VEE
113 PD_V
EE
114 nc
115 nc
C29
(110/112) (19/21) (30-31/32-33) (35/36)
D17
26 nc
27
nc
28 nc
J6
4µ7
VCC
C33
C64
SDO_EN
C32
10n
17 SDO
18
SDO
19 SDO_V
EE
20
SDO_EN
21
SDO_VCC
22
nc
23
nc
24
nc
25 nc
10n
1µ
VCC
VCC
C24
+
VCC
PCLK
J7
4µ7
+
C23
J4
4µ7
TYPICAL APPLICATION CIRCUIT
J5
BYPASS
103 nc
104 nc
105 BYPASS
10n
1µ
V
C35 CC
10n
VCC
C25
nc 100
nc 99
nc 102
nc 101
PLL_LOCK
C26
C34
+
GS1540
C27
C28
+
TYPICAL APPLICATION CIRCUIT (continued)
GO1515 VCO
POWER CONNECT
LFA
VCC
C43
C41
VCC
+
100n
10µ
C42
+
C44
VCTR 1
2
GND
6 GND
GND
100n
8
GS1540 LOCK DETECT
VCC
7 nc
VCC 3
U2
GND GO1515
5 O/P
4
GS1540
10µ
R27
R26
PLL_LOCK
VCO
Q3
LED3
150
22k
GS1540 CONFIGURATION JUMPERS
VCC
BYPASS
VCC
SDO_EN
All resistors in ohms,
all capacitors in farads,
unless otherwise shown.
APPLICATION INFORMATION
Please refer to the EBHDRX evaluation board
documentation for more detailed application and circuit
information on using the GS1540 with the GS1500 and
GS1510 Deformatters.
15
GENNUM CORPORATION
522 - 27- 00
PACKAGE DIMENSIONS
23.20 ±0.25
20.0 ±0.10
18.50 REF
GS1540
12 TYP
12.50 REF
0.75 MIN
17.20 ±0.25
0 -7
14.0 ±0.10
0.30 MAX RADIUS
0-7
0.13 MIN.
RADIUS
0.88 ±0.15
1.6
REF
3.00 MAX
0.50 BSC
0.27 ±0.08
128 pin MQFP
All dimensions are in millimetres.
2.80 ±0.25
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Upgraded to Preliminary Data Sheet; Updated Functional
Block Diagram, Absolute Maximum Ratings, AC and DC
Electrical Characteristics Tables, Pin Connections and
Descriptions, and Typical Application Circuit.
For latest product information, visit www.gennum.com
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change without notice.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright May 2000 Gennum Corporation. All rights reserved. Printed in Canada.
16
522 - 27- 00
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