Hitachi HS4318ESS01H 4-bit hmcs400-series microcomputer Datasheet

HD404318 Series
Rev. 6.0
Sept. 1998
Description
The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to
increase program productivity. Each microcomputer has an A/D converter and input capture timer built in.
They also come with high-voltage I/O pins that can directly drive a fluorescent display.
The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM.
The HD4074318 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a
PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The PROM program specifications are the same as for the 27256.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 34 I/O pins
 One input-only pin
 33 input/output pins: 21 pins are high-voltage pins (40 V, max.)
• On-chip A/D converter (8-bit × 8-channel)
• Three timers
 One event counter input
 One timer output
 One input capture timer
• 8-bit clock-synchronous serial interface (1 channel)
• Alarm output
• Built-in oscillators
 Ceramic or crystal oscillator
 External clock drive is also possible
HD404318 Series
• Seven interrupt sources
 Two by external sources
 Three by timers
 One each by the A/D converter and serial interface
• Two low-power dissipation modes
 Standby mode
 Stop mode
• Instruction cycle time 1 µs (fosc = 4 MHz)
Ordering Information
Type
Model Name
ROM (words)
RAM (digit)
Package
Mask ROM
HD404314S
4,096
384
DP-42S
HD404314H
HD404316S
FP-44A
6,144
DP-42S
HD404316H
HD404318S
FP-44A
8,192
DP-42S
HD404318H
ZTAT
HD4074318S
FP-44A
8,192
DP-42S
HD4074318H
FP-44A
Recommended PROM Programmers and Socket Adapters
PROM Programmer
Socket Adapter
Manufacture
Model Name
Package
Manufacturer
Model Name
DATA I/O Corp.
121B
DP-42S
Hitachi
HS4318ESS01H
FP-44A
AVAL Corp.
PKW-1000
DP-42S
FP-44A
2
HS4318ESH01H
Hitachi
HS4318ESS01H
HS4318ESH01H
HD404318 Series
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DP-42S
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R23
R22
R21
R20
R13
R12
R11
R10
R83
R82
R81
R80
D8
D7
D6
D5
D4/STOPC
D3/BUZZ
D2/EVNB
D1/INT1
D0/INT0
44
43
42
41
40
39
38
37
36
35
34
NC
R03 /TOC
R02 /SO
R01 /SI
R00 /SCK
RA1/Vdisp
R23
R22
R21
R20
R13
RA1/Vdisp
R00/SCK
R01/SI
R02/SO
R03/TOC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
R41/AN5
R42/AN6
R43/AN7
AV CC
V CC
FP-44A
33
32
31
30
29
28
27
26
25
24
23
R12
R11
R10
R83
R82
R81
R80
D8
D7
D6
D5
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
R41/AN5
R42/AN6
R43/AN7
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
NC
TEST
RESET
OSC1
OSC2
GND
AVSS
R30/AN0
R31/AN1
R32/AN2
R33/AN3
R40/AN4
3
HD404318 Series
PinDescription
Pin Number
Item
Symbol
Power supply VCC
DP-42S FP-44A I/O Function
21
16
Applies power voltage
10
5
Connected to ground
Vdisp (shared 1
with RA1)
39
Used as a high-voltage output power supply pin when
selected by the mask option
Test
TEST
6
1
I
Cannot be used in user applications. Connect this pin
to GND.
Reset
RESET
7
2
I
Resets the MCU
Oscillator
OSC 1
8
3
I
Input/output pin for the internal oscillator. Connect these
pins to the ceramic or crystal oscillator, or OSC 1 to an
external oscillator circuit.
OSC 2
9
4
O
D0–D 8
22–30
17–21, I/O Input/output pins addressed individually by bits; D0–D 8
are all high-voltage I/O pins. Each pin can be
23–26
individually configured as selected by the mask option.
RA 1
1
39
GND
Port
I
One-bit high-voltage input port pin
R0 0–R0 3,
2–5,
R3 0–R4 3
12–19
40–43, I/O Four-bit input/output pins consisting of standard voltage
pins
7–14
R1 0–R2 3,
31–42
27–38
I/O Four-bit input/output pins consisting of high voltage pins
R8 0–R8 3
Interrupt
INT0, INT1
22, 23
17, 18
I
Input pins for external interrupts
Stop clear
STOPC
26
21
I
Input pin for transition from stop mode to active mode
Serial
interface
SCK
2
40
I/O Serial interface clock input/output pin
SI
3
41
I
Serial interface receive data input pin
SO
4
42
O
Serial interface transmit data output pin
TOC
5
43
O
Timer output pin
EVNB
24
19
I
Event count input pin
Alarm
BUZZ
25
20
O
Square waveform output pin
A/D
converter
AVCC
20
15
Power supply for the A/D converter. Connect this pin as
close as possible to the VCC pin and at the same voltage
as VCC. If the power supply voltage to be used for the
A/D converter is not equal to VCC, connect a 0.1-µF
bypass capacitor between the AV CC and AV SS pins.
(However, this is not necessary when the AV CC pin is
directly connected to the VCC pin.)
AVSS
11
6
Ground for the A/D converter. Connect this pin as close
as possible to GND at the same voltage as GND.
AN 0–AN 7
12–19
7–14
Timer
4
I
Analog input pins for the A/D converter
HD404318 Series
Pin Description in PROM Mode
The HD4074318 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin
I/O
Pin
I/O
1
39
RA 1/V disp
I
2
40
R0 0/SCK
I/O
VCC
3
41
R0 1/SI
I/O
VCC
4
42
R0 2/SO
I/O
5
43
R0 3/TOC
I/O
6
1
TEST
I
VPP
7
2
RESET
I
RESET
8
3
OSC 1
I
VCC
9
4
OSC 2
O
10
5
GND
GND
11
6
AVSS
GND
12
7
R3 0/AN0
I/O
O0
I/O
13
8
R3 1/AN1
I/O
O1
I/O
14
9
R3 2/AN2
I/O
O2
I/O
15
10
R3 3/AN3
I/O
O3
I/O
16
11
R4 0/AN4
I/O
O4
I/O
17
12
R4 1/AN5
I/O
O5
I/O
18
13
R4 2/AN6
I/O
O6
I/O
19
14
R4 3/AN7
I/O
O7
I/O
20
15
AVCC
VCC
21
16
VCC
VCC
22
17
D0/INT0
I/O
M0
I
23
18
D1/INT1
I/O
M1
I
24
19
D2/EVNB
I/O
A1
I
25
20
D3/BUZZ
I/O
A2
I
26
21
D4/STOPC
I/O
27
23
D5
I/O
A3
I
28
24
D6
I/O
A4
I
29
25
D7
I/O
A9
I
30
26
D8
I/O
VCC
I
5
HD404318 Series
Pin Number
MCU Mode
PROM Mode
DP-42S
FP-44A
Pin
I/O
Pin
I/O
31
27
R8 0
I/O
CE
I
32
28
R8 1
I/O
OE
I
33
29
R8 2
I/O
A13
I
34
30
R8 3
I/O
A14
I
35
31
R1 0
I/O
A5
I
36
32
R1 1
I/O
A6
I
37
33
R1 2
I/O
A7
I
38
34
R1 3
I/O
A8
I
39
35
R2 0
I/O
A0
I
40
36
R2 1
I/O
A10
I
41
37
R2 2
I/O
A11
I
42
38
R2 3
I/O
A12
I
I/O: Input/output pin; I: Input pin; O: Output pin
6
HD404318 Series
INT0
GND
VCC
OSC2
OSC1
STOPC
TEST
RESET
Block Diagram
System control
Interrupt
control
D0
INT1
RAM
(384 × 4 bits)
D1
D port
D2
W
(2 bits)
Timer A
D5
D7
D8
R0 port
Timer B
D4
D6
X
(4 bits)
EVNB
D3
SPX
(4 bits)
R00
R01
R02
R03
SCK
R1 port
SPY
(4 bits)
R11
R12
R20
R21
R22
R23
ALU
AVSS
•
•
•
A/D
converter
ST
(1 bit)
CA
(1 bit)
R3 port
R30
AN0
•
•
•
R10
R13
R2 port
Serial
interface
Internal data bus
SI
SO
Internal data bus
Timer C
TOC
Internal address bus
Y
(4 bits)
R33
AN7
A
(4 bits)
R40
R4 port
AVCC
B
(4 bits)
BUZZ
R31
R32
R41
R42
R43
Buzzer
SP
(10 bits)
R80
Instruction
decoder
PC
(14 bits)
R8 port
Data bus
R81
R82
Directional
signal line
ROM
(4,096 × 10 bits)
(6,144 × 10 bits)
(8,192 × 10 bits)
RA port
R83
High voltage
pin
RA1
7
HD404318 Series
Memory Map
ROM Memory Map
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$0FFF (HD404314), $0000–$17FF (HD404316), $0000–$1FFF (HD404318,
HD4074318)): The entire ROM area can be used for program coding.
$0000
$000F
Vector address
(16 words)
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern
(4,096 words)
HD404314
Program
(4,096 words)
$0FFF
$1000
$0000
JMPL instruction
$0001 (jump to RESET, STOPC routine)
JMPL instruction
$0002
(jump to INT 0 routine)
$0003
JMPL instruction
$0004
(jump to INT 1 routine)
$0005
JMPL instruction
$0006
(jump to timer A routine)
$0007
$0008
JMPL instruction
(jump to timer B routine)
$0009
$000A
JMPL instruction
(jump to timer C routine)
$000B
$000C
JMPL instruction
$000D (jump to A/D converter routine)
$000E
JMPL instruction
(jump to serial routine)
$000F
HD404316
Program
(6,144 words)
$17FF
$1800
HD404318, HD4074318
Program
(8,192 words)
$1FFF
Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas
are to be used.
Figure 1 ROM Memory Map
8
HD404318 Series
RAM MemoryMap
Initial values
after reset
$000
RAM-mapped registers
$040
Memory registers (MR)
$050
Data (304 digits)
$180
Not used
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
Interrupt control bits area
Port mode register A
(PMRA)
Serial mode register
(SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A
(TMA)
Timer mode register B1 (TMB1)
Timer B
(TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register
(MIS)
Timer mode register C
(TMC)
Timer C
(TRCL/TWCL)
(TRCU/TWCU)
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
0000
0000
Undefined
Undefined
-000
0000
*2/0000
*1
Undefined
00-0000
*2/0000
Undefined
Not used
$3C0
Stack (64 digits)
$3FF
(ACR)
(ADRL)
(ADRU)
(AMR1)
(AMR2)
W
R
R
W
W
-000
0000
1000
0000
--00
$020
Register flag area
$023
$024 Port mode register B
(PMRB)
$025 Port mode register C
(PMRC)
(TMB2)
$026 Timer mode register B2
W
W
W
0000
00-0
-000
(DCR0)
W
0000
(DCR3)
(DCR4)
W
W
0000
0000
$016
$017
$018
$019
$01A
A/D channel register
A/D data register lower
A/D data register upper
A/D mode register 1
A/D mode register 2
Not used
Not used
Notes: 1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
$030
Port R0 DCR
2. Undefined.
Not used
R: Read only
W: Write only
R/W: Read/write
$033
$034
Port R3 DCR
Port R4 DCR
Not used
$03F
$00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W
$00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W
$00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W
$00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W
Figure 2 RAM Memory Map and Initial Values
9
HD404318 Series
Table 1
Initial Values of Flags after MCU Reset
Item
Initial Value
Interrupt flags/mask
Bit registers
RAM Address
Interrupt enable flag (IE)
0
Interrupt request flag (IF)
0
Interrupt mask (IM)
1
Watchdog timer on flag (WDON)
0
A/D start flag (ADSF)
0
Input capture status flag (ICSF)
0
Input capture error flag (ICEF)
0
I AD off flag (IAOF)
0
RAM enable flag (RAME)
0
Bit 3
Bit 2
Bit 1
Bit 0
$0000
IM0
(IM of INT0)
IF0
(IF of INT0)
RSP
(Reset SP bit)
IE
(Interrupt
enable flag)
$0001
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT1)
IF1
(IF of INT1)
$0002
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$0003
IMS
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
Interrupt control bits area
Bit 3
Bit 2
Bit 1
Bit 0
Not used
ICSF
(Input capture
status flag)
$020
Not used
ADSF
(A/D start flag)
WDON
(Watchdog
on flag)
$021
RAME
(RAM enable
flag)
IAOF
(IAD off flag)
ICEF
(Input capture
error flag)
IF: Interrupt
request flag
$022
IM: Interrupt
mask
IE: Interrupt
$023
enable flag
SP: Stack pointer
Not used
Register flag area
Figure 3 Interrupt Control Bits and Register Flag Areas Configuration
10
HD404318 Series
SEM/SEMD
REM/REMD
TM/TMD
Allowed
Allowed
Allowed
Not executed
Allowed
Allowed
RSP
Not executed
Allowed
Inhibited
WDON
Allowed
Not executed
Inhibited
ADSF
Allowed
Inhibited
Allowed
Not used
Not executed
Not executed
Inhibited
IE
IM
IAOF
IF
ICSF
ICEF
RAME
Note:
WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD
instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is
executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
Memory registers
$040 MR(0)
$041 MR(1)
$042 MR(2)
$043 MR(3)
$044 MR(4)
$045 MR(5)
$046 MR(6)
$047 MR(7)
$048 MR(8)
$049 MR(9)
$04A MR(10)
$04B MR(11)
$04C MR(12)
$04D MR(13)
$04E MR(14)
$04F MR(15)
Stack area
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
$3FF Level 1
$3C0
Bit 3
Bit 2
Bit 1
Bit 0
$3FC
ST
PC13
PC 12
PC11
$3FD
PC 10
PC9
PC 8
PC7
$3FE
CA
PC6
PC 5
PC4
$3FF
PC 3
PC2
PC 1
PC0
PC13 –PC0 : Program counter
ST: Status flag
CA: Carry flag
Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position
11
HD404318 Series
Registers and Flags
3
Accumulator
0
(A)
Initial value: Undefined, R/W
3
B register
Initial value: Undefined, R/W
W register
Initial value: Undefined, R/W
0
(B)
1
0
(W)
3
X register
Initial value: Undefined, R/W
0
(X)
3
Y register
0
(Y)
Initial value: Undefined, R/W
3
SPX register
Initial value: Undefined, R/W
SPY register
Initial value: Undefined, R/W
Carry
Initial value: Undefined, R/W
Status
Initial value: 1, no R/W
0
(SPX)
3
0
(SPY)
0
(CA)
0
Program counter
Initial value: 0,
no R/W
(ST)
13
0
(PC)
9
Stack pointer
Initial value: $3FF, no R/W
1
5
1
1
1
Figure 6 Registers and Flags
12
0
(SP)
HD404318 Series
Addressing Modes
RAM Addressing Modes
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located
in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
1 0 3
W
9
0 3
3
Y
X
7
0
3
Instruction
0
9
0
RAM address
RAM address 0 0 0 1 0 0
Register Indirect Addressing
Memory Register Addressing
9
Instruction
1st instruction
word
0 9
0
Opcode
2nd instruction
word
0
Opcode
9
0
RAM address
Direct Addressing
Figure 7 RAM Addressing Modes
13
HD404318 Series
ROM Addressing Modes
Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.
Current Page Addressing Mode: A program can branch to any address in the current page (256 words
per page) by executing the BR instruction.
Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000–$003F) by executing the CAL instruction.
Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
2nd
instruction word
1st
instruction word
9
3
Opcode
09
0
Opcode
9
5
Operand
13
0
Operand
0
13
Program counter
0
Program counter 0 0 0 0 0 0 0 0
Direct Addressing
Zero-Page Addressing
Operand
Opcode
9
7
0
Operand
13
9
3
Opcode
0
Program counter * * * * * *
B
13
Program counter 0 0
Current Page Addressing
Table Data Addressing
Figure 8 ROM Addressing Modes
14
3
0 7
0
A
0
HD404318 Series
Table 2
Instruction Set Classification
Instruction Type
Function
Number of
Instructions
Immediate
Transferring constants to the accumulator, B register, and RAM.
4
Register-to-register
Transferring contents of the B, Y, SPX, SPY, or memory registers to
the accumulator
8
RAM addressing
Available when accessing RAM in register indirect addressing mode
13
RAM register
Transferring data between the accumulator and memory.
10
Arithmetic
Performing arithmetic operations with the contents of the accumulator, 25
B register, or memory.
Compare
Comparing contents of the accumulator or memory with a constant
12
RAM bit manipulation Bit set, bit reset, and bit test.
6
ROM addressing
Branching and jump instructions based on the status condition.
8
Input/output
Controlling the input/output of the R and D ports; ROM data reference 11
with the P instruction
Control
Controlling the serial communication interface and low-power
dissipation modes.
4
Total: 101
instructions
15
HD404318 Series
Interrupts
$000,0
IE
Interrupt
request
(RESET, STOPC)
$000,2
INT0 interrupt
IF0
$000,3
IM0
$001,0
INT1 interrupt
IF1
$001,1
IM1
Priority Controller
Priority Order
Vector Address
$0000
1
$0002
2
$0004
3
$0006
4
$0008
5
$000A
6
$000C
7
$000E
$001,2
Timer A interrupt
IFTA
$001,3
IMTA
$002,0
Timer B interrupt
IFTB
$002,1
IMTB
$002,2
Timer C interrupt
IFTC
$002,3
IMTC
$003,0
A/D interrupt
IFAD
$003,1
IMAD
$003,2
Serial interrupt
IFS
$003,3
IMS
Figure 9 Interrupt Control Circuit
16
HD404318 Series
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Execution of
instruction at
start address
of interrupt
routine
Figure 10 Interrupt Processing Sequence
17
HD404318 Series
Operating Modes
The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown
in figure 11.
Table 3
Operations in Each Operating Mode
Function
Active Mode
Standby Mode
Stop Mode
System oscillator
OP
OP
Stopped
CPU
OP
Retained
Reset
RAM
OP
Retained
Retained
Timer A
OP
OP
Reset
Timers B, C
OP
OP
Reset
Serial interface
OP
OP
Reset
A/D
OP
OP
Reset
I/O
OP
Retained
Reset
Note: OP implies in operation
18
,
,
HD404318 Series
Reset by
RESET input or
by watchdog timer
RAME = 0
RESET 1
RAME = 1
RESET 2
STOPC
Active
mode
Standby mode
fOSC: Oscillate
øCPU: Stop
SBY
instruction
Interrupt
øPER: fcyc
Stop mode
fOSC: Oscillate
øCPU: fcyc
STOP
instruction
øPER: fcyc
fOSC: Stop
øCPU: Stop
øPER: Stop
fOSC: Main oscillation frequency
fcyc:
fOSC/4
øCPU: System clock
øPER: Clock for other peripheral
functions
Figure 11 MCU Status Transitions
In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least
tRC when clearing stop mode, execute the cancellation according to the timing chart in figure12.
Stop mode
Oscillator
Internal
clock
RESET
or
STOPC
tres
STOP instruction execution
tres ≥ tRC (stabilization period)
Figure 12 Timing of Stop Mode Cancellation
19
HD404318 Series
MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14.
The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power ON
RESET = 0?
No
Yes
MCU operation cycle
RAME = 0
Yes
IF = 1?
Reset MCU
No
No
IM = 0
IE = 1
Yes
Instruction
RAME = 1
execution
Reset input
SBY/STOP
instruction
IE ← 0
Stack ← (PC),
(CA), (ST)
No
Low-power mode
operation cycle
(figure 15)
PC ← (PC)+1
Figure 13 MCU Operating Sequence (Power ON)
20
PC ← vector
address
HD404318 Series
Low-power mode
operation cycle
IF = 1 and
IM = 0?
No
Yes
Stop mode
Standby mode
No
IF = 1 and
IM = 0?
Yes
No
STOPC = 0?
Yes
Hardware NOP
execution
Hardware NOP
execution
RAME = 1
PC ← Next
Iocation
PC ← Next
Iocation
Reset MCU
Instruction
execution
MCU operation
cycle
Figure 14 MCU Operating Sequence (Low-Power Mode Operation)
21
HD404318 Series
Oscillator Circuit
Figure 15 shows a block diagram of the clock generation circuit.
OSC2
1/4
System fOSC
division
oscillator
circuit
fcyc
tcyc
Timing
generator
circuit
øCPU
CPU with ROM,
RAM, registers,
flags, and I/O
øPER
Peripheral
function
interrupt
OSC1
Figure 15 Clock Generation Circuit
TEST
RESET
OSC1
OSC2
GND
AVSS
Figure 16 Typical Layout of Crystal and Ceramic Oscillator
22
HD404318 Series
Table 4
Oscillator Circuit Examples
Circuit Configuration
External clock
operation
Circuit Constants
External
oscillator
OSC 1
Open
OSC 2
Ceramic oscillator
(OSC1, OSC 2)
Ceramic oscillator: CSA4.00MG (Murata)
C1
Rf = 1 MΩ ±20%
OSC1
Ceramic
C1 = C2 = 30 pF ±20%
Rf
OSC2
C2
GND
Crystal oscillator
(OSC1, OSC 2)
Rf = 1 MΩ ±20%
C1
C1 = C2 = 10 to 22 pF ±20%
OSC1
Crystal
Crystal: Equivalent to circuit shown below
Rf
C0 = 7 pF max.
OSC2
RS = 100 Ω max.
C2
GND
L
CS
OSC1
RS
OSC2
CO
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross
other wiring (see figure 16).
23
HD404318 Series
I/O Ports
The MCU has 33 input/output pins (D0–D 8, R0–R4, R8) and one input-only pin (RA1). The following
describes the features of the I/O ports.
• The 21 pins consisting of D0–D8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage
input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as
selected by the mask option.
• All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for
NMOS open-drain output.
• In stop mode, input/output pins go to the high-impedance state
• All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by
software
Table 5
Control of Standard I/O Pins by Program
MIS3 (bit 3 of MIS)
0
DCR
0
PDR
0
1
0
1
0
1
0
1
PMOS
—
—
—
On
—
—
—
On
NMOS
—
—
On
—
—
—
On
—
—
—
—
—
—
On
—
On
CMOS buffer
Pull-up MOS
1
1
0
1
Note: — indicates off.
Data control register
(DCR0: $030, DCR3: $033, DCR4: $034)
DCR0, DCR3,
DCR4
Bit
3
2
0
1
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
DCR03,
DCR33,
DCR43,
Bits 0 to 3 CMOS Buffer Control
DCR02, DCR01, DCR00,
DCR32, DCR31, DCR30,
DCR42, DCR41, DCR40
0
CMOS buffer off
(high impedance)
1
CMOS buffer on
Correspondence between ports and DCR bits
Register
Bit 3
Bit 2
Bit 1
Bit 0
DCR0
R03
R02
R01
R00
DCR3
R33
R32
R31
R30
DCR4
R43
R42
R41
R40
Figure 17 Data Control Register (DCR)
24
HD404318 Series
Table 6
Circuit Configurations of Standard I/O Pins
I/O Pin Type
Circuit
Input/output pins
Pins
VCC
VCC
Pull-up control signal
Buffer control
signal
HLT
R0 0, R0 1, R0 3
MIS3
R3 0–R3 3,
DCR
Output data
R4 0–R4 3
PDR
Input data
Input control signal
VCC
HLT
VCC
Pull-up control signal
Buffer control
signal
Output data
R0 2
MIS3
DCR
MIS2
PDR
Input data
Input control signal
Peripheral
function pins
Input/ output
pins
VCC
HLT
VCC
Pull-up control signal
Output data
Input data
Output pins
VCC
SCK
Pull-up control signal
PMOS control
signal
Output data
VCC
SCK
HLT
VCC
Pull-up control signal
Output data
SO
MIS3
MIS2
SO
HLT
VCC
SCK
MIS3
TOC
MIS3
TOC
Notes on next page.
25
HD404318 Series
I/O Pin Type
Peripheral
function pins
Circuit
Input/ pins
Pins
VCC
SI
Input data
HLT
MIS3
PDR
SI
VCC
AN 0–AN 7
HLT
MIS3
PDR
A/D input
Input control
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins the enter high-impedance state.
2. The HLT signal is 1 in active and standby modes.
26
HD404318 Series
Table 7
Circuit Configurations for High-Voltage Input/Output Pins
I/O Pin Type
With Pull-Down Resistance
Input/output
pins
VCC
HLT
Without Pull-Down Resistance
VCC
Output
data
Pull-down
resistance
HLT
Output
data
D0–D 8,
R1 0–R1 3,
R2 0–R2 3,
Input data
R8 0–R8 3
Input data
RA 1
Input control
signal
Vdisp
Pins
Input data
Input control
signal
Input pins
Input control
signal
Peripheral
function pins
Output
pins
VCC
HLT
Pull-down
resistance
Output
data
VCC
BUZZ
HLT
Output
data
Vdisp
Input data
Input
pins
Pull-down
resistance
Vdisp
Input data
INT0,
INT1,
EVNB,
STOPC
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins the enter high-impedance state.
2. The HLT signal is 1 in active and standby modes.
3. The circuits of HD4074318 are without pull-down resistance.
27
HD404318 Series
Port mode register A (PMRA: $004)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
Bit name
PMRA3
PMRA2 PMRA1 PMRA0
PMRA0
PMRA2
R03/TOC Mode Selection
0
R03
1
TOC
PMRA3
0
D3
1
BUZZ
0
R02
1
SO
PMRA1
D3/BUZZ Mode Selection
R02/SO Mode Selection
R01/SI Mode Selection
0
R01
1
SI
Figure 18 Port Mode Register A (PMRA)
Port mode register B (PMRB: $024)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
Bit name
W
W
W
*
PMRB3 PMRB2 PMRB1 PMRB0
PMRB0
PMRB2 D2/EVNB Mode Selection
0
D2
1
EVNB
0
D4
1
STOPC
0
D0
1
INT0
PMRB1
PMRB3 D4/STOPC Mode Selection
D0/INT0 Mode Selection
D1/INT1 Mode Selection
0
D1
1
INT1
Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode,
PMRB3 is not reset but retains its value.
Figure 19 Port Mode Register B (PMRB)
28
HD404318 Series
Miscellaneous register (MIS: $00C)
Bit
3
2
1
0
Initial value
0
0
—
—
—
—
Read/Write
Bit name
W
W
MIS3
MIS2
MIS3
Pull-Up MOS
On/Off Selection
0
Pull-up MOS off
1
Pull-up MOS on
(refer to table 5)
Not used Not used
MIS2
CMOS Buffer
On/Off Selection
for Pin R02/SO
0
CMOS on
1
CMOS off
Note: The on/off status of each transistor and the peripheral function mode of each
pin can be set independently.
Figure 20 Miscellaneous Register (MIS)
29
HD404318 Series
Prescaler
The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then
outputs divided clock signals to the peripheral function modules, as shown in figure21.
Timer A
System
clock
Clock
selector
Timer B
Prescaler S
Timer C
Serial
Figure 21 Prescaler Output Supply
30
HD404318 Series
Timers
The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7.
Timer A
Timer A is an 8-bit free-running timer that has the following features:
• One of eight internal clocks can be selected from prescaler S according to the setting of timer mode
register A (TMA: $008)
• An interrupt request can be generated when timer counter A (TCA) overflows
• Input clock frequency must not be modified during timer A operation
Table 7
Timer Functions
Functions
Clock source
Timer functions
Timer output
Timer A
Timer B
Timer C
Prescaler S
Available
Available
Available
External event
—
Available
—
Free-running
Available
Available
Available
Event counter
—
Available
—
Reload
—
Available
Available
Watchdog
—
—
Available
Input capture
—
Available
—
PWM
—
—
Available
31
HD404318 Series
Timer
counter A
(TCA) Overflow
System
clock
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
øPER
3
Prescaler S (PSS)
Timer mode
register A
(TMA)
Figure 22 Timer A Block Diagram
Timer mode register A (TMA: $008)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
—
W
W
W
Not used
TMA2
TMA1
TMA0
Bit name
Source
Input clock
TMA2 TMA1 TMA0 Prescaler frequency
0
0
1
1
0
1
0
PSS
2048tcyc
1
PSS
1024tcyc
0
PSS
512tcyc
1
PSS
128tcyc
0
PSS
32tcyc
1
PSS
8tcyc
0
PSS
4tcyc
1
PSS
2tcyc
Figure 23 Timer Mode Register A (TMA)
32
Internal data bus
Timer A interrupt
request flag
(IFTA)
HD404318 Series
Timer B
Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features.
These are described as follows.
• By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter
• By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected
• By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be
written to during reload timer operation
• By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can
be read out
• Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as
an external event
• An interrupt can be requested when timer counter B overflows or when a trigger input edge is received
during input capture operation
33
HD404318 Series
Interrupt request
flag of timer B
(IFTB)
Timer read
register BU
(TRBU)
Timer read
register B lower
(TRBL)
Free-running
timer control
signal
Timer write
register B lower
(TWBL)
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
Edge
detector
øPER
2
Overflow
Timer write
register B upper
(TWBU)
Selector
EVNB
System
clock
Timer counter B
(TCB)
3
Prescaler S (PSS)
Timer mode
register B1
(TMB1)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 24 Timer B Free-Running and Reload Operation Block Diagram
34
Internal data bus
Clock
HD404318 Series
Input capture
status flag
(ICSF)
Interrupt request
flag of timer B
(IFTB)
Input capture
error flag
(ICEF)
Error
controller
Timer read
register BU
(TRBU)
Timer read
register B lower
(TRBL)
Read
signal
Edge
detector
Clock
Timer counter B
(TCB)
Overflow
Input capture
timer control
signal
Selector
3
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
System
clock
øPER
2
Internal data bus
EVNB
Timer mode
register B1
(TMB1)
Prescaler S (PSS)
Edge detection control signal
Timer mode
register B2
(TMB2)
Figure 25 Timer B Input Capture Operation Block Diagram
35
HD404318 Series
Timer mode register B1 (TMB1: $009)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMB13
TMB12
TMB11
TMB10
Bit name
TMB13
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
Input Clock Period and Input
Clock Source
TMB12
TMB11
TMB10
0
0
0
2048tcyc
1
512tcyc
0
128tcyc
1
32tcyc
0
8tcyc
1
4tcyc
0
2tcyc
1
D2/EVNB (external event input)
1
1
0
1
Figure 26 Timer Mode Register B1 (TMB1)
Timer mode register B2 (TMB2: $026)
Bit
3
Initial value
—
0
0
0
Read/Write
—
W
W
W
TMB21
TMB20
TMB21
TMB20
0
0
No detection
1
Falling edge detection
0
Rising edge detection
1
Rising and falling edge detection
Bit name
2
Not used TMB22
1
1
TMB22
0
EVNB Edge Detection Selection
Free-Running/Reload and Input Capture Selection
0
Free-Running/Reload
1
Input capture
Figure 27 Timer Mode Register B2 (TMB2)
36
HD404318 Series
Timer C
Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are described as follows.
• By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected
• By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled
• By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be
written to
• By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be
read out
• An interrupt can be requested when timer counter C overflows
• Timer counter C can be used as a watchdog timer for detecting runaway program
37
HD404318 Series
System reset signal
Watchdog on
flag (WDON)
Interrupt request
flag of timer C
(IFTC)
Watchdog timer
controller
Timer read register CU (TRCU)
TOC
Timer output
control logic
Timer read
register C lower
(TRCL)
Clock
Timer
output
control
signal
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 1024
÷ 2048
Selector
System øPER
clock
Overflow
Internal data bus
Timer counter C
(TCC)
Timer write
register C upper
(TWCU)
Free-running
timer control
signal
Timer write
register C lower
(TWCL)
3
Prescaler S (PSS)
Timer mode
register C (TMC)
Port mode
register A (PMRA)
Figure 28 Timer C Block Diagram
38
HD404318 Series
Timer mode register C (TMC: $00D)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
TMC3
TMC2
TMC1
TMC0
Bit name
TMC3
Free-Running/Reload
Timer Selection
0
Free-running timer
1
Reload timer
TMC2
TMC1
TMC0
0
0
0
2048tcyc
1
1024tcyc
0
512tcyc
1
128tcyc
0
32tcyc
1
8tcyc
0
4tcyc
1
2tcyc
1
1
0
1
Input Clock Period
Figure 29 Timer Mode Register C (TMC)
T × (N + 1)
TMC3 = 0
(Free-running
timer)
T
T × 256
TMC3 = 1
(Reload timer)
T × (256 – N)
Notes:
T: Input clock period supplied to counter. (The clock source and system clock division ratio are
determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 30 PWM Output Waveform
39
HD404318 Series
$FF + 1
Overflow
Timer C
count value
$00
CPU
operation
Time
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Normal
operation
Reset
Figure 31 Watchdog Timer Operation Flowchart
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 8. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
Table 8
PWM Output Following Update of Timer Write Register
PWM Output
Mode
Timer Write Register is Updated during
High PWM Output
Timer write
register
updated to
value N
Free running
Timer Write Register is Updated during
Low PWM Output
Timer write
register
updated to
value N
Interrupt
request
T × (255 – N) T × (N + 1)
Interrupt
request
T × (N' + 1)
T × (255 – N)
Timer write
register
updated to
value N
Reload
T
Interrupt
request
T × (255 – N)
T
Timer write
register
updated to
value N
Interrupt
request
T
T × (255 – N)
40
T × (N + 1)
T
HD404318 Series
Alarm Output Function
The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of
four alarm frequencies supplied from the PSS can be selected.
Table 9
Port Mode Register C
Bit 3
Bit 2
System Clock Divisor
0
0
÷ 2048
1
÷ 1024
0
÷ 512
1
÷ 256
1
BUZZ
Alarm output
control signal
Alarm output
controller
System øPER
clock
2
÷ 2048
÷ 1024
÷ 512
÷ 256
Selector
Port mode
register A
(PMRA)
Port mode
register C
(PMRC)
Internal data bus
PMRC
Prescaler S (PSS)
Figure 32 Alarm Output Function Block Diagram
41
HD404318 Series
Serial Interface
The MCU has a one-channel serial interface built in with the following features.
• One of 13 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
• During idle states, the serial output pin can be controlled to be high or low output
• Transmit clock errors can be detected
• An interrupt request can be generated after transfer has completed when an error occurs
Table 10
Serial Interface Operating Modes
SMR
PMRA
Bit 3
Bit 1
Bit 0
Operating Mode
1
0
0
Continuous clock output mode
1
Transmit mode
0
Receive mode
1
Transmit/receive mode
1
42
HD404318 Series
Octal
counter (OC)
SO
Serial interrupt
request flag
(IFS)
Idle
controller
SCK
I/O
controller
SI
Clock
1/2
Selector
1/2
Transfer
control
signal
Internal data bus
Serial data
register (SR)
Selector
÷2
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
3
System
clock
øPER
Prescaler S (PSS)
Serial mode
register
(SMR)
Port mode
register C
(PMRC)
Figure 33 Serial Interface Block Diagram
43
HD404318 Series
STS wait state
(Octal counter = 000,
transmit clock disabled)
MCU reset
SMR write (IFS ← 1)
SMR write
STS instruction
Transmit clock
Transmit clock wait state
(Octal counter = 000)
Transfer state
(Octal counter = 000)
8 transmit clocks or STS instruction (IFS ← 1)
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
SMR write
Continuous clock output state
(PMRA 0, 1 = 0, 0)
SMR write
MCU reset
8 transmit clocks or
SMR write (IFS ←1)
STS instruction
Transmit clock
Transmit clock
Transmit clock wait state
(Octal counter = 000)
STS instruction (IFS ← 1)
Transfer state
(Octal counter = 000)
Internal clock mode
Figure 34 Serial Interface State Transitions
Transmit clock
1
Serial output
data
2
3
4
5
LSB
Serial input
data latch
timing
Figure 35 Serial Interface Timing
44
6
7
8
MSB
,
!"
HD404318 Series
Transmit clock
wait state
State
STS wait state
Transmit clock
wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
External clock selection
SMR write
Dummy write for
state transition
Output level control in
idle states
Output level control in
idle states
PMRC write
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(input)
SO pin
Undefined
LSB
MSB
IFS
External clock mode
Flag reset at transfer completion
Transmit clock
wait state
State
STS wait state
Transfer state
STS wait state
MCU reset
Port selection
PMRA write
Internal clock selection
SMR write
Output level control in
idle states
Output level control in
idle states
PMRC write
Data write for transmission
SRL, SRU
write
STS
instruction
SCK pin
(output)
SO pin
Undefined
LSB
MSB
IFS
Internal clock mode
Flag reset at transfer completion
Figure 36 Example of Serial Interface Operation Sequence
45
HD404318 Series
Transmit clock erors are detected as illustrated in figure 37.
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
Yes
IFS = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
Transmit clock
wait state
Transmit clock wait state
Transfer state
State
Transfer state
SCK pin (input)
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit
clock error. When SMR
is written, IFS is set.
SMR write
IFS
Flag set because octal
counter reaches 000.
Transmit clock error detection procedure
Figure 37 Transmit Clock Error Detection
46
Flag reset at
transfer completion.
HD404318 Series
Table 11
Transmit Clock Selection
PMRC
SMR
Bit 0
Bit 2
Bit 1
Bit 0
System Clock Divisor
Transmit Clock Frequency
0
0
0
0
÷ 2048
4096t cyc
1
÷ 512
1024t cyc
0
÷ 128
256t cyc
1
÷ 32
64t cyc
0
÷8
16t cyc
1
÷2
4t cyc
0
÷ 4096
8192t cyc
1
÷ 1024
2048t cyc
0
÷ 256
512t cyc
1
÷ 64
128t cyc
0
÷ 16
32t cyc
1
÷4
8t cyc
1
1
1
0
0
0
1
1
0
Serial mode register (SMR: $005)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
SMR3
SMR2
SMR1
SMR0
Bit name
SMR3
R00/SCK
Mode Selection
0
R00
1
SCK
Clock Source
Output
Prescaler
Refer to
table 11
0
Output
System clock
—
1
Input
External clock
—
SMR1
SMR0
0
0
0
1
1
Prescaler
Division Ratio
SCK
SMR2
0
1
1
0
0
1
1
Figure 38 Serial Mode Register (SMR)
47
HD404318 Series
Port mode register C (PMRC: $025)
Bit
3
2
1
0
Initial value
0
0
Undefined
0
Read/Write
W
W
W
W
PMRC2
PMRC1
PMRC0
Bit name
PMRC3
PMRC0
Alarm output function.
Refer to table 9.
Serial Clock Division Ratio
0
Prescaler output divided by 2
1
Prescaler output divided by 4
PMRC1
Output Level Control in Idle States
0
Low level
1
High level
Figure 39 Port Mode Register C (PMRC)
48
HD404318 Series
A/D Converter
The MCU also contains a built-in A/D converter that uses a sequential comparison method with a
resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The
following describes the A/D converter.
• A/D mode register 1 (AMR1: $019) is used to select digital or analog ports
• A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or
analog ports
• The A/D channel register (ACR: $016) is used to select an analog input channel
• A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0
• By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be
cut off even while operating in standby or active mode
4
A/D mode
register 1
(AMR1)
3
Selector
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Encoder
+
Comp
–
AVCC
A/D
controller
Control signal
for conversion
time
A/D start flag
(ADSF)
AVSS
A/D mode
register 2
(AMR2)
A/D data
register
(ADRU, L)
Internal data bus
A/D interrupt
request flag
(IFAD)
A/D channel
register (ACR)
IAD off flag
(IAOF)
D/A
Operating mode signal (1 in stop mode)
Figure 40 A/D Converter Block Diagram
49
HD404318 Series
Notes on Usage
•
•
•
•
Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
Do not write to the A/D start flag during A/D conversion
Data in the A/D data register during A/D conversion is undefined
Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in stop mode, all current
flowing through the converter’s resistance ladder is cut off.
• If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.
A/D mode register 1 (AMR1: $019)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
W
W
W
W
AMR13
AMR12
AMR11
AMR10
Bit name
AMR10
AMR12
R32/AN2 Mode Selection
0
R32
1
AN2
AMR13
0
R33
1
AN3
0
R30
1
AN0
AMR11
R33/AN3 Mode Selection
R31/AN1 Mode Selection
0
R31
1
AN1
Figure 41 A/D Mode Register 1 (AMR1)
50
R30/AN0 Mode Selection
HD404318 Series
A/D mode register 2 (AMR2: $01A)
Bit
3
2
Initial value
—
—
0
0
Read/Write
—
—
W
W
Bit name
0
1
Not used Not used AMR21
AMR20
AMR20
Conversion Time
0
34tcyc
1
67tcyc
AMR21
R4/AN4–AN7 Pin Selection
0
R4
1
AN4–AN7
Figure 42 A/D Mode Register (AMR2)
A/D channel register (ACR: $016)
Bit
3
2
1
0
Initial value
—
0
0
0
Read/Write
Bit name
—
W
W
W
Not used
ACR2
ACR1
ACR0
ACR2 ACR1 ACR0
0
0
1
1
0
1
Analog Input Selection
0
AN0
1
AN1
0
AN2
1
AN3
0
AN4
1
AN5
0
AN6
1
AN7
Figure 43 A/D Channel Register (ACR)
51
HD404318 Series
A/D start flag (ADSF: $020, bit 2)
Bit
3
2
1
0
Initial value
—
0
0
—
Read/Write
—
R/W
W
—
Not used
ADSF
Bit name
WDON Not used
WDON
A/D Start Flag (ADSF)
0
A/D conversion completed
1
A/D conversion started
Refer to the description of timers
Figure 44 A/D Start Flag (ADSF)
IAD off flag (IAOF: $021, bit 2)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
RAME
IAOF
ICEF
ICSF
Bit name
ICSF
IAD Off Flag (IAOF)
0
IAD current flows
1
IAD current is cut off
Refer to the description of timers
ICEF
RAME
Refer to the description of timers
Refer to the description of operating
modes
Figure 45 IAD Off Flag (IAOF)
52
HD404318 Series
ADRU: $018
3
2
1
ADRL: $017
0
3
2
1
0
MSB
LSB
bit 7
bit 0
RESULT
Figure 46 A/D Data Registers
A/D data register (lower digit) (ADRL: $017)
Bit
3
2
1
0
Initial value
0
0
0
0
Read/Write
Bit name
R
R
R
R
ADRL3
ADRL2
ADRL1
ADRL0
Figure 47 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018)
Bit
3
2
1
0
Initial value
1
0
0
0
Read/Write
Bit name
R
R
R
R
ADRU3
ADRU2
ADRU1
ADRU0
Figure 48 A/D Data Register Upper Digit (ADRU)
53
HD404318 Series
Notes on Mounting
Assemble all parts including the HD404318 Series on a board, noting the points described below.
1. Connect layered ceramic type capacitors (about 0.1 µF) between AVCC and AVSS , between VCC and
GND, and between used analog pins and AVSS .
2. Connect unused analog pins to AVSS .
1. When not using an A/D converter.
VCC
AVCC
AN 0
0.1 µF
AN 1
to
AN 7
AVSS
GND
2. When using pins AN 0 and AN 1 but not using AN 2 to AN 7 .
AVCC
VCC
AN 0
AN 1
AN 2 to
AN 7
AVSS
GND
0.1 µF × 3
3. When using all analog pins.
VCC
AVCC
AN 0
AN 1
AN 2 to
AN 7
GND
AVSS
0.1 µF × 9
Figure 49 Example of Connections (1)
54
HD404318 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits.
An example connection is described in figure 50.
No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in
parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
VCC
VCC
C1
GND
C2
GND
Figure 50 Example of Connections (2)
55
HD404318 Series
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
Supply voltage
VCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +14.0
V
1
Pin voltage
VT
–0.3 to VCC + 0.3 V
2
VCC – 45 to
VCC + 0.3
V
3
Total permissible input current
∑IO
70
mA
4
Total permissible output current
–∑IO
150
mA
5
Maximum input current
IO
4
mA
6, 7
20
mA
6, 8
4
mA
9, 10
30
mA
10, 11
Maximum output current
–I O
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP ) of HD4074318.
2. Applies to all standard voltage pins.
3. Applies to high-voltage pins.
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to ports R3 and R4.
8. Applies to port R0.
9. Applies to ports R0, R3, and R4.
10. The maximum output current is the maximum current flowing from V CC to each I/O pin.
11. Applies to ports D0–D 8, R1, R2, and R8.
56
HD404318 Series
Electrical Characteristics
DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VC C, T a = –20 to +75°C,
unless otherwise specified)
Item
Symbol Pins
Min
Typ
Max
Unit Test Condition
Input high
voltage
VIH
0.8V CC
—
VCC + 0.3
V
OSC 1
VCC – 0.5 —
VCC + 0.3
V
RESET, SCK,
–0.3
—
0.2V CC
V
VCC – 40
—
0.2V CC
V
–0.3
—
0.5
V
RESET, SCK,
Notes
SI, INT0, INT1,
STOPC, EVNB
Input low voltage VIL
SI
INT0, INT1,
STOPC, EVNB
OSC 1
Output high
voltage
VOH
SCK, SO, TOC VCC – 0.5 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
SCK, SO, TOC —
—
0.4
V
I OL = 0.4 mA
I/O leakage
current
|IIL|
RESET, SCK,
—
—
1
µA
Vin = 0 V to VCC
—
—
20
µA
Vin = VCC – 40 to VCC 1
—
—
5.0
mA
VCC = 5 V,
1
SI, SO, TOC,
OSC 1
INT0, INT1,
STOPC, EVNB
Current
dissipation in
active mode
I CC
VCC
2, 5
f OSC = 4 MHz
Current
dissipation in
standby mode
I SBY
Current
dissipation in
stop mode
I STOP
VCC
—
—
8.0
mA
—
—
2.0
mA
2, 6
VCC = 5 V,
3
f OSC = 4 MHz
Stop mode
VSTOP
retaining voltage
VCC
VCC
—
—
10
µA
—
—
20
µA
2
—
—
V
VCC = 5 V
4, 5
4, 6
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. I CC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions:
MCU: Reset
Pins:
RESET, TEST at GND
R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at V disp
57
HD404318 Series
3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions:
MCU: I/O reset
Standby mode
Pins:
RESET at V CC
TEST at GND
R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at V disp
4. This is the source current when no I/O current is flowing.
Test conditions:
Pins:
R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at GND
5. Applies to the HD404314, HD404316 and HD404318.
6. Applies to the HD4074318.
I/O Characteristics for Standard Pins (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = V CC – 40 V to VCC, Ta =
–20 to +75°C, unless otherwise specified)
Item
Symbol Pins
Min
Typ
Max
Input high
voltage
VIH
Unit Test Condition
R0, R3, R4
0.7V CC
—
VCC + 0.3 V
Input low voltage VIL
R0, R3, R4
–0.3
—
0.3V CC
V
Output high
voltage
VOH
R0, R3, R4
VCC – 0.5 —
—
V
–I OH = 0.5 mA
Output low
voltage
VOL
R3, R4
—
—
0.4
V
I OL = 1.6 mA
R0
—
—
2.0
V
I OL = 10 mA
Note
Input leakage
current
|IIL|
R0, R3, R4
—
—
1
µA
Vin = 0 V to VCC
1
Pull-up MOS
–I PU
R0, R3, R4
30
150
300
µA
VCC = 5 V, Vin = 0 V
2
30
80
180
µA
Notes: 1. Output buffer current is excluded.
2. Applies to the HD404314, HD404316, and HD404318.
3. Applies to the HD4074318.
58
3
HD404318 Series
I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC,
T a = –20 to +75°C, unless otherwise specified)
Item
Symbol
Pins
Min
Typ
Max
Input high
voltage
VIH
D0–D 8, R1,
0.7V CC
—
VCC + 0.3 V
Input low
voltage
VIL
Output high
voltage
VOH
Output low
voltage
I/O leakage
current
Unit Test Condition
Note
R2, R8, RA 1
D0–D 8, R1,
VCC – 40 —
0.3V CC
V
VCC – 3.0 —
—
V
–I OH = 15 mA
VCC – 2.0 —
—
V
–I OH = 10 mA
VCC – 1.0 —
—
V
–I OH = 4 mA
—
—
VCC – 37 V
Vdisp = VCC – 40 V
—
—
VCC – 37 V
150 kΩ at VCC – 40 V 2
—
—
20
µA
Vin = VCC – 40 V to VCC 3
200
600
1000
µA
Vdisp = VCC – 35 V,
R2, R8, RA 1
D0–D 8, R1,
R2, R8, BUZZ
VOL
D0–D 8, R1,
1
R2, R8, BUZZ
|IIL|
Pull-down
I PD
MOS current
D0–D 8, R1, R2,
R8, RA1, BUZZ
D0–D 8, R1,
1
Vin = VCC
R2, R8, BUZZ
Notes: 1. Applies to pins with pull-down MOS as selected by the mask option .
2. Applies to pins without pull-down MOS as selected by the mask option.
3. Excludes output buffer current.
A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC, Ta = –20 to
+75°C, unless otherwise specified)
Item
Symbol Pins
Analog supply voltage
AVCC
AVCC
Analog input voltage
AVin
AN 0–AN 7 AVSS
Current flowing
I AD
between AV CC and AVSS
Analog input
capacitance
CA in
Min
Typ
VCC – 0.3 VCC
Max
Unit
VCC + 0.3 V
—
AVCC
V
—
—
200
µA
AN 0–AN 7 —
—
30
pF
Resolution
8
8
8
Bit
Number of input
channels
0
—
8
Chan
nel
Absolute accuracy
—
—
±2.0
LSB
Conversion time
34
—
67
t cyc
—
—
MΩ
Input impedance
Note:
AN 0–AN 7 1
Test Condition
Note
1
VCC = AVCC = 5.0 V
1. Connect this to V CC if the A/D converter is not used.
59
HD404318 Series
AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a = –20 to +75°C)
Item
Symbol Pins
Min
Typ
Max
Unit
Test Condition
Clock oscillation
frequency
f OSC
0.4
4
4.5
MHz
System clock
divided by 4
Instruction cycle time
t cyc
0.89
1
10
µs
Oscillation stabilization
time (ceramic oscillator)
t RC
OSC 1, OSC 2
—
—
7.5
ms
1
Oscillation stabilization
time (crystal oscillator)
t RC
OSC 1, OSC 2
—
—
40
ms
1
External clock high width t CPH
OSC 1
92
—
—
ns
2
External clock low width
t CPL
OSC 1
92
—
—
ns
2
External clock rise time
t CPr
OSC 1
—
—
20
ns
2
External clock fall time
t CPf
OSC 1
—
—
20
ns
2
INT0, INT1, EVNB high
widths
t IH
INT0, INT1,
2
—
—
t cyc
3
INT0, INT1, EVNB low
widths
t IL
2
—
—
t cyc
3
RESET low width
t RSTL
RESET
2
—
—
t cyc
4
STOPC low width
t STPL
STOPC
1
—
—
t RC
5
RESET rise time
t RSTr
RESET
—
—
20
ms
4
STOPC rise time
t STPr
STOPC
—
—
20
ms
5
Input capacitance
Cin
All input pins —
except TEST
—
30
pF
TEST
—
—
30
pF
6
—
—
180
pF
7
OSC 1, OSC 2
Note
EVNB
INT0, INT1,
EVNB
f = 1 MHz, Vin = 0 V
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V CC reaches 4.0 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 51.
3. Refer to figure 52.
4. Refer to figure 53.
5. Refer to figure 54.
6. Applies to the HD404314, HD404316, and HD404318.
7. Applies to the HD4074318.
60
HD404318 Series
Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a =
–20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item
Symbol
Pins
Min
Typ
Max
Unit
Test Condition
Note
Transmit clock cycle time t Scyc
SCK
1
—
—
t cyc
Load shown in figure 56
1
Transmit clock high width t SCKH
SCK
0.4
—
—
t Scyc
Load shown in figure 56
1
Transmit clock low width
t SCKL
SCK
0.4
—
—
t Scyc
Load shown in figure 56
1
Transmit clock rise time
t SCKr
SCK
—
—
80
ns
Load shown in figure 56
1
Transmit clock fall time
t SCKf
SCK
—
—
80
ns
Load shown in figure 56
1
Serial output data delay
time
t DSO
SO
—
—
300
ns
Load shown in figure 56
1
Serial input data setup
time
t SSI
SI
100
—
—
ns
1
Serial input data hold time t HSI
SI
200
—
—
ns
1
Pins
Min
Typ
Max
Unit
Transmit clock cycle time t Scyc
SCK
1
—
—
t cyc
1
Transmit clock high width t SCKH
SCK
0.4
—
—
t Scyc
1
Transmit clock low width
t SCKL
SCK
0.4
—
—
t Scyc
1
Transmit clock rise time
t SCKr
SCK
—
—
80
ns
1
Transmit clock fall time
t SCKf
SCK
—
—
80
ns
1
Serial output data delay
time
t DSO
SO
—
—
300
ns
Serial input data setup
time
t SSI
SI
100
—
—
ns
1
Serial input data hold time t HSI
SI
200
—
—
ns
1
During Transmit Clock Input
Item
Note:
Symbol
Test Condition
Load shown in figure 56
Note
1
1. Refer to figure 55.
OSC1
1/fCP
VCC – 0.5 V
0.5 V
tCPr
tCPH
tCPL
tCPf
Figure 51 External Clock Timing
61
HD404318 Series
INT0, INT1, EVNB
0.8VCC
tIL
tIH
0.2VCC
Figure 52 Interrupt Timing
RESET
0.8VCC
tRSTL
0.2VCC
tRSTr
Figure 53 RESET Timing
STOPC
0.8VCC
tSTPL
0.2VCC
tSTPr
Figure 54 STOPC Timing
62
HD404318 Series
t Scyc
t SCKf
SCK
VCC – 2.0 V (0.8VCC )*
0.8 V (0.2VCC)*
t SCKr
t SCKL
t SCKH
t DSO
VCC – 2.0 V
0.8 V
SO
t SSI
0.8V CC
0.2VCC
SI
Note:
t HSI
*VCC-2.0V and 0.8V are the threshold voltages for transmit clock output.
0.8V CC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 55 Serial Interface Timing
VCC
RL = 2.6 kΩ
Test
point
C=
30 pF
R=
12 kΩ
Hitachi
1S2074
or equivalent
Figure 56 Timing Load Circuit
63
HD404318 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and
HD404316 as an 8-kword version
(HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the
program used is for an 8-kword version.
This limitation applies when using an EPROM or a data base.
ROM 4-kword version:
HD404314
Address $1000–$1FFF
ROM 6-kword version:
HD404316
Address $1800–$1FFF
$0000
$0000
Vector address
Vector address
$000F
$0010
$000F
$0010
Zero-page subroutine
(64 words)
Zero-page subroutine
(64 words)
$003F
$0040
$003F
$0040
Pattern & program
(4,096 words)
Pattern & program
(6,144 words)
$17FF
$1800
$0FFF
$1000
Not used
$1FFF
$1FFF
Fill this area with 1s
64
Not used
HD404318 Series
HD404314/HD404316/HD404318 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order
Customer
1. ROM Size
Department
HD404314
4-kword
Name
HD404316
6-kword
ROM code name
HD404318
8-kword
LSI number
2. I/O Options
D: Without pull-down resistance
Pin name
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
D5
D6
D7
D8
E: With pull-down resistance
I/O option
I/O
D
E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin name
R1
R2
R8
RA
3. RA1/Vdisp
R10
R11
R12
R13
R20
R21
R22
R23
R80
R81
R82
R83
RA1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O option
D
E
Selected in option (3)
RA1 without pull-down resistance
Vdisp
Note: If even only one pin is selected with I/O option
E, pin RA1/Vdisp must be selected to function
as Vdisp.
4. ROM Code Media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.
6. Stop mode
5. System Oscillator for OSC1 and OSC2
7. Package
Ceramic oscillator
f=
MHz
Used
DP-42S
Crystal oscillator
f=
MHz
Not used
FP-44A
External clock
f=
MHz
65
HD404318 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
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Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
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(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
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Electronic components Group
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Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
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Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
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Tel: 535-2100
Fax: 535-1533
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Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
66