AD ADM487EARZ 5 v, â±15 kv esd protected half-duplex, rs-485/rs-422 transceiver Datasheet

5 V, ±15 kV ESD Protected
Half-Duplex, RS-485/RS-422 Transceivers
ADM485E/ADM487E/ADM1487E
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VCC
TIA/EIA RS-485-/RS-422-compliant
ESD protection on RS-485 I/O pins
±15 kV human body model
Data rates
ADM487E: 250 kbps
ADM485E/ADM1487E: 2.5 Mbps
Half-duplex options
Reduced slew rates for low EMI
−7 V to +12 V common-mode input range
Thermal shutdown and short-circuit protection
8-lead SOIC packages
ADM485E/
ADM487E/
ADM1487E
RO
R
RE
A
DE
B
D
GND
APPLICATIONS
06356-001
DI
Figure 1.
Energy/power metering
Lighting systems
Industrial control
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM485E/ADM487E/ADM1487E are 5 V, low power
data transceivers with ±15 kV ESD protection suitable for halfduplex communication on multipoint bus transmission lines.
They are designed for balanced data transmission and comply
with Telecommunication Industry Association/Electronics Industries Association (TIA/EIA) standards RS-485 and RS-422. The
ADM487E and ADM1487E have a 1/4 unit load receiver input
impedance that allows up to 128 transceivers on a bus, whereas
the ADM485E allows up to 32 transceivers on a bus. Because
only one driver is enabled at any time, the output of a disabled or
power-down driver is three-stated to avoid overloading the bus.
The driver outputs are slew rate-limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead SOIC packages.
Table 1. Selection Table
Part
Number
ADM485E
ADM487E
ADM1487E
Half-/FullDuplex
Half
Half
Half
Guaranteed
Data Rate
(Mbps)
2.5
0.25
2.5
Slew Rate
Limited
No
Yes
No
Low Power
Shutdown
No
Yes
No
Driver/Receiver
Enable
Yes
Yes
Yes
Quiescent
Current (μA)
300
120
230
Number of
Nodes on Bus
32
128
128
Pin
Count
8
8
8
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADM485E/ADM487E/ADM1487E
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................8
Applications....................................................................................... 1
Test Circuits and Switching Characteristics................................ 11
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 13
General Description ......................................................................... 1
Circuit Description .................................................................... 13
Revision History ............................................................................... 2
Applications Information .............................................................. 15
Specifications..................................................................................... 3
Differential Data Transmission ................................................ 15
Timing Specifications .................................................................. 4
Cable and Data Rate................................................................... 15
Absolute Maximum Ratings............................................................ 6
Outline Dimensions ....................................................................... 16
ESD Caution.................................................................................. 6
Ordering Guide .......................................................................... 16
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM485E/ADM487E/ADM1487E
SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 2. ADM485E/ADM487E/ADM1487E
Parameter
DRIVER
Differential Outputs
Differential Output Voltage (no Load)
Differential Output Voltage (with Load)
Δ |VOD| for Complementary Output
States
Common-Mode Output Voltage
Δ |VOC| for Complementary Output
States
Logic Inputs
Input High Voltage
Input Low Voltage
Logic Input Current
RECEIVER
Input Current (A, B)
Symbol
VOD1
VOD2
Min
Typ
2
1.5
VOC
VIH
VIL
IIN1
Max
Unit
Test Conditions/Comments
5
5
0.2
V
V
V
V
RL = 50 Ω (RS-422)
RL = 27 Ω (RS-485) (see Figure 18)
RL = 27 Ω or 50 Ω (see Figure 18)
3
0.2
V
V
RL = 27 Ω or 50 Ω (see Figure 18)
RL = 27 Ω or 50 Ω (see Figure 18)
0.8
±2
V
V
μA
DE, DI, RE
DE, DI, RE
DE, DI, RE
mA
mA
mA
mA
DE = 0 V, VIN = 12 V
VCC = 0 V or +5.25 V, VIN = −7 V (ADM485E)
DE = 0 V, VIN = 12 V
VCC = 0 V or +5.25 V, VIN = −7 V
(ADM487E/ADM1487E)
V
mV
−7 V < VCM < +12 V
VCM = 0 V
V
V
μA
kΩ
kΩ
IOUT = −4 mA, VID = +200 mV
IOUT = +4 mA, VID = −200 mV
0.4 V < VO < 2.4 V
−7 V < VCM < +12 V (ADM485E)
−7 V< VCM < +12 V (ADM487E/ADM1487E)
μA
μA
μA
μA
μA
μA
μA
mA
mA
RE = 0 V or VCC, DE = VCC (ADM485E)
RE = 0 V or VCC, DE = 0 V (ADM485E)
RE = 0 V or VCC, DE = VCC (ADM1487E)
RE = 0 V or VCC, DE = 0 V (ADM1487E)
RE = 0 V or VCC, DE = VCC (ADM487E)
RE = 0 V, DE = 0 V (ADM487E)
DE = 0 V, RE = VCC (ADM487E)
−7 V ≤ VO ≤ +12 V, applies to peak current
−7 V ≤ VO ≤ +12 V, applies to peak current
0 V ≤ VO ≤ VCC
kV
Human body model
2.0
IIN2
1.0
−0.8
0.25
−0.2
Differential Inputs
Differential Input Threshold Voltage
Input Hysteresis
Receiver Output Logic
Output Voltage High
Output Voltage Low
Three-State Output Leakage Current
Receiver Input Resistance
POWER SUPPLY
No Load Supply Current
Supply Current in Shutdown
Driver Short-Circuit Current, VO High
Driver Short-Circuit Current, VO Low
Receiver Short-Circuit Current
ESD PROTECTION
A, B Pins
VTH
ΔVTH
−0.2
VOH
VOL
IOZR
RIN
3.5
0.4
±1
12
48
ICC
ISHDN
IOSD1
IOSD2
IOSR
+0.2
70
500
300
300
230
250
120
0.5
35
35
7
900
500
500
400
400
250
10
250
250
95
±15
Rev. 0 | Page 3 of 16
ADM485E/ADM487E/ADM1487E
TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
DRIVER
Input to Output
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
tDPLH
10
40
60
ns
tDPHL
10
40
60
ns
5
10
ns
20
40
ns
45
45
45
45
70
70
70
70
ns
ns
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
60
200
ns
Output Skew to Output
tSKEW
Rise/Fall Time
tDR, tDF
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
Input to Output
tDZH
tDZL
tDLZ
tDHZ
|tPLH − tPHL| Differential Receiver Skew
tSKEW
5
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
MAXIMUM DATA RATE
tRZL
tRZL
tRLZ
tRHZ
fMAX
25
20
20
20
tRPLH
3
20
2.5
Rev. 0 | Page 4 of 16
ns
50
50
50
50
ns
ns
ns
ns
Mbps
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 23 and Figure 24)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 4 and Figure 5)
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
ADM485E/ADM487E/ADM1487E
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4. ADM487E
Parameter
DRIVER
Input to Output
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
tDPLH
250
800
2000
ns
tDPHL
250
800
2000
ns
Output Skew to Output
tSKEW
250
20
800
ns
Rise/Fall Time
tDR, tDF
250
2000
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
tDZH
tDZL
tDLZ
tDHZ
250
300
300
2000
2000
3000
3000
ns
ns
ns
ns
CRL = 100 pF, S2 closed (see Figure 21)
CRL = 100 pF, S1 closed (see Figure 22)
CRL = 15 pF, S1 closed (see Figure 22)
CRL = 15 pF, S2 closed (see Figure 21)
tRPLH
tRPHL
250
250
2000
2000
ns
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see Figure 19 and Figure 20)
CRL = 15 pF, S1 closed
(see Figure 23 and Figure 24)
CRL = 15 pF, S2 closed (see Figure 25)
CRL = 15 pF, S1 closed (see Figure 25)
CRL = 15 pF, S2 closed (see Figure 25)
tPLH, tPHL < 50% of data period
Enable Time to High Level
Enable Time to Low Level
Disable Time from Low Level
Disable Time from High Level
RECEIVER
Input to Output
1
|tPLH − tPHL| Differential Receiver Skew
tSKEW
100
Enable Time to Low Level
Enable Time to High Level
Disable Time from Low Level
Disable Time from High Level
Maximum Data Rate
Time to Shutdown 1
Driver Enable from Shutdown to Output High
Driver Enable from Shutdown to Output Low
Receiver Enable from Shutdown to Output High
tRZL
tRZL
tRLZ
tRHZ
fMAX
tDZH(SHDN)
tDZL(SHDN)
tRZL(SHDN)
tRZH(SHDN)
25
25
25
25
50
50
50
50
200
5000
5000
5000
600
250
50
ns
ns
ns
ns
ns
kbps
ns
ns
ns
ns
CL = 100 pF, S2 closed (see Figure 21)
CL = 100 pF, S1 closed (see Figure 22)
CL = 15 pF, S2 closed (see Figure 25)
CL = 15 pF, S1 closed (see Figure 25)
The ADM487E is put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
Rev. 0 | Page 5 of 16
ADM485E/ADM487E/ADM1487E
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VCC to GND
Digital I/O Voltage (DE, RE)
Driver Input Voltage (DI)
Receiver Output Voltage (RO)
Driver Output/Receiver Input Voltage
(A, B)
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
SOIC-8
Lead Temperature
Soldering (10 sec)
Rating
−0.5 V to +6 V
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−0.5 V to (VCC + 0.5 V)
−9 V to +14 V
−40° to +85°C
−65° to +150°C
158°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
260°C
Rev. 0 | Page 6 of 16
ADM485E/ADM487E/ADM1487E
RO 1
RE 2
DE 3
DI 4
ADM485E/
ADM487E/
ADM1487E
TOP VIEW
(Not to Scale)
8
VCC
7
B
6
A
5
GND
06356-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
RO
RE
DE
4
DI
5
6
7
8
GND
A
B
VCC
Description
Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
Receiver Output Enable. A low level enables the RO; a high level places it in a high impedance state.
Driver Output Enable. A high level enables the driver differential outputs, Pin A and Pin B; a low level places it
in a high impedance state.
Driver Input. When the driver is enabled, a Logic L = low on DI forces A low and B high; a Logic H = high on DI
forces Pin A high and Pin B low.
Ground Connection (0 V).
Noninverting Receiver Input A/Driver Output A.
Inverting Receiver Input B/Driver Output B.
Power Supply (5 V ± 5%).
Rev. 0 | Page 7 of 16
ADM485E/ADM487E/ADM1487E
TYPICAL PERFORMANCE CHARACTERISTICS
50
0.9
45
0.8
OUTPUT LOW VOLTAGE (V)
35
30
25
20
15
06356-016
10
5
0
0
0.5
1.0
1.5
2.0
0.7
0.6
0.5
0.4
0.3
IRO = 8mA
0.2
0.1
06356-019
OUTPUT CURRENT (mA)
40
0
–40
2.5
–20
0
OUTPUT LOW VOLTAGE (V)
20
40
60
80
TEMPERATURE (°C)
Figure 3. Output Current vs. Receiver Output Low Voltage
Figure 6. Receiver Output Low Voltage vs. Temperature
–30
45
40
–25
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
35
–20
–15
–10
30
25
20
15
10
2.0
2.5
3.0
3.5
4.0
4.5
5
0
5.0
06356-020
0
1.5
06356-017
–5
0
0.5
OUTPUT HIGH VOLTAGE (V)
Figure 4. Output Current vs. Receiver Output High Voltage
2.0
2.5
3.0
3.5
4.0
4.5
4.3
4.2
IRO = –8mA
4.1
06356-018
4.0
–20
0
20
40
60
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
–40
80
TEMPERATURE (°C)
06356-021
DIFFERENTIAL OUTPUT VOLTAGE (V)
2.3
4.4
OUTPUT HIGH VOLTAGE (V)
1.5
Figure 7. Driver Output Current vs. Differential Output Voltage
4.5
3.9
–40
1.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Driver Differential Output Voltage vs. Temperature
Figure 5. Receiver Output High Voltage vs. Temperature
Rev. 0 | Page 8 of 16
ADM485E/ADM487E/ADM1487E
140
600
500
100
SUPPLY CURRENT (µA)
80
60
40
400
300
200
DE = VCC AND RE = X
100
0
06356-022
20
0
2
4
6
8
10
DE = 0 AND RE = Ø
0
–40
12
06356-025
OUTPUT CURRENT (mA)
120
–20
0
OUTPUT LOW VOLTAGE (V)
20
40
60
80
TEMPERATURE (°C)
Figure 12. ADM487E Supply Current vs. Temperature
Figure 9. Output Current vs. Driver Output Low Voltage
10
–140
9
8
SHUTDOWN CURRENT (µA)
–100
–80
–60
–40
0
–8
6
5
4
3
2
1
06356-023
–20
7
–6
–4
–2
0
2
4
06356-026
OUTPUT CURRENT (mA)
–120
0
–60
6
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
Figure 10. Output Current vs. Driver Output High Voltage
Figure 13. Shutdown Current vs. Temperature
600
T
3
B
400
300
2
DE = VCC AND RE = X
200
A
DE = 0 AND RE = X
0
–40
1
–20
0
20
40
60
06356-027
100
06356-024
SUPPLY CURRENT (µA)
500
RO
CH1 5.00V CH2 500mV
CH3 500mV
80
TEMPERATURE (°C)
Figure 11. ADM485E/ADM1487E Supply Current vs. Temperature
M200ns
T 57.60%
A CH1
Figure 14. ADM487E Receiver tPHL
Rev. 0 | Page 9 of 16
2.80V
ADM485E/ADM487E/ADM1487E
T
3
2
3
A
2
B
T
B
A
RO
06356-028
CH1 5.00V CH2 500mV
CH3 500mV
M200ns
T 60.80%
A CH1
1
RO
2.80V
CH1 5.00V CH2 500mV
CH3 500mV
T
2
A
B
RO
06356-029
1
CH1 5.00V CH2 500mV
CH3 500mV
M20ns
T 60.80%
A CH1
M20ns
T 60.80%
A CH1
Figure 17. ADM485E/ADM1487E Receiver tPLH
Figure 15. ADM487E Receiver tPLH Driven by External RS-485 Device
3
06356-030
1
2.70V
Figure 16. ADM485E/ADM1487E Receiver tPHL
Rev. 0 | Page 10 of 16
2.70V
ADM485E/ADM487E/ADM1487E
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
Y
RL
VCC
VOD
RL = 500Ω
S1
0V OR 5V
VOC
D
Z
Figure 18. Driver DC Test Load
GENERATOR
OUT
CL
06356-003
RL
50Ω
VDD
5V
DE
DE
CL
VCC/2
0V
A
tDZL,
RL
tDZL(SHDN)
B
tDLZ
VCC
CL
2.3V
06356-004
OUT
0.5V
VOL
Figure 19. Driver Timing Test Circuit
Figure 22. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN))
RECEIVER
OUTPUT
B
VID
ATE
5V
DI
0V
R
A
1.5V
tDPLH
06356-007
VOD
tDPHL
06356-008
DI
1/2 VO
Figure 23. Receiver Propagation Delay Test Circuit
B
VO
1/2VO
0V
–VO
B
VDIFF = V (A) – V (B)
VO
80%
20%
tDR
tDF
tSKEW = tDPLH – tDPHL
RO
1.5V
VOL
GENERATOR
OUT
CL
RL = 500Ω
50Ω
5V
DE
1.5V
tDZH,
tDZH(SHDN)
0V
0.5V
VOH
2.3V
tDHZ
0V
06356-006
OUT
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
Figure 24. Receiver Propagation Delays
S1
D
–1V
tRPHL
VOH
Figure 20. Driver Propagation Delays
0 OR 5V
tRPLH
80%
20%
06356-005
VDIFF
+1V
A
Figure 21. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
Rev. 0 | Page 11 of 16
06356-009
A
ADM485E/ADM487E/ADM1487E
S1
S3
–1.5V
0V OR 5V
GENERATOR
VCC
1kΩ
VID
CL
15pF
S2
50Ω
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
+5V
RE
+5V
RE
0V
tRZH, tRZH(SHDN)
tRZL, tRZL(SHDN)
VOH
+1.5V
RO
+1.5V
VCC
+1.5V
RO
0V
VOL
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = +1.5V
+5V
+5V
RE
RE
+1.5V
0V
RO
+1.5V
tRLZ
tRHZ
+0.5V
0V
0V
VCC
VOH
RO
0V
+0.5V
Figure 25. Receiver Enable and Disable Times
Rev. 0 | Page 12 of 16
VOL
06356-010
+1.5V
ADM485E/ADM487E/ADM1487E
THEORY OF OPERATION
5V
The ADM485E/ADM487E/ADM1487E are ruggedized RS-485
transceivers that operate from a single 5 V supply. They contain
protection against high levels of electrostatic discharge and are
ideally suited for operation in electrically harsh environments
or where cables can be plugged or unplugged. These devices are
intended for balanced data transmission and comply with TIA/
EIA standards RS-485 and RS-422. They contain a differential
line driver and a differential line receiver and are suitable for
half-duplex data transmission, as the driver and receiver share
the same differential pins.
0.1µF
RE
0.1µF
VCC
VCC
DE
DI
RO
B
B
ADM485E/
ADM487E/
ADM1487E
A
GND
RO
GND
RE
06356-012
DE
A
ADM485E/
ADM487E/
ADM1487E
RS485/RS-422 LINK
DI
The input impedance on the ADM485E is 12 kΩ, allowing up
to 32 transceivers on the differential bus. The ADM487E/
ADM1487E are 48 kΩ, allowing up to 128 transceivers on the
differential bus.
Figure 26. Typical Half-Duplex Link Application
CIRCUIT DESCRIPTION
The ADM485E/ADM487E/ADM1487E are operated from
a single 5 V ± 10% power supply. Excessive power dissipation
caused by bus contention or output shorting is prevented by
a thermal shutdown circuit. If, during fault conditions, a significant temperature increase is detected in the internal driver
circuitry, this feature forces the driver output into a high
impedance state.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
A high level of robustness is achieved using internal protection
circuitry, eliminating the need for external protection components such as tranzorbs or surge suppressors.
Low electromagnetic emissions are achieved using slew-ratelimited drivers, minimizing both conducted and radiated
interference.
The ADM485E/ADM487E/ADM1487E can transmit at data
rates up to 250 kbps.
A typical application for the ADM485E/ADM487E/ADM1487E
is illustrated in Figure 26, which shows a half-duplex link where
data can be transferred at rates up to 250 kbps. A terminating
resistor is shown at both ends of the link. This termination is
not critical, because the slew rate is controlled by the ADM485E/
ADM487E/ADM1487E and reflections are minimized.
The communications network can be extended to include
multipoint connections, as shown in Figure 29. As many as
32 ADM485E transceivers or 128 ADM487E/ADM1487E
transceivers can be connected to the bus.
5V
Table 7 and Table 8 show the truth tables for transmitting and
receiving.
Table 7. Transmitting Truth Table
RE
X1
X1
0
1
1
Transmitting Inputs
DE
DI
1
1
0
0
Transmitting Outputs
B
A
1
0
X1
X1
0
1
High-Z
High-Z
1
0
High-Z
High-Z
X = don’t care.
Table 8. Receiving Truth Table
RE
Receiving Inputs
DE
0
0
0
1
1
0
0
0
0
A to B
Receiving Outputs
RO
≥ +0.2 V
≤ −0.2 V
Inputs Open Circuit
X1
1
0
1
High-Z
X = don’t care.
ESD Transient Protection Scheme
The ADM485E/ADM487E/ADM1487E use protective clamping
structures on their inputs and outputs that clamp the voltage to
a safe level and dissipate the energy present in ESD (electrostatic).
The protection structure achieves ESD protection up to ±15 kV
human body model (HBM).
Rev. 0 | Page 13 of 16
ADM485E/ADM487E/ADM1487E
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or heating.
Even if catastrophic failure does not occur immediately, the
device can suffer from parametric degradation, which can result
in degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
HIGH
VOLTAGE
GENERATOR
R2
C1
HUMAN BODY MODEL
±15kV
100pF
36.8%
10%
TIME (t)
tRL
tDL
Figure 28. Human Body Model ESD Current Waveform
Table 9. ADM483E ESD Test Results
06356-013
DEVICE
UNDER TEST
ESD TEST METHOD
90%
ESD Test Method
Human Body Model (HBM)
R2
C1
100%
06356-014
Two coupling methods are used for ESD testing: contact
discharge and air-gap discharge. Contact discharge calls for
a direct connection to the unit being tested; air-gap discharge
uses a higher test voltage but does not make direct contact with
the unit under test. With air discharge, the discharge gun is moved
toward the unit under test, developing an arc across the air gap;
hence the term air discharge. This method is influenced by
humidity, temperature, barometric pressure, distance, and rate
of closure of the discharge gun. The contact-discharge method,
though less realistic, is more repeatable and is gaining acceptance and preference over the air-gap method.
The ESD discharge can induce latch-up in the device under test.
Therefore, it is important that ESD testing on the I/O pins be
carried out while device power is applied. This type of testing
is more representative of a real-world I/O discharge where the
equipment is operating normally when the discharge occurs.
IPEAK
ESD Testing
Figure 27. ESD Generator
I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static
discharge that can damage or completely destroy the inter
face product connected to the I/O port. It is, therefore, extremely
important to have high levels of ESD protection on the I/O lines.
Rev. 0 | Page 14 of 16
I/O Pins
±15 kV
Other Pins
±3.5 V
ADM485E/ADM487E/ADM1487E
APPLICATIONS INFORMATION
DIFFERENTIAL DATA TRANSMISSION
CABLE AND DATA RATE
Differential data transmission is used to reliably transmit data
at high rates over long distances and through noisy environments. Differential transmission nullifies the effects of ground
shifts and noise signals that appear as common-mode voltages
on the line. There are two main standards approved by TIA/EIA
that specify the electrical characteristics of transceivers used in
differential data transmission.
The transmission line of choice for RS-485 communications is
a twisted pair. A twisted pair cable can cancel common-mode
noise and can also cause cancellation of the magnetic fields
generated by the current flowing through each wire, thereby
reducing the effective inductance of the pair.
To cater to true multipoint communications, the RS-485 standard
is defined. This standard meets or exceeds all the requirements
of RS-422, but also allows for up to 32 drivers and 32 receivers
to be connected to a single bus. An extended common-mode
range of −7 V to +12 V is defined. The most significant difference between RS-422 and RS-485 is that the drivers can be
disabled, thereby allowing as many as 32 drivers to be connected
to a single line. Only one driver is enabled at a time, but the
RS-485 standard contains additional specifications to guarantee
device safety in the event of line contention.
Rev. 0 | Page 15 of 16
RT
RT
D
D
R
R
D
R
D
R
Figure 29. Typical RS-485 Network
06356-015
The RS-422 standard specifies data rates up to 10 MB and line
lengths up to 4000 feet. A single driver can drive a transmission
line with up to 10 receivers.
A typical application showing a multipoint transmission network is illustrated in Figure 29. An RS-485 transmission line
can have as many as 32 transceivers on the bus. Only one driver
can transmit at a particular time, but multiple receivers can be
enabled simultaneously.
ADM485E/ADM487E/ADM1487E
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060506-A
4.00 (0.1574)
3.80 (0.1497)
Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
ADM485EARZ 1
ADM485EARZ-REEL71
ADM487EARZ1
ADM487EARZ-REEL71
ADM1487EARZ1
ADM1487EARZ-REEL71
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06356-0-1/07(0)
Rev. 0 | Page 16 of 16
Package Option
R-8
R-8
R-8
R-8
R-8
R-8