PD - 95371A
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IRFR3411PbF
IRFU3411PbF
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Lead-Free
HEXFET® Power MOSFET
D
VDSS = 100V
RDS(on) = 44mΩ
G
Description
Advanced HEXFET® Power MOSFETs from International
Rectifier utilize advanced processing techniques to
achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and
ruggedized device design that HEXFET power MOSFETs
are well known for, provides the designer with an
extremely efficient and reliable device for use in a wide
variety of applications.
ID = 32A
S
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The
straight lead, I-Pak, version (IRFU series) is for throughhole mounting applications. Power dissipation levels up
to 1.5 watts are possible in typical surface mount
applications.
D-Pak
IRFR3411
I-Pak
IRFU3411
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
32
23
110
130
0.83
± 20
16
13
7.0
-55 to + 175
A
W
W/°C
V
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
1.2
50
110
°C/W
1
12/03/04
IRFR/U3411PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
∆V(BR)DSS/∆TJ
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
EAS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Single Pulse Avalanche Energy
IGSS
Min. Typ. Max. Units
Conditions
100 ––– –––
V
VGS = 0V, I D = 250µA
––– 0.12 ––– V/°C Reference to 25°C, I D = 1mA
–––
36
44
mΩ VGS = 10V, ID = 16A
2.0
––– 4.0
V
VDS = VGS , ID = 250µA
21
––– –––
S
VDS = 50V, ID = 16A
––– ––– 25
VDS = 100V, VGS = 0V
µA
––– ––– 250
VDS = 80V, VGS = 0V, TJ = 150°C
––– ––– 100
VGS = 20V
nA
––– ––– -100
VGS = -20V
–––
48
71
ID = 16A
–––
9.0
14
nC
VDS = 80V
–––
14
21
VGS = 10V, See Fig. 6 and 13
–––
11 –––
VDD = 50V
–––
35 –––
ID = 16A
ns
–––
39 –––
RG = 5.1Ω
–––
35 –––
VGS = 10V, See Fig. 10
Between lead,
4.5 –––
–––
6mm (0.25in.)
nH
G
from package
–––
7.5 –––
and center of die contact
––– 1960 –––
VGS = 0V
––– 250 –––
VDS = 25V
–––
40 –––
pF
ƒ = 1.0MHz, See Fig. 5
––– 700 185 mJ IAS = 16A, L = 1.5mH
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
33
––– –––
showing the
A
G
integral reverse
––– ––– 110
S
p-n junction diode.
––– ––– 1.2
V
TJ = 25°C, IS = 16A, VGS = 0V
––– 115 170
ns
TJ = 25°C, IF = 16A
––– 505 760
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L =1.5mH
RG = 25Ω, IAS = 16A. (See Figure 12)
ISD ≤ 16A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TJ = 175°C .
* When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint dering techniques refer to application note
#AN-994.
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IRFR/U3411PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
4.5V
10
20µs PULSE WIDTH
TJ = 25 °C
1
0.1
1
10
100
4.5V
10
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.5
TJ = 25 ° C
100
TJ = 175 ° C
V DS = 50V
20µs PULSE WIDTH
6.0
7.0
8.0
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
5.0
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
VGS , Gate-to-Source Voltage (V)
20µs PULSE WIDTH
TJ = 175 °C
1
0.1
100
VDS , Drain-to-Source Voltage (V)
10
4.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
9.0
ID = 33A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U3411PbF
3000
VGS , Gate-to-Source Voltage (V)
2500
C, Capacitance (pF)
20
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
2000
1500
1000
Coss
500
ID = 16A
VDS = 80V
VDS = 50V
VDS = 20V
16
12
8
4
Crss
0
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
0
100
60
80
1000
ID, Drain-to-Source Current (A)
1000
ISD , Reverse Drain Current (A)
40
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100
TJ = 175 ° C
10
TJ = 25 ° C
1
0.1
0.2
20
QG , Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
100µsec
10
1msec
1
T A = 25°C
V GS = 0 V
0.6
1.0
1.4
VSD ,Source-to-Drain Voltage (V)
1.8
10msec
T J = 175°C
Single Pulse
0.1
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
Fig 8. Maximum Safe Operating Area
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IRFR/U3411PbF
RD
35
VDS
30
VGS
ID , Drain Current (A)
D.U.T.
RG
25
+
-VDD
V GS
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
Fig 10a. Switching Time Test Circuit
10
VDS
5
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC )
10
1
Thermal Response
D = 0.50
0.20
0.10
0.1
P DM
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+T C
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
L
VDS
DRIVER
D.U.T
RG
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
IRFR/U3411PbF
400
ID
6.5A
11.3A
BOTTOM 16A
TOP
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U3411PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
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7
IRFR/U3411PbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
PART NUMBER
INTERNAT IONAL
RECTIFIER
LOGO
Note: "P" in ass embly line pos ition
indicates "Lead-Free"
IRFU120
12
916A
34
ASSEMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INT ERNATIONAL
RECTIFIER
LOGO
IRFU120
12
ASSEMBLY
LOT CODE
8
34
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 9 = 1999
WEEK 16
A = ASSEMBLY S IT E CODE
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IRFR/U3411PbF
I-Pak (TO-251AA) Package Outline
( Dimensions are shown in millimeters (inches) )
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS SEMBLY
LOT CODE 5678
AS S EMB LED ON WW 19, 1999
IN T HE ASS EMB LY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF U120
919A
56
78
AS S EMB LY
LOT CODE
Note: "P" in ass embly line
pos ition indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
OR
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBER
IRFU120
56
AS S EMBLY
LOT CODE
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78
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 19
A = AS S EMBL Y S ITE CODE
9
IRFR/U3411PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
10
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